ADV101

ADV101 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a CMOS

80 MHz, Triple 8-Bit Video DAC

ADV101* Tel: 617/329-4700 Fax: 617/326-8703 FUNCTIONAL BLOCK DIAGRAM REF WHITE PIXEL INPUT PORT IOR IOG IOB CLOCK SYNC ADV101 VREF GND BLANK FS ADJUST ISYNC VAA REFERENCE AMPLIFIER COMP RED REGISTER BLUE REGISTER CONTROL REGISTER GREEN REGISTER DAC SYNC CONTROL DAC DAC

FEATURES

80 MHz Pipelined Operation

Triple 8-Bit D/A Converters RS-343A/RS-170 Compatible Outputs TTL Compatible Inputs +5 V CMOS Monolithic Construction 40-Pin DIP or 44-Pin PLCC Package Plug-In Replacement for BT101 Power Dissipation: 400 mW

APPLICATIONS

High Resolution Color Graphics CAE/CAD/CAM Applications Image Processing Instrumentation Video Signal Reconstruction Desktop Publishing SPEED GRADES

80 MHz

50 MHz

30 MHz

The ADV101 is a digital-to-analog video converter on a single monolithic chip. The part is specifically designed for high reso- lution color graphics and video systems. It consists of three, high speed, 8-bit, video D/A converters (RGB); a standard TTL input interface and high impedance, analog output, current sources. The ADV101 has three separate, 8-bit, pixel input ports, one each for red, green and blue video data. Additional video input controls on the part include sync, blank and reference white. A single +5 V supply, an external 1.23 V reference and pixel clock input are all that are required to make the part operational. The ADV101 is capable of generating RGB video output sig- nals, which are compatible with RS-343A and RS-170 video standards, without requiring external buffering. The ADV101 is fabricated in a +5 V CMOS process. Its mono- lithic CMOS construction ensures greater functionality with low power dissipation. The part is packaged in both a 0.6", 40-pin plastic DIP and a 44-pin plastic leaded (J-lead) chip carrier, PLCC. *ADV is a registered trademark of Analog Devices Inc. PRODUCT HIGHLIGHTS 1. Fast video refresh rate, 80 MHz. 2. Compatible with a wide variety of high resolution color graphics video systems. 3. Guaranteed monotonic with a maximum differential nonlin- earity of ± 0.5 LSB. Integral nonlinearity is guaranteed to be a maximum of ± 1 LSB.

REV. B–2– ADV101–SPECIFICATIONS (VAA = +5 V 6 5%; VREF = +1.235 V; RL = 37.5 V, CL = 10 pF; RSET = 560 V. ISYNC connected to IOG. All Specifications T MIN to TMAX 1 unless otherwise noted.) Parameter All Versions Units Test Conditions/Comments STATIC PERFORMANCE Resolution (Each DAC) 8 Bits Accuracy (Each DAC) Integral Nonlinearity, INL ± 1 LSB max Differential Nonlinearity, DNL ± 0.5 LSB max Guaranteed Monotonic Gray Scale Error ± 5 % Gray Scale max Max Gray Scale Current: IOG = (V REF* 12,082/RSET) mA Max Gray Scale Current: IOR, IOB = (VREF* 8,627/RSET) mA Coding Binary DIGITAL INPUTS Input High Voltage, V INH 2 V min Input Low Voltage, V INL 0.8 V max Input Current, IIN ± 1 µA max V IN = 0.4 V or 2.4 V Input Capacitance, CIN 2 10 pF max ANALOG OUTPUTS Gray Scale Current Range 15 mA min 22 mA max Output Current White Level Relative to Blank 17.69 mA min Typically 19.05 mA 20.40 mA max White Level Relative to Black 16.74 mA min Typically 17.62 mA 18.50 mA max Black Level Relative to Blank 0.95 mA min Typically 1.44 mA 1.90 mA max Blank Level on IOR, IOB 0 µA min Typically 5 µA 50 µA max Blank Level on IOG 6.29 mA min Typically 7.62 mA 9.5 mA max Sync Level on IOG 0 µA min Typically 5 µA 50 µA max LSB Size 69.1 µA typ DAC to DAC Matching 2 % typ Output Compliance, V OC –1 V min +1.4 V max Output Impedance, R OUT 2 100 k Ω typ Output Capacitance, C OUT 2 30 pF max I OUT = 0 mA VOLTAGE REFERENCE Voltage Reference Range, VREF 1.14/1.26 V min/V max V REF = 1.235 V for Specified Performance Input Current, IVREF +10 µA typ POWER REQUIREMENTS VAA 5 V nom IAA 125 mA max Typically 80 mA: 80 MHz Parts 100 mA max Typically 70 mA: 50 MHz & 35 MHz Parts Power Supply Rejection Ratio 0.5 %/% max Typically 0.12%/%: f = 1 kHz, COMP = 0.1 µF Power Dissipation 625 mW max Typically 400 mW: 80 MHz Parts 500 mW max Typically 350 mW: 50 MHz & 30 MHz Parts DYNAMIC PERFORMANCE Glitch Impulse2, 3 50 pV secs typ DAC Noise2, 3, 4 200 pV secs typ Analog Output Skew 2 ns max Typically 1 ns NOTES 1Temperature Range (T MIN to TMAX); 0°C to +70°C. 2Sample tested at +25 °C to ensure compliance. 3TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 4This includes effects due to clock and data feedthrough as well as RGB analog crosstalk. Specifications subject to change without notice.

puts. See timing notes in Figure 1. 2Temperature range (T MIN to TMAX): 0°C to +70°C. 3Sample tested at +25 °C to ensure compliance. Specifications subject to change without notice.

1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF

CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.

1. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE

TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.

1. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS

Figure 1. Video Input/Output Timing

–4– REV. B WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV101 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units Power Supply V AA 4.75 5.00 5.25 Volts Ambient Operating Temperature T A 0 +70 °C Output Load R L 37.5 Ω Reference Voltage V REF 1.14 1.235 1.26 Volts ORDERING GUIDE1 Package Speed Option2 80 MHz 50 MHz 30 MHz Plastic DIP (N-40A) ADV101KN80 ADV101KN50 ADV101KN30 PLCC3 (P-44A) ADV101KP80 ADV101KP50 ADV101KP30 NOTES 1All devices are specified for 0 °C to +70°C operation. 2N = Plastic DIP; P = Plastic Leaded Chip Carrier. 3PLCC: Plastic Leaded Chip Carrier (J-lead). ABSOLUTE MAXIMUM RATINGS 1 NOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Analog output short circuit to any power supply or common can be of an indefinite duration. DIP 20 21 REF WHITE COMP V REF FS ADJUST GND VAA ISYNC IOG IOR IOB GND SYNC BLANK V AA GND CLOCK TOP VIEW (NOT TO SCALE) ADV101 PLCC 282726 18 19 20 21 22 23 24 25 ADV101 TOP VIEW (Not to Scale) BLANK SYNC CLOCK REF WHITE COMP FS ADJUST GND GND IOG IOR IOB GND 432156 44 43 42 41 40 VAA VAA GND GND VAA VAA VREF ISYNC

–5–REV. B PIN FUNCTION DESCRIPTION Pin Mnemonic Function BLANK Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs, IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are ignored. SYNC Composite sync control input (TTL compatible). A logical zero on the SYNC input; switches off a 40 IRE cur- rent source on the I SYNC output. SYNC does not override any other control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC, BLANK and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. REF WHITE Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB out- puts to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7) REF WHITE is latched on the rising edge of clock. R0–R7, R ed, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0–G7, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular B0–B7 PCB power or ground plane. IOR, IOG, IOB Red, green and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. I SYNC Sync current output. This high impedance current source can be directly connected to the IOG output. This al- lows sync information to be encoded onto the green channel. I SYNC does not output any current while SYNC is at logical zero. The amount of current output at I SYNC while SYNC is at logical one is given by: ISYNC (mA) = 3,455 × VREF (V)/RSET (Ω ) If sync information is not required on the green channel, I SYNC should be connected to AGND. FS ADJUST Full-scale adjust control. A resistor (R SET) connected between this pin and GND, controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between R SET and the full-scale output current on IOG (assuming I SYNC is connected to IOG) is given by: RSET (Ω ) = 12,082 × VREF (V)/IOG (mA) The relationship between R SET and the full-scale output current on IOR and IOB is given by: IOR, IOB (mA) = 8,628 × VREF (V)/ RSET (Ω ) COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor must be connected between COMP and V AA. VREF Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an exter- nal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA. VAA Analog power supply (5 V ± 5%). All VAA pins on the ADV101 must be connected. GND Ground. All GND pins must be connected.

ture tube, resulting in the blackest possible picture. required, one for each color. els, while a 6-bit DAC contains 64. generate and display images. The maximum negative polarity amplitude of the video signal. The maximum positive polarity amplitude of the video signal. The peak level of the SYNC signal. is then converted to three analog (RGB) output waveforms. video outputs in a similar fashion. maintain synchronization with the pixel data stream. these video synchronization signals onto the RGB video output. SYNC and BLANK on the analog video waveform is illustrated. sor or crosshair onto the RGB video output. by the on-screen resolution, according to the following equation. 30 Hz for an interlaced system. Figure 2. Video Data Input/Output

circuitry will enable the generation of a composite SYNC signal. to logic low and ISYNC should be connected to analog GND. The required CLOCK frequency is thus 78.6 MHz. input to the ADV101 be driven by a TTL buffer (e.g., 74F244). 1Typical with full-scale IOG = 26.67 mA. V REF = 1.235 V, R SET = 560 Ω , ISYNC connected to IOG.

92.5 IRE

7.5 IRE

40 IRE

1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75 W LOAD.
2. V = 1.235V, R = 560W , I CONNECTED TO IOG.REF SET SYNC
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

Figure 3. RGB Video Output Waveform

–11–REV. B Power Planes The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV101 (V AA) and all asso- ciated analog circuitry. This power plane should be connected to the regular PCB power plane (V CC) at a single point through a ferrite bead, as illustrated in Figure 8. This bead should be lo- cated within three inches of the ADV101. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV101 power pins, voltage reference circuitry and any output amplifiers. The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. Supply Decoupling Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors. (See Figure 8.) Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of V AA should be individually decoupled to ground. This should be done by placing the ca- pacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. It is important to note that while the ADV101 contains circuitry to reject power supply noise, this rejection decreases with fre- quency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three-terminal voltage regulator. Digital Signal Interconnect The digital signal lines to the ADV101 should be isolated as much as possible from the analog outputs and other analog cir- cuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV101 should be avoided so as to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (V CC), and not the analog power plane. Analog Signal Interconnect The ADV101 should be located as close as possible to the out- put connectors thus minimizing noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV101 so as to minimize reflections. Additional information on PCB design is available in an applica- tion note entitled “Design and Layout of a Video Graphics Sys- tem for Reduced EMI.” This application note is available from Analog Devices, publication number E1309–15–10/89.

–12– REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Terminal Plastic Leaded Chip Carrier (P-44A) 40-Pin Plastic DIP (N-40A) C1380–24–4/90PRINTED IN U.S.A.