ADUUC7027BSTZ62-RL

ADUC7019 AD | Alldatasheet

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Technical content

Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI® MCU ADuC7019/20/21/22/24/25/26/27

FEATURES

Multichannel, 12-bit, 1 MSPS ADC Up to 16 ADC channels 1 Fully differential and single-ended modes 0 to VREF analog input range 12-bit voltage output DACs Up to 4 DAC outputs available1 On-chip voltage reference On-chip temperature sensor (±3°C) Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 44 MHz

41.78 MHz PLL with programmable divider

62 kB flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug Software triggered in-circuit reprogrammability On-chip peripherals UART, 2 × I2C® and SPI® serial I/O Up to 40-pin GPIO port1 4 × general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor Three-phase, 16-bit PWM generator1 Programmable logic array (PLA) External memory interface, up to 512 kB1 Power Specified for 3 V operation Active mode: 11 mA @ 5 MHz; 40 mA @ 41.78 MHz Packages and temperature range From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP1 Fully specified for –40°C to +125°C operation Tools Low-cost QuickStart™ development system Full third-party support

APPLICATIONS

Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking FUNCTIONAL BLOCK DIAGRAM 04955-001 1MSPS 12-BIT ADC DAC012-BIT DAC DAC112-BIT DAC DAC212-BIT DAC DAC312-BIT DAC PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L THREE- PHASE PWM EXT. MEMORY INTERFACE ADuC7026 ADC0 XCLKI XCLKO RST VREF ADC11 MUX TEMP SENSOR BANDGAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA

4 GENERAL

2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS Figure 1. 1 Depending on part model. See Ordering Guide for more information. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 2 of 92 TABLE OF CONTENTS

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 3 of 92

REVISION HISTORY

1/06—Rev. 0 to Rev. A 10/05—Revision 0: Initial Version

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 4 of 92 GENERAL DESCRIPTION The ADuC7019/7020/7021/7022/7024/7025/7026/7027 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporat- ing high performance multichannel ADCs, 16-bit/32-bit MCUs and Flash/EE memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional four inputs are available but are multiplexed with the four DAC output pins. The four DAC outputs are only available on certain models (ADuC7020, and ADuC7026). However, in many cases where the DAC outputs are not present, these pins can still be used as additional ADC inputs, giving a maximum of 16 ADC input channels. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 to V REF. Low-drift bandgap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. Depending on the part model, up to four buffered voltage output DACs are available on-chip. The DAC output range is programmable to one of three voltage ranges. The devices operate from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC machine, which offers up to 41 MIPS peak performance. Eight kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE memory are provided on-chip. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the UART or I 2C serial interface ports, while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart™ Development System supporting this MicroConverter® family. The parts operate from 2.7 V to 3.6 V and are specified over an industrial temperature range of −40°C to +125°C. When operating at 41.78 MHz, the power dissipation is typically 120 mW . The ADuC7019/7020/7021/7022/7024/7025/7026/7027 are available in a variety of memory models and packages.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 5 of 92 DETAILED BLOCK DIAGRAM 04955-002 77ADC0 78ADC1 79ADC2/CMP0 80ADC3/CMP1 1ADC4 2ADC5 3ADC6 4ADC7 5ADC8 6ADC9 7ADC10 76ADC11 9ADCNEG 20BM/P0.0/CMPOUT/PLAI[7]/MS2 68VREF VREF 18P4.6/AD14/PLAO[14] 19P4.7/AD15/PLAO[15] *SEE SELECTION TABLE FOR FEATURE AVAILABILITY ON DIFFERENT MODELS. P4.0/AD8/PLAO[8] P4.1/AD9/PLAO[9] P4.2/AD10/PLAO[10] P4.3/AD11/PLAO[11] P4.4/AD12/PLAO[12] P4.5/AD13/PLAO[13] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] TMS TDI TDO TCK P0.6/T1/MRST/PLAO[3]/AE P2.1/WS/PWM0H/PLAO[6] P2.2/RS/PWM0L/PLAO[7] P2.3/AE P2.4/PWM0H/MS0 P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 P2.7/PWM1L/MS3 P0.2/PWM2L/BHE P0.1/PWM2H/BLE P0.3/TRST/A16/ADCBUSY P2.0/SPM9/PLAO[5]/CONVSTART P1.7/SPM7/PLAO[0] MUX 12-BIT VOLTAGE OUTPUTDAC BUF 10 DAC0*/ADC12 12-BIT VOLTAGE OUTPUTDAC BUF 11 DAC1*/ADC13 12-BIT VOLTAGE OUTPUTDAC BUF 12 DAC2*/ADC14 12-BIT VOLTAGE OUTPUTDAC BUF 13 DAC3*/ADC15 29 P3.0/AD0/PWM0H/PLAI[8] 30 P3.1/AD1/PWM0L/PLAI[9] 31 P3.2/AD2/PWM1H/PLAI[10] 32 P3.3/AD3/PWM1L/PLAI[11] 38 P3.4/AD4/PWM2H/PLAI[12] 39 P3.5/AD5/PWM2L/PLAI[13] 46 P3.6/AD6/PWMTRIP/PLAI[14] 47 P3.7/AD7/PWMSYNC/PLAI[15]

44 XCLKO

45 XCLKI

40 IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 41 IRQ1/P0.5/ADCBUSY/PLAO[2]/MS0 43 P0.7/ECLK/XCLK/SPM8/PLAO[4] ADuC7026* DACREF DACGND DACVDD RST LVDD DGND IOVDD IOGND IOVDD IOGND AVDD AVDD REFGND AGND AGND

8 GNDREF

(31k × 16 BITS)

8192 BYTES USER RAM

(2k × 32 BITS) WAKEUP/ RTC TIMER POWER SUPPLY MONITOR PROG. CLOCK DIVIDER JTAG EMULATOR DOWNLOADER PROG. LOGIC ARRAY SPI/I2C SERIAL INTERFACE SERIAL PORT MULTIPLEXER UART SERIAL PORT POR INTERRUPT CONTROLLER 12-BIT SAR ADC 1MSPS ADC CONTROL PLL OSC BAND GAP REFERENCE CMPOUT/IRQMUXDAC TEMP SENSOR Figure 2.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 6 of 92 SPECIFICATIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and fADC/2 ADC Power-Up Time 5 μs DC Accuracy1, 2 Resolution 12 Bits Integral Nonlinearity ±0.6 ±1.0 ±1.5 LSB LSB

2.5 V internal reference

1.0 V external reference

Differential Nonlinearity3, 4 ±0.5 +0.7/−0.6 +1/−0.9 LSB LSB DC Code Distribution 1 LSB ADC input is a dc voltage ENDPOINT ERRORS5 Offset Error ±1 ±2 LSB Offset Error Match ±1 LSB Gain Error ±2 ±5 LSB Gain Error Match ±1 LSB DYNAMIC PERFORMANCE f IN = 10 kHz sine wave, fSAMPLE = 1 MSPS Signal-to-Noise Ratio (SNR) 69 dB Incl udes distortion and noise components Total Harmonic Distortion (THD) −78 dB Peak Harmonic or Spurious Noise −75 dB Channel-to-Channel Crosstalk −80 dB Measured on adjacent channels ANALOG INPUT Input Voltage Ranges Differential Mode VCM6 ±VREF/2 V Single-Ended Mode 0 to V REF V Leakage Current ±1 ±6 μA Input Capacitance 20 pF During ADC acquisition ON-CHIP VOLTAGE REFERENCE 0.47 μF from V REF to AGND Output Voltage 2.5 V Accuracy ±5 mV T A = 25°C Reference Temperature Coefficient ±40 ppm/°C Power Supply Rejection Ratio 75 dB Output Impedance 70 Ω TA = 25°C Internal VREF Power-On Time 1 ms EXTERNAL REFERENCE INPUT7 Input Voltage Range 0.625 AVDD V Input Impedance 65 kΩ DAC CHANNEL SPECIFICATIONS RL = 5 kΩ, CL = 100 pF DC ACCURACY8 Resolution 12 Bits Relative Accuracy ±2 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Offset Error ±15 mV 2.5 V internal reference Gain Error9 ±1 % Gain Error Mismatch 0.1 % % of full scale on DAC0

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 7 of 92 Parameter Min Typ Max Unit Test Conditions/Comments ANALOG OUTPUTS Output Voltage Range_0 0 to DACREF V DAC REF range: DACGND to DACVDD Output Voltage Range_1 0 to 2.5 V Output Voltage Range_2 0 to DACV DD V Output Impedance 2 Ω DAC AC CHARACTERISTICS Voltage Output Settling Time 10 μs Digital to Analog Glitch Energy ±20 nV-sec 1 LSB change at major carry COMPARATOR Input Offset Voltage ±15 mV Input Bias Current 1 μA Input Voltage Range AGND AV DD − 1.2 V Input Capacitance 7 pF Hysteresis4, 6 2 15 mV Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register Response Time 3 μs 100 mV overdrive and configured with CMPRES = 11 TEMPERATURE SENSOR Voltage Output at 25°C 780 mV Voltage TC −1.3 mV/°C Accuracy ±3 °C POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection 2.79 V Two selectable trip points 3.07 V Power Supply Trip Point Accuracy ±2.5 % Of the selected nominal trip point voltage POWER-ON RESET 2.36 V GLITCH IMMUNITY ON RESET PIN3 50 μs WATCHDOG TIMER ( WDT ) Timeout Period 0 512 sec FLASH/EE MEMORY Endurance10 10,000 cycles Data Retention11 20 years T J = 85°C DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO Logic 1 Input Current ±0.2 ±1 μA V IH = VDD or VIH = 5 V Logic 0 Input Current −40 −60 μA VIL = 0 V; except TDI on ADuC7019/20/21/22/24/25 −80 −120 μA V IL = 0 V; TDI, on ADuC7019/20/21/22/24/25 Input Capacitance 10 pF LOGIC INPUTS3 All logic inputs excluding XCLKI and XCLKO VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 2.0 V LOGIC OUTPUTS All digital outputs excluding XCLKI and XCLKO VOH, Output High Voltage 2.4 V I SOURCE = 1.6 mA VOL, Output Low Voltage12 0.4 V I SINK = 1.6 mA CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage 1.1 V VINH, Input High Voltage 1.7 V XCLKI Input Capacitance 20 pF XCLKO Output Capacitance 20 pF

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 8 of 92 Parameter Min Typ Max Unit Test Conditions/Comments INTERNAL OSCILLATOR 32.768 kHz ±3 % MCU CLOCK RATE From 32 kHz Internal Oscillator 326 kHz CD = 7 From 32 kHz External Crystal 41.78 MHz CD = 0 Using an External Clock 0.05 44 MHz T A = 85°C 0.05 41.78 MHz T A = 125°C START-UP TIME Core clock = 41.78 MHz At Power-On 130 ms From Pause/Nap Mode 24 ns CD = 0 3.06 μs CD = 7 From Sleep Mode 1.58 ms From Stop Mode 1.7 ms PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay 12 ns From input pin to output pin Element Propagation Delay 2.5 ns POWER REQUIREMENTS 13, 14 Power Supply Voltage Range AVDD − AGND and IOVDD − IOGND 2.7 3.6 V Analog Power Supply Currents AVDD Current 200 μA ADC in idle mode; all parts except ADuC7019 400 μA ADC in idle mode; ADuC7019 only DACVDD Current15 3 25 μA Digital Power Supply Current IOVDD Current in Normal Mode Code executing from Flash/EE 7 10 mA CD = 7 11 15 mA CD = 3 40 45 mA CD = 0 (41.78 MHz clock) IOVDD Current in Pause Mode 25 30 mA CD = 0 (41.78 MHz clock) IOVDD Current in Sleep Mode 250 400 μA T A = 85°C 600 1000 μA T A = 125°C Additional Power Supply Currents ADC 2 mA @ 1 MSPS 0.7 mA @ 62.5 kSPS DAC 700 μA per DAC 1 All ADC channel specifications are guaranteed during normal MicroConverter core operation. 2 Apply to all ADC input channels. 3 Measured using the factory set default values in ADCOF and ADCGN. 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory set default values in ADCOF and ADCGN using an external AD845 op amp as an input buffer stage as shown in Figure 47. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0. 8 DAC linearity is calculated using a reduced code range of 100 to 3995. 9 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 10 Endurance is qualified as per JEDEC Standard 22 method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 method A117. Retention lifetime derates with junction temperature. 12 Test carried out with a maximum of eight I/O set to a low output level. 13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: Normal Mode: 3.6 V supply, Pause Mode: 3.6 V supply, Sleep Mode: 3.6 V supply. 14 IOVDD power supply current decreases typically by 2 mA during a flash/EE erase cycle. 15 On the ADuC7019/20/21/22, this current must be added to AVDD current.

Table 2. External Memory Write Cycle Figure 3. External Memory Write Cycle

Table 3. External Memory Read Cycle Figure 4. External Memory Read Cycle

Table 4. I2C Timing in Fast Mode (400 kHz) 1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. Figure 5. I2C Compatible Interface Timing

Table 5. SPI Master Mode Timing (PHASE Mode = 1) 1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Figure 6. SPI Master Mode Timing (PHASE Mode = 1)

Table 6. SPI Master Mode Timing (PHASE Mode = 0) 1 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Figure 7. SPI Master Mode Timing (PHASE Mode = 0)

Table 7. SPI Slave Mode Timing (PHASE Mode = 1) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. 2 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. Figure 8. SPI Slave Mode Timing (PHASE Mode = 1)

Table 8. SPI Slave Mode Timing (PHASE Mode = 0) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. 2 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. Figure 9. SPI Slave Mode Timing (PHASE Mode = 0)

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 16 of 92 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GNDREF; TA = 25°C, unless otherwise noted. Table 9. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Parameter Rating AVDD to IOVDD −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V IOVDD to IOGND, AVDD to AGND −0.3 V to +6 V Digital Input Voltage to IOGND −0.3 V to +5.3 V Digital Output Voltage to IOGND −0.3 V to IOV DD + 0.3 V VREF to AGND −0.3 V to AV DD + 0.3 V Analog Inputs to AGND −0.3 V to AVDD + 0.3 V Analog Outputs to AGND −0.3 V to AV DD + 0.3 V Operating Temperature Range Industrial –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance (40-pin CSP) 26°C/W θJA Thermal Impedance (64-pin CSP) 24°C/W θJA Thermal Impedance (64-pin LQFP) 47°C/W θJA Thermal Impedance (80-pin LQFP) 38°C/W Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) 240°C Pb-Free Assemblies (20 sec to 40 sec) 260°C

Table 10. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022) 38 37 36 ADC0 Single-Ended or Differential Analog Input 0. 39 38 37 ADC1 Single-Ended or Differential Analog Input 1. 40 39 38 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input. ADuC7019)/Comparator Negative Input. 2 1 40 ADC4 Single-Ended or Differential Analog Input 4. ‒ 2 1 ADC5 Single-Ended or Differential Analog Input 5. ‒ 3 2 ADC6 Single-Ended or Differential Analog Input 6. ‒ 4 3 ADC7 Single-Ended or Differential Analog Input 7. ‒ ‒ 4 ADC8 Single-Ended or Differential Analog Input 8. ‒ ‒ 5 ADC9 Single-Ended or Differential Analog Input 9. analog power supply should be separated from IOGND and DGND. 4 6 ‒ DAC0/ADC12 DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. 5 7 ‒ DAC1/ADC13 DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. 6 ‒ ‒ DAC2/ADC14 DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. Differential Analog Input 15. 8 8 7 TMS Test Mode Select, JTAG Test Port Input. Debug and download access. 9 9 8 TDI Test Data In, JTAG Test Port Input. Debug and download access. 10 10 9 BM/P0.0/CMP OUT/PLAI[7] Multifunction I/O Pin. Comparator Output/Programmable Logic Array Input Element 7. 12 12 11 TCK Test Clock, JTAG Test Port Input. Debug and download access. 13 13 12 TDO Test Data Out, JTAG Test Port Output. Debug and download access. 14 14 13 IOGND Ground for GPIO. Typically connected to DGND. 15 15 14 IOV DD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. connected to a 0.47 μf capacitor to DGND only. 17 17 16 DGND Ground for Core Logic. Input/ ADCBUSY Signal Output. 19 19 18 RST Reset Input, Active Low. Input/Programmable Logic Array Output Element 1. Logic Array Output Element 2. Circuits/UART/ Programmable Logic Array Output Element 4. 24 24 23 XCLKO Output from the Crystal Oscillator Inverter.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 19 of 92 Pin No. 7019/7020 7021 7022 Mnemonic Description 25 25 24 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. 26 26 25 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. 27 27 26 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. 28 28 27 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. 29 29 28 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. 30 30 29 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. 31 31 30 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. 32 32 31 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. 33 33 32 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/ Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. 34 ‒ ‒ P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. 35 34 33 V REF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. 36 35 34 AGND Analog Ground. Ground reference point for the analog circuitry. 37 36 35 AV DD 3.3 V Analog Power.

42 IOV

41 IOGND

36 XCLKI

35 XCLKO

64 ADC3/CMP1

63 ADC2/CMP0

62 ADC1

61 ADC0

60 DACV

59 AV DD

58 AGND

57 DACGND

56 DAC

55 V REF

Figure 13. ADuC7024/ADuC7025 64-Lead LFCSP_VQ Pin Configuration Figure 14. ADuC7024/ADuC7025 64-Lead LQFP Pin Configuration

Table 11. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead CSP and ADuC7024/ADuC7025 64-Lead LQFP) 1 ADC4 Single-Ended or Differential Analog Input 4. 2 ADC5 Single-Ended or Differential Analog Input 5. 3 ADC6 Single-Ended or Differential Analog Input 6. 4 ADC7 Single-Ended or Differential Analog Input 7. 5 ADC8 Single-Ended or Differential Analog Input 8. 6 ADC9 Single-Ended or Differential Analog Input 9. should be separated from IOGND and DGND. to the ground of the signal to convert. This bias point must be between 0 V and 1 V. 11 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. 13 P4.6/PLAO[14] General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14. 14 P4.7/PLAO[15] General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15. and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. Input/Power-On Reset Output/Programmable Logic Array Output Element 3. 17 TCK JTAG Test Port Input, Test Clock. Debug and download access. 18 TDO JTAG Test Port Output, Test Data Out. Debug and download access. 19 IOGND Ground for GPIO. Typically connected to DGND. 20 IOV DD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 22 DGND Ground for Core Logic. Logic Array Input Element 8. Logic Array Input Element 9. Logic Array Input Element 10. Logic Array Input Element 11. 28 RST Reset Input, Active Low. Logic Array Input Element 13. Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2. Array Output Element 5/Start Conversion Input Signal for ADC. 35 XCLKO Output from the Crystal Oscillator Inverter.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 22 of 92 Pin No. Mnemonic Description 36 XCLKI Input to the Crystal Oscillator Inverter an d Input to the Internal Clock Generator Circuits. 37 P3.6/PWM TRIP/PLAI[14] General-Purpose Input and Output Port 3.6/PWM Safety Cut Off/Programmable Logic Array Input Element 14. 38 P3.7/PWM SYNC/PLAI[15] General-Purpose Input and Output Port 3.7/PWM Synchronization Input Output/Programmable Logic Array Input Element 15. 39 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. 40 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. 41 IOGND Ground for GPIO. Typically connected to DGND. 42 IOV DD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 43 P4.0/PLAO[8] General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8. 44 P4.1/PLAO[9] General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9. 45 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. 46 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. 47 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. 48 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. 49 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. 50 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. 51 P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. 52 P4.3/PLAO[11] General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11. 53 P4.4/PLAO[12] General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12. 54 P4.5/PLAO[13] General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13. 55 V REF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. 56 DAC REF External Voltage Reference for the DACs. Range: DACGND to DACV DD. 57 DACGND Ground for the DAC. Typically connected to AGND. 58 AGND Analog Ground. Ground reference point for the analog circuitry. 59 AV DD 3.3 V Analog Power. 60 DACV DD 3.3 V Power Supply for the DACs. Typically connected to AV DD. 61 ADC0 Single-Ended or Differential Analog Input 0. 62 ADC1 Single-Ended or Differential Analog Input 1. 63 ADC2/CMP0 Single-Ended or Differential An alog Input 2/Comparator Positive Input. 64 ADC3/CMP1 Single-Ended or Differential An alog Input 3/Comparator Negative Input.

54 IOV

53 IOGND

80 ADC3/CMP1

79 ADC2/CMP0

78 ADC1

77 ADC0

76 ADC11

75 DACV

74 AV DD

73 AV DD

72 AGND

71 AGND

70 DACGND

69 DAC

68 V REF

67 REFGND

Figure 15. ADuC7026/ADuC7027 80-Lead LQFP Pin Configuration Table 12. Pin Function Descriptions (ADuC7026/ADuC7027) 1 ADC4 Single-Ended or Differential Analog Input 4. 2 ADC5 Single-Ended or Differential Analog Input 5. 3 ADC6 Single-Ended or Differential Analog Input 6. 4 ADC7 Single-Ended or Differential Analog Input 7. 5 ADC8 Single-Ended or Differential Analog Input 8. 6 ADC9 Single-Ended or Differential Analog Input 9. 7 ADC10 Single-Ended or Differential Analog Input 10. should be separated from IOGND and DGND. to the ground of the signal to convert. This bias point must be between 0 V and 1 V.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 24 of 92 Pin No. Mnemonic Description 14 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. 15 TDI JTAG Test Port Input, Test Data In. Debug and download access. 16 P0.1/PWM2H/BLE General-Purpose Input and Output Port 0.1/ PWM Phase 2 High-Side Output/External Memory Byte Low Enable. 17 P2.3/AE General-Purpose Input and Output Po rt 2.3/External Memory Access Enable. 18 P4.6/AD14/PLAO[14] General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic Array Output Element 14. 19 P4.7/AD15/PLAO[15] General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic Array Output Element 15. 20 BM/P0.0/CMP OUT/PLAI[7]/MS2 Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if BM is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/ General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7/External Memory Select 2. 21 P0.6/T1/MRST/PLAO[3]/AE Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. 22 TCK JTAG Test Port Input, Test Clock. Debug and download access. 23 TDO JTAG Test Port Output, Test Data Out. Debug and download access. 24 P0.2/ PWM2L/BHE General-Purpose Input and Output Port 0.2/ PWM Phase 2 Low-Side Output/External Memory Byte High Enable. 25 IOGND Ground for GPIO. Typically connected to DGND. 26 IOV DD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 27 LV DD 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF capacitor to DGND only. 28 DGND Ground for Core Logic. 29 P3.0/AD0/PWM0 H/PLAI[8] General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 High- Side Output/Programmable Logic Array Input Element 8. 30 P3.1/AD1/PWM0 L/PLAI[9] General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 Low- Side Output/Programmable Logic Array Input Element 9. 31 P3.2/AD2/PWM1 H/PLAI[10] General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 High- Side Output/Programmable Logic Array Input Element 10. 32 P3.3/AD3/PWM1 L/PLAI[11] General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 Low- Side Output/Programmable Logic Array Input Element 11. 33 P2.4/PWM0 H/MS0 General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory Select 0. 34 P0.3/TRST/A16/ADC BUSY General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. 35 P2.5/PWM0 L/MS1 General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory Select 1. 36 P2.6/PWM1 H/MS2 General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory Select 2. 37 RST Reset Input, Active Low. 38 P3.4/AD4/PWM2 H/PLAI[12] General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 High- Side Output/Programmable Logic Array Input 12. 39 P3.5/AD5/PWM2 L/PLAI[13] General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 Low- Side Output/Programmable Logic Array Input Element 13. 40 IRQ0/P0.4/PWM TRIP/PLAO[1]/MS1 Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1/External Memory Select 1. 41 IRQ1/P0.5/ADC BUSY/PLAO[2]/MS0 Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2/External Memory Select 0. 42 P2.0/SPM9/PLAO[5]/CONVSTART Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 25 of 92 Pin No. Mnemonic Description 43 P0.7/ECLK/XCLK/SPM8/ PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output Element 4. 44 XCLKO Output from the Crystal Oscillator Inverter. 45 XCLKI Input to the Crystal Oscillator Inverter an d Input to the Internal Clock Generator Circuits. 46 P3.6/AD6/PWM TRIP/PLAI[14] General-Purpose Input and Output Port 3.6/External Memory Interface/PWM Safety Cut Off/Programmable Logic Array Input Element 14. 47 P3.7/AD7/PWM SYNC/PLAI[15] General-Purpose Input and Output Port 3.7/External Memory Interface/PWM Synchronization/Programmable Logic Array Input Element 15. 48 P2.7/PWM1 L/MS3 General-Purpose Input and Output Port 2.7/PWM Phase 1 Low-Side Output/External Memory Select 3. 49 P2.1/WS/PWM0H/PLAO[6] General-Purpose Input and Output Port 2.1/External Memory Write Strobe/PWM Phase 0 High-Side Output/Programmable Logic Array Output Element 6. 50 P2.2/RS/PWM0L/PLAO[7] General-Purpose Input and Output Port 2. 2/External Memory Read Strobe/PWM Phase 0 Low- Side Output/Programmable Logic Array Output Element 7. 51 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. 52 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. 53 IOGND Ground for GPIO. Typically connected to DGND. 54 IOV DD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 55 P4.0/AD8/PLAO[8] General-Purpose Input and Output Port 4.0/External Memory Interface/Programmable Logic Array Output Element 8. 56 P4.1/AD9/PLAO[9] General-Purpose Input and Output Port 4.1/External Memory Interface/Programmable Logic Array Output Element 9. 57 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. 58 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. 59 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. 60 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. 61 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. 62 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. 63 P4.2/AD10/PLAO[10] General-Purpose Input and Output Port 4.2/External Memory Interface/Programmable Logic Array Output Element 10. 64 P4.3/AD11/PLAO[11] General-Purpose Input and Output Port 4.3/External Memory Interface/Programmable Logic Array Output Element 11. 65 P4.4/AD12/PLAO[12] General-Purpose Input and Output Port 4.4/External Memory Interface/Programmable Logic Array Output Element 12. 66 P4.5/AD13/PLAO[13] General-Purpose Input and Output Port 4.5/External Memory Interface/Programmable Logic Array Output Element 13. 67 REFGND Ground for the Reference. Typically connected to AGND. 68 V REF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. 69 DAC REF External Voltage Reference for the DACs. Range: DACGND to DACV DD. 70 DACGND Ground for the DAC. Typically connected to AGND. 71, 72 AGND Analog Ground. Ground reference point for the analog circuitry. 73, 74 AV DD 3.3 V Analog Power.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 26 of 92 Pin No. Mnemonic Description 75 DACV DD 3.3 V Power Supply for the DACs. Typically connected to AV DD. 76 ADC11 Single-Ended or Differential Analog Input 11. 77 ADC0 Single-Ended or Differential Analog Input 0. 78 ADC1 Single-Ended or Differential Analog Input 1. 79 ADC2/CMP0 Single-Ended or Differential An alog Input 2/Comparator Positive Input. 80 ADC3/CMP1 Single-Ended or Differential An alog Input 3/Comparator Negative Input.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 30 of 92 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale − 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes for the output to settle to within a 1 LSB level for a full-scale input change.

the instruction word is 32 bits.

• T support for the thumb (16 bit) instruction set
• D support for debug
• M support for long multiplications
• I includes the embeddedICE module to support embedded system debugging THUMB MODE (T) An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16 bits, called the thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the thumb mode has two limitations:
• Thumb code usually uses more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of the time-critical code.
• The thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling. See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM thumb instruction sets. LONG MULTIPLY (M) The ARM7TDMI instruction set includes four extra instruc- tions that perform 32-bit by 32-bit multiplication with 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result. These results are achieved in fewer cycles than required on a standard ARM7 core. EMBEDDEDICE (I) EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE, the SRAM, and the memory mapped registers. EXCEPTIONS ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are:
• Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events.
• Fast interrupt or FIQ. This is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ.
• Memory abort.
• Attempted execution of an undefined instruction.
• Software interrupt instruction (SWI). This can be used to make a call to an operating system. Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ. ARM REGISTERS ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15) and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and for exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in

Figure 32. The fast interrupt mode has more registers (R8 to R12) for save critical time in the interrupt handling process.

Figure 32. Register Organization

• DDI0029G, ARM7TDMI Technical Reference Manual
• DDI0100E, ARM Architecture Reference Manual INTERRUPT LATENCY The worst case latency for a fast interrupt request (FIQ) consists of the following:
• The longest time the request can take to pass through the synchronizer
• The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC
• The time for the data abort entry
• The time for FIQ entry At the end of this time, the ARM7TDMI executes the instruc- tion at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 μs in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in thumb mode, where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.

Figure 33. Physical Memory Map

32 BITS

Figure 34. Little Endian Format executing from Flash/EE memory for optimum access speed. 41.78 MHz in thumb mode and 20.89 MHz in full ARM mode. from SRAM and Flash/EE section of this datasheet. addressing through the ARM7 banked registers.

Figure 35. Memory Mapped Registers Table 13. Complete MMR List

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 35 of 92 Address Name Byte Access Type Default Value Page ADC address base = 0xFFFF0500 0x0500 ADCCON 2 R/W 0x0600 39 0x0504 ADCCP 1 R/W 0x00 39 0x0508 ADCCN 1 R/W 0x01 40 0x050C ADCSTA 1 R 0x00 40 0x0510 ADCDAT 4 R 0x00000000 40 0x0514 ADCRST 1 R/W 0x00 40 0x0530 ADCGN 2 R/W 0x0200 40 0x0534 ADCOF 2 R/W 0x0200 40 DAC address base = 0xFFFF0600 0x0600 DAC0CON 1 R/W 0x00 48 0x0604 DAC0DAT 4 R/W 0x00000000 48 0x0608 DAC1CON 1 R/W 0x00 48 0x060C DAC1DAT 4 R/W 0x00000000 48 0x0610 DAC2CON 1 R/W 0x00 48 0x0614 DAC2DAT 4 R/W 0x00000000 48 0x0618 DAC3CON 1 R/W 0x00 48 0x061C DAC3DAT 4 R/W 0x00000000 48 UART base address = 0xFFFF0700 0x0700 COMTX 1 R/W 0x00 COMRX 1 R 0x00 63 COMDIV0 1 R/W 0x00 63 0x0704 COMIEN0 1 R/W 0x00 63 COMDIV1 1 R/W 0x00 63 0x0708 COMIID0 1 R 0x01 63 0x070C COMCON0 1 R/W 0x00 63 0x0710 COMCON1 1 R/W 0x00 64 0x0714 COMSTA0 1 R 0x60 64 0x0718 COMSTA1 1 R 0x00 64 0x071C COMSCR 1 R/W 0x00 64 0x0720 COMIEN1 1 R/W 0x04 65 0x0724 COMIID1 1 R 0x01 65 0x0728 COMADR 1 R/W 0xAA 65 0x072C COMDIV2 2 R/W 0x0000 64 Address Name Byte Access Type Default Value Page I2C0 base address = 0xFFFF0800 0x0800 I2C0MSTA 1 R 0x00 68 0x0804 I2C0SSTA 1 R 0x01 68 0x0808 I2C0SRX 1 R 0x00 69 0x080C I2C0STX 1 W 0x00 69 0x0810 I2C0MRX 1 R 0x00 69 0x0814 I2C0MTX 1 W 0x00 69 0x0818 I2C0CNT 1 R/W 0x00 69 0x081C I2C0ADR 1 R/W 0x00 69 0x0824 I2C0BYTE 1 R/W 0x00 69 0x0828 I2C0ALT 1 R/W 0x00 69 0x082C I2C0CFG 1 R/W 0x00 70 0x0830 I2C0DIV 2 R/W 0x1F1F 70 0x0838 I2C0ID0 1 R/W 0x00 70 0x083C I2C0ID1 1 R/W 0x00 70 0x0840 I2C0ID2 1 R/W 0x00 70 0x0844 I2C0ID3 1 R/W 0x00 70 0x0848 I2C0CCNT 1 R/W 0x01 70 0x084C I2C0FSTA 2 R 0x0000 71 I2C1 base address = 0xFFFF0900 0x0900 I2C1MSTA 1 R 0x00 68 0x0904 I2C1SSTA 1 R 0x01 68 0x0908 I2C1SRX 1 R 0x00 69 0x090C I2C1STX 1 W 0x00 69 0x0910 I2C1MRX 1 R 0x00 69 0x0914 I2C1MTX 1 W 0x00 69 0x0918 I2C1CNT 1 R/W 0x00 69 0x091C I2C1ADR 1 R/W 0x00 69 0x0924 I2C1BYTE 1 R/W 0x00 69 0x0928 I2C1ALT 1 R/W 0x00 69 0x092C I2C1CFG 1 R/W 0x00 69 0x0930 I2C1DIV 2 R/W 0x1F1F 70 0x0938 I2C1ID0 1 R/W 0x00 70 0x093C I2C1ID1 1 R/W 0x00 70 0x0940 I2C1ID2 1 R/W 0x00 70 0x0944 I2C1ID3 1 R/W 0x00 70 0x0948 I2C1CCNT 1 R/W 0x01 70 0x094C I2C1FSTA 2 R 0x0000 70 SPI base address = 0xFFFF0A00 0x0A00 SPISTA 1 R 0x00 0x0A04 SPIRX 1 R 0x00 66 0x0A08 SPITX 1 W 0x00 66 0x0A0C SPIDIV 1 R/W 0x1B 66 0x0A10 SPICON 2 R/W 0x0000 66

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 36 of 92 Address Name Byte Access Type Default Value Page PLA base address = 0xFFFF0B00 0x0B00 PLAELM0 2 R/W 0x0000 71 0x0B04 PLAELM1 2 R/W 0x0000 71 0x0B08 PLAELM2 2 R/W 0x0000 71 0x0B0C PLAELM3 2 R/W 0x0000 71 0x0B10 PLAELM4 2 R/W 0x0000 71 0x0B14 PLAELM5 2 R/W 0x0000 71 0x0B18 PLAELM6 2 R/W 0x0000 71 0x0B1C PLAELM7 2 R/W 0x0000 71 0x0B20 PLAELM8 2 R/W 0x0000 71 0x0B24 PLAELM9 2 R/W 0x0000 71 0x0B28 PLAELM10 2 R/W 0x0000 71 0x0B2C PLAELM11 2 R/W 0x0000 71 0x0B30 PLAELM12 2 R/W 0x0000 71 0x0B34 PLAELM13 2 R/W 0x0000 71 0x0B38 PLAELM14 2 R/W 0x0000 71 0x0B3C PLAELM15 2 R/W 0x0000 71 0x0B40 PLACLK 1 R/W 0x00 72 0x0B44 PLAIRQ 4 R/W 0x00000000 73 0x0B48 PLAADC 4 R/W 0x00000000 73 0x0B4C PLADIN 4 R/W 0x00000000 73 0x0B50 PLADOUT 4 R 0x00000000 73 0x0B54 PLALCK 1 W 0x00 73 External memory base address = 0xFFFFF000 0xF000 XMCFG 1 R/W 0x00 80 0xF010 XM0CON 1 R/W 0x00 80 0xF014 XM1CON 1 R/W 0x00 80 0xF018 XM2CON 1 R/W 0x00 80 0xF01C XM3CON 1 R/W 0x00 80 0xF020 XM0PAR 2 R/W 0x70FF 80 0xF024 XM1PAR 2 R/W 0x70FF 80 0xF028 XM2PAR 2 R/W 0x70FF 80 0xF02C XM3PAR 2 R/W 0x70FF 80 Address Name Byte Access Type Default Value Page GPIO base address = 0xFFFFF400 0xF400 GP0CON 4 R/W 0x00000000 60 0xF404 GP1CON 4 R/W 0x00000000 60 0xF408 GP2CON 4 R/W 0x00000000 60 0xF40C GP3CON 4 R/W 0x00000000 60 0xF410 GP4CON 4 R/W 0x00000000 60 0xF420 GP0DAT 4 R/W 0x000000XX 61 0xF424 GP0SET 4 W 0x000000XX 61 0xF428 GP0CLR 4 W 0x000000XX 61 0xF42C GP0PAR 4 W 0x20000000 61 0xF430 GP1DAT 4 R/W 0x000000XX 61 0xF434 GP1SET 4 W 0x000000XX 61 0xF438 GP1CLR 4 W 0x000000XX 61 0xF43C GP1PAR 4 W 0x00000000 61 0xF440 GP2DAT 4 R/W 0x000000XX 61 0xF444 GP2SET 4 W 0x000000XX 61 0xF448 GP2CLR 4 W 0x000000XX 61 0xF450 GP3DAT 4 R/W 0x000000XX 61 0xF454 GP3SET 4 W 0x000000XX 61 0xF458 GP3CLR 4 W 0x000000XX 61 0xF45C GP3PAR 4 W 0x00222222 61 0xF460 GP4DAT 4 R/W 0x000000XX 61 0xF464 GP4SET 4 W 0x000000XX 61 0xF468 GP4CLR 4 W 0x000000XX 61 Flash/EE base address = 0xFFFFF800 0xF800 FEESTA 1 R 0x20 45 0xF804 FEEMOD 2 R/W 0x0000 45 0xF808 FEECON 1 R/W 0x07 45 0xF80C FEEDAT 2 R/W 0xXXXX 45 0xF810 FEEADR 2 R/W 0x0000 45 0xF818 FEESIGN 3 R 0xFFFFFF 45 0xF81C FEEPRO 4 R/W 0x00000000 45 0xF820 FEEHIDE 4 R/W 0xFFFFFFFF 45 PWM base address = 0xFFFFFC00 0xFC00 PWMCON 2 R/W 0x0000 0xFC04 PWMSTA 2 R/W 0x0000 59 0xFC08 PWMDAT0 2 R/W 0x0000 60 0xFC0C PWMDAT1 2 R/W 0x0000 60 0xFC10 PWMCFG 2 R/W 0x0000 59 0xFC14 PWMCH0 2 R/W 0x0000 60 0xFC18 PWMCH1 2 R/W 0x0000 60 0xFC1C PWMCH2 2 R/W 0x0000 60 0xFC20 PWMEN 2 R/W 0x0000 59 0xFC24 PWMDAT2 2 R/W 0x0000 60

• Fully differential mode, for small and balanced signals
• Single-ended mode, for any single-ended signals
• Pseudo differential mode, for any single-ended signals, taking advantage of the common-mode rejection offered by the pseudo differential input The converter accepts an analog input range of 0 to V REF when operating in single-ended mode or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage VCM, in the range 0 V to AVDD, and with a maximum amplitude of 2 VREF (see Figure 36). 04955-011 AVDD VCM VCM VCM 2VREF 2VREF 2VREF

Figure 36. Examples of Balanced Signals in Fully Differential Mode connected as described later in the Band Gap Reference section. used to generate a repetitive trigger for ADC conversions.

1 LSB = FS/4096, or

Figure 37. ADC Transfer Function in Pseudo Differential Mode (see the Driving the Analog Inputs section). characteristic is shown in Figure 38.

Table 14. ADCCON MMR Bit Designations 1 MSPS ADC with an external clock <41.78 MHz. 10 8 clocks (default value). stop the ADC when continuously converting). Set by the user to enable the ADCBUSY pin. Cleared by the user to disable the ADCBUSY pin. user to place the ADC in power-down mode. 10 Pseudo differential mode. 000 Enable CONVSTART pin as a conversion input. 001 Enable Timer1 as a conversion input. 010 Enable Timer0 as a conversion input.

011 Single software conversion; sets to 000 after

100 Continuous software conversion. MMR is described in Table 15. Table 15. ADCCP1 MMR Bit Designation

00000 ADC0

00001 ADC1

00010 ADC2

00011 ADC3

00100 ADC4

00101 ADC5

00110 ADC6

00111 ADC7

01000 ADC8

01001 ADC9

01010 ADC10

01011 ADC11

01100 DAC0/ADC12

01101 DAC1/ADC13

01110 DAC2/ADC14

01111 DAC3/ADC15

10000 Temperature sensor

10001 AGND (self-diagnostic feature)

10010 Internal reference (self-diagnostic feature)

10011 AV DD/2

MMR is described in Table 16. Table 16. ADCCN MMR Bit Designation

10000 Internal reference (self-diagnostic feature)

one bit, ADCReady (Bit 0), representing the status of the ADC. section) if enabled in the ADCCON register. ADCGN is a 10-bit gain calibration register. ADCOF is a 10-bit offset calibration register. pseudo differential, and single-ended. arrays acquire the differential signal on the input. Figure 42. ADC Acquisition Phase

VCM min and VCM max for some conditions. Table 17. VCM Ranges with a range of ±3% of VREF. allows an external reference input on the VREF pin. REFCON described in Table 18. Table 18. REFCON MMR Bit Designations the reference from the VREF pin.

and more correctly referred to as Flash/EE memory. time programmable (OTP) devices at remote operating nodes. embedded firmware is hidden from user code. cycling endurance and Flash/EE memory data retention.

1. Initial page erase sequence.
2. Read/verify sequence a single Flash/EE.
3. Byte program sequence memory.
4. Second read/verify sequence endurance cycle.

endurance figure over supply temperature of 10,000 cycles. described previously, before data retention is characterized. Figure 49. Flash/EE Memory Data Retention using the serial download mode or the JTAG mode provided.

possible to walk zeros only byte wise. is, 2 kB. Write protection is activated for all types of access.

• Protection can be set and removed by writing directly into FEEHIDE MMR. This protection does not remain after reset.
• Protection can be set by writing into FEEPRO MMR. It only takes effect after a save protection command (0×0C) and a reset. The FEEPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEEPRO. A mass erase sets the key back to 0×FFFF but also erases all the user code.
• Flash can be permanently protected by using the FEEPRO MMR and a particular value of key: 0×DEADDEAD. Entering the key again to modify the FEEPRO register is not allowed. Sequence to Write the Key 1. Write the bit in FEEPRO corresponding to the page to be protected. 2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5 must equal 0). 3. Write a 32-bit key in FEEADR, FEEDAT. 4. Run the write key command 0×0C in FEECON; wait for the read to be successful by monitoring FEESTA. 5. Reset the part. To remove or modify the protection, the same sequence is used with a modified value of FEEPRO. If the key chosen is the value 0×DEAD, then the memory protection cannot be removed. Only a mass erase unprotects the part, but it also erases all user code. The sequence to write the key is illustrated in the following example (this protects writing Pages 4 to 7 of the Flash): FEEPRO=0xFFFFFFFD; //Protect pages 4 to 7 FEEMOD=0x48; //Write key enable FEEADR=0x1234; //16 bit key value FEEDAT=0x5678; //16 bit key value FEECON= 0x0C; // Write key command The same sequence should be followed to protect the part permanently with FEEADR = 0×DEAD and FEEDAT = 0×DEAD. FLASH/EE CONTROL INTERFACE Serial, parallel, and JTAG programming use the Flash/EE control interface, which includes eight MMRs outlined in this section. FEESTA Register Name Address Default Value Access FEESTA 0xFFFFF800 0x20 R FEESTA is a read-only register that reflects the status of the flash control interface as described in Table 19.

Table 19. FEESTA MMR Bit Designations register is set. Cleared when reading FEESTA register. automatically when reading FEESTA register. FEEMOD sets the operating mode of the flash control interface. Table 20 shows FEEMOD MMR bit designations. Table 20. FEEMOD MMR Bit Designations 8 Reserved. This bit should always be set to 0. protect the Flash against erase/write command. 2:0 Reserved. These bits should always be set to 0.

Table 21. Command Codes in FEECON 0x011 Single Read Load FEEDAT with the 16-bit data. FEEADR. This operation takes 20 μs. FEEADR. This operation takes 20 ms. 0x051 Single Erase Erase the page indexed by FEEADR. 0x07 Burst Read Default Command. No write is allowed. This operation takes two cycles. 16 bits and takes a maximum of 8 x 20 μs. operation takes 32,778 clock cycles. only with a mass erase (0x06) or the key. 0x0F Ping No operation; interrupt generated.

1 The FEECON register always reads 0x07 immediately after execution of any

FEEDAT is a 16-bit data register. FEEADR is another 16-bit address register. FEESIGN is a 24-bit code signature. require any software keys, see Table 22. Table 22. FEEPRO and FEEHIDE MMR Bit Designations 31 Read Protection. Cleared by user to protect all code. Set by user to allow reading the code. writing. Set by user to allow writing the pages.

two cycles to fill the pipeline with the new instructions. Table 23. Execution Cycles in ARM/Thumb Mode

1 The SWAP instruction combines an LD and STR instruction with only one

fetch, giving a total of eight cycles plus 40 μs.

2 N is the number of data to load or store in the multiple load/store instruction

0x00000020 as shown in Figure 50. Figure 50. Remap for Exception Execution 32-bit wide instead of 16-bit wide Flash/EE memory. 0x00000000, to execute the user’s reset exception routine. from the bottom of the array as this is replaced by the SRAM. address 0x00000000 by clearing Bit 0 of the REMAP MMR. Flash/EE memory at the bottom of the array.

exception service routine to identify the source of the reset. If RSTSTA is null, the reset is external. Table 24. REMAP MMR Bit Designations only 32 kB of Flash/EE memory is available. Table 25. RSTSTA MMR Bit Designations 2 Software Reset. Set by user to force a software reset. Cleared by setting the corresponding bit in RSTCLR. corresponding bit in RSTCLR.

output buffer capable of driving 5 kΩ/100 pF. band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD. DACREF is equivalent to an external reference for the DAC. The signal range is 0 V to AVDD. (see Table 27) are described in detail in this section. Table 26. DAC0CON MMR Bit Designations update the DAC using Timer1. 3 Reserved. This bit should be left at 0. 2 Reserved. This bit should be left at 0. Table 27. DAC0DAT MMR Bit Designations equivalent of which is shown in Figure 51. Figure 51. DAC Structure user selectable in software. It can be either AVDD, VREF, or DACREF. function spans from 0 V to the internal 2.5 V reference, VREF. DD mode only, codes 3995 to 4095.

be on an external pin, CMPOUT, as shown in Figure 53. Figure 53. Comparator between the center of the hysteresis range and the ground level. (VH) is ½ the width of the hysteresis range. Figure 54. Comparator Hysteresis Transfer Function which is described in Table 29. Table 29. CMPCON MMR Bit Descriptions by user to disable the comparator. 5 CMPOL Comparator Output Logic State Bit. above the negative input (CMP1). signals (2.5 V differential). signals (0.65 mV differential).

1 CMPORI Comparator Output Rising Edge

user by writing a 1 to this bit.

0 CMPOFI Comparator Output Falling Edge

voltage (CMP0). Cleared by user.

clock frequency and the power-down mode. Table 32. PLLCON MMR Bit Designations user to use the external 32 kHz crystal. 01 PLL. Default configuration. 11 External Clock on P0.7 Pin. Table 33. POWCON MMR Bit Designations 2:0 CD CPU Clock Divider Bits. Table 34. PLLCON and POWCON Write Sequence

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 53 of 92 DIGITAL PERIPHERALS THREE-PHASE PWM Each ADuC7019/7020/7021/7022/7024/7025/7026/7027 provides a flexible and programmable, three-phase pulse-width modulation (PWM) waveform generator. It can be programmed to generate the required switching patterns to drive a three- phase voltage source inverter for ac induction motor control (ACIM). Note that only active high patterns can be produced. The PWM generator produces three pairs of PWM signals on the six PWM output pins (PWM0H, PWM0L, PWM1H, PWM1L, PWM2H, and PWM2L). The six PWM output signals consist of three high-side drive signals and three low-side drive signals. The switching frequency and dead time of the generated PWM patterns are programmable using the PWMDAT0 and PWMDAT1 MMRs. In addition, three duty-cycle control registers (PWMCH0, PWMCH1, and PWMCH2) directly control the duty cycles of the three pairs of PWM signals. Each of the six PWM output signals can be enabled or disabled by separate output enable bits of the PWMEN register. In addition, three control bits of the PWMEN register permit crossover of the two signals of a PWM pair. In crossover mode, the PWM signal destined for the high-side switch is diverted to the comple- mentary low-side output. The signal destined for the low-side switch is diverted to the corresponding high-side output signal. In many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. In general, there are two common isolation techniques, optical isolation using opto-couplers, and transformer isolation using pulse transformers. The PWM controller permits mixing of the output PWM signals with a high frequency chopping signal to permit easy interface to such pulse transformers. The features of this gate-drive chopping mode can be controlled by the PWMCFG register. An 8-bit value within the PWMCFG register directly controls the chopping frequency. High frequency chopping can be independently enabled for the high-side and low-side outputs using separate control bits in the PWMCFG register. The PWM generator can operate in one of two distinct modes, single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period, so that the resulting PWM patterns are symmetrical about the midpoint of the PWM period. In the double update mode, a second updating of the PWM duty cycle values is implemented at the midpoint of the PWM period. In double update mode, it is also possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. This technique permits closed-loop controllers to change the average voltage applied to the machine windings at a faster rate. As a result, faster closed-loop bandwidths are achieved. The operating mode of the PWM block is selected by a control bit in the PWMCON register. In single update mode, a PWMSYNC pulse is produced at the start of each PWM period. In double update mode, an additional PWMSYNC pulse is produced at the midpoint of each PWM period. The PWM block can also provide an internal synchronization pulse on the PWM SYNC pin that is synchronized to the PWM switching frequency. In single update mode, a pulse is produced at the start of each PWM period. In double update mode, an additional pulse is produced at the mid-point of each PWM period. The width of the pulse is programmable through the PWMDAT2 register. The PWM block can also accept an external synchronization pulse on the PWM SYNC pin. The selection of external synchronization or internal synchronization is in the PWMCON register. The SYNC input timing can be synchronized to the internal peripheral clock, which is selected in the PWMCON register. If the external synchronization pulse from the chip pin is asynchronous to the internal peripheral clock (typical case), the external PWMSYNC is considered asynchronous and should be synchronized. The synchronization logic adds latency and jitter from the external pulse to the actual PWM outputs. The size of the pulse on the PWM SYNC pin must be greater than two core clock periods. The PWM signals produced by the ADuC7019/7020/7021/ 7022/7024/7025/7026/7027 can be shut off via a dedicated asynchronous PWM shutdown pin, PWMTRIP. When brought low, PWMTRIP instantaneously places all six PWM outputs in the off state (high). This hardware shutdown mechanism is asynchronous so that the associated PWM disable circuitry does not go through any clocked logic. This ensures correct PWM shutdown even in the event of a core clock loss. Status information about the PWM system is available to the user in the PWMSTA register. In particular, the state of the PWMTRIP pin is available, as well as a status bit that indicates whether operation is in the first half or the second half of the PWM period.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 55 of 92 Three-Phase Timing Unit PWM Switching Frequency (PWMDAT0 MMR) The PWM switching frequency is controlled by the PWM period register, PWMDAT0. The fundamental timing unit of the PWM controller is tCORE = 1/fCORE where fCORE is the core frequency of the MicroConverter. Therefore, for a 41.78 MHz fCORE, the fundamental time increment is 24 ns. The value written to the PWMDAT0 register is effectively the number of fCORE clock increments in ½ a PWM period. The required PWMDAT0 value is a function of the desired PWM switching frequency (fPWN) and is given by PWMDAT0 = fCORE/(2 × fPWM) Therefore, the PWM switching period, TS, can be written as TS = 2 × PWMDAT0 × tCORE The largest value that can be written to the 16-bit PWMDAT0 MMR is 0×FFFF = 65535, which corresponds to a minimum PWM switching frequency of fPWM(min) = 41.78 × 106/(2 × 65535) = 318.75 Hz Note that a PWMDAT0 value of 0 and 1 are not defined and should not be used. PWM Switching Dead Time (PWMDAT1 MMR) The second important parameter that must be set up in the initial configuration of the PWM block is the switching dead time. This is a short delay time introduced between turning off one PWM signal (0H, for example) and turning on the complementary signal (0L). This short time delay is introduced to permit the power switch to be turned off (in this case, 0H) to completely recover its blocking capability before the complementary switch is turned on. This time delay prevents a potentially destructive short-circuit condition from developing across the dc link capacitor of a typical voltage source inverter. The dead time is controlled by the 10-bit, read/write PWMDAT1 register. There is only one dead-time register that controls the dead time inserted into all three pairs of PWM output signals. The dead time, TD, is related to the value in the PWMDAT1 register by: TD = PWMDAT1 × 2 × t CORE Therefore, a PWMDAT1 value of 0x00A (= 10), introduces a 426 ns delay between the turn-off on any PWM signal (0H, for example) and the turn-on of its complementary signal (0L). The amount of the dead time can therefore be programmed in increments of 2t CORE (or 49 ns for a 41.78 MHz core clock). The PWMDAT1 register is a 10-bit register with a maximum value of 0x3FF (= 1023), which corresponds to a maximum programmed dead time of TD(max) = 1023 × 2 × tCORE = 1023 × 2 × 24 ×10–9 = 48.97 μs for a core clock of 41.78 MHz Obviously, the dead time can be programmed to be zero by writing 0 to the PWMDAT1 register. PWM Operating Mode (PWMCON, PWMSTA MMRs) As previously discussed, the PWM controller of the ADuC7019/7020/7021/7022/7024/7025/7026/7027 can operate in two distinct modes, single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 2 of the PWMCON register. If this bit is cleared, the PWM operates in the single update mode. Setting Bit 2 places the PWM in the double update mode. The default operating mode is single update mode. In single update mode, a single PWMSYNC pulse is produced in each PWM period. The rising edge of this signal marks the start of a new PWM cycle, and is used to latch new values from the PWM configuration registers (PWMDAT0 and PWMDAT1) and the PWM duty cycle registers (PWMCH0, PWMCH1, and PWMCH2) into the three-phase timing unit. In addition, the PWMEN register is latched into the output control unit on the rising edge of the PWMSYNC pulse. In effect, this means that the characteristics and resulting duty cycles of the PWM signals can be updated only once per PWM period at the start of each cycle. The result is symmetrical PWM patterns about the midpoint of the switching period. In double update mode, there is an additional PWMSYNC pulse produced at the midpoint of each PWM period. The rising edge of this new PWMSYNC pulse is again used to latch new values of the PWM configuration registers, duty cycle registers, and the PWMEN register. As a result, it is possible to alter both the characteristics (switching frequency and dead time) as well as the output duty cycles at the midpoint of each PWM cycle. Consequently, it is also possible to produce PWM switching patterns that are no longer symmetrical about the midpoint of the period (asymmetrical PWM patterns). In double update mode, it may be necessary to know whether operation at any point in time is in either the first half or the second half of the PWM cycle. This information is provided by Bit 0 of the PWMSTA register, which is cleared during operation in the first half of each PWM period (between the rising edge of the original PWMSYNC pulse and the rising edge of the new PWMSYNC pulse introduced in double update mode). Bit 0 of the PWMSTA register is set during operation in the second half of each PWM period. This status bit allows the user to make a determination of the particular half-cycle during implementation of the PWMSYNC interrupt service routine, if required.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 57 of 92 In general, the on-times of the PWM signals in double update mode can be defined as follows: On the high side T0HH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 + PWMCH02 − PWMDAT11 − PWMDAT12) × tCORE T0HL = (PWMDAT01/2 + PWMDAT02/2 − PWMCH01 − PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE where the subscript 1 refers to the value of that register during the first half cycle, and the subscript 2 refers to the value during the second half cycle. The corresponding duty cycles (d) are d0H = T0HH/TS = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 + PWMCH02 − PWMDAT11 − PWMDAT12)/ (PWMDAT01+ PWMDAT02) On the low side T0LH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 + PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE T0LL = (PWMDAT01/2 + PWMDAT02/2 − PWMCH01 − PWMCH02 − PWMDAT11 − PWMDAT12) × tCORE where the subscript 1 refers to the value of that register during the first half cycle, and the subscript 2 refers to the value during the second half cycle. The corresponding duty cycles (d) are d0L = T0LH/TS = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 + PWMCH02 + PWMDAT11 + PWMDAT12)/(PWMDAT01 + PWMDAT02) For the completely general case in double update mode (see Figure 58), the switching period is given by TS = (PWMDAT01 + PWMDAT02) × tCORE Again, the values of T0H and T0L are constrained to lie between zero and TS. PWM signals similar to those illustrated in Figure 57 and Figure 58 can be produced on the 1H, 1L, 2H, and 2L outputs by programming the PWMCH1 and PWMCH2 registers in a manner identical to that described for PWMCH0. The PWM controller does not produce any PWM outputs until all of the PWMDAT0, PWMCH0, PWMCH1, and PWMCH2 registers have been written to at least once. Once these registers have been written, internal counting of the timers in the three-phase timing unit is enabled. Writing to the PWMDAT0 register starts the internal timing of the main PWM timer. Provided that the PWMDAT0 register is written to prior to the PWMCH0, PWMCH1, and PWMCH2 registers in the initialization, the first PWMSYNC pulse and interrupt (if enabled) appear 1.5 × t CORE × PWMDAT0 seconds after the initial write to the PWMDAT0 register in single update mode. In double update mode, the first PWMSYNC pulse appears after PWMDAT0 × tCORE seconds. Output Control Unit The operation of the output control unit is controlled by the 9-bit read/write PWMEN register. This register controls two distinct features of the output control unit that are directly useful in the control of electronic counter measures (ECM) or binary decimal counter measures (BDCM). The PWMEN register contains three crossover bits, one for each pair of PWM outputs. Setting Bit 8 of the PWMEN register enables the crossover mode for the 0H/0L pair of PWM signals, setting Bit 7 enables crossover on the 1H/1L pair of PWM signals, and setting Bit 6 enables crossover on the 2H/2L pair of PWM signals. If crossover mode is enabled for any pair of PWM signals, the high-side PWM signal from the timing unit (0H, for example) is diverted to the associated low-side output of the output control unit so that the signal ultimately appears at the PWM0 L pin. Of course, the corresponding low-side output of the timing unit is also diverted to the complementary high-side output of the output control unit so that the signal appears at the PWM0H pin. Following a reset, the three crossover bits are cleared and the crossover mode is disabled on all three pairs of PWM signals. The PWMEN register also contains 6 bits (Bit 0 to Bit 5) that can be used to individually enable or disable each of the six PWM outputs. If the associated bit of the PWMEN register is set, the corresponding PWM output is disabled regardless of corresponding value of the duty cycle register. This PWM output signal remains in the off state as long as the corresponding enable/disable bit of the PWMEN register is set. The implementation of this output enable function is implemented after the crossover function. Following a reset, all six enable bits of the PWMEN register are cleared, and all PWM outputs are enabled by default. In a manner identical to the duty cycle registers, the PWMEN is latched on the rising edge of the PWMSYNC signal. As a result, changes to this register only become effective at the start of each PWM cycle in single update mode. In double update mode, the PWMEN register can also be updated at the midpoint of the PWM cycle. In the control of an ECM, only two inverter legs are switched at any time, and often the high-side device in one leg must be switched on at the same time as the low-side driver in a second leg. Therefore, by programming identical duty cycle values for two PWM channels (for example, PWMCH0 = PWMCH1) and setting Bit 7 of the PWMEN register to cross over the 1H/1L pair of PWM signals, it is possible to turn on the high-side switch of Phase A and the low-side switch of Phase B at the same time. In the control of ECM, it is usual for the third inverter leg (Phase C in this example) to be disabled for a number of PWM cycles. This function is implemented by disabling both the 2H and 2L PWM outputs by setting Bit 0 and Bit 1 of the PWMEN register.

Table 35. PWMCON MMR Bit Descriptions sync. Cleared to use internal sync. external synchronous sync signal. Cleared for asynchronous sync signal. to enable double update mode. by user to disable synchronization. cleared automatically with PWMTRIP. PWMSTA reflects the status of the PWM. Table 36. PWMSTA MMR Bit Descriptions 9 PWMSYNCINT PWM Sync Interrupt Bit. 8 PWMTRIPINT PWM Trip Interrupt Bit. 3 PWMTRIP Raw Signal from the PWM TRIP Pin. PWMCFG is a gate chopping register. Table 37. PWMCFG MMR Bit Descriptions 9 CHOPLO Low-side gate chopping enable bit. 8 CHOPHI High-side gate chopping enable bit. 7:0 GDCLK PWM gate chopping period (unsigned). bit definitions in Table 38. Table 38. PWMEN MMR Bit Descriptions

PWMDAT0 is an unsigned 16-bit register for switching period. PWMDAT1 is an unsigned 10-bit register for dead time. default, the GPIO pins are configured in GPIO mode. be reconfigured in GP0CON MMR. mode than GPIO. The PLA input are also always active. Table 39. GPIO Pin Function Descriptions 1 When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To configure it as a clock input, MDCLK bits in PLLCON must be set to 11. 2 The CONVSTART signal is active in all modes of P2.0.

function of each pin of port x. as described in Table 40. Table 40. GPxCON MMR Bit Descriptions GPxPAR program the parameters for Port 0, Port 1, and Port 3. Table 41. GPxPAR MMR Bit Descriptions input value of the pins configured as input. Table 42. GPxDAT MMR Bit Descriptions configure the GPIO pin as an input. 15:8 Reflect the State of Port x Pins at Reset (read only). 7:0 Port x Data Input (read only). GPxSET are data set port x registers. Table 43. GPxSET MMR Bit Descriptions MMR. Cleared to 0 by user; does not affect the data out. GPxCLR are data clear port x registers. Table 44. GPxCLR MMR Bit Descriptions

one of its specific I/O functions as described in Table 45. Table 45. SPM Configuration Table 46. UART Signal Description generation options selectable in the configuration register. There are two ways of generating the UART baud rate.

1. Normal 450 UART Baud Rate Generation.

value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL). Table 47 gives some common baud rate values. Table 47. Baud Rate Using the Normal Baud Rate Generator

1. Using the Fractional Divider.

generator produces a wider range of more accurate baud rates. Figure 61. Baud Rate Generation Options

COMTX is an 8-bit transmit register. COMRX is an 8-bit receive register. COMIEN0 is the interrupt enable register. Table 48. COMIEN0 MMR Bit Descriptions any of COMSTA1[3:0] are set. Cleared by user. COMSTA0[3:0] are set. Cleared by user. empty during a transmission. Cleared by user. during a reception. Cleared by user. COMDIV1 is a divisor latch (high byte) register. COMIID0 is the interrupt identification register. Table 49. COMIID0 MMR Bit Descriptions COMCON0 is the line control register. Table 50. COMCON0 MMR Bit Descriptions access to COMDIV0 and COMDIV1 registers. 6 BRK Set Break. Set by user to force SOUT to 0. Cleared to operate in normal mode. 4 EPS Even Parity Select Bit. Set for even parity. parity transmission or checking. generate 1 stop bit in the transmitted data.

COMCON1 is the modem control register. Table 51. COMCON1 MMR Bit Descriptions for no parity transmission or checking. COMSTA0 is the line status register. Table 52. COMSTA0 MMR Bit Descriptions cally when one of the register receives data. the maximum word length. Cleared automatically. 2 PE Parity Error. Set when a parity error occurs. written before being read. Cleared automatically. full. Cleared by reading COMRX. COMSTA1 is a modem status register. Table 53. COMSTA1 MMR Bit Descriptions storage. It is also used in network addressable UART mode. COMDIV2 is a 16-bit fractional baud divide register. Table 54. COMDIV2 MMR Bit Descriptions 15 FBEN Fractional Baud Rate Generator Enable Bit.

no parity check in this mode; the parity bit is used for address. COMADR are only used in network addressable UART mode. scratch register is the transmitted network address control bit. the device is transmitting data. COMIEN1 is an 8-bit network enable register. Table 55. COMIEN1 MMR Bit Descriptions user to disable network address mode. user to disable 9-bit transmit. user to disable 9-bit receive. 4 ENI Network Interrupt Enable Bit. cleared. Cleared for 8-bit data. 1 NABP Network Address Bit. Interrupt polarity bit. slave’s address. Cleared by user to transmit data. are reserved (see Table 56). Table 56. COMIID1 MMR Bit Descriptions processor and/or sets the appropriate status bit in COMIID1.

3.48 Mb as shown in

Table 57. The SPI interface is not and typically consists of four pins: MISO, MOSI, SCL, and CS.

being transmitted and received through the MOSI SCL period. and as an input in slave mode. divider bits and is summarized in Table 57. Table 57. SPI Speed vs. Clock Divider Bits in Master Mode accepts data from an external master up to 10.4 Mb at CD = 0. for the master and slave devices. deassertion of CS. In slave mode, CS is always an input. interface: SPISTA, SPIRX, SPITX, SPIDIV , and SPICON. register determines which bit generates the interrupt. Table 58. SPISTA MMR Bit Descriptions overflowing. Cleared by reading SPIRX register. is set. Cleared by reading SPIRX register. finished transmission disabling the SPI. data. Cleared when SPITX is empty. SPIRX is an 8-bit read-only receive register. SPITX is an 8-bit write-only transmit register. SPIDIV is an 8-bit serial clock divider register. SPICON is a 16-bit control register.

Table 59. SPICON MMR Bit Descriptions is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty. SPITX register, then a new transfer is initiated after a stall period. 11 Loop Back Enable. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. 10 Slave Output Enable. Set by user to enable the slave output. Cleared by user to disable slave output. 9 Slave Select Input Enable. Set by user in master mode to enable the output. Cleared by user to disable master output. 8 SPIRX Overflow Overwrite Enable. Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by user, the new serial byte received is discarded. 7 SPITX Underflow Mode. Set by user to transmit 0. Cleared by user to transmit the previous data. empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when RX is full. 5 LSB First Transfer Enable Bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first. 3 Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low. serial clock pulses at the end of each serial bit transfer. 1 Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode. 0 SPI Enable Bit. Set by user to enable the SPI. Cleared by user to disable the SPI. individual interrupts. See the Interrupt System section. to respond to four slave addresses. arbitration, to respond as a slave in the same cycle. fast mode (400 kHz) or standard mode (100 kHz). fUCLK = clock before the clock divider. DIVH = the high period of the clock. DIVL = the low period of the clock. The I2C×DIV register corresponds to DIVH:DIVL. bit, is ignored in the process of address recognition.

I2CxMSTA are status registers for the master channel. Table 60. I2C0MSTA MMR Bit Descriptions flushed. This bit also flushes the slave receive FIFO. has the bus. Cleared when the bus becomes available. reading the I2C0MSTA register. automatically by reading the I2C0MRX register. 2 Master Transmit IRQ. Set at the end of a transmission. Cleared automatically by writing to the I2C0MTX register. automatically by writing to the I2C0MTX register. I2CxSSTA are status registers for the slave channel. Table 61. I2C0SSTA MMR Bit Descriptions 31:15 Reserved. These bits should be written as 0. or an I2C general call reset. or an I2C general call reset. 00 Received Address Natched ID Register 0. 01 Received Address Matched ID Register 1. 10 Received Address Matched ID Register 2. 11 Received Address Matched ID Register 3.

10 Stop After Start and Matching Address

I2C START condition and matching address. Cleared by a read of the I2C0SSTA register. 01 General Call Reset and Program Address. 10 General Call Program Address. 11 General Call Matching Alternative ID. bus specification, version 2.1, Jan. 2000. busy. Cleared automatically. reading the I2C0SSTA register. automatically by reading the I2C0SSTA register. 3 Slave Receive IRQ. Set after receiving data. register or flushing the FIFO. if the slave transmit FIFO is underflowing. automatically by writing to the I2C0STX register.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 69 of 92 I2CxSRX Registers Name Address Default Value Access I2C0SRX 0xFFFF0808 0x00 R I2C1SRX 0xFFFF0908 0x00 R I2CxSRX are receive registers for the slave channel. I2CxSTX Registers Name Address Default Value Access I2C0STX 0xFFFF080C 0x00 W I2C1STX 0xFFFF090C 0x00 W I2CxSTX are transmit registers for the slave channel. I2CxMRX Registers Name Address Default Value Access I2C0MRX 0xFFFF0810 0x00 R I2C1MRX 0xFFFF0910 0x00 R I2CxMRX are receive registers for the master channel. I2CxMTX Registers Name Address Default Value Access I2C0MTX 0xFFFF0814 0x00 W I2C1MTX 0xFFFF0914 0x00 W I2CxMTXare transmit registers for the master channel. I2CxCNT Registers Name Address Default Value Access I2C0CNT 0xFFFF0818 0x00 R/W I2C1CNT 0xFFFF0918 0x00 R/W I2CxCNT are 3-bit master receive data count registers. If a master read transfer sequence is initiated, then the I2CxCNT registers denote the number of bytes (−1) to be read from the slave device. By default, this counter is 0, which corresponds to 1 byte expected. I2CxADR Registers Name Address Default Value Access I2C0ADR 0xFFFF081C 0x00 R/W I2C1ADR 0xFFFF091C 0x00 R/W I2CxADR are master address byte registers. The I2CxADR value is the device address that the master wants to communicate with. It automatically transmits at the start of a master transfer sequence if there is no valid data in the I2CxMTX register when the master enable bit is set. I2CxBYTE Registers Name Address Default Value Access I2C0BYTE 0xFFFF0824 0x00 R/W I2C1BYTE 0xFFFF0924 0x00 R/W I2CxBYTE are broadcast byte registers. Data written to these register do not go through the TxFIFO. This data is transmitted at the start of a transfer sequence before the address. Once the byte has been transmitted and acknowledged, the I2C expects another byte written in I2CxBYTE or an address written to the address register. I2CxALT Registers Name Address Default Value Access I2C0ALT 0xFFFF0828 0x00 R/W I2C1ALT 0xFFFF0928 0x00 R/W I2CxALT are hardware general call ID registers used in slave mode. I2CxCFG Registers Name Address Default Value Access I2C0CFG 0xFFFF082C 0x00 R/W I2C1CFG 0xFFFF092C 0x00 R/W I2CxCFG are configuration registers.

Table 62. I2C0CFG MMR Bit Descriptions 31:5 Reserved. These bits should be written by the user as 0. condition + matching address. Cleared by the user to disable the generation of an interrupt upon receiving a stop condition. 11 Enable Stretch SCL (Holds SCL Low). Set by the user to stretch the SCL line. Cleared by the user to disable stretching of the SCL line. action, taking interrupt latency into account. call status bits have been cleared. by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit. written to a 1, as per I2C January 2000 specification. status bit sets on any general call. It is up to the user to take correct action by reprogramming the device address. 1 Master Enable Bit. Set by user to enable the master I2C channel. Cleared by user to disable the master I2C channel. I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence. Cleared by user to disable the slave I2C channel. I2CxDIV are the clock divider registers. device ID registers of I2Cx. off SDA low for start and stop conditions. I2CxFSTA are FIFO status registers.

Table 63. I2C0FSTA MMR Bit Descriptions flushes the slave receive FIFO. once the slave Tx FIFO is flushed. 7:6 Master Rx FIFO Status Bits. 5:4 Master Tx FIFO Status Bits. 3:2 Slave Rx FIFO Status Bits. 1:0 Slave Tx FIFO Status Bits. consists of two independent but interconnected PLA blocks. part a total of 16 PLA elements. two inputs and a flip-flop. This is represented in Figure 62. Figure 62. PLA Element

• Output of Element 15 (Block 1) can be fed back to Input 0 of Mux 0 of Element 0 (Block 0)
• Output of Element 7 (Block 0) can be fed back to the Input 0 of Mux 0 of Element 8 (Block 1)

Table 64. Element Input/Output

Table 65. PLAELMx MMR Bit Descriptions 10:9 Mux (0) Control (see Table 67). 8:7 Mux (1) Control (see Table 67). by user to select the output of mux (1). clock selection for the flip-flops of Block 1. Table 66. PLACLK MMR Bit Descriptions

7 Reserved

011 HCLK

101 Timer1 Overflow

3 Reserved

Table 67. Feedback Configuration

01 Element 2 Element 2 Element 10 Element 10

10 Element 4 Element 4 Element 12 Element 12

11 Element 6 Element 6 Element 14 Element 14

01 Element 3 Element 3 Element 11 Element 11

10 Element 5 Element 5 Element 13 Element 13

11 Element 7 Element 7 Element 15 Element 15

Table 68. PLAIRQ MMR Bit Descriptions disable IRQ1 output from PLA. disable IRQ0 output from PLA. Table 69. PLAADC MMR Bit Descriptions to enable ADC start conversion from PLA. 3:0 ADC Start Conversion Source. PLADIN is a data input MMR for PLA. Table 70. PLADIN MMR Bit Descriptions Table 71. PLADOUT MMR Bit Descriptions

interrupts can be masked separately. Table 72. IRQ/FIQ MMRs Bit Description

0 All Interrupts OR’ed

1 SWI

2 Timer0

3 Timer1

4 Wake-Up Timer – Timer2

5 Watchdog Timer – Timer3

6 Flash Control

7 ADC Channel

8 PLL Lock

9 I2C0 Slave

10 I2C0 Master

11 I2C1 Master

12 SPI Slave

13 SPI Master

14 UART

15 External IRQ0

16 Comparator

17 PSM

18 External IRQ1

19 PLA IRQ0

20 PLA IRQ1

21 External IRQ2

22 External IRQ3

23 PWM Trip (IRQ only)/ PWM Sync (FIQ only)

purpose interrupt handling of internal and external events. cleared. All IRQ sources can be masked in the IRQEN MMR. masked, which does not create an IRQ exception. an atomic read-modify-write. are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.

in FIQEN does, as a side effect, clear the same bit in IRQEN. allows the control of programmed source interrupt. Table 73. SWICFG MMR Bit Descriptions

• Timer0
• Timer1
• Timer2 or Wake-Up Timer
• Timer3 or Watchdog Timer These four timers in their normal mode of operation can be either free-running or periodic. In free-running mode, the counter decreases from the maximum value until zero scale and starts again at the minimum value. (It also increases from the minimum value until full scale and starts again at the maximum value.) In periodic mode, the counter decrements/increments from the value in the load register (T×LD MMR) until zero/full scale and starts again at the value stored in the load register. The timer interval is calculated as follow: ( ) clocksource prescalerLDTInterval ××= The value of a counter can be read at any time by accessing its value register (T×V AL). Note that when a timer is being clocked from a clock other than core clock, an incorrect value could be read (due to asynchronous clock system). In this configuration, T×V AL should always be read twice. If the two readings are different, then it should be read a third time to get the correct value. Timers are started by writing in the control register of the corresponding timer (T×CON). In normal mode, an IRQ is generated each time the value of the counter reaches zero when counting down. It is also generated each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing any value to clear the register of that particular timer (T×CLRI). When using an asynchronous clock-to-clock timer, the interrupt in the timer block could take more time to clear than the time it takes for the code in the interrupt routine to execute. Ensure that the interrupt signal is cleared before leaving the interrupt service routine. This can be done by checking the IRQSTA MMR.

T2CON is the configuration MMR described in Table 76. Table 76. T2CON MMR Bit Descriptions 11 Core Clock (41 MHz/2 CD). 8 Count Up. Set by user for Timer2 to count up. 7 Timer2 Enable Bit. Set by user to enable Timer2. Cleared by user to disable Timer2 by default. free-running mode. Default mode. 10 Hr:Min:Sec:Hundredths (23 hours to 0 hour). 11 Hr:Min:Sec:Hundredths (255 hours to 0 hour). 0000 Source Clock/1 by Default. 1000 Source Clock/256 Expect ed for Format 2 and 3. clears the Timer2 interrupt. servicing to prevent it from forcing a reset of the processor. Figure 66. Timer3 Block Diagram Watchdog mode is entered by setting Bit 5 in T3CON MMR. 512 seconds using the prescaler/256, and full-scale in T3LD. reloads the counter with T3LD and begins a new timeout period. T3LD is a 16-bit register load register. T3CON is the configuration MMR described in Table 77.

Figure 71. External Memory Write Cycle with Address and Write Hold Cycles

1 WRITE STROBE WAIT STATE

1 ADDRESS WAIT STATE

Figure 72. External Memory Write Cycle with Wait States

operational power supply voltage range is 2.7 V to 3.6 V . typical split supply configuration is shown in Figure 73. Figure 73. External Dual Supply Connections others) can be powered from the AVDD supply line as well. Figure 74. External Single Supply Connections capacitors are located at each AVDD and IOVDD pin of the chip. ground reference point at all times. these pins) to act as a tank of charge as shown Figure 75.

27 LVDD

28 DGND

Figure 75. Voltage Regulator Connections

below 2.35 V typical, the internal POR holds the part in reset. Figure 79 illustrates the operation of the internal POR in detail. Figure 79. ADuC7019/7020/7021/7022/7024/7025/7026/7027 reasons. The metal plate of the board can be connected to ground.

3 GNDREF

4 DAC0

8 TMS

9 TDI

1 C1+

3 C1–

4 C2+

5 C2–

7 T2OUT

8 R2IN

PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006. Figure 80. Typical System Configuration

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 86 of 92 DEVELOPMENT TOOLS PC-BASED TOOLS Four types of development systems are available for the ADuC7019/7020/7021/7022/7024/7025/7026/7027 family:

• The ADuC7026 QuickStart Plus is intended for new users who want to have a comprehensive hardware development environment. Since the ADuC7026 contains the superset of functions available on the ADuC7019/7020/7021/ 7022/7024/7025/7026/7027 family, it is suitable for users who wish to develop on any of the parts in this family. All of the parts are fully code compatible.
• The ADuC7020, ADuC7024, and ADuC7026 QuickStart are intended for users who already have an emulator. These systems consist of the following PC-based (Windows® compatible) hardware and software development tools: Hardware
• ADuC7019/7020/7021/7022/7024/7025/7026/7027 evaluation board
• Serial port programming cable
• RDI compliant JTAG emulator (included in the ADuC7026 QuickStart Plus only) Software
• Integrated development environment, incorporating assembler, compiler, and nonintrusive JTAG-based debugger
• Serial downloader software
• Example code Miscellaneous
• CD-ROM documentation IN-CIRCUIT SERIAL DOWNLOADER The serial downloader is a Windows application that allows the user to serially download an assembled program to the on-chip program Flash/EE memory via the serial port on a standard PC. The UART based serial downloader is included in all the development systems and is usable with ADuC7019/7020/7021/ 7022/7024/7025/7026/7027 that do not contain the “I” suffix in the ordering guide. An I 2C based serial downloader is also available at www.analog.com. This software requires an USB to I2C adaptor board available from http://www.fh-pforzheim.de/ stw-svs/texte/Dongle.html. The I2C based serial downloader is only usable with the part models containing the “I” suffix in the ordering guide.

0.20 REF

0.05 MAX

0.02 NOM

0.80 MAX

0.65 TYP

0.60 MAX

0.25 MIN

Figure 81. 40-Lead Frame Chip Scale Package [LFCSP_VQ] Figure 82. 64-Lead Frame Chip Scale Package [LFCSP_VQ]

0.08 MAX

Figure 83. 64-Lead Low Profile Quad Flat Package [LQFP] Figure 84. 80-Lead Low Profile Quad Flat Package [LQFP]

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 89 of 92 ORDERING GUIDE Model ADC Channels DAC Channels FLASH/RAM GPIO Downloader Temperature Range Package

Description

ADuC7019BCPZ62I1 5 2 3 62 kB/8 kB 14 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 ADuC7019BCPZ62I-RL1 5 2 3 62 kB/8 kB 14 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 2,500 ADuC7019BCPZ62IRL71 5 2 3 62 kB/8 kB 14 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 750 ADuC7020BCPZ621 5 4 62 kB/8 kB 14 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 ADuC7020BCPZ62-RL1 5 4 62 kB/8 kB 14 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 2,500 ADuC7020BCPZ62- RL71 5 4 62 kB/8 kB 14 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 750 ADuC7020BCPZ62I1 5 4 62 kB/8 kB 14 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 ADuC7020BCPZ62I-RL1 5 4 62 kB/8 kB 14 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 2,500 ADuC7020BCPZ62IRL71 5 4 62 kB/8 kB 14 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 750 ADuC7021BCPZ621 8 2 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 ADuC7021BCPZ62-RL1 8 2 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 2,500 ADuC7021BCPZ62- RL7 8 2 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 750 ADuC7021BCPZ62I1 8 2 62 kB/8 kB 13 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 ADuC7021BCPZ62I-RL1 8 2 62 kB/8 kB 13 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 2,500 ADuC7021BCPZ62IRL71 8 2 62 kB/8 kB 13 I 2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40 750 ADuC7021BCPZ321 8 2 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 ADuC7021BCPZ32-RL1 8 2 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 2,500 ADuC7021BCPZ32- RL7 8 2 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 750 ADuC7022BCPZ621 10 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 ADuC7022BCPZ62-RL1 10 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 2,500 ADuC7022BCPZ62- RL7 10 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 750 ADuC7022BCPZ321 10 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 ADuC7022BCPZ32-RL1 10 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 2,500 ADuC7022BCPZ32- RL71 10 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40 750 ADuC7024BCPZ621 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 ADuC7024BCPZ62-RL1 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 2,500 ADuC7024BCPZ62- RL71 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 750 ADuC7024BSTZ621 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LQFP ST-64-2 ADuC7024BSTZ62-RL1 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LQFP ST-64-2 1,000

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 90 of 92 Model ADC Channels DAC Channels FLASH/RAM GPIO Downloader Temperature Range Package ADuC7025BCPZ621 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 ADuC7025BCPZ62-RL1 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 2,500 ADuC7025BCPZ62- RL71 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 750 ADuC7025BCPZ321 12 32 kB/4 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 ADuC7025BCPZ32-RL1 12 32 kB/4 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 2,500 ADuC7025BCPZ32- RL71 12 32 kB/4 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 750 ADuC7025BSTZ621 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LQFP ST-64-2 ADuC7025BSTZ62-RL1 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LQFP ST-64-2 1,000 ADuC7026BSTZ621, 3 12 4 62 kB/8 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 ADuC7026BSTZ62-RL1, 3 12 4 62 kB/8 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 1,000 ADuC7026BSTZ62I1, 3 12 4 62 kB/8 kB 40 I 2C −40°C to +125°C 80-Lead LQFP ST-80-1 ADuC7026BSTZ62I-RL1, 12 4 62 kB/8 kB 40 I 2C −40°C to +125°C 80-Lead LQFP ST-80-1 1,000 ADuC7027BSTZ621, 3 16 62 kB/8 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 ADuC7027BSTZ62-RL1, 3 16 62 kB/8 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 1,000 EVAL-ADuC7020MK ADuC7020 MiniKit EVAL-ADuC7020QS ADuC7020 QuickStart Development System EVAL-ADuC7024QS ADuC7024 QuickStart Development System EVAL-ADuC7026QS ADuC7026 QuickStart Development System EVAL-ADuC7026QSP ADuC7026 QuickStart Plus Development System 1 Z = Pb-free part. 2 One of the ADC channels is internally buffered. 3 Includes external memory interface.

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 91 of 92 NOTES

ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 92 of 92 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04955-0-1/06(A)