ADUM1234

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Isolated, Precision Half-Bridge Driver, 0.1 A Output ADuM1234 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

FEATURES

Isolated high-side and low-side outputs High side or low side relative to input: ±700 VPEAK High-side/low-side differential: 700 VPEAK

0.1 A peak output current

CMOS input threshold levels High frequency operation: 5 MHz maximum High common-mode transient immunity: >75 kV/μs High temperature operation: 105°C Wide body, RoHS compliant, 16-lead SOIC UL1577 2500 V rms input-to-output withstand voltage

APPLICATIONS

Isolated IGBT/MOSFET gate drives Plasma displays Industrial inverters Switching power supplies GENERAL DESCRIPTION The ADuM12341 is an isolated, half-bridge gate driver that employs the Analog Devices, Inc. iCoupler® technology to provide independent and isolated high-side and low-side outputs. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to optocoupler-based solutions. By avoiding the use of LEDs and photodiodes, this iCoupler gate drive device is able to provide precision timing characteristics not possible with optocouplers. Furthermore, the reliability and performance stability problems associated with optocoupler LEDs are avoided. In comparison to gate drivers employing high voltage level translation methodologies, the ADuM1234 offers the benefit of true, galvanic isolation between the input and each output. Each output can be operated up to ±700 V PEAK relative to the input, thereby supporting low-side switching to negative voltages. The differential voltage between the high side and low side can be as high as 700 VPEAK. As a result, the ADuM1234 provides reliable control over the switching characteristics of IGBT/MOSFET configurations over a wide range of positive or negative switching voltages. FUNCTIONAL BLOCK DIAGRAM ENCODE DECODE ENCODE DECODE DISABLE NC NC VDD1 NC VDDB VOB GNDB GND1 NC4 13 VDD1 GNDA3 14 VIB VOA2 15 VIA VDDA1 16 06920-001 NC = NO CONNECT ADuM1234 Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. Other patents pending.

Rev. 0 | Page 2 of 12 TABLE OF CONTENTS

REVISION HISTORY

7/07—Revision 0: Initial Version

Rev. 0 | Page 3 of 12 SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

4.5 V ≤ VDD1 ≤ 5.5 V , 12 V ≤ VDDA ≤ 18 V , 12 V ≤ VDDB ≤ 18 V . All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V , VDDA = 15 V , VDDB = 15 V . All voltages are relative to their respective grounds. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, Quiescent IDDI(Q) 3.0 4.2 mA Output Supply Current A or Output Supply Current B, Quiescent IDDA(Q), IDDB(Q) 0.3 1.2 mA Input Supply Current, 10 Mbps IDDI(10) 6.0 9.0 mA Output Supply Current A or Output Supply Current B, 10 Mbps IDDA(10), IDDB(10) 16 22 mA CL = 200 pF Input Currents IIA, IIB, IDISABLE −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VDISABLE ≤ VDD1 Logic High Input Threshold VIH 0.7 × VDD1 V Logic Low Input Threshold VIL 0.3 × VDD1 V Logic High Output Voltages VOAH,VOBH VDDA − 0.1, VDDB − 0.1 VDDA, VDDB V IOA, IOB = −1 mA Logic Low Output Voltages VOAL,VOBL 0.1 V IOA, IOB = +1 mA Output Short-Circuit Pulsed Current1 IOA(SC), IOB(SC) 100 mA SWITCHING SPECIFICATIONS Minimum Pulse Width2 PW 100 ns CL = 200 pF Maximum Switching Frequency3

10 Mbps CL = 200 pF

tPHL, tPLH 97 124 160 ns CL = 200 pF Change vs. Temperature 100 ps/°C CL = 200 pF Pulse Width Distortion, |tPLH − tPHL| PWD 8 ns CL = 200 pF Channel-to-Channel Matching, Rising or Falling Edges5 5 ns CL = 200 pF Channel-to-Channel Matching, Rising vs. Falling Edges6 13 ns CL = 200 pF Part-to-Part Matching, Rising or Falling Edges7 55 ns CL = 200 pF , Input tR = 3 ns Part-to-Part Matching, Rising vs. Falling Edges8 63 ns CL = 200 pF , Input tR = 3 ns Output Rise/Fall Time (10% to 90%) tR/tF 25 ns C L = 200 pF 1 Short-circuit duration less than 1 second. 2 The minimum pulse width is the shortest pulse width at which the specified timing parameters are guaranteed. 3 The maximum switching frequency is the maximum signal frequency at which the specified timing parameters are guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5 Channel-to-channel matching, rising or falling edges, is the magnitude of the propagation delay diffe

nnels of two different parts when one input a rising edge and the other input is a falling edge. The supply voltages, temperatures, and loads of each part are equal. rence between two channels of the same part when the inputs are either both rising or falling edges. The supply voltages and the loads on each channel are equal. 6 Channel-to-channel matching, rising vs. falling edges, is the magnitude of the propagation delay difference between two channels of the same part when one input is a rising edge and the other input is a falling edge. The supply voltages and loads on each channel are equal. 7 Part-to-part matching, rising or falling edges, is the magnitude of the propagation delay difference between the same channels of two different parts when the inputs are either both rising or falling edges. The supply voltages, temperatures, and loads of each part are equal. 8 Part-to-part matching, rising vs. falling edges, is the magnitude of the propagation delay difference between the same cha is

Rev. 0 | Page 4 of 12 PACKAGE CHARACTERISTICS Table 2. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 RI-O 1012 Ω Capacitance (Input-to-Output)1 CI-O 2.0 pF f = 1 MHz Input Capacitance CI 4.0 pF IC Junction-to-Ambient Thermal Resistance θJA 76 °C/W 1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. REGULATORY INFORMATION The ADuM1234 has been approved by the organization listed in Table 3. Refer to Table 7 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 3. UL Recognized under the 1577 component recognition program1 Single/basic insulation, 2500 V rms isolation voltage 1 In accordance with UL1577, each ADuM1234 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 4. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) RECOMMENDED OPERATING CONDITIONS Table 5. Parameter Symbol Min Max Unit Operating Temperature TA −40 +105 °C Input Supply Voltage1 VDD1 4.5 5.5 V Output Supply Voltages1 VDDA, VDDB 12 18 Input Signal Rise and Fall Times 100 ns Common-Mode Transient Immunity, Input-to-Output2 −75 +75 kV/μs Common-Mode Transient Immunity, Between Outputs2 −75 +75 kV/μs Transient Immunity, Supply Voltages2 −75 +75 kV/μs 1 All voltages are relative to their respective ground. 2 See the section for additional data. Common-Mode Transient Immunity

Ambient temperature = 25°C, unless otherwise noted.

700 VPEAK

1 All voltages are relative to their respective ground. 2 Input-to-output voltage is defined as GNDA − GND1 or GNDB − GND1. 3 Output differential voltage is defined as GNDA − GNDB. 4 Refers to common-mode transients across any insulation barrier. may cause latch-up or permanent damage. Table 7. Maximum Continuous Working Voltage1 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Figure 2. Pin Configuration Table 8. ADuM1234 Pin Function Descriptions VDD1 Input Supply Voltage, 4.5 V to 5.5 V. 4 GND 1 Ground Reference for Input Logic Signals. 5 DISABLE Input Disable. Disables the isolator inputs and refresh circuits. Outputs take on default low state. 9 GND B Ground Reference for Output B. 11 V DDB Output B Supply Voltage, 12 V to 18 V. 14 GND A Ground Reference for Output A. 16 V DDA Output A Supply Voltage, 12 V to 18 V. 1 Pin 3 and Pin 8 are internally connected. Connecting both pins to VDD1 is recommended. 2 Pin 12 and Pin 13 are floating and should be left unconnected. Table 9. Truth Table (Positive Logic) X Unpowered X L Output returns to input state within 1 μs of VDD1 power restoration.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 17. 16-Lead Standard Small Outline Package [SOIC_W] 2 13-inch tape and reel option (1,000 units).

Rev. 0 | Page 11 of 12 NOTES

Rev. 0 | Page 12 of 12 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06920-0-7/07(0)