ADUM1210BRZ

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Dual-Channel Digital Isolator ADuM1210 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.

FEATURES

Narrow body, RoHS-compliant, 8-lead SOIC Low power operation

5 V operation

1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 2.2 mA per channel maximum @ 10 Mbps

3 V/5 V level translation

High temperature operation: 105°C High data rate: dc to 10 Mbps (NRZ) Precise timing characteristics 3 ns maximum pulse width distortion 3 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals UL recognition

2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak

APPLICATIONS

Size-critical multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation Gate drive interface GENERAL DESCRIPTION The ADuM12101 is a dual-channel, digital isolator based on Analog Devices, Inc. iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with opto- couplers. The concerns of the typical optocoupler regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM1210 isolator provides two independent isolation channels operable with the supply voltage on either side, ranging from 2.7 V to 5.5 V . This provides compatibility with lower voltage systems and enables voltage translation functionality across the isolation barrier. In addition, the ADuM1210 provides low pulse width distortion (<3 ns) and tight channel-to-channel matching (<3 ns). Unlike other opto- coupler alternatives, the ADuM1210 isolator has a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. Furthermore, as an alternative to the ADuM1200 dual-channel digital isolator that defaults to an output high condition, the ADuM1210 outputs default to a logic low state when input power is off. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. Other patents pending. FUNCTIONAL BLOCK DIAGRAM ENCODE DECODE ENCODE DECODE VDD1 VIA VIB GND1 VDD2 VOA VOB GND2 05459-001 Figure 1.

Rev. C | Page 2 of 20 TABLE OF CONTENTS Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

REVISION HISTORY

6/07—Rev. B to Rev. C 3/07—Rev. A to Rev. B 2/06—Rev. 0 to Rev. A Changes to DC Correctness and Magnetic Field 7/05—Revision 0: Initial Version

Rev. C | Page 3 of 20 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V . All voltages are relative to their respective ground. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) 0.50 0.60 mA Output Supply Current, per Channel, Quiescent IDDO (Q) 0.19 0.25 mA Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal frequency

10 Mbps

VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal frequency VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal frequency Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ VDD1 Logic High Input Threshold VIH 0.7 × VDD1 V Logic Low Input Threshold VIL 0.3 × VDD1 V Logic High Output Voltages VOAH, VOBH VDD2 − 0.1 5.0 V IOx = −20 μA, VIx = VIxH VDD2 − 0.5 4.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 50 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 15 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels6 tPSKOD 15 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VCM = 1000 V, transient magnitude = 800 V Common-Mode Transient Immunity at Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current, per Channel8 IDDI (D) 0.19 mA/Mbps Output Dynamic Supply Current, per Channel8 IDDO (D) 0.05 mA/Mbps 1 Supply current values are for both channels running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 through Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

Rev. C | Page 4 of 20 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

Rev. C | Page 5 of 20 ELECTRICAL CHARACTERISTICS—3 V OPERATION unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V . All voltages are relative to their respective ground. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) 0.26 0.35 mA Output Supply Current, per Channel, Quiescent IDDO (Q) 0.11 0.20 mA Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal frequency VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal frequency VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal frequency Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB, ≤ VDD1 Logic High Input Threshold VIH 0.7 × VDD1 V Logic Low Input Threshold VIL 0.3 × VDD1 V Logic High Output Voltages VOAH, VOBH VDD2 − 0.1 3.0 V IOx = −20 μA, VIx = VIxH VDD2 − 0.5 2.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 60 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 22 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels6 tPSKOD 22 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VCM = 1000 V, transient magnitude = 800 V Common-Mode Transient Immunity at Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current, per Channel8 IDDI (D) 0.10 mA/Mbps Output Dynamic Supply Current, per Channel8 IDDO (D) 0.03 mA/Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

Rev. C | Page 6 of 20 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

Rev. C | Page 7 of 20 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) mA 5 V/3 V Operation 0.50 0.6 mA 3 V/5 V Operation 0.26 0.35 mA Output Supply Current, per Channel, Quiescent IDDO (Q) mA 5 V/3 V Operation 0.11 0.20 mA 3 V/5 V Operation 0.19 0.25 mA Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal frequency 3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal frequency 3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal frequency VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal frequency VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal frequency 3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal frequency Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ VDD1 Logic High Input Threshold VIH 0.7 × VDD1 V Logic Low Input Threshold VIL 0.3 × VDD1 V Logic High Output Voltages VOAH, VOBH VDD2 − 0.1 VDD2 V IOx = −20 μA, VIx = VIxH VDD2 − 0.5 VDD2 − 0.2 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 15 55 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 22 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels6 tPSKOD 22 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Rev. C | Page 8 of 20 Parameter Symbol Min Typ Max Unit Test Conditions Common-Mode Transient Immunity at Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VCM = 1000 V, transient magnitude = 800 V Common-Mode Transient Immunity at Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current, per Channel8 IDDI (D) 5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current, per Channel8 IDDO (D) 5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

Rev. C | Page 9 of 20 PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 RI-O 1012 Ω Capacitance (Input-to-Output)1 CI-O 1.0 pF f = 1 MHz Input Capacitance2 CI 4.0 pF IC Junction-to-Case Thermal Resistance Side 1 θJCI 46 °C/W Thermocouple located at center of package underside Side 2 θJCO 41 °C/W 1 The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM1210 is approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL CSA VDE Recognized Under 1577 Component Recognition Program1 Approved under CSA Component Acceptance Notice #5A Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Single/Basic 2500 V rms Isolation Voltage Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 peak) maximum working voltage Functional insulation per CSA 60950-1-03 and IEC 60950-1,

800 V rms (1131 V peak) maximum working voltage

Reinforced insulation, 560 V peak File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM1210 is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1210 is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

TA = 25°C, unless otherwise noted. 1 All voltages are relative to their respective ground. 2 See Figure 2 for maximum rated current values for various temperatures. latch-up or permanent damage. Table 10. Maximum Continuous Working Voltage1 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Figure 3. Pin Configuration Table 11. Pin Function Descriptions 1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. 4 GND1 Ground 1. Ground reference for Isolator Side 1. 5 GND2 Ground 2. Ground reference for Isolator Side 2. 8 VDD2 Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V. Table 12. ADuM1210 Truth Table (Positive Logic)

Rev. C | Page 17 of 20 OUTLINE DIMENSIONS CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MS-012-AA 012407-A 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45° 1.75 (0.0688) 1.35 (0.0532) SEATING PLANE 0.25 (0.0098) 0.10 (0.0040) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) BSC 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 Figure 15. 8-Lead Standard Small Outline Package [SOIC_N]

Description

ADuM1210BRZ 2 0 10 Mbps 50 ns 3 ns −40°C to +105°C 8-Lead SOIC_N R-8 1 ADuM1210BRZ-RL7 2 0 10 Mbps 50 ns 3 ns −40°C to +105°C 8-Lead SOIC_N R-8 1 1 Z = RoHS Compliant Part.

Rev. C | Page 18 of 20 NOTES

Rev. C | Page 19 of 20 NOTES

Rev. C | Page 20 of 20 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05459-0-6/07(C)