ADUM1201

ADUM1200 AD | Alldatasheet

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Dual-Channel Digital Isolators ADuM1200/ADuM1201 Rev. B Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Narrow body SOIC 8-lead package Low power operation

5 V operation

1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 8.2 mA per channel maximum @ 25 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 2.2 mA per channel maximum @ 10 Mbps 4.8 mA per channel maximum @ 25 Mbps Bidirectional communication

3 V/5 V level translation

High temperature operation: 105°C High data rate: dc to 25 Mbps (NRZ) Precise timing characteristics 3 ns maximum pulse-width distortion 3 ns maximum channel-to-channel matching High common-mode transient immunity: > 25 kV/µs Safety and regulatory approvals UL recognition

2500 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A VDE certificate of conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000 VIORM = 560 V peak

APPLICATIONS

Size-critical multichannel isolation SPI® interface/data converter isolation RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation GENERAL DESCRIPTION The ADuM120x are dual-channel digital isolators based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM120x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both parts operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM120x provide low pulse-width distortion (< 3 ns for CR grade) and tight channel-to-channel matching (< 3 ns for CR grade). Unlike other optocoupler alternatives, the ADuM120x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. FUNCTIONAL BLOCK DIAGRAMS ENCODE DECODE ENCODE DECODE VDD1 VIA VIB GND1 VDD2 VOA VOB GND2 04642-0-001 Figure 1. ADuM1200 Functional Block Diagram Figure 2. ADuM1201 Functional Block Diagram

Rev. B | Page 2 of 20 TABLE OF CONTENTS Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics

REVISION HISTORY

9/04—Data Sheet Changed from Rev. A to Rev. B 6/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Electrical Characteristics—Mixed 5 V/3 V or 4/04—Revision 0: Initial Version

Rev. B | Page 3 of 20 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V . Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) 0.50 0.60 mA Output Supply Current, per Channel, Quiescent IDDO (Q) 0.19 0.25 mA ADuM1200, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal freq.

25 Mbps (CR Grade Only)

VDD1 Supply Current IDD1 (25) 10 13 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 µA 0 ≤ VIA, VIB ≤ VDD1 or VDD2 Logic High Input Threshold VIH 0.7 VDD1, VDD2 V Logic Low Input Threshold VIL 0.3 VDD1, VDD2 V Logic High Output Voltages VOAH VDD1, VDD2 − 0.1

5.0 V IOx = −20 µA, VIx = VIxH

VOBH VDD1, VDD2 − 0.5

4.8 V IOx = −4 mA, VIx = VIxH

Logic Low Output Voltages VOAL 0.0 0.1 V IOx = 20 µA, VIx = VIxL V OBL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xAR Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 100 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching6 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 5 of 20 ELECTRICAL CHARACTERISTICS—3 V OPERATION entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V . Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) 0.26 0.35 mA Output Supply Current, per Channel, Quiescent IDDO (Q) 0.11 0.20 mA ADuM1200, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 0.01 10 µA 0 ≤ VIA, VIB, ≤ VDD1 or VDD2 Logic High Input Threshold VIH 0.7 VDD1, VDD2 V Logic Low Input Threshold VIL 0.3 VDD1, VDD2 Logic High Output Voltages VOAH VDD1, VDD2 − 0.1

3.0 V IOx = −20 µA, VIx = VIxH

VOBH VDD1, VDD2 − 0.5

2.8 V IOx = −4 mA, VIx = VIxH

Logic Low Output Voltages VOAL 0.0 0.1 V IOx = 20 µA, VIx = VIxL V OBL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xAR Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 100 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching6 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 7 of 20 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) mA 5 V/3 V Operation 0.50 0.6 mA 3 V/5 V Operation 0.26 0.35 mA Output Supply Current, per Channel, Quiescent IDDO (Q) mA 5 V/3 V Operation 0.11 0.20 mA 3 V/5 V Operation 0.19 0.25 mA ADuM1200, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 5 V/3 V Operation 10 13 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 5 V/3 V Operation 1.5 2.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 2.8 3.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 1.5 2.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.5 mA 5 MHz logic signal freq.

Rev. B | Page 8 of 20 Parameter Symbol Min Typ Max Unit Test Conditions VDD1 Supply Current IDD1 (25) 5 V/3 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 5 V/3 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 0.01 10 µA 0 ≤ VIA, VIB ≤ VDD1 or VDD2 Logic High Input Threshold VIH 0.7 VDD1, VDD2 V Logic Low Input Threshold VIL 0.3 VDD1, VDD2 V 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V Logic High Output Voltages VOAH, VOBH VDD1, VDD2 − 0.1 VDD1, VDD2 V IOx = −20 µA, VIx = VIxH VDD1, VDD2 − 0.5 VDD1, VDD2 − 0.2 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 µA, VIx = VIxL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xAR Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 50 150 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching6 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels ADuM120xBR Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 15 55 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 22 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels6 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing Directional Channels6 tPSKOD 22 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tf CL = 15 pF, CMOS signal levels 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Rev. B | Page 10 of 20 PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-Output)1 RI-O 1012 Ω Capacitance (Input-Output)1 CI-O 1.0 pF f = 1 MHz Input Capacitance CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W Thermocouple located at center of package underside IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W 1 The device is considered a 2-terminal device; Pins 1, 2, 3, and 4 are shorted together, and Pins 5, 6, 7, and 8 are shorted together. REGULATORY INFORMATION The ADuM1200/ADuM1201 have been approved by the following organizations: Table 5. UL CSA VDE Recognized under 1577 Component Recognition Program

2500 V rms isolation voltage

Approved under CSA Component Acceptance Notice #5A File 205078 Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012 Basic insulation, 560 V peak Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000, Reinforced insulation, 560 V peak File 2471900-4880-0001 1 In accordance with UL1577, each ADuM120x is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA). 2 In accordance with DIN EN 60747-5-2, each ADuM120x is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Note that the “*” marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage. This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Figure 3. Thermal Derating Curve, Dependence of Safety-

Ambient temperature = 25°C, unless otherwise noted. 1 All voltages are relative to their respective ground. 2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. degradation or loss of functionality. Table 10. ADuM1200 Truth Table (Positive Logic) Table 11. ADuM1201 Truth Table (Positive Logic)

Figure 4. ADuM1200 Pin Configuration Figure 5. ADuM1201 Pin Configuration Table 12. ADuM1200 Pin Function Descriptions

1 VDD1 Supply Voltage for Isolator Side 1,

8 VDD2 Supply Voltage for Isolator Side 2,

Table 13. ADuM1201 Pin Function Descriptions

Figure 14. Maximum Allowable Current for Various layout of such traces to avoid this possibility. rate, and the channel’s output load. CL is the output load capacitance (pF). VDDO is the output supply voltage (V). fr is the input stage refresh rate (Mbps). ADuM1200 and ADuM1201 channel configurations.

Figure 15. 8-Lead Standard Small Outline Package [SOIC] 1 R-8 = 8-lead narrow body SOIC.

Rev. B | Page 18 of 20 NOTES

Rev. B | Page 19 of 20 NOTES

Rev. B | Page 20 of 20 NOTES © 2004 Analo g De vices, Inc. All rights reserve d. Tra demarks and registered tra demarks are the prop erty of their respective owners . D04642–0–9/04(B)