ADuM1200ARZ-RL7

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Dual-Channel Digital Isolators Data Sheet ADuM1200/ADuM1201 Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.

FEATURES

Narrow body, RoHS-compliant, SOIC 8-lead package Low power operation

5 V operation

1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 8.2 mA per channel maximum @ 25 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 2.2 mA per channel maximum @ 10 Mbps 4.8 mA per channel maximum @ 25 Mbps Bidirectional communication

3 V/5 V level translation

High temperature operation: 125°C High data rate: dc to 25 Mbps (NRZ) Precise timing characteristics 3 ns maximum pulse width distortion 3 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Qualified for automotive applications Safety and regulatory approvals UL recognition

2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 V IORM = 560 V peak

APPLICATIONS

Size-critical multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation Hybrid electric vehicles, battery monitor, and motor drive GENERAL DESCRIPTION The ADuM120x1 are dual-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic transformer technologies, these isolation components provide outstanding performance characteristics superior to alternatives, such as optocouplers. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with opto- couplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temper- ature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM120x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both parts operate with the supply voltage on either side ranging from 2.7 V to 5.5 V , providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM120x provide low pulse width distortion (<3 ns for CR grade) and tight channel-to-channel matching (<3 ns for CR grade). Unlike other optocoupler alternatives, the ADuM120x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. The ADuM1200W and ADuM1201W are automotive grade versions qualified for 125°C operation. See the Automotive Products section for more information. FUNCTIONAL BLOCK DIAGRAMS ENCODE DECODE ENCODE DECODE VDD1 VIA VIB GND1 VDD2 VOA VOB GND2 04642-001 Figure 1. ADuM1200 Functional Block Diagram Figure 2. ADuM1201 Functional Block Diagram

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 2 of 28 TABLE OF CONTENTS Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V , Electrical Characteristics—Mixed 5 V/3 V , 125°C Operation 15 Electrical Characteristics—Mixed 3 V/5 V , 125°C Operation 17 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

Data Sheet ADuM1200/ADuM1201 Rev. I | Page 3 of 28

REVISION HISTORY

3/12—Rev. H to Rev. I Created Hyperlink for Safety and Regulatory Approvals 1/09—Rev. G to Rev. H 9/08—Rev. F to Rev. G 3/08—Rev. E to Rev. F 11/07—Rev. D to Rev. E 8/07—Rev. C to Rev. D 2/06—Rev. B to Rev. C Changes to DC Correctness and Magnetic Field 9/04—Rev. A to Rev. B 6/04—Rev. 0 to Rev. A Changes to Electrical Characteristics—Mixed 5 V/3 V or 4/04—Revision 0: Initial Version

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 4 of 28 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V , 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this does not apply to the ADuM1200W and ADuM1201W automotive grade products. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.60 mA Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.25 mA ADuM1200 Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal freq.

25 Mbps (CR Grade Only)

VDD1 Supply Current IDD1 (25) 10 13 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2) Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V Logic High Output Voltages VOAH, VOBH (V DD1 or VDD2) − 0.1 5.0 V IOx = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.5 4.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xAR C L = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps Propagation Delay4 t PHL, tPLH 50 150 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Change vs. Temperature 11 ps/°C Propagation Delay Skew5 t PSK 100 ns Channel-to-Channel Matching6 t PSKCD/tPSKOD 50 ns Output Rise/Fall Time (10% to 90%) tR/tF 10 ns

Data Sheet ADuM1200/ADuM1201 Rev. I | Page 5 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xBR Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching 3 Codirectional Channels6 tPSKCD ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns ADuM120xCR Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 45 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching 3 ns Codirectional Channels6 tPSKCD Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CM H| 25 35 kV/μs VIx = VDD1 or VDD2, VCM =

1000 V, transient

magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Dynamic Supply Current per Channel8 Input I DDI (D) 0.19 mA/ Mbps Output I DDO (D) 0.05 mA/ Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations. Power Consumption Power Consumption Figure 6 Figure 6 Figure 8 Figure 8 Figure 9 Figure 11 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 6 of 28 ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION All voltages are relative to their respective ground; 2.7 V ≤ VDD1 ≤ 3.6 V , 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this does not apply to ADuM1200W and ADuM1201W automotive grade products. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent I DDI (Q) 0.26 0.35 mA Output Supply Current per Channel, Quiescent I DDO (Q) 0.11 0.20 mA ADuM1200 Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ V IA, VIB ≤ (VDD1 or VDD2) Logic High Input Threshold VIH 0.7 (V DD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (V DD1 or VDD2) Logic High Output Voltages VOAH, VOBH (V DD1 or VDD2) − 0.1 3.0 V I Ox = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.5 2.8 V I Ox = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V I Ox = 20 μA, VIx = VIxL 0.04 0.1 V I Ox = 400 μA, VIx = VIxL 0.2 0.4 V I Ox = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xAR C L = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps Propagation Delay4 t PHL, tPLH 50 150 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Change vs. Temperature 11 ps/°C Propagation Delay Skew5 t PSK 100 ns Channel-to-Channel Matching6 t PSKCD/tPSKOD 50 ns Output Rise/Fall Time (10% to 90%) t R/tF 10 ns

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 8 of 28 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION 2.7 V ≤ VDD1 ≤ 3.6 V , 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V , VDD2 = 5.0 V; or VDD1 = 5.0 V , VDD2 = 3.0 V; this does not apply to ADuM1200W and ADuM1201W automotive grade products. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 5 V/3 V Operation 0.50 0.6 mA 3 V/5 V Operation 0.26 0.35 mA Output Supply Current per Channel, Quiescent IDDO (Q) 5 V/3 V Operation 0.11 0.20 mA 3 V/5 V Operation 0.19 0.25 mA ADuM1200 Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 5 V/3 V Operation 10 13 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 5 V/3 V Operation 1.5 2.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 5 V/3 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 5 V/3 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 5 V/3 V Operation 2.8 3.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 5 V/3 V Operation 1.5 2.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.5 mA 5 MHz logic signal freq.

Data Sheet ADuM1200/ADuM1201 Rev. I | Page 9 of 28 Parameter Symbol Min Typ Max Unit Test Conditions VDD1 Supply Current IDD1 (25) 5 V/3 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 5 V/3 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2) Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xAR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps Propagation Delay4 t PHL, tPLH 50 150 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Change vs. Temperature 11 ps/°C Propagation Delay Skew5 t PSK 50 ns Channel-to-Channel Matching6 t PSKCD/tPSKOD 50 ns Output Rise/Fall Time (10% to 90%) tR/tF 10 ns ADuM120xBR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 22 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns Output Rise/Fall Time (10% to 90%) tR/tF 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns ADuM120xCR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Data Sheet ADuM1200/ADuM1201 Rev. I | Page 11 of 28 ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V , 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 4. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.60 mA Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.25 mA ADVM1200W, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq.

10 Mbps (TRZ and URZ Grades Only)

VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal freq.

25 Mbps (URZ Grade Only)

VDD1 Supply Current IDD1 (25) 10 13 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 2.8 3.4 mA 12.5 MHz logic signal freq. ADVM1201W, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 7≤ VIA, VIB ≤ (VDD1 or VDD2) Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V Logic High Output Voltages VOAH, VOBH (V DD1 or VDD2) − 0.1 5.0 V IOx = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.5 4.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps Propagation Delay4 t PHL, tPLH 20 150 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 t PSK 100 ns Channel-to-Channel Matching6 t PSKCD/tPSKOD 50 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 12 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ C L = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) t R/tF 2.5 ns ADuM120xWURZ C L = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 45 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) t R/tF 2.5 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CM H| 25 35 kV/μs V Ix = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs V Ix = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Dynamic Supply Current per Channel8 Input I DDI (D) 0.19 mA/ Mbps Output IDDO (D) 0.05 mA/ Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

Data Sheet ADuM1200/ADuM1201 Rev. I | Page 13 of 28 ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 5. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.35 mA Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.20 mA ADVM1200W, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADVM1201W, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 7≤ VIA, VIB ≤ (VDD1 or VDD2) Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) Logic High Output Voltages VOAH, VOBH (V DD1 or VDD2) − 0.1 3.0 V IOx = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.5 2.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps Propagation Delay4 t PHL, tPLH 20 150 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 t PSK 100 ns Channel-to-Channel Matching6 t PSKCD/tPSKOD 50 ns Output Rise/Fall Time (10% to 90%) tR/tF 3 ns

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 14 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 60 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 22 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns Output Rise/Fall Time (10% to 90%) t R/tF 3.0 ns ADuM120xWCR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 55 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 16 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 16 ns Output Rise/Fall Time (10% to 90%) t R/tF 3.0 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CM H| 25 35 kV/μs V Ix = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs V Ix = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Dynamic Supply Current per Channel8 Input I DDI (D) 0.10 mA/ Mbps Output I DDO (D) 0.03 mA/ Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulsewidth distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

Data Sheet ADuM1200/ADuM1201 Rev. I | Page 15 of 28 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5.0 V , VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 6. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.6 mA Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.20 mA ADuM1200W, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 10 13 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201W, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ V IA, VIB ≤ (VDD1 or VDD2) Logic High Input Threshold V IH 0.7 (V DD1 or VDD2) V Logic Low Input Threshold V IL 0.3 (VDD1 or VDD2) V Logic High Output Voltages V OAH, VOBH (V DD1 or VDD2) − 0.1 V DD1 or VDD2 V I Ox = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.5 (V DD1 or VDD2) − 0.2 V I Ox = −4 mA, VIx = VIxH Logic Low Output Voltages V OAL, VOBL 0.0 0.1 V I Ox = 20 μA, VIx = VIxL 0.04 0.1 V I Ox = 400 μA, VIx = VIxL 0.2 0.4 V I Ox = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps Propagation Delay4 t PHL, tPLH 15 150 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 t PSK 50 ns Channel-to-Channel Matching6 t PSKCD/ tPSKOD 50 ns Output Rise/Fall Time (10% to 90%) t R/tF 3 ns

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 16 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 22 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns Output Rise/Fall Time (10% to 90%) t R/tF 3.0 ns ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) t R/tF 3.0 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CM H| 25 35 kV/μs V Ix = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs V Ix = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Dynamic Supply Current per Channel8 Input I DDI (D) 0.19 mA/ Mbps Output IDDO (D) 0.03 mA/ Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

Data Sheet ADuM1200/ADuM1201 Rev. I | Page 17 of 28 ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V , 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V , VDD2 = 5.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 7. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.35 mA Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.25 mA ADuM1200W, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201W, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ V IA, VIB ≤ (VDD1 or VDD2) Logic High Input Threshold V IH 0.7 (V DD1 or VDD2) V Logic Low Input Threshold V IL 0.3 (VDD1 or VDD2) V Logic High Output Voltages V OAH, VOBH (V DD1 or VDD2) − 0.1 V DD1 or VDD2 V I Ox = −20 μA, VIx = VIxH (VDD1 or VDD2) − 0.5 (V DD1 or VDD2) − 0.2 V I Ox = −4 mA, VIx = VIxH Logic Low Output Voltages V OAL, VOBL 0.0 0.1 V I Ox = 20 μA, VIx = VIxL 0.04 0.1 V I Ox = 400 μA, VIx = VIxL 0.2 0.4 V I Ox = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps Propagation Delay4 t PHL, tPLH 15 150 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 t PSK 50 ns Channel-to-Channel Matching6 t PSKCD/ tPSKOD 50 ns Output Rise/Fall Time (10% to 90%) t R/tF 3 ns

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 18 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 22 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns Output Rise/Fall Time (10% to 90%) t R/tF 2.5 ns ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) t R/tF 2.5 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CM H| 25 35 kV/μs V Ix = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs V Ix = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 IDDI (D) 0.10 mA/ Mbps Output Dynamic Supply Current per Channel8 IDDO (D) 0.05 mA/ Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.

Data Sheet ADuM1200/ADuM1201 Rev. I | Page 19 of 28 PACKAGE CHARACTERISTICS Table 8. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 R I-O 10 12 Ω Capacitance (Input-to-Output)1 C I-O 1.0 pF f = 1 MHz Input Capacitance CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θ JCI 46 °C/W Thermocouple located at center of package underside IC Junction-to-Case Thermal Resistance, Side 2 θ JCO 41 °C/W 1 The device is considered a 2-terminal device; Pin 1, Pin, 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together. REGULATORY INFORMATION The ADuM1200/ADuM1201 and ADuM1200W/ADuM1201W are approved by the organizations listed in Table 9; refer to Table 14 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 9. UL CSA VDE Recognized Under 1577 Component Recognition Program1 Approved under CSA Component Acceptance Notice #5A; approval pending for ADuM1200W/ ADuM1201W automotive 125°C temperature grade Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Single/Basic 2500 V rms Isolation Voltage Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 peak) maximum working voltage Functional insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Reinforced insulation, 560 V peak File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM120x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM120x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 10. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

uits. Note that the asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.

672 V peak

Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values

1 Does not apply to ADuM1200W and ADuM1201W automotive grade

2 Applies to ADuM1200W and ADuM1201W automotive grade products.

Ambient temperature = 25°C, unless otherwise noted.

1 Does not apply to ADuM1200W and ADuM1200W automotive grade

2 Applies to ADuM1200W and ADuM1201W automotive grade products. 3 All voltages are relative to their respective ground.

4 VDDI and VDDO refer to the supply voltages on the input and output sides of a

given channel, respectively. 6 Refers to common-mode transients across the insulation barrier. can cause latch-up or permanent damage. Table 14. Maximum Continuous Working Voltage1 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Figure 4. ADuM1200 Pin Configuration Figure 5. ADuM1201 Pin Configuration Table 15. ADuM1200 Pin Function Descriptions 1 V DD1 Supply Voltage for Isolator Side 1. 4 GND 1 Ground 1. Ground Reference for Isolator Side 1. 5 GND 2 Ground 2. Ground Reference for Isolator Side 2. 8 V DD2 Supply Voltage for Isolator Side 2. Table 16. ADuM1201 Pin Function Descriptions 1 V DD1 Supply Voltage for Isolator Side 1. 4 GND 1 Ground 1. Ground Reference for Isolator Side 1. 5 GND 2 Ground 2. Ground Reference for Isolator Side 2. 8 V DD2 Supply Voltage for Isolator Side 2. Table 17. ADuM1200 Truth Table (Positive Logic) 1 μs of VDDI power restoration. 1 μs of VDDO power restoration. Table 18. ADuM1201 Truth Table (Positive Logic) 1 μs of VDDI power restoration.

sensing threshold and does not cause a faulty output transition. from the ADuM120x to affect the operation of the component. Figure 14. Maximum Allowable Current for Various channel, and the output load of the channel. CL is the output load capacitance (pF). VDDO is the output supply voltage (V). r is the input stage refresh rate (Mbps). ADuM1200 and ADuM1201 channel configurations.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 18. 8-Lead Standard Small Outline Package [SOIC_N]

ADuM1200/ADuM1201 Data Sheet Rev. I | Page 28 of 28 Model1, 2 Number of Inputs, VDD1 Side Number of Inputs, VDD2 Side Maximum Data Rate (Mbps) Maximum Propagation Delay, 5 V (ns) Maximum Pulse Width Distortion (ns) Temperature Range Package Option ADuM1201WSRZ 1 1 1 150 40 −40°C to +125°C R-8 ADuM1201WSRZ-RL7 1 1 1 150 40 −40°C to +125°C R-8 ADuM1201WTRZ 1 1 10 50 3 −40°C to +125°C R-8 ADuM1201WTRZ-RL7 1 1 10 50 3 −40°C to +125°C R-8 ADuM1201WURZ 1 1 25 45 3 −40°C to +125°C R-8 ADuM1201WURZ-RL7 1 1 25 45 3 −40°C to +125°C R-8 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 R-8 = 8-lead narrow-body SOIC_N. AUTOMOTIVE PRODUCTS The ADuM1200W/ADuM1201W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04642-0-3/12(I)