ADuM1100UR-RL7

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Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2001–2012 Analog Devices, Inc. All rights reserved.

FEATURES

High data rate: dc to 100 Mbps (NRZ) Compatible with 3.3 V and 5.0 V operation/level translation 125°C maximum operating temperature Low power operation

5 V operation

1.0 mA maximum @ 1 Mbps 4.5 mA maximum @ 25 Mbps 16.8 mA maximum @ 100 Mbps

3.3 V operation

0.4 mA maximum @ 1 Mbps 3.5 mA maximum @ 25 Mbps 7.1 mA maximum @ 50 Mbps 8-lead SOIC_N package (RoHS compliant version available) High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals UL recognized

2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V IORM = 560 V peak

APPLICATIONS

Digital field bus isolation Opto-isolator replacement Computer peripheral interface Microprocessor system interface General instrumentation and data acquisition applications GENERAL DESCRIPTION The ADuM11001 is a digital isolator based on Analog Devices Inc., iCoupler® technology. Combining high speed CMOS and mono lith ic air core transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives, such as optocoupler devices. Configured as a pin-compatible replacement for existing high speed optocouplers, the ADuM1100 supports data rates as high as 25 Mbps and 100 Mbps. The ADuM1100 operates with a voltage supply ranging from 3.0 V to 5.5 V , boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compatible with temperatures up to 125°C. It operates at very low power, less than 0.9 mA of quiescent current (sum of both sides), and a dynamic current of less than 160 μA per Mbps of data rate. Unlike other optocoupler alternatives, the ADuM1100 provides dc correctness with a patented refresh feature that continuously updates the output signal. The ADuM1100 is offered in three grades. The ADuM1100AR and ADuM1100BR can operate up to a maximum temperature of 105°C and support data rates up to 25 Mbps and 100 Mbps, respectively. The ADuM1100UR can operate up to a maximum temperature of 125°C and supports data rates up to 100 Mbps. 1 Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578; FUNCTIONAL BLOCK DIAGRAM WATCHDOG E N C O D E D E C O D E UPDATE VDD1 VI (DATA IN) VDD1 GND1 VDD2 GND2 VO (DATA OUT) GND2 ADuM1100 NOTES 1. FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION. 02462-001 Figure 1.

Rev. I | Page 2 of 20 TABLE OF CONTENTS Electrical Specifications—Mixed 5 V/3 V or 3 V/5 V DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Method of Operation, DC Correctness, and Magnetic

Rev. I | Page 3 of 20

REVISION HISTORY

3/12—Rev. H to Rev. I Created Hyperlink for Safety and Regulatory Approvals 3/11—Rev. G to Rev. H 6/07—Rev. F to Rev. G 3/06—Rev. E to Rev. F 10/03—Rev. D to Rev. E Changes to Product Name, Features, and General Description . 1 Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation 6/03—Rev. C to Rev. D Changed DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation 4/03—Rev. B to Rev. C Changes to Method of Operation, DC Correctness, and 1/03—Rev. A to Rev. B Changed ADuM1100AR/ADuM1100BR to Added Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V 11/02—Rev. 0 to Rev. A

Rev. I | Page 4 of 20 SPECIFICATIONS ELECTRICAL SPECIFICATIONS—5 V OPERATION apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V . Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current IDD1 (Q) 0.3 0.8 mA VI = 0 V or VDD1 Output Supply Current IDD2 (Q) 0.01 0.06 mA VI = 0 V or VDD1 Input Supply Current (25 Mbps) (See Figure 5) IDD1 (25) 2.2 3.5 mA 12.5 MHz logic signal frequency Output Supply Current1 (25 Mbps) (See Figure 6) IDD2 (25) 0.5 1.0 mA 12.5 MHz logic signal frequency Input Supply Current (100 Mbps) (See Figure 5) IDD1 (100) 9.0 14 mA 50 MHz logic signal frequency, ADuM1100BR/ADuM1100UR only Output Supply Current1 (100 Mbps) (See Figure 6) IDD2 (100) 2.0 2.8 mA 50 MHz logic signal frequency, ADuM1100BR/ADuM1100UR only Input Current II −10 +0.01 +10 μA 0 V ≤ VIN ≤ VDD1 Logic High Output Voltage VOH VDD2 − 0.1 5.0 V IO = −20 μA, VI = VIH VDD2 − 0.8 4.6 V IO = −4 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 0.03 0.1 V IO = 400 μA, VI = VIL 0.3 0.8 V IO = 4 mA, VI = VIL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 6.7 10 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 100 150 Mbps CL = 15 pF, CMOS signal levels For All Grades Propagation Delay Time to Logic Low Output4, 5 (See Figure 7) tPHL 10.5 18 ns CL = 15 pF, CMOS signal levels Propagation Delay Time to Logic High Output4, 5 (See Figure 7) tPLH 10.5 18 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature6 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature)5, 7 tPSK1 8 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature, Supplies)5, 7 tPSK2 6 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic Low/High Output8 |CML|, |CMH| 25 35 kV/μs VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current9 I DDI (D) 0.09 mA/Mbps Output Dynamic Supply Current9 I DDO (D) 0.02 mA/Mbps

Rev. I | Page 6 of 20 ELECTRICAL SPECIFICATIONS—3.3 V OPERATION over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V . Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current IDD1 (Q) 0.1 0.3 mA VI = 0 V or VDD1 Output Supply Current IDD2 (Q) 0.005 0.04 mA VI = 0 V or VDD1 Input Supply Current (25 Mbps) (See Figure 5) IDD1 (25) 2.0 2.8 mA 12.5 MHz logic signal frequency Output Supply Current1 (25 Mbps) (See Figure 6) IDD2 (25) 0.3 0.7 mA 12.5 MHz logic signal frequency Input Supply Current (50 Mbps) (See Figure 5) IDD1 (50) 4.0 6.0 mA 25 MHz logic signal frequency, ADuM1100BR/ADuM1100UR only Output Supply Current1 (50 Mbps) (See Figure 6) IDD2 (50) 1.2 1.6 mA 25 MHz logic signal frequency, ADuM1100BR/ADuM1100UR only Input Current II −10 +0.01 +10 μA 0 V ≤ VIN ≤ VDD1 Logic High Output Voltage VOH VDD2 − 0.1 3.3 V IO = −20 μA, VI = VIH VDD2 − 0.5 3.0 V IO = −2.5 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIH 0.04 0.1 V IO = 400 μA, VI = VIH 0.3 0.4 V IO = 2.5 mA, VI = VIH SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 10 20 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 50 100 Mbps CL = 15 pF, CMOS signal levels For All Grades Propagation Delay Time to Logic Low Output4, 5 (See Figure 8) tPHL 14.5 28 ns CL = 15 pF, CMOS signal levels Propagation Delay Time to Logic High Output4, 5 (See Figure 8) tPLH 15.0 28 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion |tPLH − tPHL|5 PWD 0.5 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature6 10 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature)5, 7 tPSK1 15 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature, Supplies)5, 7 tPSK2 12 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic Low/High Output8 |CML|, |CMH| 25 35 kV/μs VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current9 I DDI (D) 0.08 mA/Mbps Output Dynamic Supply Current9 IDDO (D) 0.04 mA/Mbps

Rev. I | Page 8 of 20 ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION 7≤ VDD1 ≤ 3.6 V , 4.5 V ≤ VDD2 ≤ 5.5 V . All minimum/maximum specifications apply over the entire recommended operation range, VOMFTTotherwise noted. All typical specifications are at TA = 25°C, VDD1 = 3.3 V , VDD2 = 5 V or VDD1 = 5 V , VDD2 = 3.3 V . Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, Quiescent IDDI (Q) 5 V/3 V Operation 0.3 0.8 mA 3 V/5 V Operation 0.1 0.3 mA Output Supply Current, Quiescent IDDO (Q) 5 V/3 V Operation 0.005 0.04 mA 3 V/5 V Operation 0.01 0.06 mA Input Supply Current, 25 Mbps IDDI (25) 5 V/3 V Operation 2.2 3.5 mA 12.5 MHz logic signal frequency 3 V/5 V Operation 2.0 2.8 mA 12.5 MHz logic signal frequency Output Supply Current1, 25 Mbps IDDO (25) 5 V/3 V Operation 0.3 0.7 mA 12.5 MHz logic signal frequency 3 V/5 V Operation 0.5 1.0 mA 12.5 MHz logic signal frequency Input Supply Current, 50 Mbps IDDI (50) 5 V/3 V Operation 4.5 7.0 mA 25 MHz logic signal frequency 3 V/5 V Operation 4.0 6.0 mA 25 MHz logic signal frequency Output Supply Current1, 50 Mbps IDDO (50) 5 V/3 V Operation 1.2 1.6 mA 25 MHz logic signal frequency 3 V/5 V Operation 1.0 1.5 mA 25 MHz logic signal frequency Input Currents IIA −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2 Logic High Output Voltage VOH VDD2 − 0.1 3.3 V IO = −20 μA, VI = VIH 5 V/3 V Operation VDD2 − 0.5 3.0 V IO = −2.5 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 5 V/3 V Operation 0.04 0.1 V IO = 400 μA, VI = VIL 0.3 0.4 V IO = 2.5 mA, VI = VIL Logic High Output Voltage VOH VDD2 − 0.1 5.0 V IO = −20 μA, VI = VIH 3 V/5 V Operation VDD2 − 0.8 4.6 V IO = −4 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 3 V/5 V Operation 0.03 0.1 V IO = 400 μA, VI = VIL 0.3 0.8 V IO = 4 mA, VI = VIL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 20 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 50 Mbps CL = 15 pF, CMOS signal levels For All Grades Propagation Delay Time to Logic Low/High Output4, 5 tPHL, tPLH

5 V/3 V Operation (See Figure 9) 13 21 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation (See Figure 10) 16 26 ns CL = 15 pF, CMOS signal levels

Rev. I | Page 9 of 20 Parameter Symbol Min Typ Max Unit Test Conditions Pulse Width Distortion, |tPLH − tPHL|5 PWD 5 V/3 V Operation 0.5 2 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation 0.5 3 ns CL = 15 pF, CMOS signal levels Change in Pulse Width Distortion vs. Temperature6

5 V/3 V Operation 3 ps/°C CL = 15 pF, CMOS signal levels

3 V/5 V Operation 10 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew (Equal Temperature)5, 7 tPSK1

5 V/3 V Operation 12 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation 15 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew (Equal Temperature, Supplies)5, 7 tPSK2

5 V/3 V Operation 9 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation 12 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic Low/High Output8 |CML|, |CMH| 25 35 kV/μs VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current9 CPD1 5 V/3 V Operation 0.09 mA/Mbps 3 V/5 V Operation 0.08 mA/Mbps Output Dynamic Supply Current9 CPD2 5 V/3 V Operation 0.04 mA/Mbps 3 V/5 V Operation 0.02 mA/Mbps 1 Output supply current values are with no output load present. See and for information on supply current vari ation with logic signal frequency. See the section for guidance on calculating the input and output supply currents for a given data rate and output load. Figure 5 Figure 5 Figure 6 Figure 6 Power Consumption Power Consumption 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the section and th rough for information on the impact of given input rise/fall times on these parameters. Propagation Delay-Related Parameters Figure 14 Figure 18 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See and for information on supply current variation with logic signal frequency. See the section for guidance on calculating the input and output supply currents for a given data rate and output load.

Rev. I | Page 10 of 20 PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 R I-O 1012 Ω Capacitance (Input-to-Output)1 CI-O 1.0 pF f = 1 MHz Input Capacitance2 C I 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W Thermocouple located at center of package underside Package Power Dissipation PPD 240 mW 1 The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together. 2 Input capacitance is measured at Pin 2 (VI). REGULATORY INFORMATION The ADuM1100 is approved by the following organizations. Table 5. UL CSA VDE Recognized under 1577 component recognition program1 Approved under CSA Component Acceptance Notice #5A Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Single/basic insulation,

2500 V rms isolation voltage

Basic insulation per CSA 60950-1-03 and IEC 60950-1,

400 V rms (565 V peak) maximum working voltage

Reinforced insulation, 560 V peak File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1100 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.016 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table I) Maximum Working Voltage Compatible with

50 Years Service Life

VIORM 565 V peak Continuous peak voltage across the isolation barrier

tective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.

672 V peak

Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values

5 V Operation1, 2

3.3 V Operation1, 2

1 All voltages are relative to their respective ground. and Figure 20 for information on immunity to external magnetic fields.

1 All voltages are relative to their respective ground.

2 See Figure 2 for information on maximum allowable current for various

3 Refers to common-mode transients across the insulation barrier. may cause latch-up or permanent damage. Table 10. Truth Table (Positive Logic) 1 VO returns to VI state within 1 μs of power restoration. YYWW is the date code, and XXXXXX is the lot code. Figure 3. Package Branding

Figure 4. Pin Configuration Table 11. Pin Function Descriptions 1 V DD1 Input Supply Voltage, 3.0 V to 5.5 V. 3 V DD1 Input Supply Voltage, 3.0 V to 5.5 V. 4 GND 1 Input Ground Reference. 5 GND 2 Output Ground Reference. 7 GND 2 Output Ground Reference. 8 V DD2 Output Supply Voltage, 3.0 V to 5.5 V.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 21. 8-Lead Standard Small Outline Package [SOIC_N]

Rev. I | Page 20 of 20 NOTES ©2001–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02462-0-3/12(I)