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ISO721M-EP TI | Alldatasheet

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www.ti.com SLLS882 JUNE 2008 3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS Signaling Rate Mbps to 150 Mbps Controlled Baseline Low Propagation Delay One Assembly Site Low Pulse Skew (Pulse-Width Distortion) One Test Site Low-Power Sleep Mode One Fabrication Site High Electromagnetic Immunity Extended Temperature Performance of Low Input Current Requirement C to 125 C Failsafe Output Enhanced Diminishing Manufacturing Sources Drop-In Replacement for Most Opto and (DMS) Support Magnetic Isolators Enhanced Product-Change Notification Industrial Fieldbus Qualification Pedigree (1) Modbus 4000-V (peak) Isolation Profibus UL 1577, IEC 60747-5-2 (VDE 0884, Rev. DeviceNet Data Buses IEC 61010-1 Smart Distributed Systems SDS 50-kV/ µ s Transient Immunity Typical Computer Peripheral Interface (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an Servo Control Interface extended temperature range. This includes, but is not limited Data Acquisition to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated by a silicon oxide (SiO insulation barrier. This barrier provides galvanic isolation of up to 4000 Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground, and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than µ the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. SDS is a trademark of Honeywell. DeviceNet is a trademark of Open Devicenet Vendors Association, Inc. UNLESS OTHERWISE NOTED this document contains Copyright 2008, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Pulse□Width Demodulation Carrier□Detect Input Filter Data□MUX AC□Detect 3-State Output□Buffer IN EN Isolation□Barrier DC□Channel AC□Channel FUNCTION DIAGRAM OUT Vref POR ISO721M-EP SLLS882 JUNE 2008 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching, and allows fast transient voltage changes between the input and output grounds without corrupting the output. The small capacitance and resulting time constant provide for fast operation with signaling rates (2) from Mbps (dc) to 100 Mbps for the ISO721/ISO722, and Mbps to 150 Mbps with the ISO721M/ISO722M. These devices require two supply voltages of 3.3 or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS. The ISO721 has TTL input thresholds and a noise-filter at the input that prevents transient pulses of up to ns in duration from being passed to the output of the device. The ISO721M has CMOS V CC input thresholds, but do not have the noise filter and the additional propagation delay. These operation. The ISO721M is characterized for operation over the ambient temperature range of C to 125 (2) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

www.ti.com SLLS882 JUNE 2008 D PACKAGE D PACKAGE ISO721, ISO721M ISO722, ISO722M (TOP VIEW) (TOP VIEW) AVAILABLE OPTIONS (1) OUTPUT INPUT NOISE TOP-SIDE PRODUCT (2) PACKAGE ORDERING NUMBER GREEN ENABLED THRESHOLDS FILTER MARKING ISO721 (3) NO TTL YES SOIC-8 ISO721M NO CMOS NO SOIC-8 721MEP ISO721MMDREP (reel) Pb Free Sb/Br Free ISO722 (3) YES TTL YES SOIC-8 ISO722M (3) YES CMOS NO SOIC-8 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging (3) Product Preview REGULATORY INFORMATION VDE CSA UL Approved under CSA Component Recognized under 1577 Certified according to IEC 60747-5-2 Acceptance Notice: CA-5A Component Recognition Program (1) File Number: 40014131 File Number: 1698195 File Number: E181974 (1) Production tested 3000 V RMS for second in accordance with UL 1577. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

(1) RECOMMENDED OPERATING CONDITIONS IEC 60747-5-2 INSULATION CHARACTERISTICS (1) ISO721M-EP SLLS882 JUNE 2008 www.ti.com UNIT V CC Supply voltage (2) V CC1 V CC2 0.5 V to V V I Voltage at IN, OUT, or EN terminal 0.5 V to V I O Output Current mA Human-Body Model JEDEC Standard 22, Test Method A114-C.01 kV Electrostatic ESD All pins discharge Charged-Device Model JEDEC Standard 22, Test Method C101 kV T J Maximum junction temperature 170 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms values are not listed in this publication. MIN TYP MAX UNIT 4.5 5.5 V CC Supply voltage, V CC1 V CC2 V 3.6 I OH High-level output current mA I OL Low-level output current ISO72x t ui Input pulse width ns ISO72xM 6.67 V IH High-level input voltage (IN, EN V CC ISO72x V V IL Low-level input voltage (IN, EN 0.8 V IH High-level input voltage (IN, EN 0.7 V CC V CC IOS72xM V V IL Low-level input voltage (IN, EN 0.3 V CC T J Junction temperature See the Thermal Characteristics table 150 C External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9 H 1000 A/m certification over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SPECIFICATIONS UNIT V IORM Maximum working insulation voltage 560 V After Input/Output Safety Test Subgroup V PR V IORM 1.2, t 672 V Partial discharge pC Method V PR V IORM 1.6, V PR Input to output test voltage Type and sample test with t 896 V Partial discharge pC Method b1, V PR V IORM 1.875, 100 Production test with t 1050 V Partial discharge pC V IOTM Transient overvoltage t s 4000 V R S Insulation resistance V IO 500 V at T S Ω Pollution degree (1) Climatic Classification 40/125/21 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

CHARACTERISTICS: V CC1 and V CC2 V OPERATION SWITCHING CHARACTERISTICS: V CC1 and V CC2 V OPERATION ISO721M-EP www.ti.com SLLS882 JUNE 2008 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Quiescent 0.5 I CC1 V CC1 supply current V I V CC or No load mA Mbps Quiescent V I V CC or No load I CC2 V CC2 supply current mA Mbps V I V CC or No load I OH mA, See Figure V CC 0.8 4.6 V OH High-level output voltage V I OH µ See Figure V CC 0.1 I OL mA, See Figure 0.2 0.4 V OL Low-level output voltage V I OL µ See Figure 0.1 V I(HYS) Input voltage hysteresis 150 mV I IH High-level input current IN at V µ A I IL Low-level input current IN at 0.8 V High-impedance output I OZ ISO722, ISO722M EN IN at V CC µ A current C I Input capacitance to ground IN at V CC V I 0.4 sin (4E6 π pF CMTI Common-mode transient immunity V I V CC or See Figure kV/ µ s over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH Propagation delay, low-to-high-level output t PHL Propagation delay high-to-low-level output ISO72x ns t sk(p) Pulse skew PHL t PLH 0.5 EN at See Figure t PLH Propagation delay, low-to-high-level output t PHL Propagation delay, high-to-low-level output ISO721M t sk(p) Pulse skew PHL t PLH 0.5 t sk(pp) (1) Part-to-part skew ns t r Output signal rise time EN at ns See Figure t f Output signal fall time Sleep-mode propagation delay, t pHZ ns high-level-to-high-mpedance output See Figure Sleep-mode propagation delay, t pZH µ s high-impedance-to-high-level output ISO722 ISO722M Sleep-mode propagation delay, t pLZ ns low-level-to-high-impedance output See Figure Sleep-mode propagation delay, t pZL µ s high-impedance-to-low-level output t fs Failsafe output delay time from input power loss See Figure µ s 100 Mbps NRZ data input, See Figure ISO72x 100 Mbps unrestricted bit run length data input, See Figure t jit(PP) Peak-to-peak eye-pattern jitter ns 150 Mbps NRZ data input, See Figure ISO72xM 150 Mbps unrestricted bit run length data input, See Figure (1) t sk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

CHARACTERISTICS: V CC1 at V CC2 at 3.3 V OPERATION SWITCHING CHARACTERISTICS: V CC1 at V CC2 at 3.3 V OPERATION ISO721M-EP SLLS882 JUNE 2008 www.ti.com over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Quiescent 0.5 I CC1 V CC1 supply current V I V CC or No load mA Mbps Quiescent V I V CC or No load 6.5 I CC2 V CC2 supply current mA Mbps V I V CC or No load 7.5 I OH mA, See Figure V CC 0.4 V OH High-level output voltage V I OH µ See Figure V CC 0.1 3.3 I OL mA, See Figure 0.2 0.4 V OL Low-level output voltage V I OL µ See Figure 0.1 V I(HYS) Input voltage hysteresis 150 mV I IH High-level input current IN at V µ A I IL Low-level input current IN at 0.8 V High-impedance output I OZ ISO722, ISO722M EN IN at V CC µ A current C I Input capacitance to ground IN at V CC V I 0.4 sin (4E6 π pF CMTI Common-mode transient immunity V I V CC or See Figure kV/ µ s over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH Propagation delay, low-to-high-level output t PHL Propagation delay high-to-low-level output ISO72x ns t sk(p) Pulse skew PHL t PLH 0.5 EN at See Figure t PLH Propagation delay, low-to-high-level output t PHL Propagation delay, high-to-low-level output ISO721M t sk(p) Pulse skew PHL t PLH 0.5 t sk(pp) (1) Part-to-part skew ns t r Output signal rise time EN at ns See Figure t f Output signal fall time Sleep-mode propagation delay, t pHZ ns high-level-to-high-mpedance output See Figure Sleep-mode propagation delay, t pZH µ s high-impedance-to-high-level output ISO722 ISO722M Sleep-mode propagation delay, t pLZ ns low-level-to-high-impedance output See Figure Sleep-mode propagation delay, t pZL µ s high-impedance-to-low-level output t fs Failsafe output delay time from input power loss See Figure µ s 100 Mbps NRZ data input, See Figure ISO72x 100 Mbps unrestricted bit run length data input, See Figure t jit(PP) Peak-to-peak eye-pattern jitter ns 150 Mbps NRZ data input, See Figure ISO72xM 150 Mbps unrestricted bit run length data input, See Figure (1) t sk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

CHARACTERISTICS: V CC1 at 3.3 V CC2 at V OPERATION SWITCHING CHARACTERISTICS: V CC1 at 3.3 V CC2 at V OPERATION ISO721M-EP www.ti.com SLLS882 JUNE 2008 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Quiescent 0.3 0.5 I CC1 V CC1 supply current V I V CC or No load mA Mbps Quiescent V I V CC or No load I CC2 V CC2 supply current mA Mbps V I V CC or No load I OH mA, See Figure V CC 0.8 4.6 V OH High-level output voltage V I OH µ See Figure V CC 0.1 I OL mA, See Figure 0.2 0.4 V OL Low-level output voltage V I OL µ See Figure 0.1 V I(HYS) Input voltage hysteresis 150 mV I IH High-level input current IN at V µ A I IL Low-level input current IN at 0.8 V High-impedance output I OZ ISO722, ISO722M EN IN at V CC µ A current C I Input capacitance to ground IN at V CC V I 0.4 sin (4E6 π pF CMTI Common-mode transient immunity V I V CC or See Figure kV/ µ s over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH Propagation delay, low-to-high-level output t PHL Propagation delay high-to-low-level output ISO72x ns t sk(p) Pulse skew PHL t PLH 0.5 EN at See Figure t PLH Propagation delay, low-to-high-level output t PHL Propagation delay, high-to-low-level output ISO721M t sk(p) Pulse skew PHL t PLH 0.5 t sk(pp) (1) Part-to-part skew ns t r Output signal rise time EN at ns See Figure t f Output signal fall time Sleep-mode propagation delay, t pHZ ns high-level-to-high-mpedance output See Figure Sleep-mode propagation delay, t pZH µ s high-impedance-to-high-level output ISO722 ISO722M Sleep-mode propagation delay, t pLZ ns low-level-to-high-impedance output See Figure Sleep-mode propagation delay, t pZL µ s high-impedance-to-low-level output t fs Failsafe output delay time from input power loss See Figure µ s 100 Mbps NRZ data input, See Figure ISO72x 100 Mbps unrestricted bit run length data input, See Figure t jit(PP) Peak-to-peak eye-pattern jitter ns 150 Mbps NRZ data input, See Figure ISO72xM 150 Mbps unrestricted bit run length data input, See Figure (1) t sk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

CHARACTERISTICS: V CC1 and V CC2 at 3.3 V OPERATION SWITCHING CHARACTERISTICS: V CC1 and V CC2 at 3.3 V OPERATION ISO721M-EP SLLS882 JUNE 2008 www.ti.com over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Quiescent 0.3 0.5 I CC1 V CC1 supply current V I V CC or No load mA Mbps Quiescent V I V CC or No load 6.5 I CC2 V CC2 supply current mA Mbps V I V CC or No load 7.5 I OH mA, See Figure V CC 0.4 V OH High-level output voltage V I OH µ See Figure V CC 0.1 3.3 I OL mA, See Figure 0.2 0.4 V OL Low-level output voltage V I OL µ See Figure 0.1 V I(HYS) Input voltage hysteresis 150 mV I IH High-level input current IN at V µ A I IL Low-level input current IN at 0.8 V High-impedance output I OZ ISO722, ISO722M EN IN at V CC µ A current C I Input capacitance to ground IN at V CC V I 0.4 sin (4E6 π pF CMTI Common-mode transient immunity V I V CC or See Figure kV/ µ s over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH Propagation delay, low-to-high-level output t PHL Propagation delay high-to-low-level output ISO72x ns t sk(p) Pulse skew PHL t PLH 0.5 EN at See Figure t PLH Propagation delay, low-to-high-level output t PHL Propagation delay, high-to-low-level output ISO721M t sk(p) Pulse skew PHL t PLH 0.5 t sk(pp) (1) Part-to-part skew ns t r Output signal rise time EN at ns See Figure t f Output signal fall time Sleep-mode propagation delay, t pHZ ns high-level-to-high-mpedance output See Figure Sleep-mode propagation delay, t pZH µ s high-impedance-to-high-level output ISO722 ISO722M Sleep-mode propagation delay, t pLZ ns low-level-to-high-impedance output See Figure Sleep-mode propagation delay, t pZL µ s high-impedance-to-low-level output t fs Failsafe output delay time from input power loss See Figure µ s 100 Mbps NRZ data input, See Figure ISO72x 100 Mbps unrestricted bit run length data input, See Figure t jit(PP) Peak-to-peak eye-pattern jitter ns 150 Mbps NRZ data input, See Figure ISO72xM 150 Mbps unrestricted bit run length data input, See Figure (1) t sk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

• VO VIIO Input Generator VI NOTE A tftr 50% 0□V 50% VOH VOL 50 /c87 tPHLtPLH V /2CC1 V /2CC1 VCC1 90% 10% C Note□B L Input Generator NOTE A 50 /c87 OUT EN IN3□V ISOLA TION□BARRIER 0□V 0□V 50% 0.5□V VOH CL NOTE□B R =□1□k 1□%L /c87 /c177 tPZH VO VO V /2CC2V /2CC2 tPHZ VCC2VI VI VCC2 VO OUT EN IN 0□V ISOLA TION□BARRIER 0□V VO VI 0.5□V VOL 50%C NOTE□B L 50 /c87 VCC2 VCC2 V /2CC2V /2CC2 tPZL tPLZ Input Generator NOTE A VI ISO721M-EP www.ti.com SLLS882 JUNE 2008 Figure Switching Characteristic Test Circuit and Voltage Waveforms Figure ISO722 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms The input pulse is supplied by a generator having the following characteristics: PRR kHz, 50% duty cycle, t r ns, t f ns, Z O Ω C L pF and includes instrumentation and fixture capacitance within 20%. Figure ISO722 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

0□V ISOLA TION□BARRIER VI 0□V tfs 2.7□V 50% VOH VOL VCC1 VCC1 C 15□pF 20% L /c177 EN ISO722 and ISO722M ISOLA TION□BARRIER VCM VO V or 0□V CC VCC1 VCC2 IN OUT GND2 C 15□pF 20% L /c177 C =□0.1 F, I /c109 /c177 GND1 ISO721M-EP SLLS882 JUNE 2008 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) NOTE: V I transition time is 100 ns Figure Failsafe Delay Time Test Circuit and Voltage Waveforms NOTE: Pass/Fail criteria is no change in V O Figure Common-Mode Transient Immunity Test Circuit and Voltage Waveform Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

0□V VCC2/2 ISO721M-EP www.ti.com SLLS882 JUNE 2008 PARAMETER MEASUREMENT INFORMATION (continued) NOTE: Bit pattern run length is Transition Time is 800 ps. NRZ data input has no more than five consecutive ones or zeros. Figure Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

1□M/c87 Enable VCC2 500 /c87 VCC2 Output OUT IN 1□M/c87 Input VCC1 VCC1 500 /c87 VCC1 ISO721M-EP SLLS882 JUNE 2008 www.ti.com PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(101) Minimum air gap (Clearance) (1) Shortest terminal to terminal distance through air 4.8 mm Shortest terminal to terminal distance across the L(102) Minimum external tracking (Creepage) 4.3 mm package surface Tracking resistance (comparative tracking C TI DIN IEC 60112/VDE 0303 Part 175 V index) Minimum internal gap (internal clearance) Distance through insulation 0.008 mm Input to output, V IO 500 all pins on each side of the barrier tied together creating a two-terminal Ω device, T A 100 C R IO Isolation resistance Input to output, V IO 500 Ω 100 C T A T A max. Barrier capacitance C IO V I 0.4 sin (4E6 π pF Input-to-output C I Input capacitance to ground V I 0.4 sin (4E6 π pF (1) Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. IEC 60664-1 RATINGS TABLE PARAMETER TEST CONDITIONS SPECIFICATION Basic isolation group Material group IIIa Rated mains voltage 150 VRMS I-IV Installation classification Rated mains voltage 300 VRMS I-III Equivalent Input and Output Schematic Diagrams Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

Safety□Limiting□Current mA Case□Temperature C o V , =□3.6□VCC1 VCC2 V ,□V =□5.5□VCC1 CC2 ISO721M-EP www.ti.com SLLS882 JUNE 2008 Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply, and without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT θ JA 263 C/W, V I 5.5 T J 170 T A C 100 I S Safety input, output, or supply current mA θ JA 263 C/W, V I 3.6 T J 170 T A C 153 T S Maximum case temperature 150 C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. THERMAL CHARACTERISTICS (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-K Thermal Resistance (1) 263 C/W θ JA Junction-to-Air High-K Thermal Resistance (1) 125 C/W Junction-to-Board Thermal θ JB C/W Resistance Junction-to-Case Thermal θ JC C/W Resistance V CC1 V CC2 5.5 T J 150 ISO72x C L pF, Input a 100 Mbps 50% duty 159 cycle square wave P D Device Power Dissipation mW V CC1 V CC2 5.5 T J 150 ISO72xM C L pF, Input a 150 Mbps 50% duty 195 cycle square wave (1) Tested in accordance with the Low-K or High-K thermal metric definition of EIA/JESD51-3 for leaded surface mount packages. Figure θ JC THERMAL DERATING CURVE per IEC 60747-5-2 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

www.ti.com ISO721 (1) V CC1 V CC2 INPUT OUTPUT (IN) (OUT) H H PU PU L L Open H PD PU X H (1) PU powered up CC V); PD powered down CC 2.5 V), X irrelevant, H high Level; L low level ISO722 (1) V CC1 V CC2 INPUT ISO722/ISO722M OUTPUT (IN) OUTPUT ENABLE EN (OUT) H L or Open H L L or Open L PU PU X H Z Open L or Open H PD PU X L or Open H PD PU X H Z (1) PU powered up CC V); PD powered down CC 2.5 V), X irrelevant, H high Level; L low level Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

I Supply□Current − (mA ) CC RMS Signaling□Rate□(Mbps) V =□3.3□V, T CC1 V =□3.3□V, =□25 C, C =□15□pF CC2 A L o ICC2 ICC1 0 25 50 75 100 I Supply□Current − (mA ) CC RMS Signaling□Rate□(Mbps) V =□5□V, T CC1 V =□5□V, =□25 C, C =□15□pF CC2 A L o ICC2 ICC1 -40 -25 -10 5 20 35 50 65 80 95 110 125 Propagation□Delay − ns T Free-Air□Temperature CA o − − V =□3.3□V,CC1 V =□3.3□V, C =□15□pF, Air□Flow□at□7□cf/m CC2 L tPLH tPLH tPHL tPHL ISO72x ISO72xM -40 -25 -10 5 20 35 50 65 80 95 110 125 Propagation□Delay − ns T Free-Air□Temperature CA o − − V =□5□V,CC1 V =□5□V, C =□15□pF, Air□Flow□at□7□cf/m CC2 L tPLH tPLH tPHL tPHL ISO72x ISO72xM 1.1 1.05 1.15 1.2 1.25 1.3 1.35 1.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 V − V IT − Input□Voltage□Threshold T Free-Air□Temperature CA o − − Air□Flow□at□7□cf/m 5-V□(V )IT+ 5-V□(V )IT- 3.3-V□(V )IT+ 3.3-V□(V )IT- 1.4 1.7 1.6 1.5 1.8 1.9 2.1 2.2 2.3 2.4 2.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 V − V IT − Input□Voltage□Threshold T Free-Air□Temperature CA o − − 5-V□(V )IT+ 5-V□(V )IT- Air□Flow□at□7□cf/m 3.3-V□(V )IT- 3.3-V□(V )IT+ ISO721M-EP www.ti.com SLLS882 JUNE 2008 RMS SUPPLY CURRENT vs SIGNALING RATE RMS SUPPLY CURRENT vs SIGNALING RATE Figure Figure PROPAGATION DELAY vs FREE-AIR TEMPERATURE PROPAGATION DELAY vs FREE-AIR TEMPERATURE Figure 10. Figure 11. ISO72x INPUT THRESHOLD VOLTAGE vs ISO72xM INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure 12. Figure 13. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

-10 -20 -30 -40 -50 -80 -60 -70 0 1 2 3 4 5 6 I High-Level□Output□Current − mAOH V -Level□Output□VoltageOH − High − V TA =□25 C o V =□5□VCC V =□3.3□VCC 2.78 2.82 2.8 2.84 2.86 2.88 2.9 2.92 -40 -25 -10 5 20 35 50 65 80 95 110 125 V Failsafe − V CC Voltage T Free-Air□Temperature CA o − − Vfs+ Vfs- C =□15□pF, Air□Flow□at□7□cf/m L 0 1 2 3 4 5 I Low-Level□Output□Current − mAOL V Low-Level□Output□VoltageOL − − V TA =□25 C o V =□5□VCC V =□3.3□VCC ISO721M-EP SLLS882 JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) V CC1 FAILSAFE THRESHOLD VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT FREE-AIR TEMPERATURE VOLTAGE Figure 14. Figure 15. LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE Figure 16. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

VCC1 VDD1 * GND1 GND1 GND1 VCC2 VDD2 VDD2 VDD2 VOE OUT VO VO GND2 GND2 GND2 ISO722 or ISO722M ADuM1100 Isolation Isolation Isolation GND2 VCC1 IN VCC1 GND1 VCC2 OUT GND2 ISO721 or ISO721M Isolation 4 5 ISO721 or ISO721M VCC1 VCC2 IN OUT GND1 GND2 INPUT OUTPUT 0.1/c109F0.1/c109F 20 mm max . from Vcc1 20 mm max. from Vcc2 ISO721M-EP www.ti.com SLLS882 JUNE 2008 The ISO72xx isolators have the same functional pinout as most other vendors, and they are often pin-for-pin drop-in replacements. The notable differences in the products are propagation delay, signaling rate, power consumption, and transient protection rating. Table is used as a guide for replacing other isolators with the ISO72x family of single channel isolators. Figure 17. Pin Cross Reference Table CROSS REFERENCE PIN ISO721 ISO722 ISOLATOR PIN PIN PIN PIN PIN PIN PIN OR OR ISO721M ISO722M ISO721 (1) (2) V CC1 IN V CC1 GND1 GND2 OUT GND2 EN V CC2 ADuM1100 (1) (2) V DD1 V I V DD1 GND1 GND2 V O GND2 V DD2 *Leave HCPL-xxxx V DD1 V I GND1 GND2 V O NC (4) V DD2 Open (3) IL710 V DD1 V I NC (5) GND1 GND2 V O V OE V DD2 (1) The ISO72xx pin and pin are internally connected together. Either or both may be used as V CC1 (2) The ISO721 and ISO721M pin and pin are internally connected together. Either or both may be used as GND2. (3) Pin of the HCPL devices must be left open. This is not a problem when substituting an ISO72xx device since the extra V CC1 on pin may be left an open circuit as well. (4) An HCPL device PIN must be left floating (open) or grounded when an ISO722 or ISO722M device is to be used as a drop-in replacement. If pin of the ISO722 or ISO722M device is placed in a high logic state, the output of the device is disabled (5) Pin of the IL710 must not be tied to ground on the circuit board since this shorts the ISO72xx s V CC1 to ground. The IL710 pin may only be tied to V CC or left open to drop in an ISO72xx. Figure 18. Basic Application Circuit Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

www.ti.com Creepage Distance The shortest path between two conductive input-to-output leads measured along the surface of the insulation. The shortest distance path is found around the end of the package body. Clearance The shortest distance between two conductive input-to-output leads measured through air (line of sight). Input-to-Output Barrier Capacitance The total capacitance between all input terminals connected together, and all output terminals connected together. Input-to-Output Barrier Resistance The total resistance between all input terminals connected together, and all output terminals connected together. Primary Circuit An internal circuit directly connected to an external supply mains or other equivalent source that supplies the primary circuit electric power. Secondary Circuit A circuit with no direct connection to primary power, and derives its power from a separate isolated source. Comparative Tracking Index (CTI) CTI is an index used for electrical insulating materials. It is defined as the numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that produces a partially conducting path of localized deterioration on or through the surface of an insulating material as a result of the action of electric discharges on or close to an insulation surface the higher CTI value of the insulating material, the smaller the minimum creepage distance. Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track between points of different potential. This process is known as tracking Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ISO721M-EP

Insulation: Pollution Degree: Installation Category: ISO721M-EP www.ti.com SLLS882 JUNE 2008 Operational insulation Insulation needed for the correct operation of the equipment. Basic insulation Insulation to provide basic protection against electric shock. Supplementary insulation Independent insulation applied in addition to basic insulation in order to ensure protection against electric shock in the event of a failure of the basic insulation. Double insulation Insulation comprising both basic and supplementary insulation. Reinforced insulation A single insulation system which provides a degree of protection against electric shock equivalent to double insulation. Pollution Degree No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence. Pollution Degree Normally, only nonconductive pollution occurs. However, a temporary conductivity caused by condensation must be expected. Pollution Degree Conductive pollution occurs or dry nonconductive pollution occurs, which becomes conductive due to condensation that is to be expected. Pollution Degree Continuous conductivity occurs due to conductive dust, rain, or other wet conditions. Overvoltage Category This section is directed at insulation co-ordination by identifying the transient overvoltages that may occur, and by assigning four different levels as indicated in IEC 60664. Signal Level Special equipment or parts of equipment. Local Level Portable equipment etc. Distribution Level Fixed installation Primary Supply Level Overhead lines, cable systems Each category should be subject to smaller transients than the category above. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO721M-EP

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) ISO721MMDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/08627-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO721MMDREP SOIC D 8 2500 533.4 346.0 36.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2008 Pack Materials-Page 2

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