ADUM1100

ADuM1100 (Rev.L)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 19

Technical content

Rev. L DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►High data rate: dc to 100 Mbps (NRZ) ►Compatible with 3.3 V and 5.0 V operation/level translation ►125°C maximum operating temperature ►Low power operation ►5 V operation ►1.0 mA maximum @ 1 Mbps ►4.5 mA maximum @ 25 Mbps ►16.8 mA maximum @ 100 Mbps ►3.3 V operation ►0.4 mA maximum @ 1 Mbps ►3.5 mA maximum @ 25 Mbps ►7.1 mA maximum @ 50 Mbps ►8-lead SOIC_N package (RoHS compliant version available) ►High common-mode transient immunity: >25 kV/μs ►Safety and regulatory approvals ►UL 1577 ►VISO = 2500 V rms for 1 minute ►IEC/EN/CSA 62368-1 ►IEC/CSA 61010-1 ►CQC GB 4943.1 ►DIN EN IEC 60747-17 (VDE 0884-17) ►VIORM = 560 V peak

APPLICATIONS

►Digital field bus isolation ►Opto-isolator replacement ►Computer peripheral interface ►Microprocessor system interface ►General instrumentation and data acquisition applications GENERAL DESCRIPTION The ADuM11001 is a digital isolator based on Analog Devices Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives, such as optocoupler devices. Configured as a pin-compatible replacement for existing high speed optocouplers, the ADuM1100 supports data rates as high as 25 Mbps and 100 Mbps. The ADuM1100 operates with a voltage supply ranging from 3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compatible with temperatures up to 125°C. It operates at very low power, less than 0.9 mA of quiescent current (sum of both sides), and a dynamic current of less than 160 μA per Mbps of data rate. Unlike other optocoupler alternatives, the ADuM1100 provides dc correctness with a patented refresh feature that continuously updates the output signal. The ADuM1100 is offered in three grades. The ADuM1100AR and ADuM1100BR can operate up to a maximum temperature of 105°C and support data rates up to 25 Mbps and 100 Mbps, respectively. The ADuM1100UR can operate up to a maximum temperature of 125°C and supports data rates up to 100 Mbps. FUNCTIONAL BLOCK DIAGRAM Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578; 6,873,065; 7,075,329.

analog.com Rev. L | 2 of 19 Electrical Specifications—Mixed 5 V/3 V or DIN EN IEC 60747-17 (VDE 0884-17) Method of Operation, DC Correctness, and Maximum Data Rate (Mbps) and Minimum

REVISION HISTORY

1/2025—Rev. K to Rev. L Changed DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics Section to DIN Changes to DIN EN IEC 60747-17 (VDE 0884-17) Insulation Characteristics Section, Table 7, and

analog.com Rev. L | 3 of 19 ELECTRICAL SPECIFICATIONS—5 V OPERATION the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current IDD1 (Q) 0.3 0.8 mA VI = 0 V or VDD1 Output Supply Current IDD2 (Q) 0.01 0.06 mA VI = 0 V or VDD1 Input Supply Current (25 Mbps) (See Figure 5) IDD1 (25) 2.2 3.5 mA 12.5 MHz logic signal frequency Output Supply Current1 (25 Mbps) (See Figure 6) IDD2 (25) 0.5 1.0 mA 12.5 MHz logic signal frequency Input Supply Current (100 Mbps) (See Figure 5) IDD1 (100) 9.0 14 mA 50 MHz logic signal frequency, ADuM1100BR/ ADuM1100UR only Output Supply Current1 (100 Mbps) (See Figure 6) IDD2 (100) 2.0 2.8 mA 50 MHz logic signal frequency, ADuM1100BR/ ADuM1100UR only Input Current II −10 +0.01 +10 µA 0 V ≤ VIN ≤ VDD1 Logic High Output Voltage VOH VDD2 − 0.1 5.0 V IO = −20 μA, VI = VIH VDD2 − 0.8 4.6 V IO = −4 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 0.03 0.1 V IO = 400 μA, VI = VIL 0.3 0.8 V IO = 4 mA, VI = VIL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 6.7 10 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 100 150 Mbps CL = 15 pF, CMOS signal levels For All Grades Propagation Delay Time to Logic Low Output4, 5 (See Figure 7) tPHL 10.5 18 ns CL = 15 pF, CMOS signal levels Propagation Delay Time to Logic High Output4, 5 (See Figure 7) tPLH 10.5 18 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature6 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature)5, 7 tPSK1 8 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature, Supplies)5, 7 tPSK2 6 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic Low/High Output8 |CML|, | CMH| 25 35 kV/µs VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current9 IDDI (D) 0.09 mA/Mbps Output Dynamic Supply Current9 IDDO (D) 0.02 mA/Mbps 1 Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

analog.com Rev. L | 4 of 19 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

analog.com Rev. L | 5 of 19 ELECTRICAL SPECIFICATIONS—3.3 V OPERATION the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current IDD1 (Q) 0.1 0.3 mA VI = 0 V or VDD1 Output Supply Current IDD2 (Q) 0.005 0.04 mA VI = 0 V or VDD1 Input Supply Current (25 Mbps) (See Figure 5) IDD1 (25) 2.0 2.8 mA 12.5 MHz logic signal frequency Output Supply Current1 (25 Mbps) (See Figure 6) IDD2 (25) 0.3 0.7 mA 12.5 MHz logic signal frequency Input Supply Current (50 Mbps) (See Figure 5) IDD1 (50) 4.0 6.0 mA 25 MHz logic signal frequency, ADuM1100BR/ ADuM1100UR only Output Supply Current1 (50 Mbps) (See Figure 6) IDD2 (50) 1.2 1.6 mA 25 MHz logic signal frequency, ADuM1100BR/ ADuM1100UR only Input Current II −10 +0.01 +10 µA 0 V ≤ VIN ≤ VDD1 Logic High Output Voltage VOH VDD2 − 0.1 3.3 V IO = −20 μA, VI = VIH VDD2 − 0.5 3.0 V IO = −2.5 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 0.04 0.1 V IO = 400 μA, VI = VIL 0.3 0.4 V IO = 2.5 mA, VI = VIL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 10 20 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 50 100 Mbps CL = 15 pF, CMOS signal levels For All Grades Propagation Delay Time to Logic Low Output4, 5 (See Figure 8) tPHL 14.5 28 ns CL = 15 pF, CMOS signal levels Propagation Delay Time to Logic High Output4, 5 (See Figure 8) tPLH 15.0 28 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion |tPLH − tPHL|5 PWD 0.5 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature6 10 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature)5, 7 tPSK1 15 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew (Equal Temperature, Supplies)5, 7 tPSK2 12 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic Low/High Output8 |CML|, | CMH| 25 35 kV/µs VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current9 IDDI (D) 0.08 mA/Mbps Output Dynamic Supply Current9 IDDO (D) 0.04 mA/Mbps 1 Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

analog.com Rev. L | 6 of 19 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

analog.com Rev. L | 7 of 19 ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, Quiescent IDDI (Q) 5 V/3 V Operation 0.3 0.8 mA 3 V/5 V Operation 0.1 0.3 mA Output Supply Current, Quiescent IDDO (Q) 5 V/3 V Operation 0.005 0.04 mA 3 V/5 V Operation 0.01 0.06 mA Input Supply Current, 25 Mbps IDDI (25) 5 V/3 V Operation 2.2 3.5 mA 12.5 MHz logic signal frequency 3 V/5 V Operation 2.0 2.8 mA 12.5 MHz logic signal frequency Output Supply Current1, 25 Mbps IDDO (25) 5 V/3 V Operation 0.3 0.7 mA 12.5 MHz logic signal frequency 3 V/5 V Operation 0.5 1.0 mA 12.5 MHz logic signal frequency Input Supply Current, 50 Mbps IDDI (50) 5 V/3 V Operation 4.5 7.0 mA 25 MHz logic signal frequency 3 V/5 V Operation 4.0 6.0 mA 25 MHz logic signal frequency Output Supply Current1, 50 Mbps IDDO (50) 5 V/3 V Operation 1.2 1.6 mA 25 MHz logic signal frequency 3 V/5 V Operation 1.0 1.5 mA 25 MHz logic signal frequency Input Currents IIA −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2 Logic High Output Voltage VOH VDD2 − 0.1 3.3 V IO = −20 μA, VI = VIH 5 V/3 V Operation VDD2 − 0.5 3.0 V IO = −2.5 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 5 V/3 V Operation 0.04 0.1 V IO = 400 μA, VI = VIL 0.3 0.4 V IO = 2.5 mA, VI = VIL Logic High Output Voltage VOH VDD2 − 0.1 5.0 V IO = −20 μA, VI = VIH 3 V/5 V Operation VDD2 − 0.8 4.6 V IO = −4 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 3 V/5 V Operation 0.03 0.1 V IO = 400 μA, VI = VIL 0.3 0.8 V IO = 4 mA, VI = VIL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 20 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 50 Mbps CL = 15 pF, CMOS signal levels For All Grades Propagation Delay Time to Logic Low/High Output4, 5 tPHL, tPLH

5 V/3 V Operation (See Figure 9) 13 21 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation (See Figure 10) 16 26 ns CL = 15 pF, CMOS signal levels

Table 3. (Continued) Change in Pulse Width Distortion vs.

5 V/3 V Operation 3 ps/°C CL = 15 pF, CMOS signal levels

3 V/5 V Operation 10 ps/°C CL = 15 pF, CMOS signal levels

5 V/3 V Operation 12 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation 15 ns CL = 15 pF, CMOS signal levels

5 V/3 V Operation 9 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation 12 ns CL = 15 pF, CMOS signal levels

Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. edge of the VI signal to the 50% level of the rising edge of the VO signal. input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature. temperature, supply voltages, and output load within the recommended operating conditions. which the common mode is slewed.

analog.com Rev. L | 9 of 19 PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 RI-O 1012 Ω Capacitance (Input-to-Output)1 CI-O 1.0 pF f = 1 MHz Input Capacitance2 CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1θJCI 46 °C/W Thermocouple located at center of package underside IC Junction-to-Case Thermal Resistance, Side 2θJCO 41 °C/W Package Power Dissipation PPD 240 mW 1 The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together. 2 Input capacitance is measured at Pin 2 (VI). REGULATORY INFORMATION The ADuM1100 certification approvals are listed in Table 5. Table 5. UL CSA CQC VDE UL 15771 IEC/EN/CSA 62368-1 CQC GB4943.1 DIN EN IEC 60747-17 (VDE 0884-17)2 Single Protection, 2500 V rmsBasic insulation, 400 V rms Basic insulation, 400 V rms Reinforced insulation, 560 V peak Reinforced insulation, 150 V rms Reinforced insulation, 150 V rms IEC/CSA 61010-1 Basic insulation, 300 V rms Reinforced insulation, 150 V rms File E214100 File No. 205078 Certificate No. CQC14001117247 Certificate No. 40011599 1 In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA). 2 In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM1100 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 41, 2 mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4 mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 18 μm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index)CTI >400 V DIN IEC 112/VDE 0303 Part 1 Material Group II Material Group per IEC 60664-1 1 In accordance with IEC 62368-1/IEC 60601-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 meters. 2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.

analog.com Rev. L | 11 of 19 RECOMMENDED OPERATING CONDITIONS Table 8. Parameter Symbol Min Max Unit Operating Temperature ADuM1100AR/ADuM1100BR TA −40 +105 °C ADuM1100UR TA −40 +125 °C Supply Voltages1 VDD1,VDD2 3.0 5.5 V Logic High Input Voltage, 5 V Operation1, 2 (See Figure 11 and Figure 12) VIH 2.0 VDD1 V Logic Low Input Voltage, 5 V Operation1, 2 (See Figure 11 and Figure 12) VIL 0.0 0.8 V Logic High Input Voltage, 3.3 V Operation1, 2 (See Figure 11 and Figure 12) VIH 1.5 VDD1 V Logic Low Input Voltage, 3.3 V Operation1, 2 (See Figure 11 and Figure 12) VIL 0.0 0.5 V Input Signal Rise and Fall Times 1.0 ms 1 All voltages are relative to their respective ground. 2 Input switching thresholds have 300 mV of hysteresis. See the Method of Operation, DC Correctness, and Magnetic Field Immunity section, Figure 19, and Figure 20 for information on immunity to external magnetic fields.

1 All voltages are relative to their respective ground.

2 See Figure 2 for information on maximum allowable current for various temper-

ing conditions for extended periods may affect product reliability. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality. Table 10. Truth Table (Positive Logic) 1 VO returns to VI state within 1 μs of power restoration. YYWW is the date code, and XXXXXX is the lot code. Figure 3. Package Branding

Figure 4. Pin Configuration Table 11. Pin Function Descriptions 1 VDD1 Input Supply Voltage, 3.0 V to 5.5 V. 3 VDD1 Input Supply Voltage, 3.0 V to 5.5 V. 4 GND1 Input Ground Reference. 5 GND2 Output Ground Reference. 7 GND2 Output Ground Reference. 8 VDD2 Output Supply Voltage, 3.0 V to 5.5 V.

Figure 11. Typical Input Voltage Switching Threshold, Low-to-High TransitionFigure 12. Typical Input Voltage Switching Threshold, High-to-Low Transition

©2015-2025 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. L | 19 of 19 Package Drawing (Option) Package Type Package Description R-8 SOIC_N 8-Lead Standard Small Outline Package, Narrow Body For the latest package outline information and land patterns (footprints), go to Package Index. ORDERING GUIDE Model1 Temperature Range Package Description Packing QuantityPackage Option ADuM1100AR −40°C to +105°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100AR-RL7 −40°C to +105°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100ARZ −40°C to +105°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100ARZ-RL7 −40°C to +105°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100BR −40°C to +105°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100BR-RL7 −40°C to +105°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100BRZ −40°C to +105°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100BRZ-RL7 −40°C to +105°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100UR −40°C to +125°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100UR-RL7 −40°C to +125°C 8-Lead SOIC_N Reel, 1000 R-8 ADuM1100URZ −40°C to +125°C 8-Lead SOIC_N Tube, 98 R-8 ADuM1100URZ-RL7 −40°C to +125°C 8-Lead SOIC_N Reel, 1000 R-8 1 Z = RoHS Compliant Part. MAXIMUM DATA RATE (MBPS) AND MINIMUM PULSE WIDTH (NS) OPTIONS Model1 Maximum Data Rate (Mbps) Minimum Pulse Width (ns) ADuM1100AR 25 40 ADuM1100AR-RL7 25 40 ADuM1100ARZ 25 40 ADuM1100ARZ-RL7 25 40 ADuM1100BR 100 10 ADuM1100BR-RL7 100 10 ADuM1100BRZ 100 10 ADuM1100BRZ-RL7 100 10 ADuM1100UR 100 10 ADuM1100UR-RL7 100 10 ADuM1100URZ 100 10 ADuM1100URZ-RL7 100 10 1 Z = RoHS Compliant Part.