ADuC7124BCPZ126-RL

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Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler ADuC7124 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved.

FEATURES

Multichannel, 12-bit, 1 MSPS ADC Up to 12 ADC channels Fully differential and single-ended modes

0 V to VREF analog input range

12-bit voltage output DACs

2 DAC outputs available

On-chip temperature sensor (±3°C) Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 41.78 MHz

41.78 MHz PLL with programmable divider

126 kB flash/EE memory, 32 kB SRAM In-circuit download, JTAG-based debug Software-triggered in-circuit reprogrammability Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs On-chip peripherals 2× fully I2C compatible channels SPI (20 MBPS in master mode, 10 MBPS in slave mode) With 4-byte FIFO on input and output stages 2× UART channels With 16-byte FIFO on input and output stages Up to 30 GPIO port All GPIOs are 5 V tolerant 4× general-purpose timers Watchdog timer (WDT) and wake-up timer Programmable logic array (PLA)

16 PLA elements

16-bit, 6-channel PWM Power supply monitor Power Specified for 3 V operation Active mode: 11 mA at 5 MHz, 50 mA at 41.78 MHz Packages and temperature range Fully specified for −40°C to +125°C operation 64-lead LFCSP Tools Low cost QuickStart development system Full third-party support

APPLICATIONS

Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking Patient monitoring

Rev. 0 | Page 2 of 96 TABLE OF CONTENTS

REVISION HISTORY

7/10—Revision 0: Initial Version

Rev. 0 | Page 3 of 96 GENERAL DESCRIPTION The ADuC7124 is a fully integrated, 1 MSPS, 12-bit data acquisition system incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional two inputs are available but are multiplexed with the two DAC output pins. The ADC can operate in single-ended or differential input mode. The ADC input voltage range is 0 V to VREF. A low drift band gap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. The DAC output range is programmable to one of three voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. The device operates from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI®, 16-bit/32-bit RISC machine, which offers up to 41 MIPS of peak performance. Thirty-two kilobytes of SRAM and 126 kB of nonvolatile Flash/EE memory are provided on-chip. The ARM7TDMI core views all memory and registers as a single linear array. The ADuC7124 contains an advanced interrupt controller. The vectored interrupt controller (VIC) allows every interrupt to be assigned a priority level. It also supports nested interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 nested interrupt levels are supported. On-chip factory firmware supports in-circuit download via the UART serial interface port or the I 2C port, while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting this MicroConverter® family. The part contains a 16-bit PWM with six output signals. For communication purposes, the part contains 2× I 2C channels that can be individually configured for master or slave mode. An SPI interface supporting both master and slave modes is also provided. Thirdly, 2× UART channels are provided. Each UART contains a configurable 16-bit FIFO with receive and transmit buffers. The part operates from 2.7 V to 3.6 V and is specified over an industrial temperature range of −40°C to +125°C. When operating at 41.78 MHz, the power dissipation is typically 120 mW . The ADuC7124 is available in a 64-lead LFCSP package. DETAILED BLOCK DIAGRAM 1MSPS 12-BIT ADC DAC0 DAC1 PWM EXTERNAL MEMORY INTERFACE ADuC7124 ADC0 XCLKI XCLKO RST VREF ADC12 MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA VECTORED INTERRUPT CONTROLLER

4 GENERAL-

8k × 32 SRAM 63k × 16 FLASH/EEPROM SPI, 2×I2C, 2×UART GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 09123-001 12-BIT DAC 12-BIT DAC Figure 1.

Rev. 0 | Page 4 of 96 SPECIFICATIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and fADC/2 ADC Power-Up Time 5 μs DC Accuracy1 , 2 Resolution 12 Bits Integral Nonlinearity ±0.6 ±1.5 LSB 2.5 V internal reference ±1.0 LSB 1.0 V external reference Differential Nonlinearity3, 4 ±0.5 +1/−0.9 LSB 2.5 V internal reference +0.7/−0.6 LSB 1.0 V external reference DC Code Distribution 1 LSB ADC input is a dc voltage. ENDPOINT ERRORS5 Offset Error ±1 ±2 LSB Offset Error Match ±1 LSB Gain Error ±4 LSB Gain Error Match ±1 LSB DYNAMIC PERFORMANCE fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS Signal-to-Noise Ratio (SNR) 69 dB Includes distortion and noise components Total Harmonic Distortion (THD) −78 dB Peak Harmonic or Spurious Noise −75 dB Channel-to-Channel Crosstalk −90 dB Measured on adjacent channels. Input channels not being sampled have a 25 kHz sine wave connected to them. ANALOG INPUT Input Voltage Ranges4 Differential Mode VCM 6 ± VREF/2 V Single-Ended Mode 0 to VREF V Leakage Current ±1 ±6 µA Input Capacitance 24 pF During ADC acquisition ON-CHIP VOLTAGE REFERENCE 0.47 µF from VREF to AGND Output Voltage 2.5 V Accuracy ±5 mV TA = 25°C Reference Temperature Coefficient ±15 ppm/°C Power Supply Rejection Ratio 80 dB Output Impedance 45 Ω TA = 25°C Internal VREF Power-On Time 1 ms EXTERNAL REFERENCE INPUT Input Voltage Range 0.625 AVDD V DAC CHANNEL SPECIFICATIONS RL = 5 kΩ, CL = 100 pF DC Accuracy7 Resolution 12 Bits Relative Accuracy ±2 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Offset Error ±17 mV 2.5 V internal reference Gain Error8 ±1.2 % Gain Error Mismatch 0.1 % % of full scale on DAC0

Rev. 0 | Page 5 of 96 Parameter Min Typ Max Unit Test Conditions/Comments ANALOG OUTPUTS Output Voltage Range 0 0 to DACREF V DACREF range: DACGND to DACVDD Output Voltage Range 1 0 to 2.5 V Output Voltage Range 2 0 to DACVDD V Output Impedance 0.5 Ω DAC IN OP AMP MODE DAC Output Buffer in Op Amp Mode Input Offset Voltage ±0.4 mV Input Offset Voltage Drift 4 µV/°C Input Offset Current 2 nA Input Bias Current 2.5 nA Gain 70 dB 5 kΩ load Unity Gain Frequency 4.5 MHz RL = 5 kΩ, CL = 100 pF CMRR 78 dB Settling Time 12 µs RL = 5 kΩ, CL = 100 pF Output Slew Rate 3.2 V/µs RL = 5 kΩ, CL = 100 pF PSRR 75 dB DAC AC CHARACTERISTICS Voltage Output Settling Time 10 µs Digital-to-Analog Glitch Energy ±10 nV-sec 1 LSB change at major carry (where maximum number of bits simultaneously change in the DACxDAT register) COMPARATOR Input Offset Voltage ±15 mV Input Bias Current 1 µA Input Voltage Range AGND AVDD – 1.2 V Input Capacitance 8.5 pF Hysteresis4, 6 2 15 mV Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register. Response Time 4 µs 100 mV overdrive and configured with CMPRES = 11 TEMPERATURE SENSOR Voltage Output at 25°C 1.415 V Voltage TC 3.914 mV/°C Accuracy ±3 °C A single point calibration is required. θJA Thermal Impedance 64-Lead LFCSP 24 °C/W POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection 2.79 V Two selectable trip points 3.07 V Power Supply Trip Point Accuracy ±2.5 % Of the selected nominal trip point voltage POWER-ON RESET 2.41 V WATCHDOG TIMER (WDT) Timeout Period 0 512 sec FLASH/EE MEMORY Endurance9 10,000 Cycles Data Retention10 20 Years TJ = 85°C DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO Logic 1 Input Current ±0.2 ±1 µA VIH = VDD or VIH = 5 V Logic 0 Input Current −40 −60 µA VIL = 0 V; except TDI, TDO, and RTCK −80 −120 µA VIL = 0 V; TDI, TDO, and RTCK Input Capacitance 5 pF

Rev. 0 | Page 6 of 96 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS3 All logic inputs excluding XCLKI VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 2.0 V LOGIC OUTPUTS All digital outputs excluding XCLKO VOH, Output High Voltage 2.4 V ISOURCE = 1.6 mA VOL, Output Low Voltage11 0.4 V ISINK = 1.6 mA CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 1.6 V XCLKI Input Capacitance 20 pF XCLKO Output Capacitance 20 pF INTERNAL OSCILLATOR 32.768 kHz ±3 % MCU CLOCK RATE4 From 32 kHz Internal Oscillator 326 kHz CD = 7 From 32 kHz External Crystal 41.78 MHz CD = 0 Using an External Clock 0.05 44 MHz TA = 85°C 0.05 41.78 MHz TA = 125°C START-UP TIME Core clock = 41.78 MHz At Power-On 66 ms From Pause/Nap Mode 2.6 µs CD = 0 247 µs CD = 7 From Sleep Mode 1.58 ms From Stop Mode 1.7 ms PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay 12 ns From input pin to output pin Element Propagation Delay 2.5 ns POWER REQUIREMENTS12, 13 Power Supply Voltage Range AVDD to AGND and IOVDD to IOGND 2.7 3.6 V Analog Power Supply Currents AVDD Current 165 µA ADC in idle mode DACVDD Current14 0.02 µA Digital Power Supply Current IOVDD Current in Normal Mode Code executing from Flash/EE 8.7 12.5 mA CD = 7 12 17 mA CD = 3 34 50 mA CD = 0 (41.78 MHz clock) IOVDD Current in Pause Mode 20 30 mA CD = 0 (41.78 MHz clock) IOVDD Current in Sleep Mode 110 µA TA = 85°C 600 680 µA TA = 125°C Additional Power Supply Currents ADC 1.26 mA at 1 MSPS 0.7 mA at 62.5 kSPS DAC 315 µA per DAC

Rev. 0 | Page 7 of 96 Parameter Min Typ Max Unit Test Conditions/Comments ESD TESTS 2.5 V reference, TA = 25°C HBM Passed Up To 3 kV FICDM Passed Up To 1.5 kV 1 All ADC channel specifications are guaranteed during normal core operation. 2 Apply to all ADC input channels. 3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN). 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 36. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 DAC linearity is calculated using a reduced code range of 100 to 3995. 8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 9 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 10 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 11 Test carried out with a maximum of eight I/Os set to a low output level. 12 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with 3.6 V supply, and sleep mode with 3.6 V supply. 13 IOVDD power supply current increases typically by 2 mA during a Flash/EE erase cycle. 14 This current must be added to the AVDD current.

Table 2. I2C Timing in Fast Mode (400 kHz) Table 3. I2C Timing in Standard Mode (100 kHz) Figure 2. I2C Compatible Interface Timing

Table 4. SPI Master Mode Timing (Phase Mode = 1) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Figure 3. SPI Master Mode Timing (Phase Mode = 1) Table 5. SPI Master Mode Timing (Phase Mode = 0) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

Table 7. SPI Slave Mode Timing (Phase Mode = 0) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Figure 6. SPI Slave Mode Timing (Phase Mode = 0)

Rev. 0 | Page 12 of 96 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GNDREF, TA = 25°C, unless otherwise noted. Table 8. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION Parameter Rating AVDD to IOVDD −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V IOVDD to IOGND, AVDD to AGND −0.3 V to +6 V Digital Input Voltage to IOGND −0.3 V to +5.3 V Digital Output Voltage to IOGND −0.3 V to IOVDD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.3 V Analog Inputs to AGND −0.3 V to AVDD + 0.3 V Analog Outputs to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range, Industrial –40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 64-Lead LFCSP 24°C/W Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) 240°C RoHS Compliant Assemblies (20 sec to 40 sec) 260°C

1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER

HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 7. Pin Configuration Table 9. Pin Function Descriptions 1 ADC4 Single-Ended or Differential Analog Input 4. 2 ADC5 Single-Ended or Differential Analog Input 5. 3 ADC6 Single-Ended or Differential Analog Input 6. 4 ADC7 Single-Ended or Differential Analog Input 7. 5 ADC8 Single-Ended or Differential Analog Input 8. 6 ADC9 Single-Ended or Differential Analog Input 9. 8 DACGND Ground for the DAC. Typically connected to AGND. 9 DACVDD 3.3 V Power Supply for the DACs. Must be connected to AVDD. 10 DAC0/ADC12 DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. 11 DAC1/ADC13 DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. 12 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. 13 TDI JTAG Test Port Input, Test Data In. 14 XCLKO Output from the Crystal Oscillator Inverter. 15 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.

Rev. 0 | Page 14 of 96 Pin No. Mnemonic Description 16 BM/P0.0/CMP OUT/PLAI[7] Multifunction I/O Pin. Boot mode. The ADuC7124 enters download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor. General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. 17 DGND Ground for Core Logic. 18 LV DD 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF capacitor to DGND only. 19 IOV DD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 20 IOGND Ground for GPIO. Typically connected to DGND. 21 P4.6/PLAO[14] General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14. 22 P4.7/PLAO[15] General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15. 23 P0.6/T1/MRST/PLAO[3] Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. 24 TCK JTAG Test Port Input, Test Clock. Debug and download access. 25 TDO JTAG Test Port Output, Test Data Out. 26 P3.0/PWM0/PLAI[8] General-Purpose Input and Output Port 3.0/PWM Phase 0/Output/Programmable Logic Array Input Element 8. 27 P3.1/PWM1/PLAI[9] General-Purpose Input and Output Port 3.1/PWM Phase 1/Programmable Logic Array Input Element 9. 28 P3.2/PWM2/PLAI[10] General-Purpose Input and Output Port 3.2/PWM Phase 2/Programmable Logic Array Input Element 10. 29 P3.3/PWM3/PLAI[11] General-Purpose Input and Output Port 3.3/PWM Phase 3/Programmable Logic Array Input Element 11. 30 P0.3/TRST/ADC BUSY General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. JTAG Reset input. Debug and download access. If this pin is held low, JTAG access is not possible because the JTAG interface is held in reset and P0.1/P0.2/P0.3 are configured as GPIO pins. 31 P3.4/PWM4/PLAI[12] General-Purpose Input and Output Port 3.4/PWM Phase 4/Programmable Logic Array Input 12. 32 P3.5/PWM5/PLAI[13] General-Purpose Input and Output Port 3.5/PWM Phase 5/Programmable Logic Array Input Element 13. 33 RST Reset Input, Active Low. 34 IRQ0/P0.4/PWM TRIP/PLAO[1] Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. 35 IRQ1/P0.5/ADC BUSY/PLAO[2] Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2. 36 P2.0/SPM9/PLAO[5]/CONVSTART/ SOUT0 Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC/UART0 Output. 37 P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0 Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/Programmable Logic Array Output Element 4/UART0 Input. 38 IOGND Ground for GPIO. Typically connected to DGND. 39 IOV DD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 40 P3.6/PWM TRIP/PLAI[14] General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array Input Element 14. 41 P3.7/PWM SYNC/PLAI[15] General-Purpose Input and Output Port 3.7/PWM Synchronization Input Output/Programmable Logic Array Input Element 15. 42 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. 43 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. 44 P4.0/PLAO[8]/SIN1 General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8/UART1 Input.

Rev. 0 | Page 15 of 96 Pin No. Mnemonic Description 45 P4.1/PLAO[9]/SOUT1 General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9/UART1 Output. 46 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. 47 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. 48 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. 49 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. 50 P1.1/SPM1/PLAI[1]/SOUT0 Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/Timer1 Input/I2C0/Programmable Logic Array Input Element 1/UART0 Output. 51 P1.0/T1/SPM0/PLAI[0]/SIN0 Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/I2C0/Programmable Logic Array Input Element 0/UART0 Input. 52 P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. 53 P4.3/PLAO[11] General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11. 54 P4.4/PLAO[12] General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12. 55 RTCK JTAG TEST port output, JTAG Return Test Clock. 56 V REF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. 57 DAC REF External Voltage Reference for the DACs. Range: DACGND to DACVDD. 58 AV DD 3.3 V Analog Power. 59 AGND Analog Ground. Ground reference point for the analog circuitry. 60 GND REF Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. 61 ADC0 Single-Ended or Differential Analog Input 0. 62 ADC1 Single-Ended or Differential Analog Input 1. 63 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input. 64 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.

Rev. 0 | Page 19 of 96 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale – 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes the output to settle to within a 1 LSB level for a full-scale input change.

of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with four additional features.

• T support for the Thumb® (16-bit) instruction set.
• D support for debug.
• M support for long multiplications.
• I includes the EmbeddedICE module to support embedded system debugging. THUMB MODE (T) An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16 bits, called the Thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the Thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the Thumb mode has two limitations:
• Thumb code typically requires more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of time-critical code.
• The Thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling. See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM Thumb instruction sets. LONG MULTIPLY (M) The ARM7TDMI instruction set includes four extra instrucions that perform 32-bit by 32-bit multiplication with a 64-bit result and 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result. These results are achieved in fewer cycles than required on a standard ARM7 core. EmbeddedICE (I) EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watch- point registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE, SRAM, and memory mapped registers. EXCEPTIONS ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are
• Normal interrupt or IRQ. This is provided to service general- purpose interrupt handling of internal and external events.
• Fast interrupt or FIQ. This is provided to service data transfers or communication channels with low latency. FIQ has priority over IRQ.
• Memory abort.
• Attempted execution of an undefined instruction.
• Software interrupt instruction (SWI). This can be used to make a call to an operating system. Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ. ARM REGISTERS ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15), and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All excep- tion modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in Figure 22. The fas t interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means that the interrupt processing can begin without the need to save or restore these registers, and therefore, save critical time in the interrupt handling process. 09123-007 USABLE IN USER MODE SYSTEM MODES ONLY SPSR_UNDSPSR_IRQSPSR_ABTSPSR_SVC R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_UND R14_UND R10 R11 R12 R13 R14 R15 (PC) R13_IRQ R14_IRQR13_ABT R14_ABTR13_SVC R14_SVC SPSR_FIQCPSR USER MODE FIQ MODE SVC MODE ABORT MODE IRQ MODE UNDEFINED MODE

Figure 22. Register Organization

Rev. 0 | Page 21 of 96 More information relative to the model of the programmer and the ARM7TDMI core architecture can be found in the following materials from ARM:

• DDI0029G, ARM7TDMI Technical Reference Manual
• DDI-0100, ARM Architecture Reference Manual INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following:
• The longest time the request can take to pass through the synchronizer
• The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC
• The time for the data abort entry
• The time for the FIQ entry At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 µs in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.

Figure 25. Memory Mapped Registers

Table 10. IRQ Base Address = 0xFFFF0000 Table 11. System Control Base Address = 0xFFFF0200 Table 12. Timer Base Address = 0xFFFF0300

Table 13. PLL/PSM Base Address = 0xFFFF0400 Table 14. PSM Base Address = 0xFFFF0440 Table 15. Reference Base Address = 0xFFFF0480 Table 16. ADC Base Address = 0xFFFF0500 Table 17. DAC Address Base = 0xFFFF0600

Table 18. UART0 Base Address = 0xFFFF0700 Table 19. UART1 Base Address = 0xFFFF0740 Table 20. I2C0 Base Address = 0xFFFF0800

Table 21. I2C1 Base Address = 0xFFFF0900 Table 22. SPI Base Address = 0xFFFF0A00 Table 23. PLA Base Address = 0xFFFF0B00

Table 24. GPIO Base Address = 0xFFFF0400 Table 25. Flash/EE Block 0 Base Address = 0xFFFFF800

Table 26. Flash/EE Block 1 Base Address = 0xFFFFF880 Table 27. PWM Base Address= 0xFFFF0F80

track-and-hold, an on-chip reference, and an ADC.

• Fully differential mode, for small and balanced signals
• Single-ended mode, for any single-ended signals
• Pseudo differential mode, for any single-ended signals, taking advantage of the common-mode rejection offered by the pseudo differential input The converter accepts an analog input range of 0 V to V REF when operating in single-ended or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage (VCM) in the 0 V to AVDD range with a maximum amplitude of 2 × VREF (see Figure 26). 09123-011 AVDD VCM VCM VCM 2VREF 2VREF 2VREF

Figure 26. Examples of Balanced Signals in Fully Differential Mode described in the Band Gap Reference section. that measures die temperature. used to generate a repetitive trigger for ADC conversions.

1 LSB = FS/4096, or

Figure 27. ADC Transfer Function in Pseudo Differential or Single-Ended Mode the signals applied to the VIN+ and VIN– pins (that is, VIN+ – VIN–). is, therefore, the voltage that the two inputs are centered on. (see the Driving the Analog Inputs section). input/output transfer characteristic is shown in Figure 28. Figure 28. ADC Transfer Function in Differential Mode

000 Enable CONVSTART pin as a conversion input. 001 Enable Timer1 as a conversion input. 010 Enable Timer0 as a conversion input. 100 Continuous software conversion. MMR is described in Table 29. Table 29. ADCCP1 MMR Bit Designation 4:0 Positive channel selection bits. 10001 AGND (self-diagnostic feature). 10010 Internal reference (self-diagnostic feature). MMR is described in Table 30. Table 30. ADCCN MMR Bit Designation 4:0 Negative channel selection bits. one bit, ADCReady (Bit 0), representing the status of the ADC.

1. If the ADCDAT value is less than 4094, ADCGN should be

incremented until ADCDAT reads Code 4094 to Code 4095. apply to the temperature sensor. and average them in this mode. The ADCCON register must be configured to 0x37A3. T is the temperature result. corresponds to TREF = 25°C as described in Table 1. determined by characterization data. K = 0.2555°C/mV . This corresponds to the 1/voltage Tc specification from Table 1. calibration at a controlled temperature value. For some users, it is not possible to get such a known pair. TREF = 25°C but is not guaranteed. VTREF can be calculated using the TEMPREF register. Table 32. TSCON MMR Bit Designations incorrect temperature sensor readings. This bit is cleared by default.

Table 33. TEMPREF MMR Bit Designations 8 Temperature reference voltage sign. 7 to 0 Temperature sensor offset calibration voltage. pin (VREF) and used as a reference for other circuits in the system. REFCON, described in Table 34. Table 34. REFCON MMR Bit Designations 1 Internal reference power-down bit. Clear this bit to enable the internal reference. This bit is cleared by default. 0 Internal reference output enable. component but must be buffered.

reprogrammable memory space. and more correctly referred to as Flash/EE memory. The ADuC7124 contains two 64 kB arrays of Flash/EE memory. memory are available to the user. using the serial download mode or the JTAG mode provided. cycling endurance and Flash/EE memory data retention.

1. Initial page erase sequence.
2. Read/verify sequence (single Flash/EE).
3. Byte program sequence memory.
4. Second read/verify sequence (endurance cycle).

supply temperature of 10,000 cycles. Figure 38. Flash/EE Memory Data Retention using the serial download mode or the provided JTAG mode. while the device is in-circuit in its target application hardware. happens, mass erase the part using the UART downloader.

pages, that is, 2 kB. Write protection is activated for all access types. block. All 32 bits of this are used to protect four pages at a time.

• Protection can be set and removed by writing directly into FEExHID MMR. This protection does not remain after reset.
• Protection can be set by writing into FEExPRO MMR. It takes effect only after a save protection command (0x0C) and a reset. The FEExPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEExPRO. A mass erase sets the key back to 0xFFFF but also erases all the user code.
• Flash can be permanently protected by using the FEExPRO MMR and a particular value of key: 0xDEADDEAD. Entering the key again to modify the FEExPRO register is not allowed. Sequence to Write the Key 1. Write the bit in FEExPRO corresponding to the page to be protected. 2. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 must equal 0). 3. Write a 32-bit key in FEExADR and FEExDAT. 4. Run the write key command 0x0C in FEExCON; wait for the read to be successful by monitoring FEExSTA. 5. Reset the part. To remove or modify the protection, the same sequence is used with a modified value of FEExPRO. If the key chosen is the value 0xDEAD, the memory protection cannot be removed. Only a mass erase unprotects the part, but it also erases all user code. The sequence to write the key is illustrated in the following example (this protects writing Page 4 to Page 7 of the Flash): FEExPRO=0xFFFFFFFD; //Protect Page 4 to Page 7 FEExMOD=0x48; //Write key enable FEExADR=0x1234; //16 bit key value FEExDAT=0x5678; //16 bit key value FEExCON= 0x0C; //Write key command The same sequence should be followed to protect the part permanently with FEExADR = 0xDEAD and FEExDAT = 0xDEAD. FLASH/EE CONTROL INTERFACE

Table 35. FEE0DAT Register FEE0DAT is a 16-bit data register. Table 36. FEE0ADR Register FEE0ADR is a 16-bit address register. Table 37. FEE0SGN Register FEE0SGN is a 24-bit code signature. Table 38. FEE0PRO Register FEE0PRO provides protection following subsequent reset MMR. It requires a software key (see Table 54). Table 39. FEE0HID Register require any software keys (see Table 54). Table 40. FEE1DAT Register FEE1DAT is a 16-bit data register. Table 41. FEE1ADR Register FEE1ADR is a 16-bit address register. Table 42. FEE1SGN Register FEE1SGN is a 24-bit code signature. Table 43. FEE1PRO Register FEE1PRO provides protection following subsequent reset MMR. It requires a software key (see Table 55).

Table 44. FEE1HID Register require any software keys (see Table 55). Table 45. FEE0STA Register Table 46. FEE1STA Register Table 47. FEE0MOD Register Table 48. FEE1MOD Register Table 49. FEE0CON Register Table 50. FEE1CON Register Table 51. FEExSTA MMR Bit Designations 3 Flash/EE interrupt status bit. Cleared when reading the FEExSTA register. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Set automatically when a command completes unsuccessfully. Cleared automatically when reading the FEExSTA register. Set by MicroConverter when a command is complete. Cleared automatically when reading the FEExSTA register.

Table 52. FEExMOD MMR Bit Designations 4 Flash/EE interrupt enable. Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by the user to disable the Flash/EE interrupt. 3 Erase/write command protection. Set by the user to enable the erase and write commands. Cleared to protect the Flash/EE memory against the erase/write command. 2 Reserved. Should always be set to 0 by the user. 1:0 Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect. Table 53. Command Codes in FEExCON 0x011 Single read Load FEExDAT with the 16-bit data indexed by FEExADR. 0x021 Single write Write FEExDAT at the address pointed to by FEExADR. This operation takes 50 µs. comparison is returned in FEExSTA Bit 1. 0x051 Single erase Erase the page indexed by FEExADR. execution, a command sequence is required to execute this instruction. 0x0B Signature Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles. 0x0F Ping No operation, interrupt generated. 1 The FEExCON register always reads 0x07 immediately after execution of any of these commands.

Table 54. FEE0PRO and FEE0HID MMR Bit Designations Cleared by the user to protect Block 0. Set by the user to allow reading of Block 0. to Page 116, and for Page 0 to Page 3. Cleared by the user to protect the pages in writing. Set by the user to allow writing to the pages. Table 55. FEE1PRO and FEE1HID MMR Bit Designations Cleared by the user to protect Block 1. Set by the user to allow reading of Block 1. 30 Write protection for Page 127 to Page 120. Cleared by the user to protect the pages in writing. Set by the user to allow writing to the pages. Cleared by the user to protect the pages in writing. Set by the user to allow writing to the pages. execution for applications where execution time is critical. two cycles to fill the pipeline with the new instructions. one cycle (as can be done from SRAM when the CD bit = 0). more complex and are summarized in Table 56. Table 56. Execution Cycles in ARM/Thumb Mode

1 The SWAP instruction combines an LD and STR instruction with only one

fetch, giving a total of eight cycles + 40 ns.

2 N is the number of data bytes to load or store in the multiple load/store

Figure 39. Remap for Exception Execution 32-bit wide SRAM instead of 16-bit wide Flash/EE memory.

Table 57. REMAP MMR Bit Designations (Address = of the array, because this is replaced by the SRAM. Address 0x00000000 by clearing Bit 0 of the REMAP MMR. Flash/EE memory at the bottom of the array. exception service routine to identify the source of the reset. If RSTSTA is null, the reset is external. state after a watchdog or software reset. Table 58. RSTSTA MMR Bit Designations Set by the user to force a software reset. Cleared by setting the corresponding bit in RSTCLR. Set automatically when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR. Value 0x07 to the RSTCLR register. 7:3 Reserved. Always set to 0.

2 This bit is set to 1 to configure the DAC outputs to

retain their state after a watchdog or software reset. return to their default state. 1 Reserved. Always set to 0.

0 This bit is set to 1 to configure the GPIO pins to retain

their state after a watchdog or software reset. return to their default state.

Table 59. RSTCFG Write Sequence

capable of driving 5 kΩ/100 pF . band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD. DACREF is equivalent to an external reference for the DAC. The signal range is 0 V to AVDD. (see Table 63) are described in detail in this section. Table 60. DACxCON Registers Table 61. DAC0CON MMR Bit Designations DAC using HCLK (core clock). 3 Reserved. This bit should be left at 0. 2 Reserved. This bit should be left at 0. Table 62. DACxDAT Registers Table 63. DAC0DAT MMR Bit Designations Figure 40. DAC Structure user selectable in software. It can be either AVDD, VREF, or DACREF. function spans from 0 V to the internal 2.5 V reference, VREF. and, in 0-to-AVDD mode only, Code 3995 to Code 4095. effects (neglecting offset and gain error) is illustrated in Figure 41. showing no signs of endpoint linearity errors.

Figure 41. Endpoint Nonlinearities Due to Amplifier Saturation the top or bottom (respectively) of Figure 41 become larger. work with an external 0.47 µF capacitor. Table 64. Reference Source Selection for the ADC and DAC 1 00 ADC works with an internal VREF. 1 11 ADC works with an internal VREF. DACs work with an internal AVDD. the ADC cannot use the internal VREF, even in Mode 1-xx. with the DAC itself disabled. Table 65. DACBCFG MMR Bit Designations 7:2 Reserved. Always set to 0.

1 Set this bit to 1 to configure the DAC1 output

0 Set this bit to 1 to configure the DAC0 output

resume until a safe supply level is established.

1 CMPORI Comparator output rising edge

0 CMPOFI Comparator output falling edge

when using an internal oscillator or external crystal. clock source to an external device without an external buffer. Figure 44. Clocking System default, the part uses the internal oscillator feeding the PLL.

1. Enable the Timer2 interrupt and configure it for a timeout
2. Follow the write sequence to the PLLCON register, setting

the MDCLK bits to 01 and clearing the OSEL bit.

1. Force the part into NAP mode by following the correct

write sequence to the POWCON0 register.

1. When the part is interrupted from NAP mode by the

halted, and this interrupt is serviced only when the lock is restored. came from the watchdog timer.

A choice of operating modes is available on the ADuC7124. modes and indicates the power-up time. Table 68. Operating Modes Table 69. Typical Current Consumption at 25°C in mA, VDD = 3.3 V

followed to write to the PLLCON and POWCONx registers. Table 70. PLLKEYx Registers Table 71. PLLCON MMR Bit Designations 5 OSEL 32 kHz PLL input selection. 32 kHz oscillator. Set by default. 01 PLL. Default configuration. 11 External clock on the P0.7 Pin. Table 72. PLLCON Write Sequence Table 73. POWKEYx Registers Table 74. POWCON0 MMR Bit Designations 2:0 CD CPU clock divider bits. Table 75. POWCON0 Write Sequence Table 76. POWKEYx Registers

Table 77. POWCON1 MMR Bit Designations

8 SPIPO Clearing this bit powers

5 I2C1PO Clearing this bit powers

2 I2C0PO Clearing this bit powers

Table 78. POWCON1 Write Sequence

support an input voltage of 5 V . maximum of 20 GPIOs can drive 1.6 mA at the same time. P0.6, P0.7, and the eight GPIOs of P1. The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x). Each port is controlled by four or five MMRs. other than GPIO. The PLA input is always active. Table 79. GPIO Pin Function Descriptions 1 These pins should not be used by user code . configure it as a clock input, the MDCLK bits in PLLCON must be set to 11. 3 The CONVSTART signal is active in all modes of P2.0.

writing to related bits has no effect on changing drive strength. adjustable for GPIO port. Some control bits cannot be changed. Table 85. GPxDAT Registers input value of the pins configured as input. Table 86. GPxDAT MMR Bit Descriptions 31:24 Direction of the data. 15:8 Reflect the state of Port x pins at reset (read only). 7:0 Port x data input (read only). Table 87. GPxSET Registers The GPxSET are data set Port x registers. Table 88. GPxSET MMR Bit Descriptions corresponding bit in the GPxDAT MMR. Cleared to 0 by the user; does not affect the data out. Table 89. GPxCLR Registers The GPxCLR are data clear Port x registers. Table 90. GPxCLR MMR Bit Descriptions 23:16 Data Port x clear bit. corresponding bit in the GPxDAT MMR. Cleared to 0 by the user; does not affect the data out. one of its specific I/O functions as described in Table 91. Table 91. SPM Configuration Table 91 also details the mode for each of the SPMMUX pins. generation options selectable in the configuration register.

in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL). Table 92 gives some common baud rate values. Table 92. Baud Rate Using the Normal Baud Rate Generator generator, produces a wider range of more accurate baud rates. Figure 47. Baud Rate Generation Options COM0TX is an 8-bit transmit register for UART0. COM1TX is an 8-bit transmit register for UART1. COM0RX is an 8-bit receive register for UART0. COM1RX is an 8-bit receive register for UART1. COM0RX, and COM0DIV0 share the same address location. when Bit 7 of COM0CON0 is set.

COM1RX, and COM1DIV0 share the same address location. when Bit 7 of COM1CON0 is set. COM0IEN0 is the interrupt enable register for UART0. COM1IEN0 is the interrupt enable register for UART1. Table 93. COMxIEN0 MMR Bit Descriptions 3 EDSSI Modem status interrupt enable bit. interrupt if any of COMXSTA1[3:1] are set. 2 ELSI Rx status interrupt enable bit. interrupt if any of COMxSTA0[3:0] are set. 1 ETBEI Enable transmit buffer empty interrupt. buffer is empty during a transmission. 0 ERBFI Enable receive buffer full interrupt. reception. Cleared by the user. interrupt. Cleared by the user. COM0DIV1 is a divisor latch (high byte) register for UART0. COM1DIV1 is a divisor latch (high byte) register for UART1. also indicatesif the UART is at FIFO mode. also indicates if the UART is at FIFO mode.

Table 94. COMxIID0 MMR Bit Descriptions 7:6 FIFOMODE FIFO mode flag. reading COMxSTA1. Priority 4. For FIFO mode, TXFIFO is empty. For FIFO mode, set trigger level reached. below the trigger level. Priority 2. [011]: receive line status error interrupt. Cleared by reading COMxSTA0. Priority 1. 0 NINT Set to disable interrupt flags by STATUS.

1 A frame time is the time allotted for one start bit, n data bits, one parity bit,

Table 95. COMxFCR MMR Bit Descriptions trigger level, the interrupt is cleared. 2 TXRST TXFIFO reset. Writing a 1 flushes the TXFIFO. 1 RXRST RXFIFO reset. Writing a 1 flushes the RXFIFO. 0 FIFOEN Transmitter and receiver FIFOs mode enable. COM0CON0 is the line control register for UART0.

COM1CON0 is the line control register for UART1. Table 96. COMxCON0 MMR Bit Descriptions 7 DLAB Divisor latch access. Set by the user to force SOUT to 0. Cleared to operate in normal mode. 4 EPS Even parity select bit. of the number of stop bits selected. COM0CON1 is the modem control register for UART0. COM1CON1 is the modem control register for UART1. Table 97. COMxCON1 MMR Bit Descriptions Cleared by the user to be in normal mode. Set by the user to force the RTS output to 0. Set by the user to force the DTR output to 0. COM0STA0 is the line status register for UART0.

COM1STA0 is the line status register for UART1. Table 98. COMxSTA0 MMR Bit Descriptions 11 RX_error Set automatically if PE, FE, or BI is set. equal to or less than the trigger level. 6 TEMT COMxTX empty status bit.

5 THRE COMxTX and transmitter shift register

transmitter shift register (TSR). Set when an invalid stop bit occurs. Set when a parity error occurs. data is overwritten before being read. completely received in the shift register. not transferred to the FIFO. COM0STA1 is a modem status register. COM1STA1 is a modem status register. Table 99. COMxSTA1 MMR Bit Descriptions automatically by reading COMxSTA1.

Table 100. COMxDIV2 MMR Bit Descriptions 15 FBEN Fractional baud rate generator enable bit. 10:0 FBN[10:0] N (see The Fractional Divider section). full duplex up to a maximum bit rate of 20 Mbps. (8-bit) serial data, MSB first. (8-bit) serial data, MSB first. transmitted and received through the MOSI SPICLK period. mode and as an input in slave mode. accepts data from an external master up to 10 Mbps. for the master and slave devices. deasserts itself upon completion. The SPI pins of the ADuC7124 device are P1.4 to P1.7. and high at the end of a transfer. P1.5 is the master in, slave out (SPIMISO) pin. P1.6 is the master out, slave in (SPIMOSI) pin. SPIRX, SPITX, SPIDIV , and SPICON.

Function: This 32-bit MMR contains the status of the SPI interface in both master and slave modes. Table 101. SPISTA MMR Bit Designations This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE. 10:8 SPIRXFSTA[2:0] SPI Rx FIFO status bits. [001] = one valid byte in the FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. 7 SPIFOF SPI Rx FIFO overflow status bit. except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. 6 SPIRXIRQ SPI Rx IRQ status bit. number of bytes has been received. Cleared when the SPISTA register is read. 5 SPITXIRQ SPI Tx IRQ status bit. of bytes has been transmitted. Cleared when the SPISTA register is read. 4 SPITXUF SPI Tx FIFO underflow. except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. 3:1 SPITXFSTA[2:0] SPI Tx FIFO status bits. [001] = one valid byte in the FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. 0 SPIISTA SPI interrupt status bit. Set to 1 when an SPI-based interrupt occurs. Cleared after reading SPISTA.

Function: This 8-bit MMR is the SPI receive register. Function: This 8-bit MMR is the SPI transmit register. peripheral in both master and slave modes. Table 102. SPICON MMR Bit Designations 15:14 SPIMDE SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. been received into the FIFO. been received into the FIFO. have been received into the FIFO. 13 SPITFLH SPI Tx FIFO flush enable bit. Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit. Any writes to the Tx FIFO are ignored while this bit is set. Clear this bit to disable Tx FIFO flushing. 12 SPIRFLH SPI Rx FIFO flush enable bit. Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set incoming, data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer. Clear this bit to disable Rx FIFO flushing. 11 SPICONT Continuous transfer enable. Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle. 10 SPILP Loop back enable bit. Set by the user to connect MISO to MOSI and test software. Cleared by the user to be in normal mode. 9 SPIOEN Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is cleared.

Rev. 0 | Page 62 of 96 Bit Name Description 8 SPIROW SPIRX overflow overwrite enable. Set by the user, the valid data in the Rx register is overwritten by the new serial byte received. Cleared by the user, the new serial byte received is discarded. 7 SPIZEN SPI transmit zeros when Tx FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO. 6 SPITMDE SPI transfer and interrupt mode. Set by the user to initiate transfer with a write to the SPITX register. Interrupt occurs only when Tx is empty. Cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt occurs only when Rx is full. 5 SPILF LSB first transfer enable bit. Set by the user, the LSB is transmitted first. Cleared by the user, the MSB is transmitted first. 4 SPIWOM SPI wired or mode enable bit. Set to 1 enable open drain data output. External pull-ups required on data out pins. Cleared for normal output levels. 3 SPICPO Serial clock polarity mode bit. Set by the user, the serial clock idles high. Cleared by the user, the serial clock idles low. 2 SPICPH Serial clock phase mode bit. Set by the user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by the user, the serial clock pulses at the end of each serial bit transfer. 1 SPIMEN Master mode enable bit. Set by the user to enable master mode. Cleared by the user to enable slave mode. 0 SPIEN SPI enable bit. Set by the user to enable the SPI. Cleared by the user to disable the SPI.

Rev. 0 | Page 63 of 96 I2C The ADuC7124 incorporates two I2C peripherals that can be configured as a fully I2C compatible I2C bus master device or, as a fully I2C bus compatible slave device. Both I2C channels are identical. Therefore, the following descriptions apply to both channels. The two pins used for data transfer, SDA and SCL, are configured in a wired AND format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up values are between 4.7 kΩ and 10 kΩ. The I 2C bus peripheral address in the I2C bus system is programmed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (read or/write) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. The I 2C peripheral can only be configured as a master or slave at any given time. The same I2C channel cannot simultaneously support master and slave modes. The I2C interface on the ADuC7124 includes the following features:

• Support for repeated start conditions. In master mode, the ADuC7124 can be programmed to generate a repeated start. In slave mode, the ADuC7124 recognizes repeated start conditions.
• In master and slave mode, the part recognizes both 7-bit and 10-bit bus addresses.
• In I 2C master mode, the ADuC7124 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence.
• Clock stretching is supported in both master and slave modes.
• In slave mode, the ADuC7124 can be programmed to return a NACK. This allows the validiation of checksum bytes at the end of I 2C transfers.
• Bus arbitration in master mode is supported.
• Internal and external loopback modes are supported for I2C hardware testing in loopback mode.
• The transmit and receive circuits in both master and slave mode contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs. Configuring External Pins for I2C Functionality The I2C pins of the ADuC7124 device are P1.0 and P1.1 for I2C0 and P1.2 and P1.3 for I2C1. P1.0 and P1.2 are the I2C clock signals, and P1.1 and P1.3 are the I2C data signals. For instance, to configure I2C0 pins (SCL0, SDA0), Bit 0 and Bit 4 of the GP1CON register must be set to 1 to enable I2C mode. On the other hand, to configure I2C1 pins (SCL1, SDA1), Bit 8 and Bit 12 of the GP1CON register must be set to 1 to enable I2C mode, as shown in the General- Purpose Input/Output section. Serial Clock Generation The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CxDIV MMR as follows: ) (2 ) 2 (DIVLDIVH + + + = UCLK CLOCKSERIAL ff where: fUCLK is the clock before the clock divider. DIVH is the high period of the clock. DIVL is the low period of the clock. Therefore, for 100 kHz operation, DIVH = DIVL = 0xCF and for 400 kHz DIVH = 0x28, DIVL = 0x3C The I2CxDIV register corresponds to DIVH:DIVL. I2C Bus Addresses Slave Mode In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2CxID3 registers contain the device IDs. The device compares the four I2CxIDx registers to the address byte received from the bus master. To be correctly addressed, the seven MSBs of either ID register must be identical to seven MSBs of the first received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The ADuC7124 also supports 10-bit addressing mode. When Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, one 10-bit address is supported in slave mode and is stored in the I2CxID0 and I2CxID1 registers. The 10-bit address is derived as follows: I2CxID0[0] is the read/write bit and is not part of the I address. I2CxID0[7:1] = Address Bits[6:0]. I2CxID1[2:0] = Address Bits[9:7]. I2CxID1[7:3] must be set to 11110b.

the I2C address of the device. address. I2CxADR0[0] is the read/write bit. I2CxADR0[7:3] must be set to 11110b. I2CxADR0[2:1] = Address Bits[9:8]. I2CxADR1[7:0] = Address Bits[7:0]. I2CxADR0[0] is the read/write bit. The I2C peripheral interfaces consists of a number of MMRs. These are described in the I2C Master Registers section. Table 103. I2CxMCON MMR Bit Designations 15:9 Reserved. These bits are reserved and should not be written to. 8 I2CMCENI I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this bit to clear the interrupt source. 7 I2CNACKENI I2C NACK received interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a NACK. Clear this bit to clear the interrupt source. 6 I2CALENI I2C arbitration lost interrupt enable bit. Set this bit to enable interrupts when the I2C master is unable to gain control of the I2C bus. Clear this bit to clear the interrupt source. 5 I2CMTENI I2C transmit interrupt enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte. Clear this bit to clear the interrupt source. 4 I2CMRENI I2C receive interrupt enable bit. Set this bit to enable interrupts when the I2C master receives data. Cleared by user to disable interrupts when the I2C master is receiving data. 3 I2CMSEN I2C master SCL stretch enable bit. I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. 2 I2CILEN I2C internal loopback enable. Cleared by the user to disable loopback mode.

1 I2CBD I2C master backoff disable bit

Clear this bit to wait until the I2C bus becomes free. 0 I2CMEN I2C master enable bit. Set by the user to enable I2C master mode. Clear this bit to disable I2C master mode.

Rev. 0 | Page 65 of 96 I2C Master Status Register Name: I2C0MSTA, I2C1MSTA Address: 0xFFFF0804, 0xFFFF0904 Default Value: 0x0000, 0x0000 Access: Read only Function: This 16-bit MMR is the I2C status register in master mode. Table 104 I2CxMSTA MMR Bit Designations Bit Name Description 15:11 Reserved. These bits are reserved. 10 I2CBBUSY I2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. 9 I2CMRxFO Master Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. 8 I2CMTC I2C transmission complete status bit. This bit is set to 1 when a transmission is complete between the master and the slave it was communicating with. If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. Clear this bit to clear the interrupt source. 7 I2CMNA I2C master NACK data bit. This bit is set to 1 when a NACK condition is received by the master in response to a data write transfer. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 6 I2CMBUSY I2C master busy status bit. Set to 1 when the master is busy processing a transaction. Cleared if the master is ready or if another master device has control of the bus. 5 I2CAL I2C arbitration lost status bit. This bit is set to 1 when the I2C master is unable to gain control of the I2C bus. If the I2CALENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 4 I2CMNA I2C master NACK address bit. This bit is set to 1 when a NACK condition is received by the master in response to an address. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 3 I2CMRXQ I2C master receive request bit. This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCON is set, an interrupt is generated. This bit is cleared in all other conditions. 2 I2CMTXQ I2C master transmit request bit. This bit goes high if the Tx FIFO is empty or contains only one byte and the master has transmitted an Address + write. If the I2CMTENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 1-0 I2CMTFSTA I2C master Tx FIFO status bits. 00 = I2C master Tx FIFO empty. 01 = one byte in master Tx FIFO. 10 = one byte in master Tx FIFO. 11 = I2C master Tx FIFO full.

sequence from a slave device. Table 105. I2CxMCNT0 MMR Bit Descriptions (Address =

8 I2CRECNT Set this bit if greater than 256 bytes are

Clear this bit when reading 256 bytes or less. these bits should be set to 0. Table 106. I2CxADR0 MMR in 7-Bit Address Mode 0 R/W Bit 0 is the read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested. Table 107. I2CxADR0 MMR in 10-Bit Address Mode significant byte of the address.

Table 108. I2CxADR1 MMR in 10-Bit Address Mode pin. For further details, see the I2C section. Table 109. I2CxDIV MMR Table 110. I2CxSCON MMR Bit Designations 10 I2CSTXENI Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. 9 I2CSRXENI Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. Clear this interrupt source. 8 I2CSSENI I2C stop condition detected interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. 7 I2CNACKEN I2C NACK enable bit. Set this bit to NACK the next byte in the transmission sequence. Clear this bit to let the hardware control the ACK/NACK sequence. 6 I2CSSEN I2C slave SCL stretch enable bit. Clear this bit to disable clock stretching. 5 I2CSETEN I2C early transmit interrupt enable bit. 4 I2CGCCLR I2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register. Clear this bit at all other times.

3 I2CHGCEN I2C hardware general call enable. watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be written to 1, as per the I2C January 2000 bus specification. Set this bit and I2CGCEN to enable hardware general call recognition in slave mode. Clear this bit to disable recognition of hardware general call commands. 2 I2CGCEN I2C general call enable. slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. Set this bit to allow the slave ACK I2C general call commands. Clear this bit to disable recognition of general call commands. 1 ADR10EN I2C 10-bit address mode. Set to 1 to enable 10-bit address mode. Clear to 0 to enable normal address mode. 0 I2CSEN I2C slave enable bit. Set by the user to enable I2C slave mode. Clear this bit to disable I2C slave mode. Function: This 16-bit MMR is the I2C status register in slave mode. Table 111. I2CxSSTA MMR Bit Designations

14 I2CSTA This bit is set to 1 if:

• A start condition followed by a matching address is detected.
• A start byte (0x01) is received.
• General calls are enabled and a general call code of (0x00) is received. This bit is cleared on receiving a stop condition. 13 I2CREPS This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition. 12:11 I2CID[1:0] I2C address matching register. These bits indicate which I2CxIDx register matches the received address. [00] = received address matches I2CxID0. [01] = received address matches I2CxID1. [10] = received address matches I2CxID2. [11] = received address matches I2CxID3. 10 I2CSS I2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated. This bit is cleared by reading this register.

Rev. 0 | Page 69 of 96 Bit Name Description 9:8 I2CGCID[1:0] I2C general call ID bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative ID. Note that these bits are not cleared by a general call reset command. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCON. 7 I2CGC I2C general call status bit. This bit is set to 1 if the slave receives a general call command of any type. If the command received is a reset command, then all registers return to their default states. If the command received is a hardware general call, the Rx FIFO holds the second byte of the command and this can be compared with the I2CxAL T register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCON. 6 I2CSBUSY I2C slave busy status bit. Set to 1 when the slave receives a start condition. Cleared by hardware if

• The received address does not match any of the I2CxIDx registers.
• The slave device receives a stop condition.
• A repeated start address doesn’t match any of the I2CxIDx registers. 5 I2CSNA I2C slave NACK data bit. This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted under the following conditions:
• INACK was returned because there was no data in the Tx FIFO.
• The I2CNACKEN bit was set in the I2CxSCON register. This bit is cleared in all other conditions. 4 I2CSRxFO Slave Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. 3 I2CSRXQ I2C slave receive request bit. This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur when the I2CSRXENI bit in I2CxSCON is set. The Rx FIFO must be read or flushed to clear this bit. 2 I2CSTXQ I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CxSCON is = 0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur when the I2CSTXENI bit in I2CxSCON is set. This bit is cleared in all other conditions. 1 I2CSTFE I2C slave FIFO underflow status bit. This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. 0 I2CETSTA I2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CxSCON is = 0, this bit goes high if the slave Tx FIFO is empty. If the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read.

Function: This 8-bit MMR is the I2C slave receive register. Function: This 8-bit MMR is the I2C slave transmit register. slave must generate the address for the master. section for further details. Rx/Tx FIFOs in both master and slave modes. Table 112. I2CxFSTA MMR Bit Designations 9 I2CFMTX Set this bit to 1 to flush the master Tx FIFO. 8 I2CFSTX Set this bit to 1 to flush the slave Tx FIFO. 7:6 I2CMRXSTA I2C master receive FIFO status bits. [01] = byte written to FIFO. 5:4 I2CMT XSTA I2C master transmit FIFO status bits. [01] = byte written to FIFO. 3:2 I2CSRXSTA I2C slave receive FIFO status bits. [01] = byte written to FIFO. 1:0 I2CSTXSTA I2C slave transmit FIFO status bits. [01] = byte written to FIFO.

outputs and over the duty cycle of each individual output. Table 113. PWM MMRs PWMCLRI PWM interrupt clear. of PWM outputs (PWM0 and PWM1) is shown in Figure 48. Figure 48. PWM Timing

1. The length of a PWM period is defined by PWMxLEN.

PWM0 and PWM1 waveforms in Figure 48. high-side waveform (PWM0) goes low. when the timer count reaches the value held in PWM0COM1.

Table 114. PWMCON0 PWMCON MMR Bit Designations 14 SYNC Enables PWM synchronization. transition on the P3.7/PWMSYNC pin. Cleared by the user to ignore transitions on the P3.7/PWMSYNC pin. 13 PWM5INV Set to 1 by the user to invert PWM5. Cleared by the user to use PWM5 in normal mode. 12 PWM3INV Set to 1 by the user to invert PWM3. Cleared by the user to use PWM3 in normal mode. 11 PWM1INV Set to 1 by the user to invert PWM1. Cleared by the user to use PWM1 in normal mode. PWMEN bit is cleared and an interrupt is generated. Cleared by the user to disable the PWMTRIP interrupt. 9 ENA If HOFF = 0 and HMODE = 1; note that, if not in H-bridge mode, this bit has no effect. Set to 1 by the user to enable PWM outputs. Cleared by the user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 115. 8 to 6 PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider. 5 POINV Set to 1 by the user to invert all PWM outputs. Cleared by the user to use PWM outputs as normal. Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low. Cleared by the user to use the PWM outputs as normal. 3 LCOMP Load compare registers. the PWM timer from 0x00 to 0x01. Cleared by the user to use the values previously stored in the internal compare registers. Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. Cleared by the user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. Set to 1 by the user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON. Cleared by the user to operate the PWMs in standard mode. 0 PWMEN Set to 1 by the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs. 1 In H-bridge mode, HMODE = 1. See Table 115 to determine the PWM outputs.

Table 115. PWM Output Selection 2 HS = high side, LS = low side. configured in PWM mode by default (see Table 116). Table 116. Compare Registers generation of multiple interrupts. goes high and the convert start signal is generated. Table 117. PWMCON1 MMR Bit Designations (Address =

7 CSEN Set to 1 by the user to enable the PWM

to generate a convert start signal. start signal by a number of clock pulses. ADC clock edge (see Figure 49). Figure 49. ADC Conversion

part a total of 16 PLA elements. two inputs and a flip-flop. This is represented in Figure 50. Figure 50. PLA Element as one of the 16 input pins. Mux 0 of Element 0 (Block 0). Mux 0 of Element 8 (Block 1). Table 118. Element Input/Output be routed internally via the PLA. See Table 122 for further details. The PLA peripheral interface consists of the 22 MMRs. The PLAELMx are Element 0 to Element 15 control registers. flop (see Table 119 and Table 122). Table 119. PLAELMx MMR Bit Descriptions 10:9 Mux 0 control (see Table 122). 8:7 Mux 1 control (see Table 122). Set by the user to select the output of Mux 0. Cleared by the user to select the output of Mux 1. Set by the user to bypass the flip-flop.

GPIO pins as the clock input for the PLA blocks is 41.78 MHz. Table 120. PLACLK MMR Bit Descriptions 6:4 Block 1 clock source selection. 111 Internal 32,768 oscillator. 2:0 Block 0 clock source selection. Table 121. PLAIRQ MMR Bit Descriptions Table 122. Feedback Configuration

01 Element 2 Element 2 Element 10 Element 10

10 Element 4 Element 4 Element 12 Element 12

11 Element 6 Element 6 Element 14 Element 14

01 Element 3 Element 3 Element 11 Element 11

10 Element 5 Element 5 Element 13 Element 13

11 Element 7 Element 7 Element 15 Element 15

PLAADC is the PLA source for the ADC start conversion signal. Table 123. PLAADC MMR Bit Descriptions 4 ADC start conversion enable bit. 3:0 ADC start conversion source. PLADIN is a data input MMR for PLA. Table 124. PLADIN MMR Bit Descriptions 15:0 Input bit to Element 15 to Element 0. Table 125. PLADOUT MMR Bit Descriptions 15:0 Output bit from Element 15 to Element 0. system to easily configure the PLA.

interrupts can be masked separately. are used when the full-vectored interrupt controller is enabled. Table 126. IRQ/FIQ MMRs Bit Designations

0 All interrupts OR’ed

This bit is set if any FIQ is active.

1 Software interrupt User programmable interrupt

2 Timer0 General-Purpose Timer 0. 3 Timer1 General-Purpose Timer 1.

4 Timer2 or wake-up

5 Timer3 or watchdog

6 Flash Control 0 Flash controller for Block 0

7 Flash Control 1 Flash controller for Block 1

8 ADC ADC interrupt source bit. 9 UART0 UART0 interrupt source bit. 10 UART1 UART1 interrupt source bit. 12 I2C0 master IRQ I2C master interrupt source bit. 13 I2C0 slave IRQ I2C slave interrupt source bit. 14 I2C1 master IRQ I2C master interrupt source bit. 15 I2C1 slave IRQ I2C slave interrupt source bit. 16 SPI SPI interrupt source bit. 17 XIRQ0 (GPIO IRQ0 ) External Interrupt 0. 18 Comparator Voltage comparator source bit. 19 PSM Power supply monitor. 20 XIRQ1 (GPIO IRQ1) External Interrupt 1. 21 PLA IRQ0 PLA Block 0 IRQ bit. 22 XIRQ2 (GPIO IRQ2 ) External Interrupt 2. 23 XIRQ3 (GPIO IRQ3) External Interrupt 3. 24 PLA IRQ1 PLA Block 1 IRQ bit. 25 PWM PWM trip interrupt source bit. internal and external events. software in a common interrupt handler routine. sources can be masked in the IRQEN MMR. IRQSIG is read only. only be used for this purpose.

Rev. 0 | Page 78 of 96 IRQEN Register IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled or masked, which does not create an IRQ exception. The IRQEN register cannot be used to disable an interrupt. IRQEN Register Name: IRQEN Address: 0xFFFF0008 Default Value: 0x00000000 Access: Read/write IRQCLR Register IRQCLR is a write-only register that allows the IRQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, allow independent manipulation of the enable mask without requiring an atomic read-modify-write. This register should be used to disable an interrupt source only when:

• In the interrupt sources interrupt service routine.
• The peripheral is temporarily disabled by its own control register. This register should not be used to disable an IRQ source if that IRQ source has an interrupt pending or could have an interrupt pending. IRQCLR Register Name: IRQCLR Address: 0xFFFF000C Default Value: 0x00000000 Access: Write only FAST INTERRUPT REQUEST (FIQ) The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR’ ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both the IRQEN and FIQEN masks. FIQSIG FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal, the corresponding bit in the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only. FIQSIG Register Name: FIQSIG Address: 0xFFFF0104 Default Value: 0x00000000 Access: Read only FIQEN FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or maskedm which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt. FIQEN Register Name: FIQEN Address: 0xFFFF0108 Default Value: 0x00000000 Access: Read/write FIQCLR FIQCLR is a write-only register that allows the FIQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. This register should be used to disable an interrupt source only when:
• In the interrupt sources interrupt service routine.
• The peripheral is temporarily disabled by its own control register. This register should not be used to disable an IRQ source if that IRQ source has an interrupt pending or could have an interrupt pending.

software in a common interrupt handler routine. programmed source interrupt. Table 127. SWICFG MMR Bit Designations and to be detected by the user in the IRQSTA/FIQSTA register. Figure 51. Interrupt Structure

• Vectored interrupts—allows a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and IRQVEC registers.
• IRQ/FIQ interrupts—can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is maximized, it is possible to have 16 separate interrupt levels.
• Programmable interrupt priorities—using the IRQP0 to IRQP3 registers, an interrupt source can be assigned an interrupt priority level value between 0 and 7. VIC MMRs IRQBASE Register The vector base register, IRQBASE, is used to point to the start address of memory used to store 32 pointer addresses. These pointer addresses are the addresses of the individual interrupt service routines. Name: IRQBASE Address: 0xFFFF0014 Default Value: 0x00000000 Access: Read/write

Table 128. IRQBASE MMR Bit Designations 31:16 Read only Reserved Always read as 0. 15:0 R/W 0 Vector base address.

Bit 0 of the IRQCONN register. Table 129. IRQVEC MMR Bit Designations 22:7 R/W 0 IRQBASE register value. Timer 2, then these bits are [00100]. 1:0 Reserved 0 Reserved bits. Bit 0 of the IRQCONN register. Table 130. IRQP0 MMR Bit Designations Flash Block 1 controller interrupt source. Flash Block 0 controller interrupt source. 3:0 Reserved Interrupt 0 cannot be prioritized. Table 131. IRQP1 MMR Bit Designations

Table 132. IRQP2 MMR Bit Designations 30:28 IRQ3PI A priority level of 0 to 7 can be set for IRQ3. 26:24 IRQ2PI A priority level of 0 to 7 can be set for IRQ2. 18:16 IRQ1PI A priority level of 0 to 7 can be set for IRQ1. power supply monitor interrupt source. 6:4 IRQ0PI A priority level of 0 to 7 can be set for IRQ0. 2:0 SPIPI A priority level of 0 to 7 can be set for SPI. Table 133. IRQP3 MMR Bit Designations 6:4 PWMPI A priority level of 0 to 7 can be set for PWM. and prioritization of FIQ interrupts. have a higher priority than an IRQ. Table 134. IRQCONN MMR Bit Designations

1 ENFIQN Setting this bit to 1 enables nesting of FIQ

or prioritization of FIQs is allowed.

0 ENIRQN Setting this bit to 1 enables nesting of IRQ

or prioritization of IRQs is allowed. is asserted. The bit that asserts depends on the priority of the IRQ. of that priority and lower are blocked. Table 135. IRQSTAN MMR Bit Designations or prioritization of FIQs is allowed.

Bit 1 of the IRQCONN register. Table 136. FIQVEC MMR Bit Designations 31:23 Read only 0 Always read as 0. 22:7 R/W 0 IRQBASE register value. 1:0 Reserved 0 Reserved bits. Table 137. FIQSTAN MMR Bit Designations or prioritization of FIQs is allowed. individually configured as level or rising/falling edge triggered. the IRQCONE register must be appropriately configured. Table 138. IRQCONE MMR Bit Designations 31:12 Reserved These bits are reserved and should not be written to. 11:10 11 PLA1SRC[1:0] PLA IRQ1 triggers on falling edge. 10 PLA IRQ1 triggers on rising edge. 01 PLA IRQ1 triggers on low level. 00 PLA IRQ1 triggers on high level. 9:8 11 IRQ3SRC[1:0] External IRQ3 triggers on falling edge. 10 External IRQ3 triggers on rising edge. 01 External IRQ3 triggers on low level. 00 External IRQ3 triggers on high level.

7:6 11 IRQ2SRC[1:0] External IRQ2 triggers on falling edge. 10 External IRQ2 triggers on rising edge. 01 External IRQ2 triggers on low level. 00 External IRQ2 triggers on high level. 5:4 11 PLA0SRC[1:0] PLA IRQ0 triggers on falling edge. 10 PLA IRQ0 triggers on rising edge. 01 PLA IRQ0 triggers on low level. 00 PLA IRQ0 triggers on high level. 3:2 11 IRQ1SRC[1:0] External IRQ1 triggers on falling edge. 10 External IRQ1 triggers on rising edge. 01 External IRQ1 triggers on low level. 00 External IRQ1 triggers on high level. 1:0 11 IRQ0SRC[1:0] External IRQ0 triggers on falling edge. 10 External IRQ0 triggers on rising edge. 01 External IRQ0 triggers on low level. 00 External IRQ0 triggers on high level. Table 139. IRQCLRE MMR Bit Designations 31:25 Reserved These bits are reserved and should not be written to.

24 PLA1CLRI A 1 must be written to this bit in the PLA IRQ1 interrupt service routine to clear an edge-

triggered PLA IRQ1 interrupt.

21 PLA0CLRI A 1 must be written to this bit in the PLA IRQ0 interrupt service routine to clear an edge-

triggered PLA IRQ0 interrupt. 19:18 Reserved These bits are reserved and should not be written to. 16:0 Reserved These bits are reserved and should not be written to.

The ADuC7124 has four general-purpose timer/counters.

• Timer0
• Timer1
• Timer2 or wake-up timer
• Timer3 or watchdog timer These four timers in their normal mode of operation can be either free running or periodic. In free-running mode, the counter decreases from the maximum value until zero scale is reached and starts again at the minimum value. It also increases from the minimum value until full scale is reached and starts again at the maximum value. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero/full scale is reached and starts again at the value stored in the load register. The timer interval is calculated as follows: ( ) Clock Source PrescalerTxDInterval ×= The value of a counter can be read at any time by accessing its value register (TxV AL). Note that, when a timer is being clocked from a clock other than a core clock, an incorrect value may be read (due to asynchronous clock system). In this configuration, TxV AL should always be read twice. If the two readings are different, it should be read a third time to get the correct value. Timers are started by writing in the control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time the value of the counter reaches zero when counting down. It is also generated each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing any value to clear the register of that particular timer (TxCLRI). When using an asynchronous clock-to-clock timer, the interrupt in the timer block can take more time to clear than the time it takes for the code in the interrupt routine to execute. Ensure that the interrupt signal is cleared before leaving the interrupt service routine. This can be done by checking the IRQSTA MMR. Timer0 (RTOS Timer) Timer0 is a general-purpose, 16-bit timer (count down) with a programmable prescaler. The prescaler source is the core clock frequency (HCLK) and can be scaled by factors of 1, 16, or 256. Timer0 can be used to start ADC conversions as shown in the block diagram in Figure 52. 09123-036 32.768kHz OSCILLATOR UCLK HCLK PRESCALER ÷1, 16, OR 256 16-BIT DOWN COUNTER 16-BIT LOAD TIMER0 VALUE TIMER0 IRQ ADC CONVERSION

Figure 52. Timer0 Block Diagram T0LD is a 16-bit load register. T0CON is the configuration MMR described in Table 140.

Table 140. T0CON MMR Bit Descriptions Set by the user to enable Timer0. Set by the user to operate in periodic mode. 00 Core clock/1. Default value. 11 Undefined. Equivalent to 00. hours: minutes: seconds: hundredths. precision allowed by the RTOS timer when the IRQ is serviced. Timer1 can be used to start ADC conversions. Figure 53. Timer1 Block Diagram T1LD is a 32-bit load register. T1CON is the configuration MMR described in Table 141.

Table 141. T1CON MMR Bit Descriptions Set by the user to enable time capture of an event. 000 Core clock (41 MHz/2CD). 011 P1.0 raising edge triggered. Set by the user for Timer1 to count up. Set by the user to enable Timer1. Cleared by the user to disable Timer1 by default. Set by the user to operate in periodic mode. 10 Hr: min: sec: hundredths (23 hours to 0 hour). 11 Hr: min: sec: hundredths (255 hours to 0 hour). clears the Timer1 interrupt.

1. Capture of the current timer value is enabled if the Timer2

interrupt is enabled via IRQEN[4] (see Table 126). hours: minutes: seconds: hundredths. overflows or immediately when T2ICLR is written. Table 142. Timer2 Interface Registers T2LD 32-bit register. Holds 32-bit unsigned integers.

code to refresh (reload) Timer2. T2V AL is a 32-bit register that holds the current value of Timer2. This 32-bit MMR configures the mode of operation for Timer2. Table 143. T2CON MMR Bit Designations 00 External 32.768 kHz watch crystal (default). 01 External 32.768 kHz watch crystal. 10 Internal 32.768 kHz oscillator. Set by the user for Timer2 to count up. Cleared by the user for Timer2 to count down (default). Set by the user to enable Timer2. Cleared by the user to disable Timer2 (default). Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). 10 Hr: min: sec: hundredths (23 hours to 0 hours). 11 Hr: min: sec: hundredths (255 hours to 0 hours). 0000 Source clock/1 (default). 1000 Source clock/256. This setting should be used in conjunction with Timer2 Format 10 and Format 11.

servicing to prevent it from forcing a processor reset. Figure 54. Timer3 Block Diagram Watchdog mode is entered by setting Bit 5 in the T3CON MMR. value must be written to T3CLRI before the expiration period. T3LD is a 16-bit load register. T3CON is the configuration MMR described in Table 144. Table 144. T3CON MMR Bit Descriptions Set by the user for Timer3 to count up. Set by the user to enable Timer3. Set by the user to operate in periodic mode. Set by the user to enable watchdog mode. Set by the user to use the secure clear option. 00 Source clock/1 by default. 11 Undefined. Equivalent to 00. reset when the watchdog reaches 0. Cleared by the user to disable the IRQ option.

mode or resets a new timeout period in watchdog mode. register to ensure resetting the timeout period. The secure clear bit is provided for a higher level of protection. Figure 55. 8-Bit LFSR generated, even if the count has not yet expired. cannot be read; it must be tracked/generated in software.

1. Enter initial seed, 0xAA, in T3CLRI before starting Timer3
2. Enter 0xAA in T3CLRI; Timer3 is reloaded.
3. Enter 0x37 in T3CLRI; Timer3 is reloaded.
4. Enter 0x6E in T3CLRI; Timer3 is reloaded.
5. Enter 0x66. 0xDC was expected; the watchdog resets the chip.

Rev. 0 | Page 93 of 96 OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ 9.00 BSC SQ 0.50 0.40 0.30 0.50 BSC 0.20 REF 12° MAX 0.80 MAX

0.65 TYP

1.00 0.85 0.80 7.50 REF

0.05 MAX

0.02 NOM

0.60 MAX

*4.85 4.70 SQ 4.55 EXPOSED PAD (BOTTOM VIEW) *COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION 082908-B SEATING PLANE PIN 1 INDICATOR 0.30 0.25 0.18 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 64. 64-Lead Frame Chip Scale Package [LFCSP_VQ]

Description

ADuC7124BCPZ126 10 2 126 kB/32 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 260 ADuC7124BCPZ126-RL 10 2 126 kB/32 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 2500 EVAL-ADuC7124QSPZ ADuC7124 QuickStart Development System 1 Z = RoHS Compliant Part.

Rev. 0 | Page 94 of 96 NOTES

Rev. 0 | Page 95 of 96 NOTES

Rev. 0 | Page 96 of 96 NOTES I 2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09123-0-7/10(0)