ADuC7060

ADuC7060/ADuC7061 (Rev. E)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 107

Technical content

Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI Data Sheet ADuC7060/ADuC7061 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Dual (24-bit) ADCs Single-ended and differential inputs Programmable ADC output rate (4 Hz to 8 kHz) Programmable digital filters Built-in system calibration Low power operation mode Primary (24-bit) ADC channel 2 differential pairs or 4 single-ended channels PGA (1 to 512) input stage Selectable input range: ±2.34 mV to ±1.2 V 30 nV rms noise Auxiliary (24-bit) ADC: 4 differential pairs or 7 single- ended channels On-chip precision reference (±10 ppm/°C) Programmable sensor excitation current sources 200 μA to 2 mA current source range Single 14-bit voltage output DAC Microcontroller ARM7TDMI core, 16-/32-bit RISC architecture JTAG port supports code download and debug Multiple clocking options Memory 32 kB (16 kB × 16) Flash/EE memory, including 2 kB kernel 4 kB (1 kB × 32) SRAM Tools In-circuit download, JTAG based debug Low cost, QuickStart™ development system Communications interfaces SPI interface (5 Mbps) 4-byte receive and transmit FIFOs UART serial I/O and I2C (master/slave) On-chip peripherals 4× general-purpose (capture) timers including Wake-up timer Watchdog timer Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs 16-bit, 6-channel PWM General-purpose inputs/outputs Up to 14 GPIO pins that are fully 3.3 V compliant Power AVDD/DVDD specified for 2.5 V (±5%) Active mode: 2.74 mA (@ 640 kHz, ADC0 active) 10 mA (@ 10.24 MHz, both ADCs active) Packages and temperature range Fully specified for −40°C to +125°C operation 32-lead LFCSP (5 mm × 5 mm) 48-lead LFCSP and LQFP Derivatives 32-lead LFCSP (ADuC7061) 48-lead LQFP and 48-lead LFCSP (ADuC7060)

APPLICATIONS

Industrial automation and process control Intelligent, precision sensing systems, 4 mA to 20 mA loop-based smart sensors GENERAL DESCRIPTION The ADuC7060/ADuC7061 series are fully integrated, 8 kSPS, 24-bit data acquisition systems incorporating high performance multichannel sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), 16-bit/ 32-bit ARM7TDMI® MCU, and Flash/EE memory on a single chip. The ADCs consist of a primary ADC with two differential pairs or four single-ended channels and an auxiliary ADC with up to seven channels. The ADCs operate in single-ended or differential input mode. A single-channel buffered voltage output DAC is available on chip. The DAC output range is programmable to one of four voltage ranges. The devices operate from an on-chip oscillator and a PLL gene- rating an internal high frequency clock up to 10.24 MHz. The microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC machine offering up to 10 MIPS peak performance; 4 kB of SRAM and 32 kB of nonvolatile Flash/EE memory are provided on chip. The ARM7TDMI core views all memory and registers as a single linear array. The ADuC7060/ADuC7061 contains four timers. Timer1 is a wake-up timer with the ability to bring the part out of power saving mode. Timer2 is configurable as a watchdog timer. A 16-bit PWM with six output channels is also provided. The ADuC7060/ ADuC7061 contains an advanced interrupt controller. The vectored interrupt controller (VIC) allows every interrupt to be assigned a priority level. It also supports nested interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 nested interrupt levels is supported. On-chip factory firmware supports in-circuit serial download via the UART serial interface ports and nonintrusive emulation via the JTAG interface. The parts operate from 2.375 V to 2.625 V over an industrial temperature range of −40°C to +125°C.

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 2 of 107 TABLE OF CONTENTS Slave Select (P0.0/SS E

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 3 of 107

REVISION HISTORY

2/2017—Rev. E to Rev. F 10/2014—Rev. D to Rev. E Changed Register I2CMSTA, Bit 7 from I2CMNA to I2CMND; 4/2012—Rev. C to Rev. D Change to Command Sequence for Executing a Mass Erase Changes to Timers Section; Added Hr:Min:Sec: 1/128 Format Changes to Timer2 Load Register Section and Timer2 Value 5/2011—Rev. B to Rev. C Add Temporary Protection Section and Keyed Permanent Added Permanent Protection Section and Sequence to Write the Software Protection Key and Set Permanent Protection Section ... 26 Changes to Primary Channel ADC Data Register Section and 2/2010—Rev. A to Rev. B Changes to Pin 19, Pin 20, and Pin 45 Descriptions (Table 8).. 16 Changes to Pin 13, Pin 14, and Pin 29 Descriptions (Table 9).. 18 Changes to Serial Downloading (In-Circuit Programming) 6/2009—Rev. 0 to Rev. A

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 4 of 107 Changes to Primary Channel ADC Data Register Section Changes to Nonvolatile Flash/EE Memory Section and Changes Pulse-Width Modulator General Overview Section, 4/2009—Revision 0: Initial Version

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 5 of 107 FUNCTIONAL BLOCK DIAGRAM PRECISION ANALOG PERIPHERALS POR MEMORY 32kB FLASH 4kB RAM ARM7TDMI MCU 10MHz ON-CHIP OSC (3%) PLL 4× TIMERS WDT W/U TIMER PWM GPIO PORT UART PORT SPI PORT I2C PORT VIC (VECTORED INTERRUPT CONTROLLER) MUX MUX 24-BIT Σ-∆ ADC BUF 24-BIT Σ-∆ ADCPGA PRECISION REFERENCE TEMP SENSOR 14-BIT DAC RESET XTALO XTALI ADC0 ADC1 ADC5 ADC4 ADC3 ADC2 ADC6 ADC7 ADC8 ADC9 IEXC0 IEXC1 DAC0 VREF+ VREF– GND_SW ADuC7060/ ADuC7061 BUF 07079-001 Figure 1.

Table 38 (ADC auxiliary channel). Table 1. ADuC7060/ADuC7061 Specifications

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 7 of 107 Parameter Test Conditions/Comments Min Typ Max Unit ADC SPECIFICATIONS: ANALOG INPUT Internal VREF = 1.2 V Main Channel Absolute Input Voltage Range Applies to both VIN+ and VIN− 0.1 VDD − 0.7 V Input Voltage Range Gain = 11 0 1.2 V (Differential Voltage Between AIN+ and AIN–) Gain = 21 0 600 mV Gain = 41 0 300 mV Gain = 81 0 150 mV Gain = 161 0 75 mV Gain = 321 0 37.5 mV Gain = 641 0 18.75 mV Gain = 1281 0 9.375 mV Common Mode Voltage, VCM10 VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 0.5 V Input Leakage Current1 ADC0 and ADC1 10 181 nA ADC2, ADC3, ADC4, and ADC5 15 301 nA ADC6, ADC7, ADC8, and ADC9, VREF+, VREF− Measurements are taken when the ADC is not opearating 15 25 1 nA Common-Mode Rejection DC1 On ADC Input ADC = 7.8 mV 113 dB ADC = 1 V1 95 dB Common-Mode Rejection

50 Hz/60 Hz1

50 Hz/60 Hz ± 1 Hz, 16.6 Hz and

50 Hz update rate, chop on

ADC = 7.8 mV, range ± 20 mV 95 dB ADC = 1 V, range ± 1.2 V 90 dB Normal-Mode Rejection On ADC Input 50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC, chop on 75 dB 50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC, chop off 67 dB Auxiliary Channel Absolute Input Voltage Range1 Buffer enabled 0.1 AVDD − 0.1 V Buffer disabled AGND AVDD V Input Voltage Range Range-based reference source 0 1.2 V Common-Mode Rejection DC1 On ADC Input ADC = 1 V1 87 dB Common-Mode Rejection 50 Hz/60 Hz ± 1 Hz, 16.6 Hz and ADC = 1 V, range ± 1.2 V 90 dB Normal-Mode Rejection On ADC Input 50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC, chop on 75 dB 50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC, chop off 67 dB VOLTAGE REFERENCE ADC Precision Reference Internal VREF 1.2 V Initial Accuracy Measured at TA = 25°C −0.1 +0.1 % Reference Temperature Coefficient (Tempco)1, 11 −20 ±10 +20 ppm/°C Power Supply Rejection1 70 dB External Reference Input Range12 0.1 AVDD V VREF Divide-by-2 Initial Error1 0.1 %

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 8 of 107 Parameter Test Conditions/Comments Min Typ Max Unit DAC CHANNEL SPECIFICATIONS RL = 5 kΩ, CL = 100 pF Voltage Range 0 VREF V 0 AVDD − 0.2 V DAC 12-BIT MODE DC Specifications13 Resolution 12 Bits Relative Accuracy ±2 LSB Differential Nonlinearity Guaranteed monotonic ±0.2 ±1 LSB Offset Error 1.2 V internal reference ±2 ±15 mV Gain Error VREF range (reference = 1.2 V) ±1 % AVDD range ±1 % Gain Error Mismatch 0.1 % of full scale on DAC DAC 16-BIT MODE1 Only monotonic to 14 bits DC Specifications14 Resolution 14 Bits Relative Accuracy For 14-bit resolution ±3 LSB Differential Nonlinearity Guaranteed monotonic (14 bits) ±0.5 ±1 LSB Offset Error 1.2 V internal reference ±2 ±15 mV Gain Error VREF range (reference = 1.2 V) ±1 % AVDD range ±1 % Gain Error Mismatch 0.1 % of full scale on DAC DAC AC CHARACTERISTICS Voltage Output Settling Time 10 µs Digital-to-Analog Glitch Energy 1 LSB change at major carry (where maximum number of bits simultaneously change in the DAC0DAT register) ±20 nV-sec TEMPERATURE SENSOR1, 15 After user calibration Accuracy MCU in power-down or standby mode ±4 °C Voltage Output at 0°C Typical value 96 mV Voltage Tempco Typical value 0.28 mV/°C Thermal Impedance 48-lead LFCSP 27 °C/W 48-lead LQFP 55 °C/W 32-lead LFCSP 30 °C/W GROUND SWITCH1 RON 10 Ω Input Leakage 15 nA POWER-ON RESET (POR) POR Trip Level1 Refers to voltage at DVDD pin Power-on level 2.0 V Power-down level 2.25 V RESET Timeout from POR Maximum supply ramp between 1.8 V and 2.25 V; after POR trip, DVDD must reach 2.25 V within this time limit 128 ms

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 9 of 107 Parameter Test Conditions/Comments Min Typ Max Unit EXCITATION CURRENT SOURCES Output Current Available from each current source 200 1000 μA Initial Tolerance at 25°C ±5 % Drift1 0.06 %/°C Initial Current Matching at 25°C Matching between both current sources ±0.5 % Drift Matching1 20 ppm/°C Line Regulation (AVDD)1 AVDD = 2.5 V ± 5% 0.2 %/V Output Compliance1 AGND − 30 mV AVDD − 0.7 V V WATCHDOG TIMER (WDT) Timeout Period1 32.768 kHz clock, 256 prescale 0.008 512 sec Timeout Step Size 7.8 ms FLASH/EE MEMORY1 Endurance16 10,000 Cycles Data Retention17 20 Years DIGITAL INPUTS All digital inputs except NTRST Input Leakage Current Input (high) = DVDD ±1 ±10 µA Input Pull-Up Current Input (low) = 0 V 10 20 80 µA Input Capacitance 10 pF Input Leakage Current NTRST only: input (low) = 0 V ±1 ±10 µA Input Pull-Down Current NTRST only: input (high) = DVDD 30 55 100 µA LOGIC INPUTS1 All logic inputs Input Low Voltage (VINL) 0.4 V Input High Voltage (VINH) 2.0 V LOGIC OUTPUTS1 All logic outputs except XTALO Output Low Voltage (VOL) ISOURCE = 1.6 mA 0.6 V Output High Voltage (VOH) ISOURCE = 1.6 mA 2.0 V CRYSTAL OSCILLATOR1 Logic Inputs, XTALI Only Input Low Voltage (VINL) 0.8 V Input High Voltage (VINH) 1.7 V XTALI Capacitance 12 pF XTALO Capacitance 12 pF ON-CHIP OSCILLATORS Oscillator 32,768 kHz Accuracy −3 +3 % MCU CLOCK RATE Eight programmable core clock selections within this range: binary divisions 1, 2, 4, 8 . . . 64, 128 0.08 1.28 10.24 MHz Using an External Clock to P2.0/EXTCLK Pin 0.08 10.24 MHz MCU START-UP TIME At Power-On Includes kernel power-on execution time 134 ms After Reset Event Includes kernel power-on execution time 5 ms From MCU Power-Down PLL On Wake-Up from Interrupt CD = 0 4.8 μs PLL Off Wake-Up from Interrupt CD = 0 66 μs Internal PLL Lock Time 1 ms

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 10 of 107 Parameter Test Conditions/Comments Min Typ Max Unit POWER REQUIREMENTS Power Supply Voltages DVDD (±5%) 2.375 2.5 2.625 V AVDD (±5%) 2.375 2.5 2.625 V Power Consumption IDD (MCU Normal Mode)18 MCU clock rate = 10.24 MHz, ADC0 on 6 10 mA MCU clock rate = 640 kHz, ADC0 on, G = 4, ADC1/DAC off, SPI on; POWCON1 = 0x4 Full temperature range 3.1 mA Reduced temperature range −40°C to +85°C1 2.74 mA IDD (MCU Powered Down)1 Full temperature range 55 350 µA Reduced temperature range −40°C to +85°C 55 120 µA IDD (Primary ADC) PGA enabled, normal mode/low power mode; current is dependent on gain setting 0.6/0.3 mA ADC0 on, G = 1, normal mode 0.03 mA ADC0 on, G = 4, normal mode 0.44 mA ADC0 on, G = >128, normal mode 0.63 mA IDD (Auxiliary ADC) Normal mode/low power mode 0.35/0.1 mA IDD (DAC) DAC0CON = 0x10 0.33 mA PWM 0.34 mA 1 These numbers are not production tested but are guaranteed by design and/or characterization data at production release. 2 Valid for primary ADC gain setting of PGA = 4 to 64. 3 Tested at gain range = 4 after initial offset calibration. 4 Measured with an internal short. A system zero-scale calibration removes this error. ADC factory calibration done with chop off. 5 Measured with an internal short. 6 These numbers do not include internal reference temperature drift. 7 Factory calibrated at gain = 1. 8 System calibration at a specific gain range removes the error at this gain range. ADC factory calibration done with chop off. 9 Measured using an external reference. 10 Ensure common mode voltage is set so VIN*Gain setting, which is the PGA output voltage, is between 0.1V and VDD – 0.7V. 900 mV is an optimum value for the common mode voltage across all gains. 11 Measured using the box method. 12 References up to AVDD are accommodated by setting ADC0CON Bit 12. 13 Reference DAC linearity is calculated using a reduced code range of 171 to 4095. 14 Reference DAC linearity is calculated using a reduced code range of 2731 to 65,535. 15 Die temperature. 16 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles. 17 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. 18 Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.

Table 2. I2C® Timing in Standard Mode (100 kHz) Figure 2. I2C Compatible Interface Timing

Table 3. SPI Master Mode Timing (Phase Mode = 1) 1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. Figure 3. SPI Master Mode Timing (Phase Mode = 1) Table 4. SPI Master Mode Timing (Phase Mode = 0) 1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.

Table 6. SPI Slave Mode Timing (Phase Mode = 0) 1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. Figure 6. SPI Slave Mode Timing (Phase Mode = 0)

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 15 of 107 ABSOLUTE MAXIMUM RATINGS TA = −40°C to +125°C, unless otherwise noted. Table 7. Parameter Rating AGND to DGND to AVDD to DVDD −0.3 V to +0.3 V Digital I/O Voltage to DGND −0.3 V to +3.6 V VREF± to AGND −0.3 V to AVDD + 0.3 V ADC Inputs to AGND −0.3 V to AVDD + 0.3 V ESD (Human Body Model) Rating All Pins ±2 kV Storage Temperature 125°C Junction Temperature Transient 150°C Continuous 130°C Lead Temperature Soldering Reflow (15 sec) 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

1. THE LFCSP_VQ ONLY HAS AN EXPOSED PADDLE THAT MUST BE LEFT UNCONNECTED.

THIS DOES NOT APPLY TO THE LQFP. Figure 7. 48-Lead LQFP and 48-Lead LFCSP_VQ Pin Configuration Table 8. ADuC7060 Pin Function Descriptions 0 EP Exposed Paddle. The LFCSP_VQ only has an exposed paddle that must be left unconnected. This does not apply to the LQFP . 1 RESET I Reset. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin. (~100 kΩ) should be added to this pin. Input/Timer0 Input. This is a multifunction input/output pin offering four functions. dual function input/output pin. dual function input/output pin. 7 P0.5/CTS I/O General-Purpose Input and General-Purpose Output P0.5/Clear-to-Send Signal in UART Mode. 8 P0.6/RTS I/O General-Purpose Input and General-Purpose Output P0.6/Request-to-Send Signal in UART Mode. 9 DVDD S Digital Supply Pin. 11 DAC0 O DAC Output. Analog output pin.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 17 of 107 Pin No. Mnemonic Type1 Description 12 ADC5/EXT_REF2IN− I Single-Ended or Differential Analog Input 5/External Reference Negative Input. This is a dual function analog input pin. ADC5 serves as the analog input for the auxiliary ADC. EXT_REF2IN− serves as the external reference negative input by ADC for the auxiliary channel. 13 ADC4/EXT_REF2IN+ I Multifunction Analog Input Pin. This pin can be used for the single-ended or differential Analog Input 4, which is the analog input for the auxiliary ADC, or it can be used for the external reference positive input for the auxiliary channel. 14 ADC3 I Single-Ended or Differential Analog Input 3. Analog input for the primary and auxiliary ADCs. 15 ADC2 I Single-Ended or Differential Analog Input 2. Analog input for the primary and auxiliary ADCs. 16 IEXC1 O Programmable Current Source. Analog output pin. 17 IEXC0 O Programmable Current Source. Analog output pin. 18 GND_SW I Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly to the AGND system ground. 19 ADC1 I Single-Ended or Differential Analog Input 1. Analog input for the primary ADC. Negative differential input for primary ADC. 20 ADC0 I Single-Ended or Differential Analog Input 0. Analog input for the primary ADC. Positive differential input for primary ADC. 21 VREF+ I External Reference Positive Input for the Primary Channel. Analog input pin. 22 VREF− I External Reference Negative Input for the Primary Channel. Analog input pin. 23 AGND S Analog Ground. 24 AVDD S Analog Supply Pin. 25 ADC6 I Analog Input 6 for Auxiliary ADC. Single-ended or differential Analog Input 6. 26 ADC7 I Analog Input 7 for Auxiliary ADC. Single-ended or differential Analog Input 7. 27 ADC8 I Analog Input 8 for Auxiliary ADC. Single-ended or differential Analog Input 8. 28 ADC9 I Analog Input 9 for Auxiliary ADC. Single-ended or differential Analog Input 9. 29 DGND S Digital Ground. 30 DVDD S Digital Supply Pin. 31 P0.0/SS I/O General-Purpose Input and General-Purpose Output P0.0/SPI Slave Select Pin (Active Low). This is a dual function input/output pin. 32 P0.1/SCLK/SCL I/O General-Purpose Input and General-Purpose Output P0.1/SPI Clock Pin/I2C Clock Pin. This is a triple function input/output pin. 33 P0.2/MISO I/O General-Purpose Input and General-Purpose Output P0.2/SPI Master Input Slave Output. This is a dual function input/output pin. 34 P0.3/MOSI/SDA I/O General-Purpose Input and General-Purpose Output P0.3/SPI Master Output Slave Input/I2C Data Pin. This is a triple function input/output pin. 35 XTALO O External Crystal Oscillator Output Pin. 36 XTALI I External Crystal Oscillator Input Pin. 37 P0.4/IRQ0/PWM1 I/O General-Purpose Input and General-Purpose Output P0.4/External Interrupt Request 0/PWM1 Output. This is a triple function input/output pin. 38 P2.0/IRQ2/PWM0/EXTCLK I/O General-Purpose Input and General-Purpose Output P2.0/External Interrupt Request 2/PWM0 Output/External Clock Input. This is a multifunction input/output pin. 39 P1.4/PWM2 I/O General-Purpose Input and General-Purpose Output P1.4/PWM2 Output. This is a dual function input/output pin. 40 P1.5/PWM3 I/O General-Purpose Input and General-Purpose Output P1.5/PWM3 Output. This is a dual function input/output pin. 41 P1.6/PWM4 I/O General-Purpose Input and General-Purpose Output P1.6/PWM4 Output. This is a dual function input/output pin. 42 P2.1/IRQ3/PWM5 I/O General-Purpose Input and General-Purpose Output P2.1/External Interrupt Request 3/PWM5 Output. This is a triple function input/output pin.

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 18 of 107 Pin No. Mnemonic Type1 Description 43 DGND S Digital Ground. 44 DVDD S Digital Supply Pin. 45 NTRST/BM I JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (BM). The ADuC7060 enters serial download mode if BM is low at reset and executes code if BM is pulled high at reset through a 13 kΩ resistor. 46 TDO O JTAG Data Out. Output pin used for debug and download only. 47 TDI I JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 48 TCK I JTAG Clock Pin. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 1 I = input, O = output, I/O = input/output, and S = supply.

24 XTALI

23 XTALO

18 VREF–

17 VREF+

1. THE 32-LEAD LFCSP_VQ HAS AN EXPOSED PADDLE. THIS EXPOSED

PADDLE MUST BE LEFT UNCONNECTED. Figure 8. 32-Lead LFCSP Pin Configuration Table 9. ADuC7061 Pin Function Descriptions 0 EP Exposed Paddle. The 32-lead LFCSP_VQ has an exposed paddle that must be left unconnected. 1 RESET I Reset Pin. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin. (~100 kΩ) should be added to this pin. Input/Timer0 Input. This is a multifunction input/output pin offering four functions. 5 DAC0 O DAC Output. Analog output pin. EXT_REF2IN− serves as the external reference negative input by ADC for the auxiliary channel. reference positive input for the auxiliary channel. 8 ADC3 I Single-Ended or Differential Analog Input 3. Analog input for primary and auxiliary ADCs. 9 ADC2 I Single-Ended or Differential Analog Input 2. Analog input for primary and auxiliary ADCs. 10 IEXC1 O Programmable Current Source. Analog output pin. 11 IEXC0 O Programmable Current Source. Analog output pin. 16 AVDD S Analog Supply Pin. 17 VREF+ I External Reference Positive Input for the Primary Channel. Analog input pin. 18 VREF− I External Reference Negative Input for the Primary Channel. Analog input pin. Input 6. Analog input for the auxiliary ADC. ADC7. This is a multifunction input/output pin. Single-ended or differential Analog Input 7. Analog input for the auxiliary ADC.

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 20 of 107 Pin No. Mnemonic Type1 Description 21 P0.2/MISO/ADC8 I/O General-Purpose Input and General-Purpose Output P0.2/SPI Master Input Slave Output/Auxiliary ADC8 Input. This is a triple function input/output pin. Single-ended or differential Analog Input 8. Analog input for the auxiliary ADC. 22 P0.3/MOSI/SDA/ADC9 I/O General-Purpose Input and General-Purpose Output P0.3/SPI Master Output Slave Input/I2C Data Pin/Auxiliary ADC9 Input. This is a multifunction input/output pin. Single-ended or differential Analog Input 9. Analog input for the auxiliary ADC. 23 XTALO O External Crystal Oscillator Output Pin. 24 XTALI I External Crystal Oscillator Input Pin. 25 P0.4/IRQ0/PWM1 I/O General-Purpose Input and General-Purpose Output P0.4/External Interrupt Request 0/PWM1 Output. This is a triple function input/output pin. 26 P2.0/IRQ2/PWM0 I/O General-Purpose Input and General-Purpose Output P2.0/External Interrupt Request 2/PWM0 Output. This is a triple function input/output pin. 27 DGND S Digital Ground. 28 DVDD S Digital Supply Pin. 29 NTRST/BM I JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (BM). The ADuC7061 enters serial download mode if BM is low at reset and executes code if BM is pulled high at reset through a 13 kΩ resistor. 30 TDO O JTAG Data Out. Output pin used for debug and download only. 31 TDI I JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 32 TCK I JTAG Clock. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 1 I = input, O = output, I/O = input/output, and S = supply.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 21 of 107 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, when the ADC has settled. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that whereas the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, giving a valid 24-bit data conversion result at output rates from 1 Hz to 8 kHz. Note that, when software switches from one input to another (on the same ADC), the digital filter must first be cleared and then allowed to average a new result. Depending on the con- figuration of the ADC and the type of filter, this can take multiple conversion cycles. Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end- points of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB The error is expressed as a percentage of full scale. No Missing Codes No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits and specifies the number of codes (ADC results) as 2N bits, where N is no missing codes guaranteed to occur through the full ADC input range. Offset Error Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition. Offset Error Drift Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as least significant bits per degree Celsius. Gain Error Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function. Output Noise The output noise is specified as the standard deviation (or 1 × Sigma) of the distribution of the ADC output codes collected when the ADC input voltage is at a dc voltage. It is expressed as micro root mean square. The output, or root mean square (rms) noise, can be used to calculate the effective resolution of the ADC as defined by the following equation: Effective Resolution = log2(Full-Scale Range/rms Noise) bits The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × Sigma of the distribution of ADC output codes collected when the ADC input voltage is at dc. The peak-to-peak noise is, therefore, calculated as 6.6 × rms Noise The peak-to-peak noise can be used to calculate the ADC (noise free code) resolution for which there is no code flicker within a 6.6-Sigma limit as defined by the following equation: Noise Free Code Resolution = log2 NoisePeaktoPeak RangeScaleFull bits Data Sheet Acronyms ADC analog-to-digital converter ARM advanced RISC machine JTAG joint test action group LSB least significant byte/bit LVF low voltage flag MCU microcontroller MMR memory mapped register MSB most significant byte/bit PID protected identifier POR power-on reset PSM power supply monitor rms root mean square

features, as listed in Table 10. Table 10. ARM7TDMI Features However, the Thumb mode has three limitations.

• Relative to ARM, the Thumb code usually requires more instructions to perform the same task. Therefore, ARM code is best for maximizing the performance of time- critical code in most applications.
• The Thumb instruction set does not include some instructions that are needed for exception handling, so ARM code can be required for exception handling.
• When an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at that address. The first command is required to be in ARM code. MULTIPLIER (M) The ARM7TDMI instruction set includes an enhanced multiplier, with four extra instructions to perform 32-bit by 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result. EmbeddedICE (I) The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. These registers are con- trolled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. When in a debug state, the processor registers can be interrogated, as can the Flash/EE, SRAM, and memory mapped registers. ARM7 Exceptions The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are as follows: Type 1: normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Note that the ADuC7060/ADuC7061 supports eight configurable priority levels for all IRQ sources. Type 2: fast interrupt or FIQ. This is provided to service data transfer or a communication channel with low latency. FIQ has priority over IRQ. Note that the ADuC7060/ADuC7061 supports eight configurable priority levels for all FIQ sources. Type 3: memory abort (prefetch and data). Type 4: attempted execution of an undefined instruction. Type 5: software interrupts (SWI) instruction that can be used to make a call to an operating system. Typically, the programmer defines interrupts as IRQ, but for higher priority interrupts, the programmer can define interrupts as the FIQ type. The priority of these exceptions and vector addresses are listed in Table 11.

Table 11. Exception Priorities and Vector Addresses

1 Hardware reset 0x00

2 Memory abort (data) 0x10

3 FIQ 0x1C

4 IRQ 0x18

5 Memory abort (prefetch) 0x0C

6 Software interrupt1 0x08

6 Undefined instruction1 0x04

1 A software interrupt and an undefined instruction exception have the same

priority and are mutually exclusive. with a reserved location at 0x14. The stack pointer contains the current location of the stack.

such as C, it is necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used. reducing the response time of the interrupt handling process. Figure 9. Register Organization compilers have an option to compile without using this command. time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is five cycles. the synchronizer plus the time to enter the exception mode. for example, when executing interrupt service routines. memory map results in a data abort exception. Figure 10. Memory Map

32 BITS

Figure 11. Little Endian Format array. SRAM is read/writable in 8-, 16-, and 32-bit segments.

memory array, from Address 0x00000000 to Address 0x00000020. can run in full 32-bit ARM mode and at maximum core speed. Address 0x00000000, to execute the user’s reset exception routine. memory to the bottom of the memory array. Table 12. Remap MMR Bit Designations Set by user to remap the SRAM to 0x00000000. section. Note that the flash page size is 512 bytes. flash control interface as described in Table 13. Table 13. FEESTA MMR Bit Designations reading the FEESTA register. automatically when reading the FEESTA register. FEEMOD sets the operating mode of the flash control interface. Table 14 lists FEEMOD MMR bit designations.

Table 14. FEEMOD MMR Bit Designations 8 Reserved. Always set this bit to 1. 4 Flash/EE interrupt enable. interrupt occurs when a command is complete. Cleared by user to disable the Flash/EE interrupt. 3 Erase/write command protection. Set by user to enable the erase and write commands. 2:0 Reserved. Always set these bits to 0. Table 15. Command Codes in FEECON 0x011 Single read Load FEEDAT with the 16-bit data. Indexed by FEEADR. 0x021 Single write Write FEEDAT at the address pointed to by FEEADR. This operation takes 50 μs. comparison is returned in FEESTA Bit 0 and Bit 1. 0x051 Single erase Erase the page indexed by FEEADR. operation takes 16,389 clock cycles. 0x0F Ping No operation; interrupt generated. 1 The FEECON register always reads 0x07 immediately after execution of any of these commands.

value for flash read and write commands. boundary causes a data abort exception to occur. register (LFSR) operation initiated by the signature command. reset of the MMR. It requires a software key (see Table 16). FEEHID are cleared by a reset (see Table 16). Table 16. FEEPRO and FEEHID MMR Bit Designations accesses for protected pages if this bit is cleared. Set by the user to allow reading the code via JTAG. represents two pages. Each page is 512 bytes in size. and Page 1. Cleared to protect Page 0 and Page 1. and Page 3. Cleared to protect Page 2 and Page 3. back to 0xFFFF but also erases the entire user code space.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 27 of 107 Permanent Protection Permanent protection can be set via FEEPRO, similar to how keyed permanent protection is set, with the only difference being that the software key used is 0xDEADDEAD. When the FEEPRO write sequence is saved, only a mass erase sets the software protection key back to 0xFFFFFFFF . This also erases the entire user code space. Sequence to Write the Software Protection Key and Set Permanent Protection 1. Write in FEEPRO corresponding to the pages to be protected. 2. Write the new (user-defined) 32-bit software protection key in FEEADR (Bits[31:16]) and FEEDAT (Bits[15:0]). 3. Write 10 in FEEMOD (Bits[6:5]) and set FEEMOD (Bit 3). 4. Run the protect command (Code 0x0C) in FEECON. To remove or modify the protection, the same sequence can be used with a modified value of FEEPRO. The previous sequence for writing the key and setting permanent protection is illustrated in the following example, this protects writing Page 4 and Page 5 of the Flash/EE: Int a = FEESTA; // Ensure FEESTA is cleared FEEPRO = 0xFFFFFFFB; // Protect Page 4 and Page 5 FEEADR = 0x66BB; // 32-bit key value (Bits[31:16]) FEEDAT = 0xAA55; // 32-bit key value (Bits[15:0]) FEEMOD = 0x0048 // Lock security sequence FEECON = 0x0C; // Write key command while (FEESTA & 0x04){} // Wait for command to finish Command Sequence for Executing a Mass Erase FEEDAT = 0x3CFF; FEEADR = 0xFFC3; FEEMOD = FEEMOD|0x8; //Erase key enable FEECON = 0x06; //Mass erase command

indirect addressing through the ARM7 banked registers. user software. Figure 12 shows the full MMR memory map. except for the Flash/EE memory, the GPIOs, and the PWM. Figure 12. Memory Mapped Registers

Table 17. IRQ Address Base = 0xFFFF0000 0x0000 IRQSTA 4 R 0x00000000 Active IRQ source status. 0x0004 IRQSIG 4 R Current state of all IRQ sources (enabled and disabled). 0x0008 IRQEN 4 R/W 0x00000000 Enabled IRQ sources. 0x000C IRQCLR 4 W 0x00000000 MMR to disable IRQ sources. 0x0010 SWICFG 4 W 0x00000000 Software interrupt configuration MMR. which can contain up to 32 pointers to separate subroutine handlers. Source 7. An interrupt can have a priority setting of 0 to 7. 0x0030 IRQCONN 4 R/W 0x00000000 Used to enable IRQ and FIQ interrupt nesting. 0x0038 IRQCLRE 4 R/W 0x00000000 Used to clear an edge-level-triggered interrupt source. caused an interrupt exception. 0x0100 FIQSTA 4 R 0x00000000 Active FIQ source status. 0x0104 FIQSIG 4 R Current state of all FIQ sources (enabled and disabled). 0x0108 FIQEN 4 R/W 0x00000000 Enabled FIQ sources. 0x010C FIQCLR 4 W 0x00000000 MMR to disable FIQ sources. Table 18. System Control Address Base = 0xFFFF0200 0x0220 REMAP1 1 R/W 0x00 Remap control register. See the Remap Operation section. 0x0230 RSTSTA 1 R/W 0x01 RSTSTA status MMR. See the Reset section. 0x0234 RSTCLR 1 W 0x00 Register for clearing the RSTSTA register.

Table 19. Timer Address Base = 0xFFFF0300 0x0320 T0LD 4 R/W 0x00000000 Timer0 load register. 0x0324 T0VAL 4 R 0xFFFFFFFF Timer0 value register. 0x0328 T0CON 4 R/W 0x01000000 Timer0 control MMR. 0x032C T0CLRI 1 W N/A Timer0 interrupt clear register. 0x0330 T0CAP 4 R 0x00000000 Timer0 capture register. 0x0340 T1LD 4 R/W 0x00000000 Timer1 load register. 0x0344 T1VAL 4 R 0xFFFFFFFF Timer1 value register. 0x0348 T1CON 2 R/W 0x0000 Timer1 control MMR. 0x034C T1CLRI 1 W N/A Timer1 interrupt clear register. 0x0360 T2LD 2 R/W 0x3BF8 Timer2 load register. 0x0364 T2VAL 2 R 0x3BF8 Timer2 value register. 0x0368 T2CON 2 R/W 0x0000 Timer2 control MMR. 0x036C T2CLRI 1 W N/A Timer2 interrupt clear register. 0x0380 T3LD 2 R/W 0x0000 Timer3 load register. 0x0384 T3VAL 2 R 0xFFFF Timer3 value register. 0x0388 T3CON 4 R/W 0x00000000 Timer3 control MMR. 0x038C T3CLRI 1 W N/A Timer3 interrupt clear register. 0x0390 T3CAP 2 R 0x0000 Timer3 capture register. Table 20. PLL Base Address = 0xFFFF0400 0x0404 POWKEY1 2 W 0xXXXX POWCON0 prewrite key. 0x0408 POWCON0 1 R/W 0x7B Power control and core speed control register. 0x040C POWKEY2 2 W 0xXXXX POWCON0 postwrite key. 0x0410 PLLKEY1 2 W 0xXXXX PLLCON prewrite key. 0x0414 PLLCON 1 R/W 0x00 PLL clock source selection MMR. 0x0418 PLLKEY2 2 W 0xXXXX PLLCON postwrite key. 0x0434 POWKEY3 2 W 0xXXXX POWCON1 prewrite key. 0x0438 POWCON1 2 R/W 0x124 Power control register. 0x043C POWKEY4 2 W 0xXXXX POWCON1 postwrite key. 0x0464 GP0KEY1 2 W 0xXXXX GP0CON1 prewrite key. 0x046C GP0KEY2 2 W 0xXXXX GP0CON1 postwrite key.

Table 21. ADC Address Base = 0xFFFF0500 0x0500 ADCSTA 2 R 0x0000 ADC status MMR. 0x0504 ADCMSKI 2 R/W 0x0000 ADC interrupt source enable MMR. 0x0508 ADCMDE 1 R/W 0x03 ADC mode register. 0x050C ADC0CON 2 R/W 0x8000 Primary ADC control MMR. 0x0510 ADC1CON 2 R/W 0x0000 Auxiliary ADC control MMR. 0x0514 ADCFLT 2 R/W 0x0007 ADC filter control MMR. 0x0518 ADCCFG 1 R/W 0x00 ADC configuration MMR. 0x051C ADC0DAT 4 R 0x00000000 Primary ADC result MMR. Primary ADC offset calibration setting. 0x052C ADC0GN1 2 R/W 0x5555 Primary ADC offset MMR. configuration bit (ADCLPMCFG[1:0]) in Table 42. 0x0534 ADC0RCR 2 R/W 0x0001 Primary ADC result counter/reload MMR. 0x0538 ADC0RCV 2 R 0x0000 Primary ADC result counter MMR. 0x053C ADC0TH 2 R/W 0x0000 Primary ADC 16-bit comparator threshold MMR. 0x0540 ADC0THC 2 R/W 0x0001 Primary ADC 16-bit comparator threshold counter limit. 0x0548 ADC0ACC 4 R 0x00000000 Primary ADC accumulator. 0x054C ADC0ATH 4 R/W 0x00000000 Primary ADC 32-bit comparator threshold MMR. 0x0570 IEXCON 1 R/W 0x00 Excitation current sources control register. 1 Updated by the kernel to part specific calibration value. Table 22. DAC Control Address Base = 0xFFFF0600 0x0600 DAC0CON 2 R/W 0x0200 DAC control register. 0x0604 DAC0DAT 4 R/W 0x00000000 DAC output data register. Table 23. UART Base Address = 0xFFFF0700 0x0700 COMTX 1 W N/A UART transmit register. 0x0700 COMRX 1 R 0x00 UART receive register. 0x0700 COMDIV0 1 R/W 0x00 UART Standard Baud Rate Generator Divisor Value 0. 0x0704 COMIEN0 1 R/W 0x00 UART Interrupt Enable MMR 0. 0x0704 COMDIV1 1 R/W 0x00 UART Standard Baud Rate Generator Divisor Value 1. 0x0708 COMIID0 1 R 0x01 UART Interrupt Identification 0. 0x070C COMCON0 1 R/W 0x00 UART Control Register 0. 0x0710 COMCON1 1 R/W 0x00 UART Control Register 1. 0x0714 COMSTA0 1 R 0x60 UART Status Register 0. 0x0718 COMSTA1 1 R 0x00 UART Status Register 1. 0X072C COMDIV2 2 R/W 0x0000 UART fractional divider MMR.

Table 24. I2C Base Address = 0xFFFF0900 0x0900 I2CMCON 2 R/W 0x0000 I2C master control register. 0x0904 I2CMSTA 2 R 0x0000 I2C master status register. 0x0908 I2CMRX 1 R 0x00 I2C master receive register. 0x090C I2CMTX 1 W 0x00 I2C master transmit register. this register prior to reading from a slave device. number of bytes already received during a read from slave sequence. communications. Only used in 10-bit mode. 0x0924 I2CDIV 2 R/W 0x1F1F I2C clock control register. Used to configure the SCLK frequency. 0x0928 I2CSCON 2 R/W 0x0000 I2C slave control register. 0x092C I2CSSTA 2 R/W 0x0000 I2C slave status register. 0x0930 I2CSRX 1 R 0x00 I2C slave receive register. 0x0934 I2CSTX 1 W 0x00 I2C slave transmit register. 0x0938 I2CALT 1 R/W 0x00 I2C hardware general call recognition register. 0x093C I2CID0 1 R/W 0x00 I2C Slave ID0 register. Slave bus ID register. 0x0940 I2CID1 1 R/W 0x00 I2C Slave ID1 register. Slave bus ID register. 0x0944 I2CID2 1 R/W 0x00 I2C Slave ID2 register. Slave bus ID register. 0x0948 I2CID3 1 R/W 0x00 I2C Slave ID3 register. Slave bus ID register. 0x094C I2CFSTA 2 R/W 0x0000 I2C FIFO status register. Used in both master and slave modes. Table 25. SPI Base Address = 0xFFFF0A00 0x0A00 SPISTA 4 R 0x00000000 SPI status MMR. 0x0A04 SPIRX 1 R 0x00 SPI receive MMR. 0x0A08 SPITX 1 W 0x00 SPI transmit MMR. 0x0A0C SPIDIV 1 W 0x1B SPI baud rate select MMR. 0x0A10 SPICON 2 R/W 0x0000 SPI control MMR. Table 26. GPIO Base Address = 0xFFFF0D00 0x0D00 GP0CON0 4 R/W 0x00000000 GPIO Port 0 control MMR. 0x0D04 GP1CON 4 R/W 0x00000000 GPIO Port 1 control MMR. 0x0D08 GP2CON 4 R/W 0x00000000 GPIO Port 2 control MMR. 0x0D20 GP0DAT 4 R/W 0x000000XX GPIO Port 0 data control MMR. 0x0D24 GP0SET 4 W 0x000000XX GPIO Port 0 data set MMR. 0x0D28 GP0CLR 4 W 0x000000XX GPIO Port 0 data clear MMR. 0x0D2C GP0PAR 4 R/W 0x00000000 GPIO Port 0 pull-up disable MMR. 0x0D30 GP1DAT 4 R/W 0x000000XX GPIO Port 1 data control MMR. 0x0D34 GP1SET 4 W 0x000000XX GPIO Port 1 data set MMR. 0x0D38 GP1CLR 4 W 0x000000XX GPIO Port 1 data clear MMR. 0x0D3C GP1PAR 4 R/W 0x00000000 GPIO Port 1 pull-up disable MMR. 0x0D40 GP2DAT 4 R/W 0x000000XX GPIO Port 2 data control MMR. 0x0D44 GP2SET 4 W 0x000000XX GPIO Port 2 data set MMR. 0x0D48 GP2CLR 4 W 0x000000XX GPIO Port 2 data clear MMR. 0x0D4C GP2PAR 4 R/W 0x00000000 GPIO Port 2 pull-up disable MMR.

Table 27. Flash/EE Base Address = 0xFFFF0E00 0x0E00 FEESTA 2 R 0x20 Flash/EE status MMR. 0x0E04 FEEMOD 2 R/W 0x0000 Flash/EE control MMR. 0x0E08 FEECON 1 R/W 0x07 Flash/EE control MMR. 0x0E0C FEEDAT 2 R/W 0xXXXX Flash/EE data MMR. 0x0E10 FEEADR 2 R/W 0x0000 Flash/EE address MMR. 0x0E18 FEESIG 3 R 0xFFFFFF Flash/EE LFSR MMR. 0x0E1C FEEPRO 4 R/W 0x00000000 Flash/EE protection MMR. 0x0E20 FEEHID 4 R/W 0xFFFFFFFF Flash/EE protection MMR. Table 28. PWM Base Address = 0xFFFF0F80 0x0F84 PWM0COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 0 and PWM Output 1. 0x0F88 PWM0COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 0 and PWM Output 1. 0x0F8C PWM0COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 0 and PWM Output 1. 0x0F90 PWM0LEN 2 R/W 0x0000 Frequency control for PWM Output 0 and PWM Output 1. 0x0F94 PWM1COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 2 and PWM Output 3. 0x0F98 PWM1COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 2 and PWM Output 3. 0x0F9C PWM1COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 2 and PWM Output 3. 0x0FA0 PWM1LEN 2 R/W 0x0000 Frequency control for PWM Output 2 and PWM Output 3. 0x0FA4 PWM2COM0 2 R/W 0x0000 Compare Register 0 for PWM Output 4 and PWM Output 5. 0x0FA8 PWM2COM1 2 R/W 0x0000 Compare Register 1 for PWM Output 4 and PWM Output 5. 0x0FAC PWM2COM2 2 R/W 0x0000 Compare Register 2 for PWM Output 4 and PWM Output 5. 0x0FB0 PWM2LEN 2 R/W 0x0000 Frequency control for PWM Output 4 and PWM Output 5.

code to initiate a software reset event. to initiate a software reset. Table 29. RSTSTA/RSTCLR MMR Bit Designations Cleared by setting the corresponding bit in RSTCLR. Automatically set when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR.

1 If the software reset bit in RSTSTA is set, any write to RSTCLR that does not

clear this bit generates a software reset. Table 30. Device Reset Implications

Figure 13. Clocking System

1. Enable the Timer1 interrupt and configure it for a timeout
2. Follow the write sequence to the PLLCON register, setting the

OSEL bits to [10] and clearing the EXTCLK bit.

1. Force the part into nap mode by following the correct write

sequence to the POWCON register.

1. When the part is interrupted from nap mode by the Timer1

To switch to an external clock on P2.0, configure P2.0 in Mode 0. ance is 1%. The external clock is divided by 2 internally on the part. default, the part uses the internal oscillator feeding the PLL. different modes and indicates the power-up time. other parts on the test board where these values are measured.

powers down the PWM and UART blocks. immediately before writing to POWCON0. controlling the CPU clock (HCLK). Table 31. POWCON0 MMR Bit Designations 7 Reserved This bit must always be set to 0. Cleared by user to power down the external crystal circuitry. Set by user to enable the external crystal circuitry. source remain in normal power mode. enabled; Bit 3, Bit 4, and Bit 5 must be cleared simultaneously. Set by default, and set by hardware on a wake-up event. SRAM, Flash/EE memory and GPIO interfaces, and SPI/I2C and UART serial ports. must be cleared simultaneously. Set by default and/or by hardware on a wake-up event. Wake-up timer (Timer1) can remain active. Cleared to power down the ARM core. Set by default and set by hardware on a wake-up event.

PWM, UART and I2C/SPI blocks. Table 32. POWCON1 MMR Bit Designations 15:9 Reserved This bit must always be set to 0. 8 PWMOFF PWM power-down bit. Set by user to 1 to enable the PWM block. This bit is set by default. Cleared by user to 0 to power down the PWM block. 7:6 Reserved Reserved bits. Always clear these bits to 0. 5 UARTOFF UART power-down bit. Set by user to 1 to enable the UART block. This bit is set by default. Cleared by user to 0 to power down the UART block. 4:3 Reserved Reserved bits. Always clear these bits to 0. 2 I2CSPIOFF I2C/SPI power-down bit. Set by user to 1 to enable the I2C/SPI blocks. This bit is set by default. Cleared by user to 0 to power down the I2C/SPI blocks. 1:0 Reserved Reserved Bits. Always clear these bits to 0. Table 33. ADuC7060/ADuC7061 Power Saving Modes

1111 Active Yes Yes Yes Yes Yes 130 ms at CD = 0

1000 Sleep Yes Yes 66 μs at CD = 0; 900 μs at CD = 7

0000 Stop Yes 66 μs at CD = 0; 900 μs at CD = 7

Table 34. Typical Current Consumption at 25°C in mA1 1 All values listed in Table 34 have been taken with both ADCs turned off. 2 In active mode, GP0PAR bit 7 =1. therefore, setting this bit in user code will not affect the BMoperation. Function: This register selects the clock input to the PLL. Table 35. PLLCON MMR Bit Designations 7:3 Reserved These bits must always be set to 0.

2 EXTCLK Set this bit to 1 to select external clock input

Clear this bit to disable the external clock. 1:0 OSEL Oscillator selection bits. [00] = internal 32,768 Hz oscillator. [01] = internal 32,768 Hz oscillator. [11] = internal 32,768 Hz oscillator.

Figure 14. Analog Block Diagram with up to seven single-ended input channels. four single-ended input channels. The auxiliary ADC incorporates a buffer on its input stage. weigh scale, or strain gage type applications.

Table 36. Primary ADC—Typical Output RMS Noise in Normal Mode (μV)1 1 The input voltage range is centered around the common-mode voltage and should meet the input voltage range specified in the Electrical Specifications section. Table 37. Primary ADC—Typical Output RMS Effective Number of Bits in Normal Mode (Peak-to-Peak Bits in Parentheses) Table 38. Auxilary ADC—Typical Output RMS Noise to the ADC4/EXT_REF2IN+ and ADC5/EXT_REF2IN− pins. By default, each ADC uses the internal 1.2 V reference source. bits in the ADC0 control register, ADC0CON. bits in the ADC1 control register, ADC1CON. for ADC0, the HIGHEXTREF0 bit must be set in ADC0CON. Figure 15. Example Circuit Using Diagnostic Current Sources

Table 39. Example Scenarios for Using Diagnostic Current Sources diagnostic currents disabled. with diagnostic currents disabled. for further details on the decimation factor values. giving an ADC throughput range of 50 Hz to 8 kHz. speeds, put ADC into idle mode before restarting. in applications where drift and noise rejection are required. controlled by the ADC0PGA[3:0] bits in the ADC0CON MMR. allows up to 2 mA to output current on a single excitation pin.

• ADCMDE[4:3]—Setting these bits enables normal mode, low power mode, or low power plus mode.
• ADCMDE[5]—Setting this bit configures the part for low power mode.
• ADCMDE[7]—Clearing this bit further reduces power consumption by reducing the frequency of the ADC clock.

counter reaches a preset value (ADC0RCR). any further software processing. channel that measures die temperature. The typical temperature coefficient is 0.28 mV/°C. Figure 16. ADC Output vs. Temperature MMRs that are described in detail in the following sections. the ADCSTA MMR to determine the source of the interrupt. ADCMSKI MMR described in Table 41.

Table 40. ADCSTA MMR Bit Designations 15 ADCCALSTA ADC calibration status. This bit is set automatically in hardware to indicate that an ADC calibration cycle has been completed. This bit is cleared after ADCMDE is written to. This bit is reserved for future functionality. 13 ADC1CERR Auxiliary ADC conversion error. This bit is cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register. 12 ADC0CERR Primary ADC conversion error. This bit is cleared when a valid (in-range) conversion result is written to the ADC0DAT register. 11:7 Not used. These bits are reserved for future functionality and should not be monitored by user code. 6 ADC0ATHEX ADC0 accumulator comparator threshold exceeded. comparator threshold register, ADC0ATH. This bit is cleared when the value in ADC0ACC does not exceed the value in ADC0ATH. 5 Not used. This bit is reserved for future functionality and should not be monitored by user code. primary ADC conversions equals the value in the ADC0THV MMR. Otherwise, this bit is cleared. changed via the ADC0CON MMR. 2 Not used. This bit is reserved for future functionality and should not be monitored by user code. 1 ADC1RDY Auxiliary ADC result ready bit. ADC1DAT MMR. It is also set at the end of a calibration sequence. the primary ADC is not enabled. 0 ADC0RDY Primary ADC result ready bit. ADC0DAT MMR. It is also set at the end of a calibration sequence. This bit is cleared by reading ADC0DAT.

same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled. By default, all bits are 0, meaning all ADC interrupt sources are disabled. Table 41. ADCMSKI MMR Bit Designations 7 Not used. This bit is reserved for future functionality and should not be monitored by user code. 6 ADC0ATHEX_INTEN ADC0 accumulator comparator threshold exceeded interrupt enable bit. When set to 1, this bit enables an interrupt when the ADC0ATHEX bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 5 Not used. This bit is reserved for future functionality and should not be monitored by user code. 4 ADC0THEX_INTEN Primary channel ADC comparator threshold exceeded interrupt enable bit. When set to 1, this bit enables an interrupt when the ADC0THEX bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 3 ADC0OVR_INTEN When set to 1, this bit enables an interrupt when the ADC0OVR bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 2 Not used. This bit is reserved for future functionality and should not be monitored by user code. 1 ADC1RDY_INTEN Auxiliary ADC result ready bit. When set to 1, this bit enables an interrupt when the ADC1RDY bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 0 ADC0RDY_INTEN Primary ADC result ready bit. When set to 1, this bit enables an interrupt when the ADC0RDY bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. Function: The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 42. ADCMDE MMR Bit Designations 7 ADCCLKSEL Set this bit to 1 to enable ADCCLK = 512 kHz. This bit should be set for normal ADC operation. Clear this bit to enable ADCCLK = 131 kHz. This bit should be cleared for low power ADC operation. 6 Not used. This bit is reserved for future functionality and should not be monitored by user code. 5 ADCLPMEN Enable low power mode. This bit has no effect if ADCMDE[4:3] = 00 (ADC is in normal mode). This bit must be set to 1 in low power mode. Clearing this bit in low power mode results in erratic ADC results.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 45 of 107 Bit Name Description 4:3 ADCLPMCFG[1:0] ADC power mode configuration. [00] = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance. [01] = ADC low power mode. [10] = ADC normal mode, same as [00]. [11] = ADC low power plus mode (low power mode and PGA off). 2:0 ADCMD[2:0] ADC operation mode configuration. [000] = ADC power-down mode. All ADC circuits and the input amplifier are powered down. [001] = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts at a frequency equal to fADC. ADCxRDY must be cleared to enable new data to be written to ADC0DAT/ADC1DAT. [010] = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC enters idle mode when the single shot conversion is complete. A single conversion takes two to three ADC clock cycles, depending on the chop mode. [011] = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. The part enters this mode after calibration. [100] = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using an internally generated 0 V. The calibration is carried out at the user-programmed ADC settings; therefore, as with a normal single ADC conversion, it takes two to three ADC conversion cycles before a fully settled calibration result is ready. The calibration result is automatically written to the ADCxOF MMR of the respective ADC. The ADC returns to idle mode, and the calibration and conversion ready status bits are set at the end of an offset calibration cycle. Note: Always use ADC0 for single-ended self-calibration cycles on the primary ADC. Always use ADC0/ADC1 when self-calibrating for a differential input to the primary ADC. [101] = ADC self-gain calibration. In this mode, a gain calibration against an internal reference voltage is performed on all enabled ADCs. A gain calibration is a two-stage process and takes twice the time of an offset calibration. The calibration result is automatically written to the ADCxGN MMR of the respective ADC. The ADC returns to idle mode and the calibration and conversion ready status bits are set at the end of a gain calibration cycle. An ADC self-gain calibration should only be carried out on the primary channel ADC. Note that self-gain calibration works only when the gain = 1; do not use it when the gain > 1. [110] = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC channels against an external zero-scale voltage driven at the ADC input pins. To do this, short the channel externally. [111] = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels against an external full-scale voltage driven at the ADC input pins. The ADCxGN register is updated after a full-scale calibration sequence. Primary ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default value: 0x8000 Access: Read and write Function: The primary channel ADC control MMR is a 16-bit register. If the primary ADC is reconfigured via ADC0CON, the auxiliary ADC is also reset.

Table 43. ADC0CON MMR Bit Designations 15 ADC0EN Primary channel ADC enable. This bit is set to 1 by user code to enable the primary ADC. 14:13 ADC0DIAG[1:0] Diagnostic current source enable bits. [01] = enables a 50 μA current source on the selected positive input (for example, ADC0). [10] = enables a 50 μA current source on the selected negative input (for example, ADC1). [11] = enables a 50 μA current source on both selected inputs (for example, ADC0 and ADC1). Clear this bit when using the internal reference or an external reference of less than 1.35 V. 11 AMP_CM This bit is set to 1 by user to set the PGA output common-mode voltage to AVDD/2. 10 ADC0CODE Primary channel ADC output coding. This bit is set to 1 by user code to configure primary ADC output coding as unipolar. This bit is cleared to 0 by user code to configure primary ADC output coding as twos complement. ADC5 to a minimum level of 0.1 V. [0000] = ADC0/ADC1 (differential mode). [0001] = ADC0/ADC5 (single-ended mode). [0010] = ADC1/ADC5 (single-ended mode). [0011] = VREF+, VREF−. Note: This is the reference selected by the ADC0REF bits. [0100] = Not used. This bit combination is reserved for future functionality and should not be written. [0101] = ADC2/ADC3 (differential mode). [0110] = ADC2/ADC5 (single-ended mode). [0111] = ADC3/ADC5 (single-ended mode). [1000] = internal short to ADC1. [1001] = internal short to ADC1. 5:4 ADC0REF[1:0] Primary channel ADC reference select. HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V. [11] = (AVDD, AGND) divide-by-two selected. 3:0 ADC0PGA[3:0]. Primary channel ADC gain select. Note, nominal primary ADC full-scale input voltage = (VREF/gain). [0000] = ADC0 gain of 1. Buffer of negative input is bypassed. [0010] = ADC0 gain of 4 (default value). Enables the in-amp. [0110] = ADC0 gain of 64 (maximum PGA gain setting). [0111] = ADC0 gain of 128 (extra gain implemented digitally). [1XXX] = ADC0 gain is undefined.

Function: The auxiliary ADC control MMR is a 16-bit register. Table 44. ADC1CON MMR Bit Designations 15 ADC1EN Auxiliary channel ADC enable. This bit is set to 1 by user code to enable the auxiliary ADC. Clearing this bit to 0 powers down the auxiliary ADC. ADCs cannot enable the diagnostic current sources at the same time. [01] = enables a 50 μA current source on selected positive input (for example, ADC2). [10] = enables a 50 μ A current source on selected negative input (for example, ADC3). [11] = enables a 50 μ A current source on both selected inputs (for example, ADC2 and ADC3). Clear this bit when using the internal reference or an external reference of less than 1.35 V. 11 ADC1CODE Auxiliary channel ADC output coding. This bit is set to 1 by user code to configure auxiliary ADC output coding as unipolar. This bit is cleared to 0 by user code to configure auxiliary ADC output coding as twos complement. ADC5 to a minimum level of 0.1 V. [0000] = ADC2/ADC3 (differential mode). [0001] = ADC4/ADC5 (differential mode). [0010] = ADC6/ADC7 (differential mode). [0011] = ADC8/ADC9 (differential mode). [0100] = ADC2/ADC5 (single-ended mode). [0101] = ADC3/ADC5 (single-ended mode). [0110] = ADC4/ADC5 (single-ended mode). [0111] = ADC6/ADC5 (single-ended mode). [1000] = ADC7/ADC5 (single-ended mode). [1001] = ADC8/ADC5 (single-ended mode). [1010] = ADC9/ADC5 (single-ended mode). [1011] = internal temperature sensor+/internal temperature sensor−. [1100] = VREF+, VREF−. Note: This is the reference selected by the ADC1REF bits. [1111] = internal short to ADC3.

6:4 ADC1REF[2:0] Auxiliary channel ADC reference select. HIGHEXTREF1 bit if reference voltage exceeds 1.35 V. [100] = (AVDD, ADC3). ADC3 can be used as the negative input terminal for the reference source. 3:2 BUF_BYPASS[1:0] Buffer bypass. [00] = full buffer on. Both positive and negative buffer inputs active. [01] = negative buffer is bypassed, positive buffer is on. [10] = negative buffer is on, positive buffer is bypassed. [11] = full buffer bypass. Both positive and negative buffer inputs are off. 1:0 Digital gain. Select for auxiliary ADC inputs. into idle mode before restarting. Table 45. ADCFLT MMR Bit Designations 14 RAVG2 Running average-by-2 enable bit. not reduce the ADC output rate but does increase the settling time by one conversion period. Cleared by user to disable the running average function. 13:8 AF[5:0] Averaging factor (AF). The values written to these bits are used to implement a programmable first-order sinc3 post filter. decimation factor) in this table.

where fNOTCH is the location of the first notch in the response. when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125. For SF = 126, fADC is forced to 60 Hz. For SF = 127, fADC is forced to 50 Hz. For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 46. that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode. 2 In low power mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All fADC calculations should be divided by 4 (approximately). Table 46. ADC Conversion Rates and Settling Times 1 An additional time of approximately 60 µs per ADC is required before the first ADC is available. Table 47. Allowable Combinations of SF and AF

Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 48. ADCCFG MMR Bit Designations 7 GNDSW_EN Analog ground switch enable. When this bit is cleared, the analog ground switch is disconnected from the external pin. 6:5 ADC0ACCEN[1:0] Primary channel (32-bit) accumulator enable. (ADCSTA[0] set twice) before the accumulator can be re-enabled to ensure that the accumulator is reset. accumulator total; the accumulator is clamped to a minimum value of 0. to accumulate negatively, below 0. [11] = accumulator and comparator active. This causes an ADC0 interrupt if ADCMSKI[6] is set. 4:3 ADC0CMPEN[1:0] Primary ADC comparator enable bits. [01] = comparator active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH. counter value (ADC0THV) to 0. counter value (ADC0THV) toward 0. 2 ADC0OREN ADC0 overrange enable. reading must be outside this range for greater than 125 µs for the flag to be set. Do not use this feature in ADC low power mode. 1 GNDSW_RES_EN Set to 1 to enable a 20 kΩ resistor in series with the ground switch. Clear this bit to disable this resistor. 0 ADCRCEN ADC result counter enable. Set by user to enable the result count mode. ADC interrupts occur if ADC0RCR = ADC0RCV. Cleared to disable the result counter. ADC interrupts occur after every conversion.

all asserted ready flags (ADCSTA[1:0]). Table 49. ADC0DAT MMR Bit Designations 23:0 ADC0 24-bit conversion result. conversion result from the auxiliary ADC. Table 50. ADC1DAT MMR Bit Designations 23:0 ADC1 24-bit conversion result. calibration coefficient for the primary ADC. ADC must be in idle mode for at least 23 µs. Table 51. ADC0OF MMR Bit Designations 15:0 ADC0 16-bit offset calibration value. Table 52. ADC1OF MMR Bit Designations 15:0 ADC1 16-bit offset calibration value.

idle mode for at least 23 μs. Table 53. ADC0GN MMR Bit Designations 15:0 ADC0 16-bit calibration gain value. at power-on with a factory default value. Table 54. ADC1GN MMR Bit Designations 15:0 ADC1 16-bit gain calibration value. counter enable bit in the ADCCFG MMR. Table 55. ADC0RCR MMR Bit Designations 15:0 ADC0 result counter limit/reload register. interrupts, generating a lower interrupt rate. result counter is enabled via ADCCFG[0]. the ADC0CON or ADCMDE is written. Table 56. ADC0RCV MMR Bit Designations 15:0 ADC0 result counter register.

Table 57. ADC0TH MMR Bit Designations 15:0 ADC0 16-bit comparator threshold register. Table 58. ADC0THC MMR Bit Designations 7:0 ADC0 8-bit threshold counter limit register. Table 59. ADC0THV MMR Bit Designations 7:0 ADC0 8-bit threshold exceeded counter register. determine when it is safe to read this MMR. reconfiguring the primary channel ADC. Table 60. ADC0ACC MMR Bit Designations 31:0 ADC0 32-bit accumulator register.

Table 61. ADC0ATH MMR Bit Designations Figure 17. Primary ADC Accumulator/Comparator/Counter Block Diagram

The DAC has four selectable ranges.

• 0 V to VREF (internal band gap 1.2 V reference)
• VREF− to VREF+
• ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+
• 0 V to AVDD The maximum signal range is 0 V to AVDD. Op Amp Mode As an option, the DAC can be disabled and its output buffer used as an op amp. MMR INTERFACE The DAC is configurable through a control register and a data register. DAC0CON Register Name: DAC0CON Address: 0xFFFF0600 Default value: 0x0200 Access: Read and write

Table 63. DAC0CON MMR Bit Designations 9 DACPD Set to 1 to power down DAC output (DAC output is tristated). Clear this bit to enable the DAC. sections for further details on electrical specifications. Clear this bit to enable the DAC buffer. 7 OPAMP Set to 1 to place the DAC output buffer in op amp mode. Clear this bit to enable the DAC output buffer for normal DAC operation. 6 DACBUFBYPASS Set to 1 to bypass the output buffer and send the DAC output directly to the output pin. Clear this bit to buffer the DAC output. 5 DACCLK Cleared to 0 to update the DAC on the negative edge of HCLK. where the next value in the waveform is written to DAC0DAT at regular intervals of Timer0. 4 DACCLR Set to 1 for normal DAC operation. 3 DACMODE Set to 1 to enable the DAC in 16-bit interpolation mode. Set to 0 to enable the DAC in normal 12-bit mode. 2 Rate Used with interpolation mode. Set to 1 to configure the interpolation clock as UCLK/16. Set to 0 to configure the interpolation clock as UCLK/32. 1:0 DAC range bits [11] = 0 V to AVDD range. [10] = ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+. [00] = 0 V to VREF (1.2 V) range. Internal reference source.

reprogrammable memory space. and, more correctly, referred to as Flash/EE memory. devices at remote operating nodes. cycling endurance and Flash/EE memory data retention.

• Initial page erase sequence
• Read/verify sequence for a single Flash/EE
• Byte program sequence memory
• Second read/verify sequence endurance cycle In reliability qualification, every half word (16-bit wide) location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. The Flash/EE memory endurance qualification is carried out in accordance with JEDEC Retention Lifetime Specification A117 over the industrial temperature range of −40°C to +125°C. The results allow the specification of a minimum endurance figure over a supply temperature of 10,000 cycles. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts are qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature J = 85°C). As part of this qualification procedure, the Flash/ EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time that the Flash/EE memory is reprogrammed. Also note that retention lifetime, based on activation energy of 0.6 eV , derates with T J, as shown in Figure 22. 150 300 450 600 30 40 55 70 85 100 125 135 150 RETENTION (Years) JUNCTION TEMPERATURE (°C) 07079-016

Figure 22. Flash/EE Memory Data Retention using the serial download mode or the provided JTAG mode. is not completed in this period, a reset occurs.

request (FIQ). All the interrupts can be masked separately. source, as described in Table 65. enabled by setting the ENIRQN bit in the IRQCONN register. interrupt controller is enabled. Table 65. IRQ/FIQ MMR Bit Designations

0 All interrupts OR’ed

1 Software interrupt User programmable interrupt

2 Undefined This bit is not used

3 Timer0 General-Purpose Timer0

4 Timer1 or wake-up

5 Timer2 or watchdog

6 Timer3 or STI timer General-Purpose Timer3

7 Undefined This bit is not used

8 Undefined This bit is not used

9 Undefined This bit is not used

10 ADC ADC interrupt source bit

11 UART UART interrupt source bit

12 SPI SPI interrupt source bit

13 XIRQ0 (GPIO IRQ0) External Interrupt 0

14 XIRQ1 (GPIO IRQ1) External Interrupt 1

15 I2C master IRQ I2C master interrupt source bit

16 I2C slave IRQ I2C slave interrupt source bit

17 PWM PWM trip interrupt source bit

18 XIRQ2 (GPIO IRQ2) External Interrupt 2

19 XIRQ3 (GPIO IRQ3) External Interrupt 3

internal and external events. IRQ are described in the following sections. to disable an interrupt. Clear to 0 has no effect.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 61 of 107 IRQCLR Register Name: IRQCLR Address: 0xFFFF000C Default value: 0x00000000 Access: Write only IRQSTA IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. IRQSTA Register Name: IRQSTA Address: 0xFFFF0000 Default value: 0x00000000 Access: Read only FAST INTERRUPT REQUEST (FIQ) The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR’ ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks. FIQSIG FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal, the corresponding bit in the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only. FIQSIG Register Name: FIQSIG Address: 0xFFFF0104 Default value: Undefined Access: Read only FIQEN FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corre- sponding source request is disabled or masked, which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt. FIQEN Register Name: FIQEN Address: 0xFFFF0108 Default value: 0x00000000 Access: Read and write FIQCLR FIQCLR is a write-only register that allows the FIQEN register to clear in order to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. FIQCLR Register Name: FIQCLR Address: 0xFFFF010C Default value: 0x00000000 Access: Write only FIQSTA FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine.

Table 66. SWICFG MMR Bit Designations and to be detected by the user in the IRQSTA/FIQSTA register.

• Vectored interrupts—allows a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and IRQVEC registers.
• IRQ/FIQ interrupts—can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is maximized, it is possible to have 16 separate interrupt levels.
• Programmable interrupt priorities—using the IRQP0 to IRQP2 registers, an interrupt source can be assigned an interrupt priority level value from 0 to 7. VIC MMRS IRQBASE The vector base register, IRQBASE, is used to point to the start address of memory used to store 32 pointer addresses. These pointer addresses are the addresses of the individual interrupt service routines. IRQBASE Register Name: IRQBASE Address: 0xFFFF0014 Default value: 0x00000000 Access: Read and write

Table 67. IRQBASE MMR Bit Designations 31:16 Read only Reserved Always read as 0. 15:0 R/W 0 Vector base address. setting Bit 0 of the IRQCONN register.

Table 68. IRQVEC MMR Bit Designations 1:0 Reserved 0 Reserved bits. for a level between 0 and 7. Level 0 is the highest priority level. Table 69. IRQP0 MMR Bit Designations 31:27 Reserved Reserved bits. 11:7 Reserved Reserved bits. 3:0 Reserved Interrupt 0 cannot be prioritized. Table 70. IRQP1 MMR Bit Designations 26:24 IRQ1PI A priority level of 0 to 7 can be set for IRQ1. 22:20 IRQ0PI A priority level of 0 to 7 can be set for IRQ0. 14:12 UARTPI A priority level of 0 to 7 can be set for UART. Table 71. IRQP2 MMR Bit Designations 31:15 Reserved Reserved bit. 14:12 IRQ3PI A priority level of 0 to 7 can be set for IRQ3. 10:8 IRQ2PI A priority level of 0 to 7 can be set for IRQ2.

and prioritization of FIQ interrupts. have a higher priority than an IRQ. Table 72. IRQCONN MMR Bit Designations

1 ENFIQN Setting this bit to 1 enables nesting of FIQ

or prioritization of FIQs is allowed.

0 ENIRQN Setting this bit to 1 enables nesting of IRQ

or prioritization of IRQs is allowed. this register, all interrupts of that priority and lower are blocked. Table 73. IRQSTAN MMR Bit Designations or prioritization of FIQs is allowed. setting Bit 1 of the IRQCONN register. Table 74. FIQVEC MMR Bit Designations 31:23 Read only 0 Always read as 0. 22:7 Read only 0 IRQBASE register value. 1:0 Reserved 0 Reserved bits.

Table 75. FIQSTAN MMR Bit Designations or prioritization of FIQs is allowed. configured as level triggered or rising/falling edge triggered. must be appropriately configured. appropriate bit in the IRQCLRE register. Table 76. IRQCONE MMR Bit Designations 31:8 Reserved These bits are reserved and should not be written to. 7:6 IRQ3SRC[1:0] [11] = External IRQ3 triggers on falling edge. [10] = External IRQ3 triggers on rising edge. [01] = External IRQ3 triggers on low level. [00] = External IRQ3 triggers on high level. 5:4 IRQ2SRC[1:0] [11] = External IRQ2 triggers on falling edge. [10] = External IRQ2 triggers on rising edge. [01] = External IRQ2 triggers on low level. [00] = External IRQ2 triggers on high level. 3:2 IRQ1SRC[1:0] [11] = External IRQ1 triggers on falling edge. [10] = External IRQ1 triggers on rising edge. [01] = External IRQ1 triggers on low level. [00] = External IRQ1 triggers on high level. 1:0 IRQ0SRC[1:0] [11] = External IRQ0 triggers on falling edge. [10] = External IRQ0 triggers on rising edge. [01] = External IRQ0 triggers on low level. [00] = External IRQ0 triggers on high level.

Table 77. IRQCLRE MMR Bit Designations

19 IRQ3CLRI A 1 must be written to this bit in the IRQ3

18 IRQ2CLRI A 1 must be written to this bit in the IRQ2

14 IRQ1CLRI A 1 must be written to this bit in the IRQ1

13 IRQ0CLRI A 1 must be written to this bit in the IRQ0

• Timer0
• Timer1 or wake-up timer
• Timer2 or watchdog timer
• Timer3 The four timers in their normal mode of operation can be either free running or periodic. In free running mode, the counter decrements/increments from the maximum or minimum value until zero/full scale and starts again at the maximum or minimum value. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero/full scale and starts again at the value stored in the load register. Note that the TxLD MMR should be configured before the TxCON MMR. The timer interval is calculated as follows: If the timer is set to count down then Interval = (TxLD x Prescaler) / Source Clock If the timer is set to count up then Interval = ((Full Scale - TxLD) x Prescaler) / Source Clock. The value of a counter can be read at any time by accessing its value register (TxV AL). Timers are started by writing in the control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time that the value of the counter reaches zero (if counting down) or full scale (if counting up). An IRQ can be cleared by writing any value to the clear register of the particular timer (TxCLRI).

Table 78. Timer Event Capture

0 Reserved

1 Timer0

2 Timer1 or wake-up timer

3 Timer2 or watchdog timer

4 Timer3

5 Reserved

6 Reserved

7 Reserved

8 ADC

9 UART

10 SPI

11 XIRQ0

12 XIRQ1

13 I2C master

14 I2C slave

15 PWM

16 XIRQ2 (GPIO IRQ2)

17 XIRQ3 (GPIO IRQ3)

Table 79. Hr:Min:Sec: hundreds format

with a prescaler of 1 (ignoring the external GPIOs). hours:minutes:seconds:hundredths. timer value is copied to T0CAP , and the timer continues to run. IRQ source enabled can be used with the timer capture feature.

• T0LD, T0V AL, and T0CAP are 32-bit registers and hold 32-bit, unsigned integers of which T0V AL and T0CAP are read only.
• T0CLRI is an 8-bit register and writing any value to this register clears the Timer0 interrupt.
• T0CON is the configuration MMR, which is described in Table 80. Timer0 features a postscaler that allows the user to count between 1 and 256 the number of Timer0 timeouts. To activate the post- scaler, the user sets Bit 18 and writes the desired number to count into Bits[24:31] of T0CON. When that number of timeouts is reached, Timer0 can generate an interrupt if T0CON[18] is set. Note that, if the part is in a low power mode and Timer0 is clocked from the GPIO or low power oscillator source, Timer0 continues to operate. Timer0 reloads the value from T0LD when Timer0 overflows. Timer0 Load Registers Name: T0LD Address: 0xFFFF0320 Default value: 0x00000000 Access: Read and write Function: T0LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Timer0 Clear Register Name: T0CLRI Address: 0xFFFF032C Access: Write only Function: This 8-bit, write-only MMR is written (with any value) by user code to clear the interrupt. Timer0 Value Register Name: T 0 VA L Address: 0xFFFF0324 Default value: 0xFFFFFFFF Access: Read only Function: T0V AL is a 32-bit register that holds the current value of Timer0. TIMER0 VALUE 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY/CD CORE CLOCK FREQUENCY GPIO PRESCALER 1, 16, 256, OR 32,768 TIMER0 IRQ 32-BIT UP/DOWN COUNTER 8-BIT POSTSCALER 32-BIT LOAD CAPTUREIRQ[31:0] 07079-017

Figure 23. Timer0 Block Diagram

Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Function: This 32-bit MMR configures the mode of operation of Timer0. Table 80. T0CON MMR Bit Designations 31:24 T0PVAL 8-bit postscaler. By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1. By reading these eight bits, the current value of the counter is read. 23 T0PEN Timer0 enable postscaler. Cleared to disable the Timer0 postscaler. 22:20 Reserved. These bits are reserved and should be written as 0 by user code. 18 T0SRCI Timer0 interrupt source. Set to select interrupt generation from the postscaler counter. Cleared to select interrupt generation directly from Timer0. 17 T0CAPEN Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16:12 T0CAPSEL Event Select Bits[17:0]. The events are described in Table 78. Set by user for Timer0 to count up. Cleared by user for Timer0 to count down (default). Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default).

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 70 of 107 Bit Name Description 5:4 T0FORMAT Format. [00] = binary (default). [01] = reserved. [10] = hours:minutes:seconds:hundredths (23 hours to 0 hours). [11] = hours:minutes:seconds:hundredths (255 hours to 0 hours). 3:0 T0SCALE Prescaler. [0000] = source clock/1 (default). [0100] = source clock/16. [1000] = source clock/256. [1111] = source clock/32,768. Note that all other values are undefined. TIMER1 OR WAKE-UP TIMER Timer1 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from one of four clock sources, namely, the core clock (which is the default selection), external 32.768 kHz watch crystal, or the 32.768 kHz oscillator. The selected clock source can be scaled by a factor of 1, 16, 256, or 32,768. The wake-up timer continues to run when the core clock is disabled. This gives a minimum resolution of 97.66 ns when operating at CD zero, the core is operating at 10.24 MHz, and with a prescaler of 1 (ignoring the external GPIOs). The counter can be formatted as a plain 32-bit value or as hours:minutes:seconds:hundredths. Timer1 reloads the value from T1LD either when Timer1 overflows or immediately when T1LD is written. The Timer1 interface consists of four MMRS.

• T1LD and T1V AL are 32-bit registers and hold 32-bit, unsigned integers. T1V AL is read only.
• T1CLRI is an 8-bit register. Writing any value to this register clears the Timer1 interrupt.
• T1CON is the configuration MMR, described in Table 81. Timer1 Load Registers Name: T1LD Address: 0xFFFF0340 Default value: 0x00000000 Access: Read and write Function: T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Timer1 Clear Register Name: T1CLRI Address: 0xFFFF034C Access: Write only Function: This 8-bit, write-only MMR is written (with any value) by user code to clear the interrupt. Timer1 Value Register Name: T 1 VA L Address: 0xFFFF0344 Default value: 0xFFFFFFFF Access: Read only Function: T1V AL is a 32-bit register that holds the current value of Timer1.

Figure 24. Timer1 Block Diagram Function: This 16-bit MMR configures the mode of operation of Timer1. Table 81. T1CON MMR Bit Designations 10: 9 T1CLKSEL Clock source select. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down (default). Set by user to enable Timer1. Cleared by user to disable Timer1 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). [10] = hours:minutes:seconds:hundredths (23 hours to 0 hours). This is only valid with a 32 kHz clock. [11] = hours:minutes:seconds:hundredths (255 hours to 0 hours). This is only valid with a 32 kHz clock. [0000] = source clock/1 (default). hours:minutes:seconds:hundredths. See Format 10 and Format 11 listed with Bits[5:4] in this table (Table 81).

overflows or immediately when T2CLRI is written. maximum prescaler/256 and full scale in T2LD. erase cycle and kernel execution. reloads the counter with T2LD and begins a new timeout period. should configure a minimum timeout period of 30 ms only. watchdog timer continues to count during power-down. The Timer2 interface consists of four MMRs.

• T2CON is the configuration MMR, described in (Table 82).
• T2LD and T2V AL are 16-bit registers (Bit 0 to Bit 15) and hold 16-bit, unsigned integers. T2V AL is read only.
• T2CLRI is an 8-bit register. Writing any value to this register clears the Timer2 interrupt in normal mode or resets a new timeout period in watchdog mode. Timer2 Load Register Name: T2LD Address: 0xFFFF0360 Default value: 0x3BF8 Access: Read and write Function: This 16-bit MMR holds the Timer2 reload value. Timer2 Clear Register Name: T2CLRI Address: 0xFFFF036C Access: Write only Function: This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer2 in watchdog mode to prevent a watchdog timer reset event. Timer2 Value Register Name: T 2 VA L Address: 0xFFFF0364 Default value: 0x3BF8 Access: Read only Function: This 16-bit, read-only MMR holds the current Timer2 count value. PRESCALER 1, 16, 256 TIMER2 IRQ WATCHDOG RESET16-BIT UP/DOWN COUNTER32.768kHz 16-BIT LOAD TIMER2 VALUE 07079-019

Figure 25. Timer2 Block Diagram

Function: This 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 82. Table 82. T2CON MMR Bit Designations 15:9 Reserved. These bits are reserved and should be written as 0 by user code. 8 T2DIR Count up/count down enable. Set by user code to configure Timer2 to count up. Cleared by user code to configure Timer2 to count down. Set by user code to enable Timer2. Cleared by user code to disable Timer2. 6 T2MOD Timer2 operating mode. Set by user code to configure Timer2 to operate in periodic mode. Cleared by user to configure Timer2 to operate in free running mode. 5 WDOGMDEN Watchdog timer mode enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. 4 Reserved. This bit is reserved and should be written as 0 by user code. 3:2 T2SCALE Timer2 clock (32.768 kHz) prescaler. 1 WDOGENI Watchdog timer IRQ enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. 0 T2PDOFF Stop Timer2 when power-down is enabled. Set by user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON0 MMR.

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 74 of 107 TIMER3 Timer3 is a general-purpose, 16-bit, count up/count down timer with a programmable prescaler. Timer3 can be clocked from the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. Timer3 has a capture register (T3CAP) that can be triggered by a selected IRQ source initial assertion. Once triggered, the current timer value is copied to T3CAP , and the timer continues to run. This feature can be used to determine the assertion of an event with increased accuracy. The Timer3 interface consists of five MMRs.

• T3LD, T3V AL, and T3CAP are 16-bit registers and hold 16-bit, unsigned integers. T3V AL and T3CAP are read only.
• T3CLRI is an 8-bit register. Writing any value to this register clears the interrupt.
• T3CON is the configuration MMR, described in Table 83. Timer3 Load Registers Name: T3LD Address: 0xFFFF0380 Default value: 0x0000 Access: Read and write Function: T3LD is a 16-bit register that holds the 16-bit value that is loaded into the counter. Timer3 Clear Register Name: T3CLRI Address: 0xFFFF038C Access: Write only Function: This 8-bit, write-only MMR is written (with any value) by user code to clear the interrupt. Timer3 Value Register Name: T 3 VA L Address: 0xFFFF0384 Default value: 0xFFFF Access: Read only Function: T3V AL is a 16-bit register that holds the current value of Timer3. Time3 Capture Register Name: T3CAP Address: 0xFFFF0390 Default value: 0x0000 Access: Read only Function: This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Timer3 Control Register Name: T3CON Address: 0xFFFF0388 Default value: 0x00000000 Access: Read and write Function: This 32-bit MMR configures the mode of operation of Timer3.

Table 83. T3CON MMR Bit Designations 17 T3CAPEN Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16:12 T3CAPSEL Event select range, 0 to 17. The events are described in Table 78. Set by user for Timer3 to count up. Cleared by user for Timer3 to count down (default). Set by user to enable Timer3. Cleared by user to disable Timer3 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default mode). [0000] = source clock/1 (default).

Table 84. PWM MMRs PWMCLRI PWM interrupt clear. pair of PWM outputs (PWM0 and PWM1) is shown in Figure 26. Figure 26. PWM Timing

1. The length of a PWM period is defined by PWMxLEN.

PWM0 and PWM1 waveforms in Figure 26. high-side waveform (PWM0) goes low. when the timer count reaches the value held in PWM0COM1.

Table 85. PWMCON MMR Bit Designations 15 Reserved This bit is reserved. Do not write to this bit. 14 Sync Enables PWM synchronization. transition on the P1.2/SYNC pin. Cleared by user to ignore transitions on the P1.2/SYNC pin. 13 PWM5INV Set to 1 by user to invert PWM5. Cleared by user to use PWM5 in normal mode. 12 PWM3INV Set to 1 by user to invert PWM3. Cleared by user to use PWM3 in normal mode. 11 PWM1INV Set to 1 by user to invert PWM1. Cleared by user to use PWM1 in normal mode. cleared and an interrupt is generated. Cleared by user to disable the PWMTRIP interrupt. 9 ENA If HOFF = 0 and HMODE = 1. Note that, if not in H-bridge mode, this bit has no effect. Set to 1 by user to enable PWM outputs. Cleared by user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 86. 8:6 PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider. 5 POINV Set to 1 by user to invert all PWM outputs. Cleared by user to use PWM outputs as normal. Set to 1 by user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low. Cleared by user to use the PWM outputs as normal. 3 LCOMP Load compare registers. PWM timer from 0x00 to 0x01. Cleared by user to use the values previously stored in the internal compare registers. Set to 1 by user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. Cleared by user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. Set to 1 by user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON. Cleared by user to operate the PWMs in standard mode. 0 PWMEN Set to 1 by user to enable all PWM outputs. Cleared by user to disable all PWM outputs. 1 In H-bridge mode, HMODE = 1. See Table 86 to determine the PWM outputs.

Table 86. PWM Output Selection 2 HS = high side, LS = low side. Table 87. Compare Registers

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 79 of 107 PWM0COM0 Compare Register Name: PWM0COM0 Address: 0xFFFF0F84 Default value: 0x0000 Access: Read and write Function: PWM0 output pin goes high when the PWM timer reaches the count value stored in this register. PWM0COM1 Compare Register Name: PWM0COM1 Address: 0xFFFF0F88 Default value: 0x0000 Access: Read and write Function: PWM0 output pin goes low when the PWM timer reaches the count value stored in this register. PWM0COM2 Compare Register Name: PWM0COM2 Address: 0xFFFF0F8C Default value: 0x0000 Access: Read and write Function: PWM1 output pin goes low when the PWM timer reaches the count value stored in this register. PWM0LEN Register Name: PWM0LEN Address: 0xFFFF0F90 Default value: 0x0000 Access: Read and write Function: PWM1 output pin goes high when the PWM timer reaches the value stored in this register. PWM1COM0 Compare Register Name: PWM1COM0 Address: 0xFFFF0F94 Default value: 0x0000 Access: Read and write Function: PWM2 output pin goes high when the PWM timer reaches the count value stored in this register. PWM1COM1 Compare Register Name: PWM1COM1 Address: 0xFFFF0F98 Default value: 0x0000 Access: Read and write Function: PWM2 output pin goes low when the PWM timer reaches the count value stored in this register. PWM1COM2 Compare Register Name: PWM1COM2 Address: 0xFFFF0F9C Default value: 0x0000 Access: Read and write Function: PWM3 output pin goes low when the PWM timer reaches the count value stored in this register. PWM1LEN Register Name: PWM1LEN Address: 0xFFFF0FA0 Default value: 0x0000 Access: Read and write Function: PWM3 output pin goes high when the PWM timer reaches the value stored in this register.

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 80 of 107 PWM2COM0 Compare Register Name: PWM2COM0 Address: 0xFFFF0FA4 Default value: 0x0000 Access: Read and write Function: PWM4 output pin goes high when the PWM timer reaches the count value stored in this register. PWM2COM1 Compare Register Name: PWM2COM1 Address: 0xFFFF0FA8 Default value: 0x0000 Access: Read and write Function: PWM4 output pin goes low when the PWM timer reaches the count value stored in this register. PWM2COM2 Compare Register Name: PWM2COM2 Address: 0xFFFF0FAC Default value: 0x0000 Access: Read and write Function: PWM5 output pin goes low when the PWM timer reaches the count value stored in this register. PWM2LEN Register Name: PWM2LEN Address: 0xFFFF0FB0 Default value: 0x0000 Access: Read and write Function: PWM5 output pin goes high when the PWM timer reaches the value stored in this register. PWMCLRI Register Name: PWMCLRI Address: 0xFFFF0FB8 Default value: 0x0000 Access: Write only Function: Write any value to this register to clear a PWM interrupt source. This register must be written to before exiting a PWM interrupt service routine; otherwise, multiple interrupts occur.

tion options selectable in the configuration register. and ADuC7060/ADuC7061 fractional divider. Table 88 lists common baud rate values. Table 88. Baud Rate Using the Standard Baud Rate Generator generator allows the generation of accurate high speed baud rates. Figure 27. Fractional Divider Baud Rate Generation Table 89 lists common baud rate values. Table 89. Baud Rate Using the Fractional Baud Rate Generator

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 82 of 107 UART Transmit Register Write to this 8-bit register (COMTX) to transmit data using the UART. COMTX Register Name: COMTX Address: 0xFFFF0700 Access: Write only UART Receive Register This 8-bit register (COMRX) is read to receive data transmitted using the UART. COMRX Register Name: COMRX Address: 0xFFFF0700 Default value: 0x00 Access: Read only UART Divisor Latch Register 0 This 8-bit register (COMDIV0) contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates. COMDIV0 Register Name: COMDIV0 Address: 0xFFFF0700 Default value: 0x00 Access: Read and write UART Divisor Latch Register 1 This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates. COMDIV1 Register Name: COMDIV1 Address: 0xFFFF0704 Default value: 0x00 Access: Read and write UART Control Register 0 This 8-bit register (COMCON0) controls the operation of the UART in conjunction with COMCON1. COMCON0 Register Name: COMCON0 Address: 0xFFFF070C Default value: 0x00 Access: Read and write

Table 90. COMCON0 MMR Bit Designations 7 DLAB Divisor latch access. Set by user to enable access to the COMDIV0 and COMDIV1 registers. Set by user to force transmit to 0. Cleared to operate in normal mode. 5 SP Stick parity. Set by user to force parity to defined values. 4 EPS Even parity select bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. Cleared by user to generate one stop bit in the transmitted data.

Table 91. COMCON1 MMR Bit Designations 7:5 Reserved bits. Not used. the transmit pin is forced high. 3:2 Reserved bits. Not used. Set by user to force the RTS output to 0. Set by user to force the DTR output to 0. current status on the UA RT. Table 92. COMSTA0 MMR Bit Designations 6 TEMT COMTX and shift register empty status bit. more data is present in the shift register. 5 THRE COMTX empty status bit. Set automatically if COMTX is empty. present in the shift register. Set when the stop bit is invalid. Set when a parity error occurs. Set automatically when COMRX is full.

Function: COMSTA1 is a modem status register. Table 93. COMSTA1 MMR Bit Designations Cleared automatically by reading COMSTA1. individual UART interrupt sources. Table 94. COMIEN0 MMR Bit Designations 3 EDSSI Modem status interrupt enable bit. interrupt if COMSTA1[4] or COMSTA1[0] are set. 2 ELSI Receive status interrupt enable bit. 1 ETBEI Enable transmit buffer empty interrupt. 0 ERBFI Enable receive buffer full interrupt. buffer is full during a reception.

Table 95. COMIID0 MMR Bit Designations fractional divider for the ADuC7060/ADuC7061. Table 96. COMDIV2 MMR Bit Designations 15 FBEN Fractional baud rate generator enable bit. Table 88 for common baud rate values.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 87 of 107 I2C Each ADuC7060/ADuC7061 incorporates an I2C peripheral that can be configured as a fully I2C-compatible I2C bus master device or as a fully I2C bus-compatible slave device. The two pins used for data transfer, SDA and SCL, are configured in a wire-AND’e d format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up resistor values are between 4.7 kΩ and 10 kΩ. Users program the I2C bus peripheral (addressed in the I2C bus system). This ID can be modified any time that a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (read or write) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. The I2C peripheral can be configured only as a master or a slave at any given time. The same I2C channel cannot simultaneously support master and slave modes. The I2C interface on the ADuC7060/ADuC7061 includes the following features:

• Support for repeated start conditions. In master mode, the ADuC7060/ADuC7061 can be programmed to generate a repeated start. In slave mode, the ADuC7060/ADuC7061 recognizes repeated start conditions.
• In master and slave modes, the part recognizes both 7-bit and 10-bit bus addresses.
• In I2C master mode, the ADuC7060/ADuC7061 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence.
• Clock stretching can be enabled by other devices on the bus without causing any issues with the ADuC7060/ ADuC7061. However, the ADuC7060/ADuC7061 cannot enable clock stretching.
• In slave mode, the ADuC7060/ADuC7061 can be programmed to return a no acknowledge (NACK). This allows the validation of checksum bytes at the end of I2C transfers.
• Bus arbitration in master mode is supported.
• Internal and external loopback modes are supported for I2C hardware testing.
• The transmit and receive circuits in both master and slave modes contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs. CONFIGURING EXTERNAL PINS FOR I2C FUNCTIONALITY The I2C functions of the P0.1/SCLK/SCL and P0.3/MOSI/SDA pins of the ADuC7060/ADuC7061 device are P0.1 and P0.3. The function of P0.1 is the I2C clock signal (SCL) and the function of P0.3 is the I2C data signal (SDA). To configure P0.1 and P0.3 for I2C mode, Bit 4 and Bit 12 of the GP0CON0 register must be set to 1. Bit 1 of the GP0CON1 register must also be set to 1 to enable I2C mode. Note that, to write to GP0CON1, the GP0KEY1 register must be set to 0x7 immediately before writing to GP0CON1. Also, the GP0KEY2 register must be set to 0x13 immediately after writing to GP0CON1. The following code example shows this in detail: GP0CON0 = BIT4 + BIT12; // Select SPI/I2C alternative function for P0.1 and P0.3 GP0KEY1 = 0x7; // Write to GP0KEY1 GP0CON1 = BIT1; // Select I2C functionality for P0.1 and P0.3 GP0KEY2 = 0x13; // Write to GP0KEY2

ADuC7060/ADuC7061 Data Sheet Rev. F | Page 88 of 107 SERIAL CLOCK GENERATION The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CDIV MMR as follows: ) (2 )2( DIVLDIVH +++ = UCLK CLOCKSERIAL ff where: fUCLK is the clock before the clock divider. DIVH is the high period of the clock. DIVL is the low period of the clock. Thus, for 100 kHz operation DIVH = DIVL = 0x33 and for 400 kHz DIVH = 0x0A, DIVL = 0x0F The I2CDIV register corresponds to DIVH:DIVL. I2C BUS ADDRESSES Slave Mode In slave mode, the I2CID0, I2CID1, I2CID2, and I2CID3 registers contain the device IDs. The device compares the four I2CIDx registers to the address byte received from the bus master. To be correctly addressed, the 7 MSBs of any ID register must be identical to the 7 MSBs of the first received address byte. The least significant bit of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The ADuC7060/ADuC7061 also supports 10-bit addressing mode. When Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in the I2CID0 and I2CID1 registers. The 10-bit address is derived as follows: I2CID0[0] is the read/write bit and is not part of the I2C address. I2CID0[7:1] = Address Bits[6:0]. I2CID1[2:0] = Address Bits[9:7]. I2CID1[7:3] must be set to 11110b. Master Mode In master mode, the I2CADR0 register is programmed with the I2C address of the device. In 7-bit address mode, I2CADR0[7:1] are set to the device address. I2CADR0[0] is the read/write bit. In 10-bit address mode, the 10-bit address is created as follows: I2CADR0[7:3] must be set to 11110b. I2CADR0[2:1] = Address Bits[9:8]. I2CADR1[7:0] = Address Bits[7:0]. I2CADR0[0] is the read/write bit. I2C REGISTERS The I2C peripheral interface consists overall of 19 MMRs. Nine of these are master related only, nine are slave related only, and one MMR is common to both master and slave modes. I2C Master Registers I2C Master Control, I2CMCON Register Name: I2CMCON Address: 0xFFFF0900 Default value: 0x0000 Access: Read and write Function: This 16-bit MMR configures the I2C peripheral in master mode.

Table 97. I2CMCON MMR Bit Designations 15:9 Reserved. These bits are reserved and should not be written to. 8 I2CMCENI I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. 7 I2CNACKENI I2C no acknowledge (NACK) received interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a no acknowledge. Clear this interrupt source. 6 I2CALENI I2C arbitration lost interrupt enable bit. Set this bit to enable interrupts when the I2C master did not gain control of the I2C bus. Clear this interrupt source. 5 I2CMTENI I2C transmit interrupt enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte. Clear this interrupt source. 4 I2CMRENI I2C receive interrupt enable bit. Set this bit to enable interrupts when the I2C master receives data. Cleared by user to disable interrupts when the I2C master is receiving data. 3 Reserved. A value of 0 should be written to this bit. 2 I2CILEN I2C internal loopback enable. Cleared by user to disable loopback mode. 1 I2CBD I2C master backoff disable bit. Clear this bit to back off until the I2C bus becomes free. 0 I2CMEN I2C master enable bit. Set by user to enable the I2C master mode. Cleared to disable the I2C master mode.

Function: This 16-bit MMR is the I2C status register in master mode. Table 98. I2CMSTA MMR Bit Designations 15:11 Reserved. These bits are reserved. 10 I2CBBUSY I2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. 9 I2CMRxFO Master receive FIFO overflow. This bit is set to 1 when a byte is written to the receive FIFO when it is already full. This bit is cleared in all other conditions. 8 I2CMTC I2C transmission complete status bit. communicating. If the I2CMCENI bit in I2CMCON is set, an interrupt is generated when this bit is set. Clear this interrupt source.

7 I2CMND I2C master no acknowledge data bit

the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 6 I2CMBUSY I2C master busy status bit. Set to 1 when the master is busy processing a transaction. Cleared if the master is ready or if another master device has control of the bus. 5 I2CAL I2C arbitration lost status bit. interrupt is generated when this bit is set. This bit is cleared in all other conditions. 4 I2CMNA I2C master no acknowledge address bit. I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 3 I2CMRXQ I2C master receive request bit. This bit is set to 1 when data enters the receive FIFO. If the I2CMRENI in I2CMCON is set, an interrupt is generated. This bit is cleared in all other conditions. 2 I2CMTXQ I2C master transmit request bit. + write. If the I2CMTENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 1:0 I2CMTFSTA I2C master transmit FIFO status bits. [00] = I2C master transmit FIFO empty. [01] = 1 byte in master transmit FIFO. [10] = 1 byte in master transmit FIFO. [11] = I2C master transmit FIFO full.

sequence from a slave device. Table 99. I2CMCNT0 MMR Bit Designations

8 I2CRECNT Set this bit if more than 256 bytes are

Table 100. I2CADR0 MMR in 7-Bit Address Mode 0 R/W Bit 0 is the read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested. Table 101. I2CADR0 MMR in 10-Bit Address Mode

significant byte of the address. Table 102. I2CADR1 MMR in 10-Bit Address Mode Table 103. I2CDIV MMR Bit Designations

Table 104. I2CSCON MMR Bit Designations 10 I2CSTXENI Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. 9 I2CSRXENI Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. Clear this interrupt source. 8 I2CSSENI I2C stop condition detected interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. 7 I2CNACKEN I2C no acknowledge enable bit. Set this bit to no acknowledge the next byte in the transmission sequence. Clear this bit to let the hardware control the acknowledge/no acknowledge sequence. 6 Reserved. A value of 0 should be written to this bit. 5 I2CSETEN I2C early transmit interrupt enable bit. 4 I2CGCCLR I2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status and ID bits in the I2CSSTA register. Clear this bit at all other times. LSB of the I2CALT register should always be written to 1, as per the I2C January 2000 bus specification. take corrective action by reprogramming the device address. 1 ADR10EN I2C 10-bit address mode. Set to 1 to enable 10-bit address mode. Clear to 0 to enable normal address mode. 0 I2CSEN I2C slave enable bit. Set by user to enable I2C slave mode. Clear to disable I2C slave mode.

Function: This 16-bit MMR is the I2C status register in slave mode. Table 105. I2CSSTA MMR Bit Designations general calls are enabled and a general call code of 0x00 is received. 13 I2CREPS This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition. A read of the I2CSSTA register also clears this bit. 12:11 I2CID[1:0] I2C address matching register. These bits indicate which I2CIDx register matches the received address. [00] = received address matches I2CID0. [01] = received address matches I2CID1. [10] = received address matches I2CID2. [11] = received address matches I2CID3. 10 I2CSS I2C stop condition after start detected bit. I2CSSENI bit in I2CSCON is set, an interrupt is generated. This bit is cleared by reading this register. 9:8 I2CGCID[1:0] I2C general call ID bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative ID. Note that these bits are not cleared by a general call reset command. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CSCON. 7 I2CGC I2C general call status bit. the receive FIFO holds the second byte of the command, and this can be compared with the I2CALT register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CSCON. 6 I2CSBUSY I2C slave busy status bit. Set to 1 when the slave receives a start condition. a stop condition, or a repeated start address does not match any of the I2CIDx registers. 5 I2CSNA I2C slave no acknowledge data bit. I2CNACKEN bit was set in the I2CSCON register. This bit is cleared in all other conditions. 4 I2CSRxFO Slave receive FIFO overflow. This bit is set to 1 when a byte is written to the receive FIFO when it is already full. This bit is cleared in all other conditions. 3 I2CSRXQ I2C slave receive request bit. I2CSRXENI bit in I2CSCON is set. The receive FIFO must be read or flushed to clear this bit.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 95 of 107 Bit Name Description 2 I2CSTXQ I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CSCON is =0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CSCON is set. This bit is cleared in all other conditions. 1 I2CSTFE I2C slave FIFO underflow status bit. This bit goes high if the transmit FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. 0 I2CETSTA I2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CSCON is =0, this bit goes high if the slave transmit FIFO is empty. If the I2CSETEN bit in I2CSCON = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read. I2C Slave Receive, I2CSRX, Register Name: I2CSRX Address: 0xFFFF0930 Default value: 0x00 Access: Read only Function: This 8-bit MMR is the I2C slave receive register. I2C Slave Transmit, I2CSTX, Register Name: I2CSTX Address: 0xFFFF0934 Default value: 0x00 Access: Write only Function: This 8-bit MMR is the I2C slave transmit register. I2C Hardware General Call Recognition, I2CALT, Register Name: I2CALT Address: 0xFFFF0938 Default value: 0x00 Access: Read and write Function: This 8-bit MMR is used with hardware general calls when the I2CSCON Bit 3 is set to 1. This register is used in cases where a master is unable to generate an address for a slave and, instead, the slave must generate the address for the master. I2C Slave Device ID, I2CIDx, Registers Name: I2CIDx Addresses: 0xFFFF093C = I2CID0 0xFFFF0940 = I2CID1 0xFFFF0944 = I2CID2 0xFFFF0948 = I2CID3 Default value: 0x00 Access: Read and write Function: These 8-bit MMRs are programmed with the I2C bus IDs of the slave. See the I2C Bus Addresses section for further details.

Table 106. I2CFSTA MMR Bit Designations

9 I2CFMTX Set this bit to 1 to flush the master

8 I2CFSTX Set this bit to 1 to flush the slave transmit

7:6 I2CMRXSTA I2C master receive FIFO status bits. [01] = byte written to FIFO. 5:4 I2CMTXSTA I2C master transmit FIFO status bits. [01] = byte written to FIFO. 3:2 I2CSRXSTA I2C slave receive FIFO status bits. 1:0 I2CSTXSTA I2C slave transmit FIFO status bits. [01] = byte written to FIFO.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 97 of 107 SERIAL PERIPHERAL INTERFACE The ADuC7060/ADuC7061 integrates a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 2.56 Mbps. The SPI port can be configured for master or slave operation and typically consists of four pins: MISO, MOSI, SCLK, and SS. MISO (MASTER IN, SLAVE OUT) PIN The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, most significant bit first. MOSI (MASTER OUT, SLAVE IN) PIN The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, most significant bit first. SCLK (SERIAL CLOCK I/O) PIN The master serial clock (SCL) synchronizes the data being transmitted and received through the MOSI SCLK period. Therefore, a byte is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output in master mode and as an input in slave mode. In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the SPIDIV register as follows: )1(2 SPIDIV ff UCLK CLOCKSERIAL +×= The maximum speed of the SPI clock is independent of the clock divider bits. In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 5.12 Mbps. In both master and slave modes, data transmit on one edge of the SCLK signal and sample on the other. Therefore, it is important that the polarity and phase be configured the same for the master and slave devices. SLAVE SELECT (P0.0/SS) INPUT PIN In SPI slave mode, a transfer is initiated by the assertion of SS on the P0.0/SS pin, which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by deassertion of SS. In slave mode, SS is always an input. In SPI master mode, SS is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon completion. CONFIGURING EXTERNAL PINS FOR SPI FUNCTIONALITY The SPI pins of the ADuC7060/ADuC7061 device are represented by the P0[0:3] function of the following pins:

• P0.0/SS is the slave chip select pin. In slave mode, this pin is an input and must be driven low by the master. In master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer.
• P0.1/SCLK/SCL is the SCLK pin.
• P0.2/MISO is the master in, slave out (MISO) pin.
• P0.3/MOSI/SDA is the master out, slave in (MOSI) pin. To configure P0.0 to P0.3 for SPI mode, Bit 0, Bit 4, Bit 8, and Bit 12 of the GP0CON0 register must be set to 1. Bit 1 of the GP0CON1 must be set to 1. Note that to write to GP0CON1, the GP0KEY1 register must be set to 0x7 immediately before writing to GP0CON1. Also, the GP0KEY2 register must be set to 0x13 immediately after writing to GP0CON1. The following code example shows this in detail: GP0CON0 = BIT0 + BIT4 + BIT8 + BIT12; //Select SPI/I2C alternative function for P0[0...3] GP0KEY1 = 0x7; //Write to GP0KEY1 GP0CON1 &=~ BIT1; //Select SPI functionality for P0.0 to P0.3 GP0KEY2 = 0x13; //Write to GP0KEY2

The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV , and SPICON. Function: This 32-bit MMR contains the status of the SPI interface in both master and slave modes. Table 107. SPISTA MMR Bit Designations indicated in the SPIMDE bits in SPICON. This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE. 10:8 SPIRXFSTA[2:0] SPI receive FIFO status bits. [000] = receive FIFO is empty. [001] = 1 valid byte in the FIFO. [010] = 2 valid bytes in the FIFO. [011] = 3 valid bytes in the FIFO. [100] = 4 valid bytes in the FIFO. 7 SPIFOF SPI receive FIFO overflow status bit. interrupt except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. 6 SPIRXIRQ SPI receive IRQ status bit. number of bytes has been received. Cleared when the SPISTA register is read. 5 SPITXIRQ SPI transmit IRQ status bit. of bytes has been transmitted. Cleared when the SPISTA register is read. 4 SPITXUF SPI transmit FIFO underflow. interrupt except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. 3:1 SPITXFSTA[2:0] SPI transmit FIFO status bits. [000] = transmit FIFO is empty. [001] = 1 valid bytes in the FIFO. [010] = 2 valid bytes in the FIFO. [011] = 3 valid bytes in the FIFO. [100] = 4 valid bytes in the FIFO. 0 SPIISTA SPI interrupt status bit. Set to 1 when an SPI based interrupt occurs. Cleared after reading SPISTA.

Function: This 8-bit MMR is the SPI receive register. Function: This 8-bit MMR is the SPI transmit register. Table 108. SPIDIV MMR Bit Designations in both master and slave modes.

Table 109. SPICON MMR Bit Designations 15:14 SPIMDE SPI IRQ mode bits. These bits are configured when transmit/receive interrupts occur in a transfer. have been received into the FIFO. bytes have been received into the FIFO. bytes have been received into the FIFO. is full or 4 bytes are present. 13 SPITFLH SPI transmit FIFO flush enable bit. writes to the transmit FIFO are ignored while this bit is set. Clear this bit to disable transmit FIFO flushing. 12 SPIRFLH SPI receive FIFO flush enable bit. receive FIFO initiates a transfer. Clear this bit to disable receive FIFO flushing. 11 SPICONT Continuous transfer enable. in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle. 10 SPILP Loopback enable bit. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. 9 SPIOEN Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is cleared. 8 SPIROW SPIRX overflow overwrite enable. Set by user, the valid data in the receive register is overwritten by the new serial byte received. Cleared by user, the new serial byte received is discarded. 7 SPIZEN SPI transmit zeros when transmit FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the transmit FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the transmit FIFO. 6 SPITMDE SPI transfer and interrupt mode. Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs only when the transmit FIFO is empty. Cleared by user to initiate transfer with a read of the SPI register. Interrupt occurs only when the receive FIFO is full. 5 SPILF LSB first transfer enable bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first. 4 SPIWOM SPI wired or mode enable bit. Set to 1 to enable the open-drain data output enable. External pull-ups are required on data out pins. Clear for normal output levels. 3 SPICPO Serial clock polarity mode bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low. 2 SPICPH Serial clock phase mode bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer.

Data Sheet ADuC7060/ADuC7061 Rev. F | Page 101 of 107 Bit Name Description 1 SPIMEN Master mode enable bit. Set by user to enable master mode. Cleared by user to enable slave mode. 0 SPIEN SPI enable bit. Set by user to enable the SPI. Cleared by user to disable the SPI.

the GPIO pins retain their state. The GPIO pins are grouped into three port buses. Table 110 lists all the GPIO pins and their alternative functions. the correct bits of the GPxCON register. Table 110. GPIO Multifunction Pin Descriptions 0 P0.0/SS GPIO SS (SPI slave select). P0.1/SCLK/SCL GPIO SCLK/SCL (serial clock/SPI clock). P0.2/MISO GPIO MISO (SPI—master in/slave out). P0.3/MOSI/SDA GPIO MOSI (SPI—master out/slave in). P0.4/IRQ0/PWM1 GPIO/IRQ0 PWM1 (PWM Output 1). P0.5/CTS GPIO CTS. UART clear to send pin. P0.6/RTS GPIO RTS. UART request to send pin. 1 P1.0/IRQ1/SIN/T0 GPIO/IRQ1 SIN (serial input). P1.1/SOUT GPIO SOUT (serial output). P1.2/SYNC GPIO PWM sync (PWM sync input pin). P1.3/TRIP GPIO PWM trip (PWM trip input pin). P1.4/PWM2 GPIO PWM2 (PWM Output 2). P1.5/PWM3 GPIO PWM3 (PWM Output 3). P1.6/PWM4 GPIO PWM4 (PWM Output 4). 2 P2.0/IRQ2/PWM0/EXTCLK GPIO/IRQ2/EXTCLK PWM0 (PWM Output 0). P2.1/IRQ3/PWM5 GPIO/IRQ3 PWM5 (PWM Output 5). GPxCON are the Port x (where x is 0, 1, or 2) control registers, which select the function of each pin of Port x as described in Table 112. Table 111. GPxCON Registers

Table 112. GPxCON MMR Bit Designations 25:24 Selects the function of the P0.6/RTS and P1.6/PWM pins. 21:20 Selects the function of the P0.5/CTS and P1.5/PWM3 pins. 9:8 Selects the function of the P0.2/MISO and P1.2/SYNC pins. input value of the pins that are configured as input. Table 113. GPxDAT Registers Table 114. GPxDAT MMR Bit Designations 31:24 Direction of the data. Set to 1 by user to configure the GPIO pin as an output. Cleared to 0 by user to configure the GPIO pin as an input. 15:8 Reflect the state of Port x pins at reset (read only). 7:0 Port x data input (read only). GPxSET are data set Port x registers. Table 115. GPxSET Registers Table 116. GPxSET MMR Bit Designations corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data output. GPxCLR are data clear Port x registers. Table 117. GPxCLR Registers Table 118. GPxCLR MMR Bit Designations 23:16 Data Port x clear bit. the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data output. disable the internal pull-up resistor on P0.2. Table 119. GPxPAR Registers

Table 120. GPxPAR MMR Bit Designations GPL[7:0] = 0, normal operation. GPDS[x] = 0, maximum source current is 2 mA. GPDS[x] = 1, maximum source current is 4 mA. 7:0 GPPD[7:0] Pull-Up Disable Port x[7:0]. GPPD[x] = 0, pull-up resistor is active. GPPD[x] = 1, pull-up resistor is disabled. GP0CON1 = user value, and GP0KEY2 = 0x13. Table 121. GP0CON1 Write Sequence Table 122. GP0CON1 MMR Bit Designations These bits must always be set to 0.

1 SPII2CS

must be set to 0 for this bit to work. functions in SPI mode, clear this bit to 0. functions in I2C mode, set this bit to 1. This bit is cleared by default. as GPIO pins or as ADC input pins. as ADC inputs, set this bit to 1. as digital I/O, clear this bit to 0. This bit is cleared by default. immediately after writing to GP0CON1.

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Figure 30. 32-Lead Lead Frame Chip Scale Package [LFCSP] COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.

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