ADUC7036BCPZ

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Integrated Precision Battery Sensor for Automotive ADuC7036 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved.

FEATURES

Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs Programmable ADC throughput from 1 Hz to 8 kHz On-chip ±5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable gain from 1 to 512 ADC input range: −200 mV to +300 mV Digital comparators with current accumulator feature Voltage channel Buffered, on-chip attenuator for 12 V battery inputs Temperature channel External and on-chip temperature sensor options Microcontroller ARM7TDMI core, 16-/32-bit RISC architecture

20.48 MHz PLL with programmable divider

On-chip precision oscillator On-chip low power oscillator External (32.768 kHz) watch crystal JTAG port supports code download and debug Memory 96 kB Flash/EE memory, 6 kB SRAM 10,000-cycle Flash/EE endurance, 20-year Flash/EE retention In-circuit download via JTAG and LIN On-chip peripherals SAEJ2602/LIN 2.0-compatible (slave) support via UART with hardware synchronization Flexible wake-up I/O pin, master/slave SPI serial I/O 9-pin GPIO port, 3× general-purpose timers Wake-up and watchdog timers Power supply monitor and on-chip power-on reset Power Operates directly from 12 V battery supply Current consumption Normal mode 10 mA at 10 MHz Low power monitor mode Package and temperature range 48-lead, 7 mm × 7 mm LFCSP Fully specified for −40°C to +115°C operation

APPLICATIONS

Battery sensing/management for automotive systems FUNCTIONAL BLOCK DIAGRAM PRECISION ANALOG ACQUISITION BUF RESULT ACCUMULATOR DIGITAL COMPARATOR TEMPERATURE SENSOR VDD VREF VTEMP VBAT IIN– IIN+ PRECISION REFERENCE PGA 2.6V LDO PSM POR ARM7TDMI MCU 20MHz 3× TIMERS WDT WU TIMER MEMORY 98kB FLASH 6kB RAM ADuC7036 PRECISION OSC LOW POWER OSC ON-CHIP PLL GPIO PORT UART PORT SPI PORT LIN MUX BUF 16-BIT Σ-∆ ADC 16-BIT Σ-∆ ADC GND_SW REG_AVDD REG_DVDD AGND DGND VSS IO_VSS GPIO_2/MISO GPIO_3/MOSI GPIO_1/SCLK GPIO_4/ECLK TDO NTRST TDI TCK TMS GPIO_5/IRQ1/RxD GPIO_6/TxD GPIO_7/IRQ4 GPIO_8/IRQ5 RESET WU STI LIN/BSD XTAL1 XTAL2 07474-001 GPIO_0/IRQ0/SS Figure 1.

Rev. C | Page 2 of 132 TABLE OF CONTENTS Handling Interrupts from the High Voltage Peripheral

Rev. C | Page 3 of 132

REVISION HISTORY

2/11—Rev. B to Rev. C 4/10—Rev. A to Rev. B 7/09—Rev. 0 to Rev. A 10/08—Revision 0: Initial Version

Rev. C | Page 4 of 132 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.5 V to 18 V , VREF = 1.2 V internal reference, fCORE = 20.48 MHz (unless otherwise noted) driven from external 32.768 kHz watch crystal or on-chip precision oscillator. All specifications TA = −40°C to +115°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ADC SPECIFICATIONS Conversion Rate1 Chop off, ADC normal operating mode 4 8000 Hz Chop on, ADC normal operating mode 4 2600 Hz Chop on, ADC low power mode 1 650 Hz Current Channel No Missing Codes1 Valid for all ADC update rates and ADC modes 16 Bits Integral Nonlinearity1, 2 ±10 ±60 ppm of FSR Offset Error2, 3 , 4 , 5 Chop off, 1 LSB = (36.6/gain) μV −10 ±3 +10 LSB Offset Error1, 3, 6 Chop on −2 ±0.5 +2 μV Offset Error1, 3 Chop on, low power or low power plus mode, MCU powered down 100 −50 −300 nV Offset Error1, 3 Chop on, normal mode +0.5 −1.25 −3 μV Offset Error Drift6 Chop off, valid for ADC gains of 4 to 64, normal mode 0.03 LSB/°C Offset Error Drift6 Chop off, valid for ADC gains of 128 to 512, normal mode 30 nV/°C Offset Error Drift6 Chop on 10 nV/°C Total Gain Error1, 3, 7 , 8 , 9 , 10 Normal mode −0.5 ±0.1 +0.5 % Total Gain Error1, 3, 7, 9 Low power mode, using ADCREF MMR −4 ±0.2 +4 % Total Gain Error1, 3, 7, 9, 11 Low power plus mode, using precision VREF −1 ±0.2 +1 % Gain Drift 3 ppm/°C PGA Gain Mismatch Error ±0.1 % Output Noise1, 12 4 Hz update rate, gain = 512, ADCFLT = 0xBF1D 60 90 nV rms

4 Hz update rate, gain = 512, ADCFLT = 0x3F1D 75 115 nV rms

10 Hz update rate, gain = 512, ADCFLT = 0x961F 100 150 nV rms

10 Hz update rate, gain = 512, ADCFLT = 0x161F 120 180 nV rms

1 kHz update rate, gain ≥ 64, ADCFLT = 0x8101 0.8 1.2 μV rms 1 kHz update rate, gain ≥ 64, ADCFLT = 0x0101 1 1.5 μV rms 1 kHz update rate, gain = 512, ADCFLT = 0x0007 0.6 0.9 μV rms 1 kHz update rate, gain = 32, ADCFLT = 0x0007 0.8 1.2 μV rms 1 kHz update rate, gain = 8, ADCFLT = 0x8101 2.1 4.1 μV rms 1 kHz update rate, gain = 8, ADCFLT = 0x0007 1.6 2.4 μV rms 1 kHz update rate, gain = 8, ADCFLT = 0x0101 2.6 3.9 μV rms 1 kHz update rate, gain = 4, ADCFLT = 0x0007 2.0 2.8 μV rms 8 kHz update rate, gain = 32, ADCFLT = 0x0000 2.5 3.5 μV rms 8 kHz update rate, gain = 4, ADCFLT = 0x0000 14 21 μV rms ADC low power mode, fADC = 10 Hz, gain = 128 1.25 1.9 μV rms ADC low power mode, fADC = 1 Hz, gain = 128 0.35 0.5 μV rms ADC low power plus mode, fADC = 1 Hz, gain = 512 0.1 0.15 μV rms ADC low power plus mode, fADC = 250 Hz, gain = 512 0.6 0.9 μV rms

Rev. C | Page 5 of 132 Parameter Test Conditions/Comments Min Typ Max Unit Voltage Channel13 No Missing Codes1 Valid at all ADC update rates 16 Bits Integral Nonlinearity1 ±10 ±60 ppm of FSR Offset Error3, 5 Chop off, 1 LSB = 439.5 μV −10 ±1 +10 LSB Offset Error1, 3 Chop on 0.3 1 LSB Offset Error Drift Chop off 0.03 LSB/°C Total Gain Error1, 3, 7, 10, 14 Includes resistor mismatch −0.25 ±0.06 +0.25 % Total Gain Error1, 3, 7, 10, 14 Temperature range = −25°C to +65°C −0.15 ±0.03 +0.15 % Gain Drift Includes resistor mismatch drift 3 ppm/°C Output Noise1, 12, 15 4 Hz update rate, ADCFLT = 0xBF1D 60 90 μV rms

10 Hz update rate, ADCFLT = 0x961F 60 90 μV rms

1 kHz update rate, ADCFLT = 0x0007 180 270 μV rms 1 kHz update rate, ADCFLT = 0x8101 240 307 μV rms 1 kHz update rate, ADCFLT = 0x0101 270 405 μV rms 8 kHz update rate, ADCFLT = 0x0000 1600 2400 μV rms Temperature Channel No Missing Codes1 Valid at all ADC update rates 16 Bits Integral Nonlinearity1 ±10 ±60 ppm of FSR Offset Error3, 4, 5, 16 Chop off, 1 LSB = 19.84 μV in unipolar mode −10 ±3 +10 LSB Offset Error1, 3 Chop on −5 +1 +5 LSB Offset Error Drift Chop off 0.03 LSB/°C Total Gain Error1, 3, 14 Using REG_AVDD as the reference −0.2 ±0.06 +0.2 % Gain Drift 3 ppm/°C Output Noise1 1 kHz update rate 7.5 11.25 μV rms ADC SPECIFICATIONS ANALOG INPUT Internal VREF = 1.2 V Current Channel Absolute Input Voltage Range Applies to both IIN+ and IIN− −200 +300 mV Input Voltage Range17 , 18 Gain = 119 ±1.2 V Gain = 219 ±600 mV Gain = 419 ±300 mV Gain = 8 ±150 mV Gain = 16 ±75 mV Gain = 32 ±37.5 mV Gain = 64 ±18.75 mV Gain = 128 ±9.375 mV Gain = 256 ±4.68 mV Gain = 512 ±2.3 mV Input Leakage Current1 −3 +3 nA Input Offset Current1, 20 0.5 1.5 nA Voltage Channel Absolute Input Voltage Range 4 18 V Input Voltage Range 0 to 28.8 V VBAT Input Current VBAT = 18 V 3 5.5 8 μA Temperature Channel VREF = (REG_AVDD and GND_SW)/2 Absolute Input Voltage Range 100 1300 mV Input Voltage Range 0 to VREF V VTEMP Input Current1 2.5 100 nA

Rev. C | Page 6 of 132 Parameter Test Conditions/Comments Min Typ Max Unit VOLTAGE REFERENCE ADC Precision Reference Internal VREF 1.2 V Power-Up Time1 0.5 ms Initial Accuracy1 Measured at TA = 25°C −0.15 +0.15 % Temperature Coefficient1, 21 −20 ±5 +20 ppm/°C Reference Long-Term Stability22 100 ppm/1000 hr External Reference Input Range23 0.1 1.3 V VREF Divide-by-2 Initial Error1 0.1 0.3 % ADC Low Power Reference Internal VREF 1.2 V Initial Accuracy Measured at TA = 25°C −5 +5 % Initial Accuracy1 Using ADCREF, measured at TA = 25°C 0.1 % Temperature Coefficient1, 21 −300 ±150 +300 ppm/°C ADC DIAGNOSTICS VREF/1361 At any gain settings 8.5 9.4 mV Voltage Attenuator Current Source1 Differential voltage increase on the attenuator when the current source is on, temperature range = −40°C to +85°C 3.1 3.8 V RESISTIVE ATTENUATOR Divider Ratio 24 Resistor Mismatch Drift 3 ppm/°C ADC GROUND SWITCH Resistance Direct path to ground 10 Ω Resistance1 20 kΩ resistor selected 10 20 30 kΩ Input Current Allowed contunious current through the switch with direct path to ground 6 mA TEMPERATURE SENSOR24 After user calibration Accuracy MCU in power-down or standby mode ±3 °C MCU in power-down or standby mode, temperature range = −25°C to +65°C ±2 °C POWER-ON RESET (POR) POR Trip Level Refers to voltage at VDD pin 2.85 3 3.15 V POR Hysteresis 300 mV Reset Timeout from POR 20 ms LOW VOLTAGE FLAG (LVF) LVF Level Refers to voltage at VDD pin 1.9 2.1 2.3 V POWER SUPPLY MONITOR (PSM) PSM Trip Level Refers to voltage at VDD pin 6 V WATCHDOG TIMER (WDT) Timeout Period1 32.768 kHz clock, 256 prescale 0.008 512 sec Timeout Step Size 7.8 ms FLASH/EE MEMORY1 Endurance25 10,000 Cycles Data Retention26 20 Years DIGITAL INPUTS All digital inputs except NTRST Input Leakage Current Input high = REG_DVDD ±1 ±10 μA Input Pull-Up Current Input low = 0 V −80 −20 −10 μA Input Capacitance 10 pF Input Leakage Current NTRST only: input low = 0 V ±1 ±10 μA Input Pull-Down Current NTRST only: input high = REG_DVDD 30 55 100 μA

Rev. C | Page 7 of 132 Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS1 All logic inputs VINL, Input Low Voltage 0.4 V VINH, Input High Voltage 2 V CRYSTAL OSCILLATOR1 Logic Inputs, XTAL1 Only VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 1.7 V XTAL1 Capacitance 12 pF XTAL2 Capacitance 12 pF ON-CHIP OSCILLATORS Low Power Oscillator 131.072 kHz Accuracy27 Includes drift data from 1000 hour life test −3 +3 % Precision Oscillator 131.072 kHz Accuracy Includes drift data from 1000 hour life test −1 +1 % MCU CLOCK RATE Eight programmable core clock selections within this range (binary divisions 1, 2, 4, 8,…64, 128) 0.16 10.24 20.48 MHz MCU START-UP TIME At Power-On Includes kernel power-on execution time 25 ms After Reset Event Includes kernel power-on execution time 5 ms From MCU Power-Down Oscillator Running Wake Up from Interrupt 2 ms Wake Up from LIN 2 ms Crystal Powered Down Wake Up from Interrupt 500 ms Internal PLL Lock Time 1 ms LIN INPUT/OUTPUT GENERAL Baud Rate 1000 20,000 Bits/sec VDD Supply voltage range at which the LIN interface is functional 7 18 V Input Capacitance 5.5 pF Input Leakage Current Input (low) = IO_VSS −800 −400 μA LIN Comparator Response Time1 Using 22 Ω resistor 38 90 μs ILIN_DOM_MAX Current limit for driver when LIN bus is in dominant state, VBAT = VBAT (max) 40 200 mA ILIN_PAS_REC Driver off, 7 V < VLIN < 18 V, VDD = VLIN − 0.7 V −20 +20 μA ILIN1 VBAT disconnected, VDD = 0 V, 0 < VLIN < 18 V 10 μA ILIN_PAS_DOM1 Input leakage VLIN = 0 V −1 mA ILIN_NO_GND 28 Control unit disconnected from ground, GND = VDD, 0 V < VLIN < 18 V, VBAT = 12 V −1 +1 mA VLIN_DOM1 LIN receiver dominant state, VDD > 7 V 0.4 VDD V VLIN_REC1 LIN receiver recessive state, VDD > 7 V 0.6 VDD V VLIN_CNT1 LIN receiver center voltage, VDD > 7 V 0.475 VDD 0.5 VDD 0.525 VDD V VHYS1 LIN receiver hysteresis voltage 0.175 VDD V VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage, VDD = 7 V RLOAD = 500 Ω 1.2 V RLOAD = 1000 Ω 0.6 V VLIN_DOM_DRV_HISUP1 LIN dominant output voltage, VDD = 18 V RLOAD = 500 Ω 2 V RLOAD = 1000 Ω 0.8 V VLIN_RECESSIVE LIN recessive output voltage 0.8 VDD V VBAT Shift28 0 0.1 VDD V GND Shift28 0 0.1 VDD V

Rev. C | Page 8 of 132 Parameter Test Conditions/Comments Min Typ Max Unit RSLAVE Slave termination resistance 20 30 47 kΩ VSERIAL DIODE28 Voltage drop at the serial diode, DSER_INT 0.4 0.7 1 V Symmetry of Transmit Propagation Delay1 VDD (min) = 7 V −2 +2 μs Receive Propagation Delay1 VDD (min) = 7 V 6 μs Symmetry of Receive Propagation Delay1 VDD (min) = 7 V −2 +2 μs LIN VERSION 1.3 SPECIFICATION Bus load conditions (CBUS||RBUS):1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω dt dV 1 Slew rate Dominant and recessive edges, VBAT = 18 V 1 2 3 V/μs dt dV 1 Slew rate Dominant and recessive edges, VBAT = 7 V 0.5 3 V/μs tSYM1 Symmetry of rising and falling edge, VBAT = 18 V −5 +5 μs Symmetry of rising and falling edge, VBAT = 7 V −4 +4 μs LIN VERSION 2.0 SPECIFICATION Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω D1 Duty Cycle 1, TH REC (MAX) = 0.744 × VBAT, THDOM (MAX) = 0.581 × VBAT, VSUP = 7 V…18 V; tBIT = 50 μs, D1 = tBUS_REC (MIN)/(2 × tBIT) 0.396 D2 Duty Cycle 2, TH REC (MIN) = 0.284 × VBAT, THDOM (MIN) = 0.422 × VBAT, VSUP = 7 V…18 V; tBIT = 50 μs, D2 = tBUS_REC (MAX)/(2 × tBIT) 0.581 BSD INPUT/OUTPUT29 Baud Rate 1164 1200 1236 Bits/sec Input leakage current Input high = VDD, or input low = IO_VSS −50 +50 μA VOL, Output Low Voltage 1.2 V VOH, Output High Voltage 0.8 VDD V IO(SC) Short-Circuit Output Current VBSD = VDD = 12 V 50 80 120 mA VINL, Input Low Voltage 1.8 V VINH, Input High Voltage 0.7 VDD V WAKE UP RLOAD = 300 Ω, CBUS = 91 nF, RLIMIT = 39 Ω VDD1 Supply voltage range at which the WU pin is functional 7 18 V Input Leakage Current Input high = VDD 0.4 2.1 mA Input low = IO_VSS −50 +50 μA VOH 30 Output high level 5 V VOL30 Output low level 2 V VIH Input high level 4.6 V VIL Input low level 1.2 V Monoflop Timeout Timeout period 0.6 1.3 2 sec IO(SC) Short-Circuit Output Current 100 140 mA SERIAL TEST INTERFACE RLOAD = 500 Ω, CBUS = 2.4 nF, RLIMIT = 39 Ω Baud Rate 40 kbps Input Leakage Current Input high = VDD or input low = IO_VSS −50 +70 μA VDD Supply voltage range for which STI is functional 7 18 V VOH Output high level 0.6 VDD V VOL Output low level 0.4 VDD V VIH Input high level 0.6 VDD V VIL Input low level 0.4 VDD V

Rev. C | Page 9 of 132 Parameter Test Conditions/Comments Min Typ Max Unit PACKAGE THERMAL SPECIFICATIONS Thermal Shutdown1, 31 140 150 160 °C Thermal Impedance (θJA)32 48-lead LFCSP, stacked die 45 °C/W POWER REQUIREMENTS Power Supply Voltages VDD (Battery Supply) 3.5 18 V REG_DVDD, REG_AVDD33 2.5 2.6 2.7 V Power Consumption IDD (MCU Normal Mode)34 MCU clock rate = 10.24 MHz, ADC off 10 20 mA MCU clock rate = 20.48 MHz, ADC off (valid for ADuC7036CCPZ and ADuC7036DCPZ only) 20 30 mA IDD (MCU Powered Down)1 ADC low power mode, measured over the range of T A = −10°C to +40°C, continuous ADC conversion 300 400 μA ADC low power mode, measured over the range of T A = −40°C to +85°C, continuous ADC conversion 300 500 μA ADC low power plus mode, measured over the range of TA = −10°C to +40°C, continuous ADC conversion 520 700 μA Average current, measured with wake-up and watchdog timer clocked from the low power oscillator, T A = −40°C to +85°C 120 300 μA IDD (MCU Powered Down) Average current, measured with wake-up and watchdog timer clocked from low power oscillator over a range of T A = −10°C to +40°C 120 175 μA IDD (Current ADC) 1.7 mA IDD (Voltage/Temperature ADC) 0.5 mA IDD (Precision Oscillator) 400 μA 1 These numbers are not production tested but are guaranteed by design and/or characterization data at production release. 2 Valid for current ADC gain setting of PGA = 4 to 64. 3 These numbers include temperature drift. 4 Tested at gain range = 4; self-offset calibration removes this error. 5 Measured with an internal short after an initial offset calibration. 6 Measured with an internal short. 7 These numbers include internal reference temperature drift. 8 Factory-calibrated at gain = 1. 9 System calibration at a specific gain range (and temperature) removes the error at this gain range (and temperature). 10 Includes an initial system calibration. 11 Using ADC normal mode voltage reference. 12 Typical noise in low power modes is measured with chop enabled. 13 Voltage channel specifications include resistive attenuator input stage. 14 System calibration removes this error at the specified temperature. 15 RMS noise is referred to voltage attenuator input (for example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 μV) and scaled by the attenuator (divide-by-24) to yield these input referred noise specifications/values. 16 Valid after an initial self-calibration. 17 In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV. 18 It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach can also be used to reduce the ADC input range (LSB size). 19 Limited by minimum/maximum absolute input voltage range. 20 Valid for a differential input less than 10 mV. 21 Measured using box method. 22 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. 23 References of up to REG_AVDD can be accommodated by enabling an internal divide-by-2. 24 Die temperature. 25 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles. 26 Retention lifetime equivalent at junction temperature (TJ) of 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. 27 Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code. 28 These numbers are not production tested, but are supported by LIN compliance testing. 29 BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and CL = 10 nF maximum. 30 Specified after RLIMIT of 39 Ω. 31 The MCU core is not shut down but interrupted, and high voltage I/O pins are disabled in response to a thermal shutdown event. 32 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature. 33 Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA), and REG_AVDD (ISOURCE = 1 mA). 34 The specification listed is typical; additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.

Table 2. SPI Master Mode Timing—Phase Mode = 1 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 2. SPI Master Mode Timing—Phase Mode = 1

Table 3. SPI Master Mode—Phase Mode = 0 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 3. SPI Master Mode Timing—Phase Mode = 0

Table 4. SPI Slave Mode Timing—Phase Mode = 1 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 4. SPI Slave Mode Timing—Phase Mode = 1

Table 5. SPI Slave Mode Timing (Phase Mode = 0) 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 5. SPI Slave Mode Timing—Phase Mode = 0

Figure 6. LIN 2.0 Timing Specification

Rev. C | Page 15 of 132 ABSOLUTE MAXIMUM RATINGS TA = −40°C to +115°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Parameter Rating AGND to DGND to VSS to IO_VSS −0.3 V to +0.3 V VBAT to AGND −22 V to +40 V VDD to VSS −0.3 V to +33 V VDD to VSS for 1 sec −0.3 V to +40 V LIN to IO_VSS −16 V to +40 V STI and WU to IO_VSS −3 V to +33 V Wake-Up Continuous Current 50 mA High Voltage I/O Pins Short-Circuit Current 100 mA Digital I/O Voltage to DGND −0.3 V to REG_DVDD + 0.3 V VREF to AGND −0.3 V to REG_AVDD + 0.3 V ADC Inputs to AGND −0.3 V to REG_AVDD + 0.3 V ESD Human Body Model (HBM) Rating HBM-ADI0082 (Based on ANSI/ESD STM5.1-2007). All Pins except LIN and VBAT. 1 kV LIN and VBAT ±6 kV IEC 61000-4-2 for LIN and VBAT ±7 kV Storage Temperature 125°C Junction Temperature Transient 150°C Continuous 130°C Lead Temperature Soldering Reflow (15 sec) 260°C ESD CAUTION

1. THE EXPOSED PAD SHOULD BE CONNECTED TO DGND.

Figure 7. Pin Configuration Table 7. Pin Function Descriptions recommended that this pin be strapped via a resistor to REG_DVDD. pull-up resistor and should be left unconnected when not in use. should be left unconnected when not in use. be left unconnected when not in use. be left unconnected when not in use. 6 TCK I JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part. unconnected when not in use. 8, 34, 35 DGND S Ground Reference for On-Chip Digital Circuits. NC No Connect. These pins are not internally connected and are reserved for possible future use. Therefore, do not externally connect these pins. These pins can be grounded, if required. internal, weak pull-up resistor. This pin is left unconnected when not in use.

Rev. C | Page 17 of 132 Pin No. Mnemonic Type 1 Description 11 NTRST I JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part. NTRST is an input pin only and has an internal, weak pull-down resistor. This pin remains unconnected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN boot load mode. 12 TMS I JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports on the part. TMS is an input pin only and has an internal, weak pull-up resistor. This pin is left unconnected when not in use. 13 VBAT I Battery Voltage Input to Resistor Divider. 14 VREF I External Reference Input Terminal. When this input is not used, connect it directly to the AGND system ground. It can also be left unconnected. 15 GND_SW I Switch to Internal Analog Ground Reference. This pin is the negative input for the external temperature channel and external reference. When this input is not used, connect it directly to the AGND system ground. 18 VTEMP I External Pin for NTC/PTC Temperature Measurement. 19 IIN+ I Positive Differential Input for Current Channel. 20 IIN− I Negative Differential Input for Current Channel. 21, 22 AGND S Ground Reference for On-Chip Precision Analog Circuits. 24 REG_AVDD S Nominal 2.6 V Output from On-Chip Regulator. 27 GPIO_0/IRQ0/SS I/O General-Purpose Digital I/O 0/External Interrupt Request 0/Slave Select Input for SPI Interface. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 28 GPIO_1/SCLK I/O General-Purpose Digital I/O 1/Serial Clock Input for SPI Interface. By default and after a power- on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 29 GPIO_2/MISO I/O General-Purpose Digital I/O 2/Master Input, Slave Output for SPI Interface. By default and after a power-on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 30 GPIO_3/MOSI I/O General-Purpose Digital I/O 3/Master Output, Slave Input for SPI Interface. By default and after a power-on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 31 GPIO_4/ECLK I/O General-Purpose Digital I/O 4/2.56 MHz Clock Output. By default and after a power-on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 33 REG_DVDD S Nominal 2.6 V Output from the On-Chip Regulator. 36 XTAL1 O Crystal Oscillator Output. If an external crystal is not used, this pin is left unconnected. 37 XTAL2 I Crystal Oscillator Input. If an external crystal is not used, connect this pin to the DGND system ground. 41 WU I/O High Voltage Wake-Up Pin. This high voltage I/O pin has an internal, 10 kΩ pull-down resistor and a high-side driver to VDD. If this pin is not being used, it should not be connected externally. 42 VDD S Battery Power Supply to On-Chip Regulator. 44 VSS S Ground Reference. This is the ground reference for the internal voltage regulators. 46 STI I/O High Voltage Serial Test Interface Output Pin. If this pin is not used, externally connect it to the IO_VSS ground reference. 47 IO_VSS S Ground Reference for High Voltage I/O Pins. 48 LIN/BSD I/O Local Interconnect Network I/O/Bit Serial Device I/O. This is a high voltage pin. EPAD Exposed pad The exposed pad should be connected to DGND. 1 I = input, O = output, I/O = input/output, S = supply.

Rev. C | Page 19 of 132 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC after the ADC has settled. The Σ-Δ conversion techniques used on this part mean that while the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, providing a valid 16-bit data conversion result for output rates from 1 Hz to 8 kHz. Note that when software switches from one input to another on the same ADC, the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this may require multiple conversion cycles. Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end- points of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB The error is expressed as a percentage of full scale. No Missing Codes No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits (as 2 N bits, where N is no missing codes) and specifies the number of codes (ADC results) that are guaranteed to occur through the full ADC input range. Offset Error Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition. Offset Error Drift Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSBs per degrees Celsius. Gain Error Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function. Output Noise The output noise is specified as the standard deviation (that is, 1 × Σ) of the distribution of ADC output codes that are collected when the ADC input voltage is at a dc voltage. It is expressed as microvolts rms (μV rms). The output, or rms noise, can be used to calculate the effective resolution of the ADC as defined by the following equation: Effective Resolution = log 2(Full-Scale Range/RMS Noise) where Effective Resolution is expressed in bits. The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × Σ of the distribution of ADC output codes that are collected when the ADC input voltage is at dc. The peak-to- peak noise is therefore calculated as 6.6 times the rms noise. The peak-to-peak noise can be used to calculate the ADC (noise-free code) resolution for which there is no code flicker within a 6.6 × Σ limit, as defined by the following equation: Noise-Free Code Resolution = log 2(Full-Scale Range/Peak-to- Peak Noise) where Noise-Free Code Resolution is expressed in bits.

interconnect network (LIN) interface that is integrated on chip. or an external serial communication event. results to a lower performance specification. nonintrusive emulation is also supported via the JTAG interface. development system supporting the ADuC7036. performance, at temperatures from 115°C to 125°C. Table 8. ARM7TDMI particularly well-suited for embedded applications. However, the Thumb mode has three limitations.

• Relative to ARM, the Thumb code usually requires more instructions to perform a task. Therefore, ARM code is best for maximizing the performance of time-critical code in most applications.
• The Thumb instruction set does not include some instructions that are needed for exception handling, so ARM code may be required for exception handling.
• When an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at that address. The first command is required to be in ARM code. Multiplier (M) The ARM7TDMI instruction set includes an enhanced multiplier with four extra instructions to perform 32-bit by 32-bit multiplication with a 64-bit result, or 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result. EmbeddedICE (I) The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. These registers are con- trolled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. Once in a debug state, the processor registers can be interrogated, as can the Flash/EE, SRAM, and memory mapped registers.

• Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events.
• Fast interrupt or FIQ. This is provided to service data transfer or a communication channel with low latency. FIQ has priority over IRQ.
• Memory abort (prefetch and data).
• Attempted execution of an undefined instruction.
• Software interrupt (SWI) instruction that can be used to make a call to an operating system. Typically, the programmer defines interrupts as IRQ, but for higher priority interrupts, the programmer can define interrupts as the FIQ type. The priority of these exceptions and vector address are listed in Table 9.

Table 9. Exception Priorities and Vector Addresses

1 Hardware reset 0x00

2 Memory abort (data) 0x10

3 FIQ 0x1C

4 IRQ 0x18

5 Memory abort (prefetch) 0x0C

6 Software interrupt1 0x08

6 Undefined instruction1 0x04

1 A software interrupt and an undefined instruction exception have the same

priority and are mutually exclusive. execute and LIN download mode is entered. the available RAM area and descends using the area as required. such as C, it is necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used. reducing the response time of the interrupt handling process. Figure 11. Register Organization mode, which reduces the time to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is five cycles. the synchronizer plus the time to enter the exception mode. required, for example, when executing interrupt service routines. architecture, sees memory as a linear array of 232 byte locations.

• The first 94 kB of this memory space is used as an area into which the on-chip Flash/EE or SRAM can be remapped.
• The ADuC7036 features a second 4 kB area at the top of the memory map used to locate the MMRs, through which all on-chip peripherals are configured and monitored.
• The ADuC7036 features an SRAM size of 6 kB.
• The ADuC7036 features 96 kB of on-chip Flash/EE memory, 94 kB of which are available to the user and 2 kB of which are reserved for the on-chip kernel. Any access, either a read or a write, to an area not defined in the memory map results in a data abort exception. Memory Format The ADuC7036 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. BIT 31 BYTE 2 A BYTE 3 B BYTE 1 BYTE 0 BIT 0

32 BITS

Figure 12. Little Endian Format Figure 13. Memory Map array. SRAM is readable/writeable in 8-, 16-, and 32-bit segments. memory array, from Address 0x00000000 to Address 0x00000020. mapped to Address 0x00000000. It is possible to logically remap the SRAM to Address 0x00000000. that when an exception occurs, the core defaults to ARM mode.

always be written in Flash/EE. may observe abnormal program operation. space, starting at Address 0x00000000. Table 10. SYSMAP0 MMR Bit Designations Set by the user to remap the SRAM to 0x00000000. Flash/EE memory to 0x00000000.

cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234. The bit designations in RSTCLR mirror those of RSTSTA. all four kinds of reset events are shown in Table 12. event and can be written to by user code to initiate a software reset. Table 11. RSTSTA/RSTCLR MMR Bit Designations 7 to 4 Not used. These bits are not used and always read as 0. Set automatically to 1 when an external reset occurs. Cleared by setting the corresponding bit in RSTCLR. Set to 1 by user code to generate a sofware reset. Set automatically to 1 when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR.

1 If the software reset bit in RSTSTA is set, any write to RSTCLR that does not

clear this bit generates a software reset. Table 12. Device Reset Implications 1 RAM is not valid in the case of a reset following a LIN download. mechanism if the LVF status bit, HVMON[3], is 1. See the Low Voltage Flag (LVF) section for more information.

Rev. C | Page 25 of 132 FLASH/EE MEMORY The ADuC7036 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogram- mable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased, with the erasure performed in page blocks. Therefore, flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit program- mability, high density, and low cost. Incorporated within the ADuC7036, Flash/EE memory technology allows the user to update program code space in-circuit without the need to replace one-time programmable (OTP) devices at remote operating nodes. The Flash/EE memory is located at Address 0x80000. Upon a hard reset, the Flash/EE memory maps to Address 0x00000000. The factory-set default contents of all Flash/EE memory locations is 0xFF. Flash/EE can be read in 8-, 16-, and 32-bit segments and written in 16-bit segments. The Flash/EE is rated for 10,000 endurance cycles. This rating is based on the number of times that each byte is cycled, that is, erased and programmed. Imple- menting a redundancy scheme in the software ensures that none of the flash locations reach 10,000 endurance cycles. The user can also write data variables to the Flash/EE memory during run-time code execution, for example, for storing diagnostic battery parameter data. The entire Flash/EE is available to the user as code and non- volatile data memory. There is no distinction between data and program space during ARM code processing. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. When operating at speeds of less than 20.48 MHz, the Flash/EE memory controller can transparently fetch the second 16-bit halfword (part of the 32-bit ARM operation code) within a single core clock period. Therefore, for speeds less than 20.48 MHz (that is, CD > 0), it is recommended to use ARM mode. For 20.48 MHz operation (that is, CD = 0), it is recommended to operate in Thumb mode. The page size of this Flash/EE memory is 512 bytes. Typically, it takes the Flash/EE controller 20 ms to erase a page, regardless of CD. Writing a 16-bit word at CD = 0, 1, 2, or 3 requires 50 μs; at CD = 4 or 5, 70 μs; at CD = 6, 80 μs; and at CD = 7, 105 μs. It is possible to write to a single 16-bit location only twice between erasures; that is, it is possible to walk bytes, not bits. If a location is written to more than twice, the contents of the Flash/EE page may become corrupt. PROGRAMMING FLASH/EE MEMORY IN-CIRCUIT The Flash/EE memory can be programmed in-circuit, using a serial download mode via the LIN interface or the integrated JTAG port. Serial Downloading (In-Circuit Programming) The ADuC7036 facilitates code download via the LIN/BSD pin. JTAG Access The ADuC7036 features an on-chip JTAG debug port to facilitate code downloading and debugging. ADuC7036 Flash/EE Memory The total 96 kB of Flash/EE is organized as 47,000 × 16 bits. Of this total, 94 kB is designated as user space, and 2 kB is reserved for boot loader/kernel space. FLASH/EE CONTROL INTERFACE The access to and control of the Flash/EE memory on the ADuC7036 are managed by an on-chip memory controller. The controller manages the Flash/EE memory as two separate blocks (Block 0 and Block 1). Block 0 consists of the 32 kB of Flash/EE memory that is mapped from Address 0x00090000 to Address 0x00097FFF, including the 2 kB kernel space that is reserved at the top of this block. Block 1 consists of the 64 kB of Flash/EE memory that is mapped from Address 0x00080000 to Address 0x0008FFFF. It should be noted that the MCU core can continue to execute code from one memory block while an active erase or program cycle is being carried out on the other block. If a command operates on the same block as the code currently executing, the core is halted until the command is complete. This also applies to code execution. User code, LIN, and JTAG programming use the Flash/EE control interface, consisting of the following MMRs:

• FEExSTA (x = 0 or 1): Read only register. Reflects the status of the Flash/EE control interface.
• FEExMOD (x = 0 or 1): Sets the operating mode of the Flash/EE control interface.
• FEExCON (x = 0 or 1): 8-bit command register. The commands are interpreted as described in Table 13.
• FEExDAT (x = 0 or 1): 16-bit data register.
• FEExADR (x = 0 or 1): 16-bit address register.
• FEExSIG (x = 0 or 1): Holds the 24-bit code signature as a result of the signature command being initiated.
• FEExHID (x = 0 or 1): Protection MMR. Controls read and write protection of the Flash/EE memory code space. If previously configured via the FEExPRO register, FEExHID may require a software key to enable access.
• FEExPRO (x= 0 or 1): A buffer of the FEExHID register. Stores the FEExHID value and is automatically down- loaded to the FEExHID registers on subsequent reset and power-on events. Note that user software must ensure that the Flash/EE controller completes any erase or write cycle before the PLL is powered down. If the PLL is powered down before an erase or write cycle is completed, the Flash/EE page or byte may be corrupted.

bit designations for each of the Flash/EE control MMRs. Table 13. Command Codes in FEE0CON and FEE1CON 0x002 Reserved Reserved. This command should not be written by user code. 0x012 Single read Load FEExDAT with the 16-bit data indexed by FEExADR. 0x022 Single write Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs. 0x032 Erase write Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms. returned in FEExSTA, Bit 1 or Bit 0. 0x052 Single erase Erase the page indexed by FEExADR. Sequence for Executing a Mass Erase section). 0x08 Reserved Reserved. This command should not be written by user code. 0x09 Reserved Reserved. This command should not be written by user code. 0x0A Reserved Reserved. This command should not be written by user code. that is loaded into FEE0SIG. the page specified in FEE0ADR upwards, including the kernel, security bits, and Flash/EE key. If FEE0ADR is greater than 0x97800, the kernel and manufacturing data are signed. This operation takes 120 μs. (0x06) or with the software protection key. 0x0D Reserved Reserved. This command should not be written by user code. 0x0E Reserved Reserved. This command should not be written by user code. 0x0F Ping No operation, interrupt generated. 1 The x represents 0 or 1, designating Flash/EE Block 0 or Block 1. 2 The FEE0CON register reads 0x07 immediately after the execution of this command.

Run the mass erase command (Code 0x06) in FEExCON. disabled. That is, FEE1HID/FEE1PRO are set to 0xFFFFFFFF. tion or by erasing the lower 64 kB. Table 14. FEE0STA and FEE1STA MMR Bit Designations 7 to 4 Not used. These bits are not used and always read as 0. 3 Flash/EE interrupt status bit. interrupt enable bit in the FEExMOD register is set. Set automatically when the Flash/EE controller is busy. Cleared automatically when the controller is not busy. 1 The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1. System Identification FEE0ADR section. when a Flash/EE command is executed via FEExCON.

or to be written to the Flash/EE memory. the mode of operation of the Flash/EE memory controllers. Table 15. FEE0MOD and FEE1MOD MMR Bit Designations 15 to 7 Not used. These bits are reserved for future functionality and should be written as 0 by user code. 6, 5 Flash/EE security lock bits. These bits must be written as [6:5] = 10 to complete the Flash/EE security protect sequence. 4 Flash/EE controller command complete interrupt enable. Set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command. Cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command. 3 Flash/EE erase/write enable. Set by user code to enable the Flash/EE erase and write access via FEExCON. Cleared by user code to disable the Flash/EE erase and write access via FEExCON. 2 Reserved. Should be written as 0. 1 Flash/EE controller abort enable. Set to 1 by user code to enable the Flash/EE controller abort functionality. 0 Reserved. Should be written as 0. 1 The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1.

Rev. C | Page 29 of 132 FLASH/EE MEMORY SECURITY The 94 kB of Flash/EE memory available to the user can be read and write protected using the FFE0HID and FEE1HID registers. In Block 0, the FEE0HID MMR protects the 30 kB. Bits[0:28] of this register protect Page 0 to Page 57 from writing. Each bit protects two pages, that is, 1 kB. Bits[29:30] protect Page 58 and Page 59, respectively; that is, each bit write protects a single page of 512 bytes. The MSB of this register (Bit 31) protects Block 0 from being read via JTAG. The FEE0PRO register mirrors the bit definitions of the FEE0HID MMR. The FEE0PRO MMR allows user code to lock the protect- tion or security configuration of the Flash/EE memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. This flexibility allows the user to set and test protection settings temporarily using the FEE0HID MMR and, subsequently, lock the required protection configu- ration (using FEE0PRO) when shipping protection systems into the field. In Block 1 (64 kB), the FEE1HID MMR protects the 64 kB. Bits[0:29] of this register protect Page 0 to Page 119 from writing. Each bit protects four pages, that is, 2 kB. Bit 30 protects Page 120 to Page 127; that is, Bit 30 write protects eight pages of 512 bytes. The MSB of this register (Bit 31) protects Flash/EE Block 1 from being read via JTAG. As with Block 0, the FEE1PRO register mirrors the bit definitions of the FEE1HID MMR. The FEE1PRO MMR allows user code to lock the protection or security configuration of the Flash/EE memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. There are three levels of protection: temporary protection, keyed permanent protection, and permanent protection. Temporary Protection Temporary protection can be set and removed by writing directly into the FEExHID MMR. This register is volatile and, therefore, protection is in place only while the part remains powered on. This protection is not reloaded after a power cycle. Keyed Permanent Protection Keyed permanent protection can be set via FEExPRO, which is used to lock the protection configuration. The software key used at the start of the required FEExPRO write sequence is saved once and must be used for any subsequent access of the FEExHID or FEExPRO MMRs. A mass erase sets the key back to 0xFFFF but also erases the entire user code space. Permanent Protection Permanent protection can be set via FEExPRO, in a manner similar to the way keyed permanent protection is set, with the only difference being that the software key used is 0xDEADDEAD. When the FEExPRO write sequence is saved, only a mass erase sets the key back to 0xFFFFFFFF. The mass erase also erases the entire user code space. Sequence to W rite the Key and Set Permanent Protection 1. Write FEExPRO corresponding to the pages to be protected. 2. Write the new (user-defined) 32-bit key in FEExADR, Bits[31:16] and FEExDAT, Bits[15:0]. 3. Write Bits[6:5] = 0x10 in FEExMOD. 4. Run the write key command (Code 0x0C) in FEExCON. To remove or modify the protection, the same sequence can be used with a modified value of FEExPRO. The previous sequence for writing the key and setting permanent protection is illustrated in the following example sequence, which protects writing Page 4 and Page 5 of the Flash/EE. Int a = FEExSTA; //Ensure FEExSTA is cleared FEExPRO =0 xFFFFFFFB; //Protect Page 4 and Page 5 FEExADR = 0x66BB; //32-bit key value (Bits[31:16]) FEExDAT = 0xAA55; //32-bit key value (Bits[15:0]) FEExMOD = 0x0048 //Lock security sequence FEExCON = 0x0C; //Write key command while (FEExSTA & 0x04){} //Wait for command to finish

Function: These registers are written by user code to configure the protection of the Flash/EE memory. Table 16. FEE0HID and FEE0PRO MMR Bit Designations Set by user code to allow reading the 32 kB Flash/EE block code via JTAG read access. Cleared by user code to protect the 32 kB Flash/EE block code via JTAG read access. Set by user code to allow writes to Page 59. Cleared by user code to write protect Page 59. Set by user code to allow writes to Page 58. Cleared by user code to write protect Page 58. 28 to 0 Write protection bits. each page consists of 512 bytes. each page consists of 512 bytes. 1 The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1. Function: These registers are written by user code to configure the protection of the Flash/EE memory. Table 17. FEE1HID and FEE1PRO MMR Bit Designations Set by user code to allow reading of the 64 kB Flash/EE block code via JTAG read access. Cleared by user code to read protect the 64 kB Flash/EE block code via JTAG read access. 30 Write protection bit. Write protects eight pages. Each page consists of 512 bytes. Set by user code to allow writes to Page 120 to Page 127 of the 64 kB Flash/EE code memory. Cleared by user code to write protect Page 120 to Page 127 of the 64 kB Flash/EE code memory. 29 to 0 Write protection bits. each page consists of 512 bytes. and each page consists of 512 bytes.

cycling endurance and Flash/EE memory data retention. described previously, before data retention is characterized. Figure 14. Flash/EE Memory Data Retention execution for applications where execution time is critical. cycles to fill the pipeline with the new instructions. needed to fetch any instruction. before accessing data for any value of CD bits. four cycles are needed to fill the pipeline if CD = 0. are more complex and are summarized in Table 18. Table 18. Typical Execution Cycles in ARM/Thumb Mode multiple load/store instruction. command. The abort operation typically requires 10 clock cycles. SRAM, allowing the core to immediately service the interrupt.

Rev. C | Page 32 of 132 ON-CHIP KERNEL The ADuC7036 features an on-chip kernel resident in the top 2 kB of the Flash/EE code space. After any reset event, this kernel copies the factory-calibrated data from the manufacturing data space into the various on-chip peripherals. The peripherals calibrated by the kernel are as follows:

• Power supply monitor (PSM)
• Precision oscillator
• Low power oscillator
• REG_AVDD/REG_DVDD
• Low power voltage reference
• Normal mode voltage reference
• Current ADC (offset and gain)
• Voltage/temperature ADC (offset and gain) User MMRs that can be modified by the kernel and differ from their POR default values are as follows:
• R0 to R15
• GP0CON/GP2CON
• SYSCHK
• ADCMDE/ADC0CON
• FEE0ADR/FEE0CON/FEE0SIG
• HVDAT/HVCON
• HVCFG0/HVCFG1
• T3LD The ADuC7036 also features an on-chip LIN downloader. The derivatives ADuC7036BCPZ and ADuC7036CCPZ use Protocol 4 for programming Flash/EE memory via LIN, where Protocol 6 is used on derivative ADuC7036DCPZ. The protocols are described in Application Note AN-881 (Protocol 4) and Application Note AN-946 (Protocol 6). Flowcharts of the execution of the kernel are shown in Figure 15 and Figure 16. The current revision of the kernel can be derived from SYSSER1, as described in Table 99. After a POR, the watchdog timer is disabled once the kernel code is exited. For the duration of the kernel execution, the watchdog timer is active with a timeout period of 500 ms. This ensures that when an error occurs in the kernel, the ADuC7036 automatically resets. After any other reset, the watchdog timer maintains user code configuration for the period of the kernel and is refreshed just prior to kernel exit. A minimum watchdog period of 30 ms is required to allow correct LIN downloader operation. If LIN download mode is entered, the watchdog is periodically refreshed. Normal kernel execution time, excluding LIN download, is approximately 5 ms. It is possible to enter and leave LIN download mode only through a reset. SRAM is not modified during normal kernel execution; rather, SRAM is modified during a LIN download kernel execution. Note that even with NTRST = 0, user code is not executed unless Address 0x14 contains either 0x27011970 or the checksum of Page 0, excluding Address 0x14. If Address 0x14 does not contain this information, user code is not executed and LIN download mode is entered. During kernel execution, JTAG access is disabled. With NTRST = 1, user code is always executed. The ADuC7036DCPZ allows for user-defined bootloader functionality. The bootloader can be of any size up to 30 kB but must be located at the top of user flash. The top-most three words must be the following:
• Address 0x977FC must contain the checksum of the bootloader.
• Address 0x977F8 must contain the lowest address of the bootloader block.
• Address 0x977F4 must contain the entry point of the bootloader code. The kernel uses the values at these addresses in determining if the bootloader is valid. Note that this bootloader checksum is the sum of all half words from the value pointed to by 0x977F8 up to the half word at 0x977F6.

Figure 15. ADuC7036BCPZ and ADuC7036CCPZ Kernel Flowchart

Figure 16. ADuC7036DCPZ Kernel Flowchart

bank for the ADuC7036 is shown in Figure 17. (described in the ARM Registers section) reside in the MMR area. only 16 of the MMR bits can be read. Figure 17. Top-Level MMR Map

In Table 19 to Table 30, addresses are listed in hexadecimal code. Access types include R for read, W for write, and RW for read and write. Table 19. IRQ Address Base = 0xFFFF0000 0x0000 IRQSTA 4 R 0x00000000 Active IRQ source. See the Interrupt System section and Table 50. 0x0008 IRQEN 4 RW 0x00000000 Enabled IRQ sources. See the Interrupt System section and Table 50. 0x000C IRQCLR 4 W N/A MMR to disable IRQ sources. See the Interrupt System section and Table 50. 0x0100 FIQSTA 4 R 0x00000000 Active IRQ source. See the Interrupt System section and Table 50. 0x0108 FIQEN 4 RW 0x00000000 Enabled IRQ sources. See the Interrupt System section and Table 50. 0x010C FIQCLR 4 W N/A MMR to disable IRQ sources. See the Interrupt System section and Table 50. 1 Depends on the level on the external interrupt pins (GPIO_0, GPIO_5, GPIO_7, and GPIO_8). Table 20. System Control Address Base = 0xFFFF0200 0x0220 SYSMAP0 1 RW N/A Remap control register. See the Remap Operation section and Table 10. Reset status MMR. See the Reset section and Table 11 and Table 12. 0x0234 RSTCLR 1 W N/A RSTSTA clear MMR. See the Reset section and Table 11 and Table 12. 0x0560 SYSALI 1 4 R N/A System assembly lot ID. See the Part Identification section for details. 0x0240 SYSCHK 1 4 RW N/A Kernel checksum. See the System Kernel Checksum section. Table 21. Timer Address Base = 0xFFFF0300 0x0320 T1LD 4 RW 0x00000000 Timer1 load register. See the Timer1 and Timer1 Load Register sections. 0x0324 T1VAL 4 R 0xFFFFFFFF Timer1 value register. See the Timer1 and Timer1 Value Register sections. 0x0328 T1CON 4 RW 0x01000000 Timer1 control MMR. See the Timer1 and Timer1 Control Register sections. 0x0330 T1CAP 4 R 0x00000000 Timer1 capture register. See the Timer1 and Timer1 Capture Register sections.

Register sections and Table 55. and Timer 3 Control Register sections and Table 56. 0x0390 T4CAP 2 R 0x0000 Timer4 capture register. See the Timer4—STI Timer section. Table 22. PLL Base Address = 0xFFFF0400 0x0400 PLLSTA 1 R N/A PLL status MMR. See the PLLSTA Register section and Table 44. 0x0404 POWKEY0 4 W N/A POWCON prewrite key. See the POWCON Prewrite Key section. 0x0408 POWCON 1 RW 0x79 Power control and core speed control register. See the POWCON Register section. 0x040C POWKEY1 4 W N/A POWCON postwrite key. See the POWCON Postwrite Key section. 0x0410 PLLKEY0 4 W N/A PLLCON prewrite key. See the PLLCON Prewrite Key section. 0x0414 PLLCON 1 RW 0x00 PLL clock source selection MMR. See the PLLCON Register section. 0x0418 PLLKEY1 4 W N/A PLLCON postwrite key. See the PLLCON Postwrite Key section. 0x042C OSC0TRM 1 RW 0xX8 Low power oscillator trim bits MMR. See the OSC0TRM Register section. 0x0440 OSC0CON 1 RW 0x00 Low power oscillator calibration control MMR. See the OSC0CON Register section. 0x0444 OSC0STA 1 R 0x00 Low power oscillator calibration status MMR. See the OSC0STA Register section.

Table 23. ADC Address Base = 0xFFFF0500 0x0500 ADCSTA 2 R 0x0000 ADC status MMR. See the ADC Status Register section and Table 35. 0x0508 ADCMDE 1 RW 0x00 ADC mode register. See the ADC Mode Register section and Table 36. Register section and Table 38. 0x0518 ADCFLT 2 RW 0x0007 ADC filter control MMR. See the ADC Filter Register section and Table 39. 0x0520 ADC0DAT 2 R 0x0000 Current ADC result MMR. See the Current Channel ADC Data Register section. 0x0524 ADC1DAT 2 R 0x0000 V-ADC result MMR. See the Voltage Channel ADC Data Register section. 0x0528 ADC2DAT 2 R 0x0000 T-ADC result MMR. See the Temperature Channel ADC Data Register section. Calibration Register section. Calibration Register section. Threshold Count Limit Register section. Threshold Count Register section. Reference Scaling Factor section.

Table 24. UART Base Address = 0XFFFF0700 0x0700 COMTX 1 W N/A UART transmit register. See the UART Tx Register section. COMRX 1 R 0x00 UART receive register. See the UART Rx Register section. Divisor Latch Register 0 section. Register 0 section and Table 84. Divisor Latch Register 1 section. Identification Register 0 section and Table 85. Register section and Table 86. Table 25. LIN Hardware Sync Base Address = 0XFFFF0780 Register section and Table 92. Control Register 0 section and Table 93. Register 1 section and Table 94. Table 26. High Voltage Interface Base Address = 0xFFFF0800 Control Register section and Table 71 and Table 72.

Table 27. STI Base Address = 0xFFFF0880 0x0880 STIKEY0 4 W N/A STICON prewrite key. See the Serial Test Interface Key0 Register section. 0x0888 STIKEY1 4 W N/A STICON postwrite key. See the Serial Test Interface Key1 Register section. 0x088C STIDAT0 2 RW 0x0000 STI Data MMR 0. See the Serial Test Interface Data0 Register section. 0x0890 STIDAT1 2 RW 0x0000 STI Data MMR 1. See the Se rial Test Interface Data1 Register section. 0x0894 STIDAT2 2 RW 0x0000 STI Data MMR 2. See the Se rial Test Interface Data2 Register section. Table 28. SPI Base Address = 0xFFFF0A00 0x0A00 SPISTA 1 R 0x00 SPI status MMR. See th e SPI Status Register section and Table 90. 0x0A04 SPIRX 1 R 0x00 SPI receive MMR. See the SPI Receive Register section. 0x0A08 SPITX 1 W N/A SPI transmit MMR. S ee the SPI Transmit Register section. 0x0A0C SPIDIV 1 RW 0x1B SPI baud rate sele ct MMR. See the SPI Divider Register section. 0x0A10 SPICON 2 RW 0x0000 SPI control MMR. See th e SPI Control Register section and Table 89. Table 29. GPIO Base Address = 0xFFFF0D00 0x0D00 GP0CON 4 RW 0x11100000 GPIO Port0 control MMR. See the GPIO Port0 Control Register section and Table 59. 0x0D04 GP1CON 4 RW 0x10000000 GPIO Port1 control MMR. See the GPIO Port1 Control Register section and Table 60. 0x0D08 GP2CON 4 RW 0x01000000 GPIO Port2 control MMR. See the GPIO Port2 Control Register section and Table 61. 0x0D20 GP0DAT 1 4 RW 0x000000XX GPIO Port0 data control MMR. See the GPIO Port0 Data Register section and Table 62. 0x0D24 GP0SET 4 W N/A GPIO Port0 data set MMR. See th e GPIO Port0 Set Register section and Table 65. 0x0D28 GP0CLR 4 W N/A GPIO Port0 data clear MMR. See the GPIO Port0 Clear Register section and Table 68. 0x0D30 GP1DAT 1 4 RW 0x000000XX GPIO Port1 data control MMR. See the GPIO Port1 Data Register section and Table 63. 0x0D34 GP1SET 4 W N/A GPIO Port1 data set MMR. See th e GPIO Port1 Set Register section and Table 66. 0x0D38 GP1CLR 4 W N/A GPIO Port1 data clear MMR. See the GPIO Port1 Clear Register section and Table 69. 0x0D40 GP2DAT 1 4 RW 0x000000XX GPIO Port2 data control MMR. See the GPIO Port2 Data Register section and Table 64. 0x0D44 GP2SET 4 W N/A GPIO Port2 data set MMR. See th e GPIO Port2 Set Register section and Table 67. 0x0D48 GP2CLR 4 W N/A GPIO Port2 data clear MMR. See the GPIO Port2 Clear Register section and Table 70. 1 Depends on the level on the external GPIO pins.

Table 30. Flash/EE Base Address = 0xFFFF0E00 0x0E00 FEE0STA 1 R 0x20 Flash/EE status MMR. 0x0E04 FEE0MOD 1 RW 0x00 Flash/EE control MMR. 0x0E08 FEE0CON 1 RW 0x07 Flash/EE control MMR. See Table 13. 0x0E0C FEE0DAT 2 RW 0x0000 Flash/EE data MMR. 0x0E10 FEE0ADR 2 RW Nonzero Flash/EE address MMR. 0x0E18 FEE0SIG 3 R 0xFFFFFF Flash/EE LFSR MMR. 0x0E1C FEE0PRO 4 RW 0x00000000 Flash/EE protection MMR. See the Flash/EE Memory Security section and Table 16. 0x0E20 FEE0HID 4 RW 0xFFFFFFFF Flash/EE protection MMR. See the Flash/EE Memory Security section and Table 16. 0x0E80 FEE1STA 1 R 0x20 Flash/EE status MMR. 0x0E84 FEE1MOD 1 RW 0x00 Flash/EE control MMR. 0x0E88 FEE1CON 1 RW 0x07 Flash/EE control MMR. See Table 13. 0x0E8C FEE1DAT 2 RW 0x0000 Flash/EE data MMR. 0x0E90 FEE1ADR 2 RW 0x0000 Flash/EE address MMR. 0x0E98 FEE1SIG 3 R 0xFFFFFF Flash/EE LFSR MMR. 0x0E9C FEE1PRO 4 RW 0x00000000 Flash/EE protection MMR. See the Flash/EE Memory Security section and Table 17. 0x0EA0 FEE1HID 4 RW 0xFFFFFFFF Flash/EE protection MMR. See the Flash/EE Memory Security section and Table 17.

Rev. C | Page 42 of 132 16-BIT, Σ-Δ ANALOG-TO-DIGITAL CONVERTERS The ADuC7036 incorporates two independent Σ-Δ analog-to- digital converters (ADCs): the current channel ADC (I-ADC) and the voltage/temperature channel ADC (V-/T-ADC). These precision measurement channels integrate on-chip buffering, a programmable gain amplifier, 16-bit, Σ-Δ modulators, and digital filtering for precise measurement of current, voltage, and temperature variables in 12 V automotive battery systems. CURRENT CHANNEL ADC (I-ADC) The I-ADC converts battery current sensed through an external 100 μΩ shunt resistor. On-chip programmable gain means that the I-ADC can be configured to accommodate battery current levels from ±1 A to ±1500 A. As shown in Figure 18, the I-ADC employs a Σ-Δ conversion technique to attain 16 bits of no missing codes performance. The Σ-Δ modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital infor- mation. A modified Sinc3, programmable, low-pass filter is then used to decimate the modulator output data stream to give a valid 16-bit data conversion result at programmable output rates from 4 Hz to 8 kHz in normal mode and from 1 Hz to 2 kHz in low power mode. The I-ADC also incorporates counter, comparator, and accu- mulator logic. This allows the I-ADC result to generate an interrupt after a predefined number of conversions has elapsed or the I-ADC result exceeds a programmable threshold value. A fast ADC overrange feature is also supported. Once enabled, a 32-bit accumulator automatically sums the 16-bit I-ADC results. The time to a first valid (fully settled) result on the current channel is three ADC conversion cycles with chop mode disabled and two ADC conversion cycles with chop mode enabled.

Figure 18. Current ADC, Top-Level Overview

additional battery parameters, such as voltage and temperature. sensor circuit, or an on-chip temperature sensor. this is internally implemented in the voltage channel. via an on-chip, high voltage (divide-by-24), resistive attenuator. the voltage attenuator input is selected. temperature sensor or an external temperature sensor input. ADC conversion cycles with chop mode disabled. overview of this ADC signal chain is shown in Figure 19. Figure 19. Voltage/Temperature ADC, Top-Level Overview

Low Power Voltage Reference Scaling Factor section. logic OR’ ed to produce a single ADC interrupt to the MCU core. the ADCSTA MMR to determine the source of the interrupt. the ready bits have not been cleared. related to the mode of operation or current status of the ADCs. Table 35. ADCSTA MMR Bit Designations Set automatically in hardware to indicate that an ADC calibration cycle has been completed. Cleared after ADCMDE is written to. 14 ADC temperature conversion error. result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. Cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register. 13 ADC voltage conversion error. clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. Cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register. 12 ADC current conversion error. clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. Cleared when a valid (in-range) current conversion result is written to the ADC0DAT register. 11 to 5 Not used. These bits are reserved for future functionality and should not be monitored by user code. 4 Current channel ADC comparator threshold. Valid only if the current channel ADC comparator is enabled via the ADCCFG MMR. Cleared automatically by hardware when reconfiguring the ADC or if the comparator is disabled. 3 Current channel ADC overrange bit. approximate) over range. This bit is updated every 125 μs. Cleared by software only when ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the ADC0CON MMR. 2 Temperature conversion result ready bit. temperature data register (ADC2DAT MMR). It is also set at the end of a calibration. Cleared by reading either ADC2DAT or ADC0DAT. 1 Voltage conversion result ready bit. register (ADC1DAT MMR). It is also set at the end of a calibration. Cleared by reading either ADC1DAT or ADC0DAT. 0 Current conversion result ready bit. register (ADC0DAT MMR). It is also set at the end of a calibration.

meaning all ADC interrupt sources are disabled. Function: This 8-bit register configures the mode of operation of the ADC subsystem. Table 36. ADCMDE MMR Bit Designations 7 Not used. This bit is reserved for future functionality and should be written as 0 by user code. Set to 1 to select the 20 kΩ resistor as shown in Figure 21. Set to 0 to select the direct path to ground as shown in Figure 21 (default). 5 Low power mode reference select. Set to 0 to enable the low power voltage reference in either low power mode or low power plus mode (default). 4 to 3 ADC power mode configuration. 00 = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance. (131 kHz) oscillator to directly drive the ADC circuits. also ensures that the ADC noise performance is better than that achieved in ADC low power mode. 2 to 0 ADC operation mode configuration. 000 = ADC power-down mode. All ADC circuits (including internal reference) are powered down. 001 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts. the single shot conversion is complete. A single conversion takes two to three ADC clock cycles depending on the chop mode. 011 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. conversion ready status bits are set at the end of an offset calibration cycle. therefore, as with a normal, single ADC conversion, it takes three ADC conversion cycles before a fully settled calibration result is ready. external full-scale voltage driven at the ADC input pins.

Function: This 16-bit register is used to configure the I-ADC. Note that if the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ADC are also reset. Table 37. ADC0CON MMR Bit Designations 15 Current channel ADC enable. Set to 1 by user code to enable the I-ADC. Cleared to 0 to power down the I-ADC and reset the respective ADC ready bit in the ADCSTA MMR to 0. 14, 13 IIN current source enable. 01 = enables the 50 μA current source on IIN+. 10 = enables the 50 μA current source on IIN−. 11 = enables the 50 μA current source on both IIN− and IIN+. 12 to 10 Not used. These bits are reserved for future functionality and should be written as 0. 9 Current channel ADC output coding. Set to 1 by user code to configure I-ADC output coding as unipolar. Cleared to 0 by user code to configure I-ADC output coding as twos complement. 8 Not used. This bit is reserved for future functionality and should be written as 0. 7, 6 Current channel ADC input select. 00 = IIN+, IIN− are selected. 01 = IIN−, IIN− are selected. Diagnostic, internal short configuration. selected, REG_AVDD is used for VREF in this mode. This leads to ADC0DAT scaled by 2. 5, 4 Current channel ADC reference select. 01 = external reference inputs (VREF, GND_SW) selected. 10 = external reference inputs divided-by-2 (VREF, GND_SW)/2 selected, which allows an external reference up to REG_AVDD. 11 = (REG_AVDD, AGND) divided-by-2 selected. 3 to 0 Current channel ADC gain select. The nominal I-ADC full-scale input voltage = (VREF/gain). 1xxx = I-ADC gain is undefined.

Function: This 16-bit register is used to configure the V-/T-ADC. Note that when selecting the VBAT attenuator input, the voltage attenuator buffers are automatically enabled. Table 38. ADC1CON MMR Bit Designations 15 Voltage/temperature channel ADC enable. Set to 1 by user code to enable the V-/T-ADC. Cleared to 0 to power down the V-/T-ADC. 14, 13 VTEMP current source enable. 01 = enables 50 μA current source on VTEMP . 10 = enables 50 μA current source on GND_SW. 11 = enables 50 μA current source on both VTEMP and GND_SW. 12 to 10 Not used. These bits are reserved for future functionality and should not be modified by user code. 9 Voltage/temperature channel ADC output coding. Set to 1 by user code to configure V-/T-ADC output coding as unipolar. Cleared to 0 by user code to configure V-/T-ADC output coding as twos complement. 8 Not used. This bit is reserved for future functionality and should be written as 0 by user code. 7, 6 Voltage/temperature channel ADC input select. 00 = VBAT/24, AGND. VBAT attenuator selected. The high voltage buffers are enabled automatically in this configuration. 01 = VTEMP , GND_SW. External temperature input selected, conversion result written to ADC2DAT. gradient is 0.33 mV/°C; this is only applicable to the internal temperature sensor. 11 = internal short. Shorted input. 5, 4 Voltage/temperature channel ADC reference select. 00 = internal, 1.2 V precision reference selected. 01 = external reference inputs (VREF, GND_SW) selected. 10 = external reference inputs divided-by-2 (VREF , GND_SW)/2 selected. This allows an external reference up to REG_AVDD. 11 = (REG_AVDD, AGND)/2 selected for the voltage channel. (REG_AVDD, GND_SW)/2 selected for the temperature channel. 3 to 0 Not used. These bits are reserved for future functionality and should not be written as 0 by user code.

Function: This 16-bit register controls the speed and resolution of the on-chip ADCs. Note that if ADCFLT is modified, the current and voltage/temperature ADCs are reset. Table 39. ADCFLT MMR Bit Designations drift, but the ADC output rate is reduced by a factor of three if AF = 0 (see Sinc3 decimation factor, Bits[6:0], in this table). does not reduce the ADC output rate but does increase the settling time by one conversion period. Cleared by the user to disable the running average function. 13 to 8 Averaging factor (AF). The values written to these bits are used to implement a programmable first-order Sinc3 postfilter. decimation factor, in this table. location of the first notch in the response. chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125. For SF = 126, fADC is forced to 60 Hz. For SF = 127, fADC is forced to 50 Hz. For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 40. that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.

Table 40. ADC Conversion Rates and Settling Times 1 An additional time of approximately 60 μs per ADC is required before the first ADC is available. Table 41. Allowable Combinations of SF and AF

Function: This 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 42. ADCCFG MMR Bit Designations 7 Analog ground switch enable. Cleared by user code to disconnect the external GND_SW pin. 6, 5 Current channel (32-bit) accumulator enable. before the accumulator can be reenabled to ensure that the accumulator is reset. Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum value of 0. Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions. accumulate negatively, below 0. 4, 3 Current channel ADC comparator enable. 01 = comparator active, interrupt asserted if absolute value of I-ADC conversion result is |I| ≥ ADC0TH. number of ADC0TCL conversions. A conversion value of |I| < ADC0TH resets the threshold counter value (ADC0THV) to 0. number of ADC0TCL conversions. A conversion value of |I| < ADC0TH decrements the threshold counter value (ADC0THV) toward 0. 2 Current channel ADC overrange enable. overrange for the active gain setting, then the overrange bit in the ADCSTA MMR is set. Cleared by user code to disable the overrange feature. 1 Not used. This bit is reserved for future functionality and should be written as 0 by user code. 0 Current channel ADC, result counter enable. V-/T-ADC conversion results are not stored) when the ADC counter interrupt occurs.

Rev. C | Page 53 of 132 Current Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF0520 Default Value: 0x0000 Access: Read only Function: This ADC data MMR holds the 16-bit conversion result from the I-ADC. The ADC does not update this MMR if the ADC0 conversion result ready bit (ADCSTA[0]) is set. A read of this MMR by the MCU clears all asserted ready flags (ADCSTA[2:0]). Voltage Channel ADC Data Register Name: ADC1DAT Address: 0xFFFF0524 Default Value: 0x0000 Access: Read only Function: This ADC data MMR holds the 16-bit voltage conversion result from the V-/T-ADC. The ADC does not update this MMR if the voltage conversion result ready bit (ADCSTA[1]) is set. If I-ADC is not active, a read of this MMR by the MCU clears all asserted ready flags (ADCSTA[2:1]). Temperature Channel ADC Data Register Name: ADC2DAT Address: 0xFFFF0528 Default Value: 0x0000 Access: Read only Function: This ADC data MMR holds the 16-bit temperature conversion result from the V-/T-ADC. The ADC does not update this MMR if the temperature conversion result ready bit (ADCSTA[2]) is set. If I-ADC and V-ADC are not active, a read of this MMR by the MCU clears all asserted ready flags (ADCSTA[2]). A read of this MMR clears ADCSTA[2]. Current Channel ADC Offset Calibration Register Name: ADC0OF Address: 0xFFFF0530 Default Value: Part specific, factory programmed Access: Read/write Function: This ADC offset MMR holds a 16-bit offset calibration coefficient for the I-ADC. The register is configured at power- on with a factory default value. However, this register automati- cally overwrites if an offset calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Voltage Channel ADC Offset Calibration Register Name: ADC1OF Address: 0xFFFF0534 Default Value: Part specific, factory programmed Access: Read/write Function: This offset MMR holds a 16-bit offset calibration coefficient for the voltage channel. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if an offset calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Temperature Channel ADC Offset Calibration Register Name: ADC2OF Address: 0xFFFF0538 Default Value: Part specific, factory programmed Access: Read/write Function: This ADC offset MMR holds a 16-bit offset calibration coefficient for the temperature channel. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if an offset calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Current Channel ADC Gain Calibration Register Name: ADC0GN Address: 0xFFFF053C Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling the I-ADC conversion result. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if a gain calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs.

Rev. C | Page 54 of 132 Voltage Channel ADC Gain Calibration Register Name: ADC1GN Address: 0xFFFF0540 Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling a voltage channel conversion result. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if a gain calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Temperature Channel ADC Gain Calibration Register Name: ADC2GN Address: 0xFFFF0544 Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling a temperature channel conversion result. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if a gain calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Current Channel ADC Result Counter Limit Register Name: ADC0RCL Address: 0xFFFF0548 Default Value: 0x0001 Access: Read/write Function: This 16-bit MMR sets the number of conversions that are required before an ADC interrupt is generated. By default, this register is set to 0x0001. The ADC counter function must be enabled via the ADC result counter enable bit in the ADCCFG MMR. Current Channel ADC Result Count Register Name: ADC0RCV Address: 0xFFFF054C Default Value: 0x0000 Access: Read only Function: This 16-bit, read only MMR holds the current number of I-ADC conversion results. It is used in conjunction with ADC0RCL to mask I-ADC interrupts, generating a lower interrupt rate. When ADC0RCV = ADC0RCL, the value in ADC0RCV resets to 0 and recommences counting. It can also be used in conjunction with the accumulator (ADC0ACC) to allow an average current calculation to be undertaken. The result counter is enabled via ADCCFG[0]. This MMR is also reset to 0 when the I-ADC is reconfigured, that is, when the ADC0CON or ADCMDE is written. Current Channel ADC Threshold Register Name: ADC0TH Address: 0xFFFF0550 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR sets the threshold against which the absolute value of the I-ADC conversion result is compared. In unipolar mode, ADC0TH[15:0] are compared, and in twos complement mode, ADC0TH[14:0] are compared. Current Channel ADC Threshold Count Limit Register Name: ADC0TCL Address: 0xFFFF0554 Default Value: 0x01 Access: Read/write Function: This 8-bit MMR determines how many cumulative (that is, values that are below the threshold decrement or that reset the count to 0) I-ADC conversion result readings above ADC0TH must occur before the I-ADC comparator threshold bit is set in the ADCSTA MMR, generating an ADC interrupt. The I-ADC comparator threshold bit is asserted as soon as ADC0THV = ADC0TCL. Current Channel ADC Threshold Count Register Name: ADC0THV Address: 0xFFFF0558 Default Value: 0x00 Access: Read only Function: This 8-bit MMR is incremented every time the absolute value of an I-ADC conversion result is |I| ≥ ADC0TH. This register is decremented or reset to 0 every time the absolute value of an I-ADC conversion result is |I| < ADC0TH. The configuration of this function is enabled via the current channel ADC comparator bits in the ADCCFG MMR.

Rev. C | Page 55 of 132 Current Channel ADC Accumulator Register Name: ADC0ACC Address: 0xFFFF055C Default Value: 0x00000000 Access: Read only Function: This 32-bit MMR holds the current accumulator value. The I-ADC ready bit in the ADCSTA MMR should be used to determine when it is safe to read this MMR. The MMR value is reset to 0 by disabling the accumulator in the ADCCFG MMR or reconfiguring the current channel ADC. Low Power Voltage Reference Scaling Factor Register Name: ADCREF Address: 0xFFFF057C Default Value: Part specific, factory programmed Access: Read/write. Care should be taken not to write to this register. Function: This MMR allows user code to correct for the initial error of the LPM reference. Value 0x8000 corresponds to no error when compared to the normal mode reference. The magni- tude of the ADC result should be multiplied by the value in ADCREF and divided by 0x8000 to compensate for the actual value of the low power reference. If the LPM voltage reference is 1% below 1.2 V , the value of ADCREF is approximately 0x7EB9. If the LPM voltage reference is 1% above 1.2 V , the value of ADCREF is approximately 0x8147. This register corrects the effective value of the LPM reference at the temperature at which the reference is measured during the Analog Devices, Inc., production flow, which is 25°C. There is no change to the temperature coefficient of the LPM reference when using the ADCREF MMR. This register should not be used if the precision reference is being used in low power mode (if ADCMDE[5] is set). ADC POWER MODES OF OPERATION The ADCs can be configured into various reduced or full power modes of operation by changing the configuration of ADCMDE[4:3], and the ARM7 MCU can be configured in low power modes of operation (POWCON[5:3]). The core power modes are independently controlled and are not related to the ADC power modes described in the following sections. ADC Normal Power Mode In normal mode, the current and voltage/temperature channels are fully enabled. The ADC modulator clock is 512 kHz and enables the ADCs to provide regular conversion results at a rate between 4 Hz and 8 kHz (see the ADC Filter Register section). Both channels are under full control of the MCU and can be reconfigured at any time. The default ADC update rate for all channels in this mode is 1 kHz. Note that the I-ADC and V-/T-ADC channels can be configured to initiate periodic single conversion cycles in normal power mode with high accuracy before returning to ADC full power-down mode. This flexibility is facilitated by full MCU control via the ADCMDE MMR, which ensures the feasibility of continuous periodic monitoring of battery current, voltage, and temperature settings while minimizing the average dc current consumption. In ADC normal mode, the PLL must not be powered down. ADC Low Power Mode In ADC low power mode, the I-ADC is enabled in a reduced power and reduced accuracy configuration. The ADC modu- lator clock is driven directly from the on-chip 131 kHz low power oscillator, which allows the ADC to be configured at update rates as low as 1 Hz (ADCFLT). The gain of the ADC in this mode is fixed at 128. All ADC peripheral functions (result counter, digital comparator and accumulator) described in the ADC Normal Power Mode section can also be enabled in low power mode. Typically, in low power mode, only the I-ADC is configured to run at a low update rate, continuously monitoring battery current. The MCU is in power-down mode and wakes up when the I-ADC interrupts the MCU. Such an interrupt occurs after the I-ADC detects a current conversion beyond a preprogrammed threshold, a setpoint, or a set number of conversions. It is also possible to select either the ADC precision voltage reference or the ADC low power mode voltage reference via ADCMDE[5]. ADC Low Power Plus Mode In low power plus mode, the I-ADC channel is enabled in a mode almost identical to low power mode (ADCMDE[4:3]). However, in this mode, the I-ADC gain is fixed at 512, and the ADC consumes an additional 200 μA (approximately) to yield improved noise performance relative to the low power mode setting. All ADC peripheral functions (result counter, digital comparator, and accumulator) described in the ADC Normal Power Mode section can also be enabled in low power plus mode. As in low power mode, only the I-ADC is configured to run at a low update rate, continuously monitoring battery current. The MCU is in power-down mode and wakes up only when the I-ADC interrupts the MCU. This happens after the I-ADC detects a current conversion result that exceeds a preprogrammed threshold or a setpoint. It is also possible to select either the ADC precision voltage reference or the ADC low power mode voltage reference via ADCMDE[5].

Figure 28. Typical Digital Filter Response at fADC = 1 Hz (ADCFLT = 0xBD1F) Table 43. Common ADCFLT Configurations

Rev. C | Page 59 of 132 ADC CALIBRATION As shown in detail in the top-level diagrams (Figure 18 and Figure 19), the signal flow through all ADC channels can be described as follows: 1. An input voltage is applied through an input buffer (and through PGA in the case of the I-ADC) to the Σ-Δ modulator. 2. The modulator output is applied to a programmable digital decimation filter. 3. The filter output result is then averaged if chopping is used. 4. An offset value (ADCxOF) is subtracted from the result. 5. This result is scaled by a gain value (ADCxGN). 6. The result is formatted as twos complement/offset binary and rounded to 16 bits or clamped to ±full scale. Each ADC has a specific offset and gain correction or calibra- tion coefficient associated with it that are stored in MMR-based offset and gain registers (ADCxOF and ADCxGN). The offset and gain registers can be used to remove offsets and gain errors within the part, as well as system-level offset and gain errors external to the part. These registers are configured at power-on with a factory- programmed calibration value. These factory-set calibration values vary from part to part, reflecting the manufacturing variability of internal ADC circuits. However, these registers can also be overwritten by user code if the ADC is in idle mode and are automatically overwritten if an offset or gain calibration cycle is initiated by the user through the ADC operation mode configuration bits in the ADCMDE[2:0] MMR. Two types of automatic calibration are available to the user: self-calibration or system calibration. Self-Calibration In self-calibration of offset errors, the ADC generates its calibration coefficient based on an internally generated 0 V , whereas in self-calibration of gain errors, the coefficient is based on the full-scale voltage. Although self-calibration can correct offset and gain errors within the ADC, it cannot compensate for external errors in the system, such as shunt resistor tolerance/drift and external offset voltages. Note that in self-calibration mode, ADC0GN must contain the values for PGA = 1 before a calibration scheme is started. System Calibration In system calibration of offset errors, the ADC generates its calibration coefficient based on an externally generated zero- scale voltage, whereas in system calibration of gain errors, the coefficient is based on the full-scale voltage. The calibration coefficient is applied to the external ADC input for the duration of the calibration cycle. The duration of an offset calibration is a single conversion cycle (3/fADC chop off, 2/fADC chop on) before returning the ADC to idle mode. A gain calibration is a two-stage process and, there- fore, takes twice as long as an offset calibration cycle. When a calibration cycle is initiated, any ongoing ADC conversion is immediately halted, the calibration is automatically performed at the ADC update rate programmed in ADCFLT, and the ADC is always returned to idle after any calibration cycle. It is strongly recommended that ADC calibration be initiated at as low an ADC update rate as possible (and, therefore, requires a high SF value in ADCFLT) to minimize the impact of ADC noise during calibration. Using the Offset and Gain Calibration If the chop enable bit, ADCFLT[15], is enabled, internal ADC offset errors are minimized and an offset calibration may not be required. If chopping is disabled, however, an initial offset calibration is required and may need to be repeated, particularly after a large change in temperature. Depending on system accuracy requirements, a gain calibration, particularly in the context of the I-ADC (with internal PGA), may need to be performed at all relevant system gain ranges. If it is not possible to apply an external full-scale current on all gain ranges, apply a lower current and then scale the result produced by the calibration. For example, apply a 50% current, and then divide the resulting ADC0GN value by 2 and write this value back into ADC0GN. Note that there is a lower limit for the input signal that can be applied during a system calibration because ADC0GN is only a 16-bit register. The input span (that is, the difference between the system zero-scale value and the system full-scale value) should be greater than 40% of the nominal full- scale-input range (that is, >40% of VREF/gain). The on-chip Flash/EE memory can be used to store multiple calibration coefficients. These calibration coefficients can be copied directly into the relevant calibration registers by user code and are based on the system configuration. In general, the simplest way to use the calibration registers is to let the ADC calculate the values required as part of the ADC automatic calibration modes. A factory-programmed or end-of-line calibration for the I-ADC is a two-step procedure. Apply 0 A current. Configure the ADC in the required PGA setting, and write to ADCMDE[2:0] to perform a system zero-scale calibration. This writes a new offset calibration value into ADC0OF. Apply a full-scale current for the selected PGA setting. Write to ADCMDE to perform a system full-scale calibration. This writes a new gain calibration value into ADC0GN. Understanding the Offset and Gain Calibration Registers The output of a typical block in the ADC signal flow (described in the ADC Sinc3 Digital Filter Response section through the Using the Offset and Gain Calibration section) can be consid- ered a fractional number with a span for a ±full-scale input of approximately ±0.75. The span is less than ±1 because there is attenuation in the modulator to accommodate some overrange capacity on the input signal. The exact value of the attenuation varies slightly from part to part because of manufacturing tolerances.

Rev. C | Page 60 of 132 For the current channel ADC, The offset coefficient is read from the ADC0OF calibration register and is a 16-bit, twos complement number. The range of this number, in terms of the signal chain, is effectively ±1. Therefore, 1 LSB of the ADC0OF register is not the same as 1 LSB of the ADC0DAT register. NOMREF IN OUT ADCxGN ADCxGNADCxOFKV PGA VADC ×−= ⎥ ⎡ ×× where K is dependent on the PGA gain setting and ADC mode. A positive value of ADC0OF indicates that when offset is subtracted from the output of the filter, a negative value is added. The nominal value of this register is 0x0000, indicating zero offset is to be removed. The actual offset of the ADC can vary slightly from part to part and at different PGA gains. The offset within the ADC is minimized if the chopping mode is enabled (that is, ADCFLT[15] = 1). Normal Mode In normal mode, K = 1 for PGA gains of 1, 4, 8, 16, 32, and 64; K = 2 for PGA gains of 2 and 128; K = 4 for a PGA gain of 256; and K = 8 for a PGA gain of 512. Low Power Mode In low power mode, K = 32 for a PGA gain of 128. In addition, if the REG_AVDD/2 reference is used, the K factor doubles. The gain coefficient is read from the ADC0GN register and is a unitless scaling factor. The 16-bit value in this register is divided by 16,384 and then multiplied by the offset-corrected value. The nominal value of this register equals 0x5555, corresponding to a multiplication factor of 1.3333, and scales the nominal ±0.75 signal to produce a full-scale output signal of ±1. The resulting output signal is checked for overflow/underflow and converted to twos complement or unipolar mode before being output to the data register. Low Power Plus Mode In low power plus mode, K = 8 for a PGA gain of 512. In addition, if the REG_AVDD/2 reference is used, the K factor doubles. ADC DIAGNOSTICS The ADuC7036 features a diagnostic capability and open- circuit detection on both ADCs. Current ADC Diagnostics The actual gain and the required scaling coefficient for zero gain error vary slightly from part to part at different PGA set- tings in normal and low power modes. The value downloaded into ADC0GN during a power-on reset represents the scaling factor for a PGA gain of 1. If a different PGA setting is used, however, some gain error may be present. To correct this error, overwrite the calibration coefficients via user code or perform an ADC calibration. The ADuC7036 features the capability to detect open-circuit conditions on the current channel inputs. This is accomplished using the two current sources on IIN+ and IIN−, which are controlled via ADC0CON[14:13]. Note that the IIN+ and IIN− current sources have a tolerance of ±30%. Therefore, a PGA gain ≥ 2 (ADC0CON[3:0] ≥ 0001) must be used when current sources are enabled. The simplified ADC transfer function can be described as Temperature ADC Diagnostics The ADuC7036 features the capability to detect open-circuit conditions on the temperature channel inputs. This is accomplished using the two current sources on VTEMP and GND_SW , which are controlled via ADC1CON[14:13]. NOMREF IN OUT ADCxGN ADCxGNADCxOFV PGA VADC ×⎥ ⎡ × −= where the equation is valid for the voltage/temperature chan- nel ADC. Voltage ADC Diagnostics The ADuC7036 features the capability to detect open-circuit conditions on the voltage channel input. This is accomplished using the current source on the voltage attenuator, controlled by the high voltage register HVCFG1[7].

including the on-chip precision analog circuits. functions with an output capacitor (0.47 μF) on REG_AVDD. 32 kHz is recommended to ensure the stability of the regulators. monitoring of the battery power supply. 10 Ω and 10 μF, as shown on Figure 60). if the high voltage IRQ is enabled via IRQEN[16] or FIQEN[16]. An example of this operation is shown in Figure 29. that the contents of the SRAM remain valid after a reset event. Figure 29. Typical Power-On Cycle

controls both the core clock frequency and the power-down mode. core begins executing code as soon as the PLL starts oscillating. the PLL output divide-by-8 to the locked PLL output. resuming normal code execution. (prewrite key) and POWKEY1 (postwrite key). lock state of the PLL and the status of the external crystal. Table 44. PLLSTA MMR Bit Designations low at a frequency of 32.768 kHz. 1 PLL lock status bit. This is a read only bit. Set when the PLL is locked and outputting 20.48 MHz. fCORE divide-by-8 clock source. Set if the PLL lock status bit signal goes low. Cleared by writing 1 to this bit.

written before and after PLLCON. PLLKEY0 is the prewrite key. written before and after PLLCON. PLLKEY1 is the postwrite key. select the PLL source clock from three different oscillator sources. Table 45. PLLCON MMR Bit Designations 7 to 2 Reserved. These bits should be written as 0 by user code. 00 = lower power, 131 kHz oscillator. 01 = precision 131 kHz oscillator. 10 = external 32.768 kHz crystal.

1 If the user code switches MCU clock sources, a dummy MCU cycle should be

included after the clock switch is written to PLLCON. written before and after POWCON. POWKEY0 is the prewrite key.

Table 46. POWCON MMR Bit Designations 7 Precision 131 kHz input enable. Set by the user to enable the precision 131 kHz input enable. The precision 131 kHz oscillator must also be enabled using HVCFG0[6]. Setting this bit increases current consumption by approximately 50 μA. It should be disabled when not in use. Cleared by the user to power-down the precision 131 kHz input enable. Set by the user to enable the external crystal circuitry. Cleared by the user to power down the external crystal circuitry. remain in normal power mode. Set by default and set by hardware on a wake-up event. and Bit 5 must be cleared simultaneously. interfaces, and SPI and UART serial ports. oscillator even if this bit is set. cleared simultaneously. LIN can still respond to wake-up events even if this bit is cleared. Set by default, and set by hardware on a wake-up event. Cleared to power down the ARM core. 001 = 10.24 MHz, 97.66 ns (this is default setting on power up).

trim register are used to implement this feature. at 131 kHz or through a divide-by-4 block generating 32.768 kHz. typical trim range is between 127 kHz and 135 kHz. OSC0CON: control bits for calibration.

• OSC0STA: calibration status register.
• OSC0V AL0: 9-bit counter, Counter 0.
• OSC0V AL1: 10-bit counter, Counter 1.
• OSC0TRM: oscillator trim register. A calibration routine flowchart is shown in Figure 31. User code configures and enables the calibration sequence using OSC0CON. When the OSC0V AL0 precision power oscillator calibration counter reaches 0x1FF, both counters are disabled. User code then reads back the value of the low power oscillator calibration counter. There are three possible scenarios:
• OSC0V AL0 = OSC0V AL1. No further action is required.
• OSC0V AL0 > OSC0V AL1. The low power oscillator is running slow. OSC0TRM must be decreased.
• OSC0V AL0 < OSC0V AL1. The low power oscillator is running fast. OSC0TRM must be increased. When the value in OSC0TRM has been changed, the routine should be run again, and the new frequency should be checked. Using the internal precision 131 kHz oscillator requires approx- imately 4 ms to execute the calibration routine. If the external 32.768 kHz crystal is used, the time increases to 16 ms. Prior to the start of the clock calibration routine, the user must switch to either the precision 131 kHz oscillator or the external 32.768 kHz watch crystal to serve as the PLL clock source. If this is not done, the PLL may lose lock each time OSC0TRM is modified, thereby increasing the time required to calibrate the low power oscillator. BEGIN CALIBRATION ROUTINE WHILE OSC0STA[0] = 1 INCREASE OSC0TRM DECREASE OSC0TRM OSC0VAL0 < OSC0VAL1 OSC0VAL0 > OSC0VAL1 END CALIBRATION ROUTINE IS ERROR WITHIN DESIRED LEVEL? OSC0VAL0 = OSC0VAL1 NO YES 07474-030

Figure 31. OSC0TRM Calibration Routine

Function: This 8-bit register controls the low power oscillator trim. Table 47. OSC0TRM MMR Bit Designations 7 to 4 Reserved. Should be written as 0. Table 48. OSC0CON MMR Bit Designations 7 to 5 Reserved. Should be written as 0. Set to select external 32.768 kHz crystal. Cleared to select internal precision 131 kHz oscillator. Cleared to abort calibration. oscillator calibration routine. Table 49. OSC0STA MMR Bit Designations Set by hardware on full completion of a calibration cycle. Cleared by a read of OSC0VAL1. 0 Set if calibration is in progress. Cleared if calibration is complete. precision oscillator or the 32.768 kHz external crystal.

request (FIQ). All the interrupts can be masked separately. IRQSIG[2] is set and can be cleared only by writing to T0CLRI. ARM core can then be powered up only by a reset event. Table 50. IRQ/FIQ MMRs Bit Designations

0 All interrupts OR’ed (FIQ only)

1 SWI: not used in IRQEN/IRQCLR and FIQEN/FIQCLR

2 Timer0 See the Timer0—Lifetime Timer section. 3 Timer1 See the Timer1 section. 4 Timer2 or wake-up timer See the Timer2—Wake-Up Timer section. 5 Timer3 or watchdog timer See the Timer3—Watchdog Timer section. 6 Timer4 or STI timer See the Timer4—STI Timer section. 7 LIN hardware See the LIN (Local Interconnect Network) Interface section. 8 Flash/EE interrupt See the Flash/EE Control Interface section. 9 PLL lock See the System Clocks section. 10 ADC See the 16-Bit, Σ-Δ Analog-to-Digital Converters section. 11 UART See the UART Serial Interface section. 12 SPI master See the Serial Peripheral Interface section. 13 XIRQ0 (GPIO IRQ0) See the General-Purpose I/O section. 14 XIRQ1 (GPIO IRQ1) See the General-Purpose I/O section.

15 Reserved

16 IRQ3 high voltage IRQ High voltage interrupt; see the High Voltage Peripheral Control Interface

17 SPI slave See the Serial Peripheral Interface section. 18 XIRQ4 (GPIO IRQ4) See the General-Purpose I/O section. 19 XIRQ5 (GPIO IRQ5) See the General-Purpose I/O section.

interrupt handling of internal and external events. that is currently enabled by IRQ source status (see Figure 32). in the IRQEN MMR. IRQSIG is read only. source request is enabled to create an IRQ exception signal. disabled or masked and does not create an IRQ exception signal. The IRQEN register cannot be used to disable an interrupt. bit in the IRQEN register without affecting the remaining bits. an automatic read-modify-write instruction. FIQSIG, FIQEN, FIQCLR, and FIQSTA. source can be disabled in both IRQEN and FIQEN masks. Table 51. SWICFG MMR Bit Designations controller and by the user in the IRQSTA or FIQSTA register.

Figure 32. Interrupt Structure

The ADuC7036 features five general-purpose timer/counters.

• Timer0, or the lifetime timer
• Timer1, or general-purpose timer
• Timer2, or the wake-up timer
• Timer3, or the watchdog timer
• Timer4, or the STI timer The five timers in their normal mode of operation can be in either free running mode or periodic mode. Timers are started by writing data to the control register of the corresponding timer (TxCON). The counting mode and speed depend on the configuration chosen in TxCON. In normal mode, an IRQ is generated each time the value of the counter reaches 0 when counting down, or each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing any value to clear the register of that particular timer (TxCLRI). The three timers in their normal mode of operation can be either free-running or periodic. In free-running mode, starting with the value in the TxLD register, the counter decrements/increments from the maximum/ minimum value until zero/full scale and starts again at the maximum/minimum value. This means that, in free-running mode, TxV AL is not reloaded when the relevant interrupt bit is set but the count simply rolls over as the counter underflows or overflows. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero/full scale starts again from this value. This means when the relevant interrupt bit is set, TxV AL is reloaded with TxLD and counting starts again from this value. Loading the TxLD register with zero is not recommended. The value of a counter can be read at any time by accessing its value register (TxV AL). In addition, Timer0, Timer1, and Timer4 each have a capture register (T0CAP , T1CAP , and T4CAP , respectively) that can hold the value captured by an enabled IRQ event. The IRQ events are described in Table 52.

Table 52. Timer Event Capture

0 Timer0, or the lifetime timer

1 Timer1, or general-purpose timer

2 Timer2, or the wake-up timer

3 Timer3, or the watchdog timer

4 Timer4, or the STI timer

5 LIN hardware

6 Flash/EE interrupt

7 PLL lock

8 ADC

9 UART

10 SPI master

11 XIRQ0 (GPIO_0)

12 XIRQ1 (GPIO_5)

13 Reserved

14 IRQ3 high voltage interrupt

15 SPI slave

16 XIRQ4 (GPIO_7); see the General-Purpose I/O section

17 XIRQ5 (GPIO_8); see the General-Purpose I/O section

user MMR interface by the synchronization (SYNC) block.

Rev. C | Page 73 of 132 Starting Timer2 When starting Timer2, it is recommended to first load Timer2 with the required TxLD value. Next, start the timer by setting the T2CON bits as required. This enables the timer, but only once the T2CON bits have been latched internally in the Timer2 clock domain. Therefore, it is advised that a delay of more than three clock periods (that is, 100 μs for a 32 kHz timer clock source) is inserted to allow both the T2LD value and the T2CON value to be latched through the synchronization logic and reach the Timer2 domain. After the delay, it is recommended that any (inadvertent) Timer2 interrupts are now cleared using T2CLRI=0x00. Finally, the Timer2 system interrupt can be unmasked by setting the appro-priate bit in the IRQEN MMR. An example of this code is as follows, where the assumption is that Timer2 is halted: Example Code T2LD = 0x1; //Reload Timer T2CON = 0x02CF; //Enable T2—Low Power Osc, 32768 prescaler Delay(100us); //Include Delay to ensure T2CON bits take effect T2CLRI = 0 ; //*ClearTimerIrq IRQEN = WAKEUP_TIMER_BIT; //Unmask Timer2

value can be read from T0V AL0 and T0V AL1. timer value is copied to T0CAP , and the timer continues running. Timer0 reloads the value from T0LD when Timer0 overflows. register holding the 16-bit value that is loaded into the counter. mode, both 16-bit T0V AL0 and 32-bit T0V AL1 are used. clears the interrupt. T0CLRI is available only in 16-bit mode. T0CON is a configuration MMR and is described in Table 53. value) by user code to clear the interrupt. are read only registers. In 16-bit mode, 16-bit T0V AL0 is used. In 48-bit mode, both 16-bit T0V AL0 and 32-bit T0V AL1 are used. an enabled IRQ event. This register is available only in 16-bit mode. Figure 35. Timer0 Block Diagram

Function: This 32-bit MMR configures the mode of operation for Timer0. Table 53. T0CON MMR Bit Designations Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event select range (0 to 17). The events are as defined in Table 52. 01 = low power 32.768 kHz oscillator. 10 = external 32.768 kHz watch crystal. 11 = precision 32.768 kHz oscillator. 8 Count up. Available in 16-bit mode only. Set by user for Timer0 to count up. Cleared by user for Timer0 to count down (default). Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 0 = 16-bit operation (default). 0000 = source clock/1 (default).

imum resolution of 48.83 ns results. time expressed as hours:minutes:seconds:hundredths. determine the assertion of an event with increased accuracy. configuration MMR and is described in Table 54. is reached, Timer1 generates an interrupt if T1CON[18] is set. Timer1 reloads the value from T1LD when Timer1 overflows. of the assembly lot ID (0x00000000). by user code to clear the interrupt. Function: This 32-bit register holds the current value of Timer1. Figure 36. Timer1 Block Diagram

Table 54. T1CON MMR Bit Designations By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1. By reading these eight bits, the current value of the counter is read. 23 Timer1 enable postscaler. Set to enable the Timer1 postscaler. If enabled, interrupts are generated after T1CON[31:24] periods as defined by T1LD. Cleared to disable the Timer1 postscaler. 22 to 20 Reserved. These bits are reserved and should be written as 0 by user code. 19 Postscaler compare flag. Read only. Set if the number of Timer1 overflows is equal to the number written to the postscaler. Set to select interrupt generation from the postscaler counter. Cleared to select interrupt generation directly from Timer1. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event select range (0 to 17). The events are described in Table 52. 001 = low power 32.768 kHz oscillator. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down (default). Set by user to enable Timer1. Cleared by user to disable Timer1 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). 0000 = source clock/1 (default).

32.768 kHz watch crystal, or the precision 32.768 kHz oscillator. expressed as hours:minutes:seconds:hundredths. Timer2 reloads the value from T2LD when Timer2 overflows. MMR and is described in Table 55. by user code to clear the interrupt. Function: This 32-bit register holds the current value of Timer2. Figure 37. Timer2 Block Diagram

Function: This 16-bit MMR configures the mode of operation of Timer2. Table 55. T2CON MMR Bit Designations 01 = low power (32.768 kHz) oscillator. 10 = external 32.768 kHz watch crystal. 11 = precision 32.768 kHz oscillator. Set by user for Timer2 to count up. Cleared by user for Timer2 to count down (default). Set by user to enable Timer2. Cleared by user to disable Timer2 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). This is valid only with a 32 kHz clock. 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). This is valid only with a 32 kHz clock. 0000 = source clock/1 (default). format. See the 10 and 11 settings for the format bits (Bits[5:4]) in this table.

servicing to prevent it from forcing a reset of the processor. Timer3 reloads the value from T3LD when Timer3 overflows. a maximum prescaler/256 and full scale in T3LD. reloads the counter with T3LD and begins a new timeout period. should configure only a minimum timeout period of 30 ms. power-down. This can be disabled by setting Bit 0 in T3CON. timer continues to count during power-down. configuration MMR described in Table 56. Function: This 16-bit MMR holds the Timer3 reload value. mode to prevent a watchdog timer reset event. Figure 38. Timer3 Block Diagram

Function: The 16-bit MMR configures the Timer3 mode of operation as described in Table 56. Table 56. T3CON MMR Bit Designations 15 to 9 Reserved. These bits are reserved and should be written as 0 by user code. 8 Count up/count down enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. Set by user code to enable Timer3. Cleared by user code to disable Timer3. Set by user code to configure Timer3 to operate in periodic mode. Cleared by user code to configure Timer3 to operate in free running mode. 5 Watchdog timer mode enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. 4 Reserved. This bit is reserved and should be written as 0 by user code. 3 to 2 Timer3 clock (32.768 kHz) prescaler. 00 = source clock/1 (default). 1 Watchdog timer IRQ enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. Set by user code to stop Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR. Cleared by user code to enable Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR.

determine the assertion of an event with increased accuracy. MMR and is described in Table 57. by user code to clear the interrupt. Function: This 16-bit register holds the current value of Timer4. Figure 39. Timer4 Block Diagram

Table 57. T4CON MMR Bit Designations Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event select range (0 to 17). The events are described in Table 52. 1 = low power 32.768 kHz oscillator. Set by user for Timer4 to count up. Cleared by user for Timer4 to count down (default). Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 0000 = source clock/1 (default).

a source capability of 0.1 mA. Table 58. A typical GPIO structure is shown Figure 40. 1ONLY AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8. Figure 40. Typical GPIO Structure and GPIO_8. These interrupts are level triggered and active high. must be present until either IRQSTA or FIQSTA are interrogated. core clock to guarantee recognition.

• GPxDAT: Portx configuration and data register
• GPxSET: Portx data set
• GPxCLR: Portx data clear where x corresponds to the port number (0, 1, or 2). During normal operation, user code can control the function and state of the external GPIO pins using these general-purpose registers. All GPIO pins retain their external level (high or low) during power-down (POWCON) mode.

Table 58. External GPIO Pin to Internal Port Signal Assignments Port0 GPIO_0 P0.0 General-purpose I/O. IRQ0 External Interrupt Request 0. SS Slave select I/O for SPI. GPIO_1 P0.1 General-purpose I/O. SCLK Serial clock I/O for SPI. GPIO_2 P0.2 General-purpose I/O. MISO Master input, slave output for SPI. GPIO_3 P0.3 General-purpose I/O. MOSI Master output, slave input for SPI. GPIO_4 P0.4 General-purpose I/O. P 0.51 High voltage serial interface. P 0.61 High voltage serial interface. Port1 GPIO_5 P1.0 General-purpose I/O. IRQ1 External Interrupt Request 1. GPIO_6 P1.1 General-purpose I/O. Port2 GPIO_7 Port 2.0 General-purpose I/O. IRQ4 External Interrupt Request 4. LIN output pin2 Used to read directly from LIN pin for conformance testing. GPIO_8 P2.1 General-purpose I/O. IRQ5 External Interrupt Request 5. LIN HV input pin2 Used to directly drive LIN pin for conformance testing. GPIO_11 2 P2.42 General-purpose I/O. GPIO_12 2 P2.52 General-purpose I/O. GPIO_13 1 P2.6 1 General-purpose I/O; STI data output. readback (GPIO_11) capability.

Function: This 32-bit MMR selects the pin function for each Port0 pin. Table 59. GP0CON MMR Bit Designations 31 to 29 Reserved. These bits are reserved and should be written as 0 by user code. 28 Reserved. This bit is reserved and should be written as 1 by user code. 27 to 25 Reserved. These bits are reserved and should be written as 0 by user code. using the HVCON and HVDAT registered high voltage interface. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. using the HVCON and HVDAT registered high voltage interface. 19 to 17 Reserved. These bits are reserved and should be written as 0 by user code. 16 GPIO_4 function select bit. Set to 1 by user code to configure the GPIO_4 pin as ECLK, enabling a 2.56 MHz clock output on this pin. Cleared by user code to 0 to configure the GPIO_4 pin as a general-purpose I/O (GPIO) pin. 15 to 13 Reserved. These bits are reserved and should be written as 0 by user code. 12 GPIO_3 function select bit. Set to 1 by user code to configure the GPIO_3 pin as MOSI, master output, and slave input data for the SPI port. Cleared by user code to 0 to configure the GPIO_3 pin as a general-purpose I/O (GPIO) pin. 11 to 9 Reserved. These bits are reserved and should be written as 0 by user code. 8 GPIO_2 function select bit. Set to 1 by user code to configure the GPIO_2 pin as MISO, master input and slave output data for the SPI port. Cleared by user code to 0 to configure the GPIO_2 pin as a general-purpose I/O (GPIO) pin. 7 to 5 Reserved. These bits are reserved and should be written as 0 by user code. 4 GPIO_1 function select bit. Set to 1 by user code to configure the GPIO_1 pin as SCLK, serial clock I/O for the SPI port. Cleared by user code to 0 to configure the GPIO_1 pin as a general-purpose I/O (GPIO) pin. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_0 function select bit. Set to 1 by user code to configure the GPIO_0 pin as SS, serial clock I/O for the SPI port. Cleared by user code to 0 to configure the GPIO_0 pin as a general-purpose I/O (GPIO) pin.

Function: This 32-bit MMR selects the pin function for each Port1 pin. Table 60. GP1CON MMR Bit Designations 31 to 5 Reserved. These bits are reserved and should be written as 0 by user code. 4 GPIO_6 function select bit. Set to 1 by user code to configure the GPIO_6 pin as TxD, transmit data for UART serial port. Cleared by user code to 0 to configure the GPIO_6 pin as a general-purpose I/O (GPIO) pin. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_5 function select bit. Set by user code to 1 to configure the GPIO_5 pin as RxD. Receive data for UART serial port. Cleared by user code to 0 to configure the GPIO_5 pin as a general-purpose I/O (GPIO) pin.

Function: This 32-bit MMR selects the pin function for each Port2 pin. Table 61. GP2CON MMR Bit Designations 31 to 25 Reserved. These bits are reserved and should be written as 0 by user code. 24 GPIO_13 function select bit. Set to 1 by user code to route the STI data output to the STI pin. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. 20 GPIO_12 function select bit. Set to 1 by user code to route the UART TxD (transmit data) to the LIN/BSD data pin. This configuration is used in LIN mode. interface, and it can also be used to support diagnostic write capability to the high voltage I/O pins (see HVCFG1[2:0] in Table 75). 19 to 17 Reserved. These bits are reserved and should be written as 0 by user code. 16 GPIO_11 function select bit. and to the UART RxD (receive data). This mode must be configured by user code when using LIN or BSD modes. diagnostic readback on all external high voltage I/O pins (see HVCFG1[2:0] in Table 75). 15 to 5 Reserved. These bits are reserved and should be written as 0 by user code. 4 GPIO_8 function select bit. interface as a standalone component without any interaction from MCU or UART. Cleared by user code to 0 to configure the GPIO_8 pin as a general-purpose I/O (GPIO) pin. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_7 function select bit. Cleared by user code to 0 to configure the GPIO_7 pin as a general-purpose I/O (GPIO) pin.

value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 62. GP0DAT MMR Bit Designations 31 to 29 Reserved. These bits are reserved and should be written as 0 by user code. 28 Port 0.4 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 0.4 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.4 as an input. 27 Port 0.3 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 0.3 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.3 as an input. 26 Port 0.2 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 0.2 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.2 as an input. 25 Port 0.1 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 0.1 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.1 as an input. 24 Port 0.0 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 0.0 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 0.0 as an input. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. 20 Port 0.4 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.4. 19 Port 0.3 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.3. 18 Port 0.2 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.2. 17 Port 0.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.1. 16 Port 0.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 0.0. 15 to 5 Reserved. These bits are reserved and should be written as 0 by user code.

value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 63. GP1DAT MMR Bit Designations 31 to 26 Reserved. These bits are reserved and should be written as 0 by user code. 25 Port 1.1 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 1.1 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 1.1 as an input. 24 Port 1.0 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 1.0 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 1.0 as an input. 23 to 18 Reserved. These bits are reserved and should be written as 0 by user code. 17 Port 1.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 1.1. 16 Port 1.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 1.0. 15 to 2 Reserved. These bits are reserved and should be written as 0 by user code.

value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 64. GP2DAT MMR Bit Designations 31 Reserved. This bit is reserved and should be written as 0 by user code. 30 Port 2.6 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 2.6 as an output. 29 Port 2.5 direction select bit. diagnostic write capability to the high voltage I/O pins. Cleared to 0 by user code to configure the GPIO pin assigned to Port 2.5 as an input. 28 Port 2.4 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 2.4 as an output. diagnostic readback capability from the high voltage I/O pins (see HVCFG1[2:0]). 27 to 26 Reserved. These bits are reserved and should be written as 0 by user code. 25 Port 2.1 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 2.1 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 2.1 as an input. 24 Port 2.0 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port 2.0 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port 2.0 as an input. 23 Reserved. This bit is reserved and should be written as 0 by user code. 22 Port 2.6 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 2.6. 21 Port 2.5 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 2.5. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. 17 Port 2.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 2.1. 16 Port 2.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port 2.0. 15 to 7 Reserved. These bits are reserved and should be written as 0 by user code. 3 to 2 Reserved. These bits are reserved and should be written as 0 by user code.

Table 65. GP0SET MMR Bit Designations 31 to 21 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_4 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_4 pin. Set to 1 by user code to set the external GPIO_3 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_3 pin. Set to 1 by user code to set the external GPIO_2 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_2 pin. Set to 1 by user code to set the external GPIO_1 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_1 pin. Set to 1 by user code to set the external GPIO_0 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_0 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. Table 66. GP1SET MMR Bit Designations 31 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_6 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin. Set to 1 by user code to set the external GPIO_5 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

using the GP2SET MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP2DAT). Table 67. GP2SET MMR Bit Designations 31 to 23 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_13 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_13 pin. Set to 1 by user code to set the external GPIO_12 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_12 pin. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_8 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin. Set to 1 by user code to set the external GPIO_7 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. this using the GP0CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP0DAT). Table 68. GP0CLR MMR Bit Designations 31 to 21 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_4 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_4 pin. Set to 1 by user code to clear the external GPIO_3 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_3 pin. Set to 1 by user code to clear the external GPIO_2 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_2 pin. Set to 1 by user code to clear the external GPIO_1 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_1 pin. Set to 1 by user code to clear the external GPIO_0 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_0 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

this using the GP1CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP1DAT). Table 69. GP1CLR MMR Bit Designations 31 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_6 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin. Set to 1 by user code to clear the external GPIO_5 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. this using the GP2CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP2DAT). Table 70. GP2CLR MMR Bit Designations 31 to 23 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_13 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin. Set to 1 by user code to clear the external GPIO_12 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_8 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin. Set to 1 by user code to clear the external GPIO_7 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

via the HVCON and HVDAT MMRs. a read/write command is complete.

• Precision oscillator
• Wake-up (WU) pin functionality
• Power supply monitor (PSM)
• Low voltage flag (LVF)
• LIN operating modes
• STI diagnostics
• High voltage diagnostics
• High voltage attenuator buffers circuit
• High voltage (HV) temperature monitor ARM7 MCU AND PERIPHERALS HIGH VOLTAGE INTERFACE MMRs HVCON HVDAT PRECISION OSCILLATORHVCFG0[6] LVFHVCFG0[2] LIN MODES PSMHVCFG0[3] ATTENUATOR AND BUFFERHVCFG1[5] HVCFG1[7] HV TEMP MONITOR HVCFG1[6] HVCFG1[3] HVCFG0 (INDIRECT) HIGH VOLTAGE REGISTERS HVCFG1 HVSTA HVMON SERIAL INTERFACE CONTROLLER SERIAL DATA SERIAL CLOCK HIGH VOLTAGE INTERRUPT CONTROLLER PSM—HVSTA[5] WU—HVSTA[4] OVER TEMP—HVSTA[3] LIN S-SCT—HVSTA[2] STI S-SCT—HVSTA[1] WU S-SCT—HVSTA[0] IRQ3 (IRQEN[16]) HIGH VOLTAGE DIAGNOSTIC CONTROLLER WU DIAGNOSTIC INPUT HVCFG0[4] STI DIAGNOSTIC INPUT P2.6 LIN DIAGNOSTIC INPUT P2.5 WU DIAGNOSTIC OUTPUT HVMON[7] STI DIAGNOSTIC OUTPUT HVMON[5] LIN DIAGNOSTIC OUTPUT P2.4 HVCFG0[5] HVCFG0[1:0] WU I/O CONTROL HVCFG0[4] HVCFG1[4] HVCFG1[4] STI I/O CONTROL HVCFG1[3] 07474-038

Figure 41. High Voltage Interface, Top-Level Block Diagram

store data to be written to, or read back from, the indirect registers. Table 71. HVCON MMR Write Bit Designations 0x00 = read back High Voltage Register HVCFG0 into HVDAT. 0x01 = read back High Voltage Register HVCFG1 into HVDAT. 0x02 = read back High Voltage Status Register HVSTA into HVDAT. 0x03 = read back High Voltage Status Register HVMON into HVDAT. 0x08 = write the value in HVDAT to the High Voltage Register HVCFG0. 0x09 = write the value in HVDAT to the High Voltage Register HVCFG1. Table 72. HVCON MMR Read Bit Designations 2 Transmit command to high voltage die status. 1 = command completed successfully. 1 Read command from high voltage die status. 1 = command completed successfully. described in this table should not be written to HVCON unless busy = 0. Busy = 0, high voltage interface is not busy and has completed the command written to HVCON. Bit 1 and Bit 2 are valid.

Function: This 12-bit register holds data to be written indirectly to, and read indirectly from, the following high voltage interface registers. Table 73. HVDAT MMR Bit Designations 11 to 8 Command with which High Voltage Data HVDAT[7:0] is associated. These bits are read only and should be written as 0s. 0x00 = read back High Voltage Register HVCFG0 into HVDAT. 0x01 = read back High Voltage Register HVCFG1 into HVDAT. 0x02 = read back High Voltage Status Register HVSTA into HVDAT. 0x03 = read back High Voltage Status Register HVMON into HVDAT. 0x08 = write the value in HVDAT to the High Voltage Register HVCFG0. 0x09 = write the value in HVDAT to the High Voltage Register HVCFG1. 7 to 0 High voltage data to read/write.

HVDAT MMR, and data is read back from this register via the HVDAT MMR. Table 74. HVCFG0 Bit Designations 7 Wake-up/STI thermal shutdown disable. Set to 1 to disable the automatic shutdown of the wake-up/STI driver when a thermal event occurs. Cleared to 0 to enable the automatic shutdown of the wake-up/STI driver when a thermal event occurs. 6 Precision oscillator enable bit. voltage interface latency of 10 μs). Cleared to 0 to power down the precision 131 kHz oscillator. 5 Bit serial device (BSD) mode enable bit. Set to 1 to disable the internal (LIN) pull-up and configure the LIN/BSD pin for BSD operation. Cleared to 0 to enable the internal (LIN) pull-up resistor on the LIN/BSD pin. Set to 1 to assert the external WU pin high. Cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor. 3 Power supply monitor (PSM) enable bit. generates an interrupt if the voltage at the VDD pin drops below 6 V. Cleared to 0 to disable the power supply (voltage at the VDD pin) monitor. 2 Low voltage flag (LVF) enable bit. determine if the REG_DVDD voltage previously dropped below 2.1 V. Cleared to 0 to disable the LVF function. 1 to 0 LIN operating mode. These bits enable/disable the LIN driver. 01 = reserved (not LIN V2.0 compliant).

HVDAT, and data is read back from this register using HVDAT. Table 75. HVCFG1 Bit Designations 7 Voltage attenuator diagnostic enable bit. Set to 1 to turn on a 1.29 μA current source that adds 170 mV differential voltage to the voltage channel measurement. Cleared to 0 to disable the voltage attenuator diagnostic. negative temperature coefficient of typically −2.1 mV/°C. monitor is routed directly to the voltage channel ADC. Cleared to 0 to disable the on-chip, high voltage temperature monitor. 5 Voltage channel short enable bit. allow noise to be measured as a self-diagnostic test. Cleared to 0 to disable an internal short on the voltage channel. 4 WU and STI readback enable bit. monitored via the HVMON register (HVMON[7] and HVMON[5]). Cleared to 0 to disable input capability on the external WU and STI pins. 3 High voltage I/O driver enable bit. has passed) as well as reenabling the high voltage I/O pins. 2 Enable/disable short-circuit protection (LIN/BSD and STI). does not disable the short-circuiting pin. circuiting pin. When disabled, the I/O pin can only be reenabled by writing to HVCFG1[3]. 1 WU pin timeout (monoflop) counter enable/disable. Set to disable the WU I/O timeout counter. 0 WU open-circuit diagnostic enable. Cleared to disable an internal WU I/O diagnostic pull-up resistor.

Function: This 8-bit, read only register reflects the current status of enabled high voltage related circuits and functions on the ADuC7036. read back from this register via HVDAT. Table 76. HVMON Bit Designations 7 WU pin diagnostic readback. When enabled via HVCFG1[4], this read only bit reflects the state of the external WU pin. 0 = a thermal shutdown event has not occurred. 1 = a thermal shutdown event has occurred. 5 STI pin diagnostic readback. When enabled via HVCFG1[4], this read only bit reflects the state of the external STI pin. 0 = the voltage channel ADC input buffer is disabled. 1 = the voltage channel ADC input buffer is enabled. 3 Low voltage flag status bit. Valid only if enabled via HVCFG0[2]. 0 (at power-on) = REG_DVDD has dropped below 2.1 V. In this state, RAM contents can be deemed corrupt. cleared by reenabling the low voltage flag in HVCFG0[2]. 2 LIN/BSD short-circuit status flag. 0 = the LIN/BSD driver is operating normally. 1 = the LIN/BSD driver has experienced a short-circuit condition and is cleared automatically by writing to HVCFG1[3]. 1 STI short-circuit status flag. 0 = the STI driver is operating normally. 1 = the STI driver has experienced a short-circuit condition and is cleared automatically by writing to HVCFG1[3]. 0 Wake-up short-circuit status flag. 0 = the wake-up driver is operating normally. 1 = the wake-up driver has experienced a short-circuit condition.

automatically loads the current value of the high voltage status register (HVSTA) into the HVDAT register. Table 77. HVSTA Bit Designations 7 to 6 Reserved. These bits should not be used and are reserved for future use. 5 PSM status bit. Valid only if enabled via HVCFG0[3]. This bit is not latched and the IRQ needs to be enabled to detect it. 0 = the voltage at the VDD pin stays above 6 V. 1 = the voltage at the VDD pin drops below 6 V. 4 WU request status bit. Valid only if enabled via HVCFG1[4]. 0 = the WU pin has not generated a high voltage interrupt. 1 = a rising or falling edge transition on the WU pin generated a high voltage interrupt (when enabled via HVCFG1[4]). 3 Overtemperature. This bit is always enabled. 0 = a thermal shutdown event has not occurred. disabled once a thermal shutdown has occurred. 2 LIN/BSD short-circuit status flag. 0 = normal LIN/BSD operation. Cleared automatically by reading the HVSTA register. 1 = a LIN/BSD short circuit is detected. In this condition, the LIN driver is automatically disabled. 1 STI short-circuit status flag. 0 = normal STI driver operation. Cleared automatically by reading the HVSTA register. 1 = the STI driver has experienced a short-circuit condition. 0 Wake-up short-circuit status flag. 0 = normal wake-up operation. 1 = a wake-up short-circuit is detected.

internal 10 kΩ pull-down resistor and high-side FET driver. output by writing directly to HVCFG0[4]. the High Voltage Peripheral Control Interface section). a monoflop (that is, a 1.3 sec timeout timer) is included. driver should be disabled after 1.3 sec. a high voltage interrupt is generated, and HVMON[0] is set. 39 Ω) is above or below a typical voltage of 3 V . Figure 42. WU Circuit, Block Diagram

An interrupt controller is integrated with the high voltage circuits. (IRQ3) signal and interrupt the MCU core. after 10 μs to indicate the HVSTA contents are available in HVDAT. the appropriate action can be taken. disabling the LVF functionality using HVCFG0[2]. STI pins, as described in Table 78. Table 78. High Voltage Diagnostics more than 100 mA is continuously drawn. Drive LIN or STI high LIN or STI readback reads back low. Drive WU low Readback high in HVMON[7]. than 100 mA typically is sourced.

conversion on data characters received from the ARM7TDMI. GPIO_6/ TxD pins of the ADuC7036. options selectable in the configuration register. fractional divider baud rate generation. Table 79 lists common baud rate values. Table 79. Baud Rate Using the Standard Baud Rate Generator generator, allows the generation of accurate, high speed baud rates. Figure 43. Fractional Divider Baud Rate Generation an input by a nonwhole number, M.N. divides an input by a nonwhole number, M.N. Table 80 lists common baud rate values. Table 80. Baud Rate Using the Fractional Baud Rate Generator

Rev. C | Page 105 of 132 UART REGISTER DEFINITIONS The UART interface consists of the following registers:

• COMTX: 8-bit transmit register
• COMRX: 8-bit receive register
• COMDIV0: divisor latch (low byte)
• COMDIV1: divisor latch (high byte)
• COMCON0: line control register
• COMCON1: line control register
• COMSTA0: line status register
• COMIEN0: interrupt enable register
• COMIID0: interrupt identification register
• COMDIV2: 16-bit fractional baud divide register COMTX, COMRX, and COMDIV0 share the same address location. COMTX, COMIEN0, and COMRX can be accessed when Bit 7 in the COMCON0 register is cleared, and COMDIV0 and COMDIV1 can be accessed when Bit 7 of COMCON0 is set. UART Tx Register Name: COMTX Address: 0xFFFF0700 Access: Write only Function: Writing to this 8-bit register transmits data using the UART . UART Rx Register Name: COMRX Address: 0xFFFF0700 Default Value: 0x00 Access: Read only Function: This 8-bit register is read from to receive data transmitted using the UART. UART Divisor Latch Register 0 Name: COMDIV0 Address: 0xFFFF0700 Default Value: 0x00 Access: Read/write Function: This 8-bit register contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates. UART Divisor Latch Register 1 Name: COMDIV1 Address: 0xFFFF0704 Default Value: 0x00 Access: Read/write Function: This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates.

Function: This 8-bit register controls the operation of the UART in conjunction with COMCON1. Table 81. COMCON0 MMR Bit Designations 7 DLAB Divisor latch access. Set by user to enable access to COMDIV0 and COMDIV1. Set by user to force TxD to 0. Cleared to operate in normal mode. 5 SP Stick parity. Set by user to force parity to defined values. 4 EPS Even parity select bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. eight bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by the user to generate one stop bit in the transmitted data. 1 to 0 WLS Word length select. Function: This 8-bit register controls the operation of the UART in conjunction with COMCON0. Table 82. COMCON1 MMR Bit Designations 00 = RxD driven by LIN input; required for LIN communications using the LIN pin. 10 = RxD driven by GP5; required for serial communications using the GPIO_5/IRQ1/RxD pin (RxD). 4 LOOPBACK Loopback. Set by user to enable loopback mode. In loopback mode, the TxD is forced high.

Function: This 8-bit, read only register reflects the current status of the UART. Table 83. COMSTA0 MMR Bit Designations 6 TEMT COMTX and shift register empty status bit. transmitted; that is, no more data is present in the shift register. Cleared automatically by writing to COMTX. 5 THRE COMTX empty status bit. previous data may not have been transmitted yet and may still be present in the shift register. Cleared automatically by writing to COMTX. Set when SIN is held low for more than the maximum word length. Set when the stop bit is invalid. Set when a parity error occurs. Set automatically if data is overwritten before being read. Set automatically when COMRX is full.

Function: This 8-bit register enables and disables the individual UART interrupt sources. Table 84. COMIEN0 MMR Bit Designations 3 EDSSI Reserved. This bit should be written as 0. 2 ELSI RxD status interrupt enable bit. Set by the user to enable generation of an interrupt if any of the COMSTA0[3:1] register bits are set. 1 ETBEI Enable transmit buffer empty interrupt. 0 ERBFI Enable receive buffer full interrupt. Set by the user to enable an interrupt when the buffer is full during a reception. Function: This 8-bit register reflects the source of the UART interrupt. Table 85. COMIID0 MMR Bit Designations

Function: This 16-bit register controls the operation of the fractional divider for the ADuC7036. Table 86. COMDIV2 MMR Bit Designations 15 FBEN Fractional baud rate generator enable bit. Set by the user to enable the fractional baud rate generator. Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator. the M fractional divider and Table 80 for common baud rate values. and Table 80 for common baud rate values.

transmitted and received simultaneously, that is, full duplex. and consists of four pins that are multiplexed with four GPIOs. Table 88. SPI Speed vs. Clock Divider Bits in Master Mode Table 87. SPI Output Pins input line in master mode and as an output line in slave mode. as byte-wide (8-bit) serial data, MSB first. the master and slave devices. output line in master mode and as an input line in slave mode. as byte-wide (8-bit) serial data, MSB first. . In slave mode, SS is always an input. master mode and as an input in slave mode.

• SPICON: 16-bit control register
• SPISTA: 8-bit, read only status register
• SPIDIV: 8-bit, serial clock divider register
• SPITX: 8-bit, write only transmit register
• SPIRX: 8-bit, read only receive register

Function: This 16-bit MMR configures the serial peripheral interface. Table 89. SPICON MMR Bit Designations 12 Continuous transfer enable. the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty. exists in the SPITX register, a new transfer is initiated after a stall period. Set by the user to connect MISO to MOSI and test software. Cleared by the user to be in normal mode. Set by the user to enable the slave output. Cleared by the user to disable the slave output. 9 Slave select input enable. Set by the user in master mode to enable the output. Cleared by the user to disable the output. 8 SPIRX overflow overwrite enable. Set by the user; the valid data in the SPIRX register is overwritten by the new serial byte received. Cleared by the user; the new serial byte received is discarded. Set by the user to transmit the previous data. Cleared by the user to transmit 0. 6 Transfer and interrupt mode (master mode). Set by the user to initiate a transfer with a write to the SPITX register. An interrupt occurs when SPITX is empty. Cleared by the user to initiate a transfer with a read of the SPIRX register. An interrupt occurs when SPIRX is full. 5 LSB first transfer enable bit. Set by the user; the LSB is transmitted first. Cleared by the user; the MSB is transmitted first. 3 Serial clock polarity mode bit. Set by the user; the serial clock idles high. Cleared by the user; the serial clock idles low. 2 Serial clock phase mode bit. Set by the user; the serial clock pulses at the beginning of each serial bit transfer. Cleared by the user; the serial clock pulses at the end of each serial bit transfer. Set by the user to enable master mode. Cleared by the user to enable slave mode. Set by the user to enable the SPI. Cleared by the user to disable the SPI.

serial peripheral interface. Table 90. SPISTA MMR Bit Designations 5 SPIRX data register overflow status bit. Set if SPIRX is overflowing. Cleared by reading the SPIRX register. Set automatically if Bit 3 or Bit 5 is set. Cleared by reading the SPIRX register. 3 SPIRX data register full status bit. Cleared by reading the SPIRX register. 2 SPITX data register underflow status bit. Set automatically if SPITX is underflowing. Cleared by writing in the SPITX register. Set automatically if Bit 0 is cleared or Bit 2 is set. transmission is finished, by disabling the SPI. 0 SPITX data register empty status bit. during transmission of data. Cleared when SPITX is empty. serial peripheral interface. serial peripheral interface. on the calculation of the baud rate, refer to Equation 3.

diagnostics on finished production units. the baud rate is determined by the overflow rate of Timer4. The STI port is configured and controlled via six MMRs.

• STIKEY0: Serial Test Interface Key0
• STIKEY1: Serial Test Interface Key1
• STIDAT0: Data0 (16-bit) holds two bytes
• STIDAT1: Data1 (16-bit) holds two bytes
• STIDAT2: Data2 (16-bit) holds two bytes
• STICON: controls the serial test interface Serial Test Interface Key0 Register Name: STIKEY0 Address: 0xFFFF0880 Access: Write only Function: The STIKEY0 MMR is used in conjunction with the STIKEY1 MMR to protect the STICON MMR. STIKEY0 must be written with 0x0007 immediately before any attempt to write to STICON. STIKEY1 must be written with 0x00B9 immedi- ately after STICON is written to ensure the STICON write sequence completes successfully. If STIKEY0 is not written, is written out of sequence, or is written incorrectly, any subsequent write to the STICON MMR is ignored. Serial Test Interface Key1 Register Name: STIKEY1 Address: 0xFFFF0888 Access: Write only Function: The STIKEY1 MMR is used in conjunction with the STIKEY0 MMR to protect the STICON MMR. STIKEY1 must be written with 0x00B9 immediately after any attempt to write to STICON. STIKEY0 must be written with 0x0007 immediately before STICON is written to ensure the STICON write sequence complets successfully. If STIKEY1 is not written, is written out of sequence, or is written incorrectly, any previous write to the STICON MMR is ignored. Serial Test Interface Data0 Register Name: STIDAT0 Address: 0xFFFF088C Default Value: 0x0000 Access: Read/write Function: The STIDAT0 MMR is a 16-bit register that holds the first and second data bytes that are to be transmitted on the STI pin as soon as the STI port is enabled. The first byte to be transmitted occupies Bits[0:7], and the second byte occupies Bits[8:15]. Serial Test Interface Data1 Register Name: STIDAT1 Address: 0xFFFF0890 Default Value: 0x0000 Access: Read/write Function: The STIDAT1 MMR is a 16-bit register that holds the third and fourth data bytes that are to be transmitted on the STI pin when the STI port is enabled. The third byte to be transmitted occupies Bits[0:7], and the fourth byte occupies Bits[8:15]. Serial Test Interface Data2 Register Name: STIDAT2 Address: 0xFFFF0894 Default Value: 0x0000 Access: Read/write Function: The STIDAT2 MMR is a 16-bit register that is used to hold the fifth and sixth data bytes that are to be transmitted on the STI pin when the STI port is enabled. The fifth byte to be transmitted occupies Bits[0:7], and the sixth byte occupies Bits[8:15]. PARITY BIT START BIT STI BYTE0 STI BYTE1 STI BYTE2 PARITY BIT WITH TWO STOP BITS 07474-041

Figure 44. Serial ADC Test Interface Example, 3-Byte Transmission

STIKEY0 MMR is written with 0x0007.

1. The sequence is completed by writing 0x00B9 to STIKEY1.

Function: The STI Control MMR is an 16-bit register that configures the mode of operation of the serial test interface. Note that the GPIO_13 must be configured for STI operation in GP2CON for STI communications. Table 91. STICON MMR Bit Designations 15 to 9 Reserved. These bits are reserved for future use and should be written as 0 by user code. 8 to 5 State bits, read only. If the interface is in the middle of a transmission, these bits are not 0. write the bytes to be transmitted into the STIDAT0, STIDAT1, and STIDAT2 MMRs. 1 Reset serial test interface. 1 = resets the serial test interface. A subsequent read of STICON returns all 0s. 0 = operates in normal mode (default). 0 Serial test interface enable. This bit is set by user code. 1 = enables the serial test interface. 0 = disables the serial test interface.

Figure 45. STI Output Structure

• Configure Timer4 for baud rate generation.
• Correctly enable STICON using STIKEY0 and STIKEY1 for secure access.
• Required bytes to be transmitted are written into STIDAT0, STIDAT1, and STIDAT2. Timer4 is configured with the correct load value to generate an overflow at the required baud rate. If the STI port is being used to transmit ADC conversion results, the baud rate must be suffi- cient to output each ADC result (16-bits) before the next ADC conversion result is available. For example, if the ADC is sampling at 1 kHz, the baud rate must be sufficient to output 36 bits as follows: (3 × 8 bits (16-bit ADC result and a checksum byte, for example)) + (3 × 1 start bit) + (3 × 1 parity bit) + (3 × 2 stop bits) = 36 bits. Therefore, the serial test interface must transmit data at greater than 36 kbps. The closest standard baud rate is 38.4 kbps; as such, the reload value written to the Timer4 load MMR (T4LD) is 0x0106 (267 decimal). This value is based on a prescaler of 1 and is calculated as follows, using a core clock of 10.24 MHz: 267kbps 4 . 38 MHz 24 . 10=== Rate BaudDesired FrequencyClock CoreT4LD When the Timer4 load value is written and the timer itself is configured and enabled using the T4CON MMR, the STI port must be configured. This is accomplished by writing to the STICON MMR in a specific sequence using the STIKEY0 and STIKEY1 MMRs as described in the previous sections. Finally, the STI port does not begin transmission until the required number of transmit bytes are written into the STIDATx MMRs. As soon as STI starts transmitting, the value in the STICON MMR changes from the value initially written to this register. User code can ensure that all data is transmitted by continuously polling the STICON MMR until it reverts back to the value originally written to it. To disable the serial interface, user code must write a 0 to STICON[0]. Example Code An example code segment configuring the STI port to transmit five bytes and then to transmit two bytes follows: T4LD = 267; // Timer4 reload value T4CON = 0xC0; // Enable T4, selecting core clock in periodic mode STIKEY0 = 07; // STICON start write sequence STICON = 0x11; // Enable and transmit five bytes STIKEY1 = 0xb9; // STICON complete write STIDAT0 = 0xAABB; // Five bytes for STIDAT1 = 0xCCDD; // transmission STIDAT2 = 0xFF; while(STICON != 0x09) // Wait for transmission to complete STIKEY0 = 07; // STICON start write sequence STICON = 0x05; // Enable and transmit two bytes STIKEY1 = 0xb9; // STICON complete write STIDAT0 = 0xEEFF; // Two bytes for transmission while(STICON != 0x09) // Wait for transmission to complete

to 20 kBaud, and it is compatible with the LIN 2.0 standard. the PLL is used for the synchronous byte timing.

• LHSSTA: LHS status register. This MMR contains infor- mation flags that describe the current status on the interface.
• LHSCON0: LHS Control Register 0. This MMR controls the configuration of the LHS timer.
• LHSCON1: LHS start and stop edge control register. This MMR dictates on which edge of the LIN synchronization byte the LHS starts/stops counting.
• LHSV AL0: LHS synchronization 16-bit timer. This MMR is controlled by LHSCON0.
• LHSV AL1: LHS break timer register. GPIO_12 FUNCTION SELECT GP2CON[20] GPIO_12 GP2DAT[29] AND GPSDAT[21] UART LHS HARDWARE RxD TxD BPF INTERNAL SHORT-CIRCUIT TRIP REFERENCE INTERNAL SHORT-CIRCUIT SENSE RESISTORSHORT-CIRCUIT CONTROL HVCFG1[2] OUTPUT DISABLE LIN MODE HVCFG0[1:0] INPUT VOLTAGE THRESHOLD REFERENCE LIN ENABLE (INTERNAL PULL-UP) HVCFG0[5] FOUR LIN INTERRUPT SOURCES: BREAK LHSSTA[0] START LHSSTA[1] STOP LHSSTA[2] BREAK ERROR LHSSTA[4] VDD RxD ENABLE LHSCON0[8] LHSVAL0 LHSVAL1 LHS INTERRUPT IRQEN[7] 5MHz 131kHz LHS INTERRUPT LOGIC VDD SCR IO_VSS OVERVOLTAGE PROTECTION EXTERNAL LIN PIN MASTER ECU PROTECTION DIODE MASTER ECU PULL-UP C LOAD 07474-043

Figure 46. LIN I/O Block Diagram

Function: This LHS status register is a 32-bit register whose bits reflect the current operating status of the LIN interface. Table 92. LHSSTA MMR Bit Designations 31 to 7 Reserved. These read only bits are reserved for future use. 6 Rising edge detected (BSD mode only). Set to 1 by hardware to indicate a rising edge has been detected on the BSD bus. Cleared to 0 after user code reads the LHSSTA MMR. Set to 1 by hardware to indicate an LHS reset command has completed successfully. Cleared to 0 after user code reads the LHSSTA MMR. overflows to indicate the LIN bus has stayed low too long, thus indicating a possible LIN bus error. Cleared to 0 after user code reads the LHSSTA MMR. Set to 1 by hardware when the value in LHSVAL0 (LIN synchronization bit timer) equals the value in the LHSCMP register. Cleared to 0 after user code reads the LHSSTA MMR. Set to 1 by hardware when a stop condition is detected. Cleared to 0 after user code reads LHSSTA MMR. 1 Start condition interrupt. Set to 1 by hardware when a start condition is detected. Cleared to 0 after user code reads LHSSTA MMR. 0 Break timer compare interrupt. Timer1 Register section for more information). Cleared to 0 after user code reads the LHSSTA MMR.

Function: This 16-bit LHS control register, in conjunction with the LHSCON1 register, is used to configure the LIN mode of operation. Table 93. LHSCON0 MMR Bit Designations 15 to 13 Reserved. These bits are reserved for future use and should be written as 0 by user software. 12 Rising edge detected interrupt disable. BSD mode Set to 1 to disable the rising edge detected interrupt. Cleared to 0 to enable the break rising edge detected interrupt. LIN mode Set to 1 to enable the rising edge detected interrupt. Cleared to 0 to disable the break rising edge detected interrupt. 11 Break timer compare interrupt disable. Set to 1 to disable the break timer compare interrupt. Cleared to 0 to enable the break timer compare interrupt. 10 Break timer error interrupt disable. Set to 1 to disable the break timer error interrupt. Cleared to 0 to enable the break timer error interrupt. 9 LIN transceiver, standalone test mode. the GPIO_7 Function Select Bit 0 and GPIO_8 Function Select Bit 4 in the GP2CON register. Cleared to 0 by user code to operate the LIN in normal mode, it is driven directly from the on-chip UART. subsequent LIN sync byte have been detected so that the UART can receive the subsequent LIN data fields. read value) equals the break timer compare value (LHSVAL1 write value), and if the break timer overflows. This configuration can be used in BSD read mode to detect fault conditions on the BSD bus. width in transmitted data bits. 7 Sync timer stop edge type bit. Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register. Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4] register. Set to 1 by user code to select BSD mode of operation. Cleared to 0 by user code to select LIN mode of operation.

5 Enable compare interrupt bit. configuration is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be transmitted. Cleared to 0 by user code to disable compare interrupts. Set to 1 by user code to generate an interrupt when a stop condition occurs. Cleared to 0 by user code to disable interrupts when a stop condition occurs. Set to 1 by user code to generate an interrupt when a start condition occurs. Cleared to 0 by user code to disable interrupts when a start condition occurs. Set to 1 by user code to enable LHS functionality. Cleared to 0 by user code to disable LHS functionality. Set to 1 by user code to clear the internal edge counters in the LHS peripheral. Cleared automatically to 0 after a 15 μs delay. Set to 1 by user code to reset all LHS logic to default conditions. Cleared automatically to 0 after a 15 μs delay. stop condition interrupt can be used to ensure that this scenario is avoided. Function: This 32-bit LHS control register, in conjunction with the LHSCON0 register, is used to configure the LIN mode of operation. Table 94. LHSCON1 MMR Bit Designations 31 to 8 Reserved. These bits are reserved for future use and should be written as 0 by user software. edge. Note that the first falling edge is considered to be the falling edge at the start of the LIN break pulse.

register contents being reset to 0. not to the LIN break timer but to a LIN break compare register. timing through the LHSV AL0 register does not occur. break symbol, sync byte, protected identifier, and data bytes. support and manage LIN-based transmissions and receptions. Synchronization Status Register section. Figure 50. The protected identifier consists of two subfields: the number of bytes is user configurable at the system-level design. the revision of LIN for which the system is designed. The data byte frame carries between one and eight bytes of data.

in this case 0x3F, a break compare interrupt is generated. that the UART is configured to receive the protected identifier. of this process follows Figure 49. Figure 52. Example LIN Configuration

Rev. C | Page 123 of 132 LIN Diagnostics The ADuC7036 features the capability to nonintrusively monitor the current state of the LIN/BSD pin. This readback functionality is implemented using GPIO_11. The current state of the LIN/BSD pin is contained in GP2DAT[4]. It is also possible to drive the LIN/BSD pin high and low through user software, allowing the user to detect open-circuit conditions. This functionality is implemented via GPIO_12. To enable this functionality, GPIO_12 must be configured as a GPIO through GP2CON[20]. After it is configured, the LIN/BSD pin can be pulled high or low using GP2DAT. The ADuC7036 also features short-circuit protection on the LIN/BSD pin. If a short-circuit condition is detected on the LIN/BSD pin, HVSTA[2] is set. This bit is cleared by reenabling the LIN driver using HVCFG1[3]. It is possible to disable this feature through HVCFG1[2]. LIN Operation During Thermal Shutdown When a thermal event occurs, that is, when HVSTA[3] is set, LIN communications continue uninterrupted.

nication occurs at 1200 bps ± 3%. Table 95. BSD Bit Level Description all of which are under software control. Figure 53. BSD I/O Hardware Interface

Rev. C | Page 125 of 132 BSD RELATED MMRS The ADuC7036 emulates the BSD communication protocol using a software (bit bang) interface with some hardware assis- tance form LIN hardware synchronization logic. In effect, the ADuC7036 BSD interface uses the following protocols:

• An internal GPIO signal (GPIO_12) that is routed to the external LIN/BSD pin and is controlled directly by software to generate 0s and 1s.
• When reading bits, the LIN synchronization hardware uses LHSV AL1 to count the width of the incoming pulses so that user code can interpret the bits as sync, 0, or 1.
• When writing bits, user code toggles a GPIO pin and uses the LHSCAP and LHSCMP registers to time pulse widths and generate an interrupt when the BSD output pulse width has reached its required width. The ADuC7036 MMRs required for BSD communication are as follows:
• LHSSTA: LIN hardware synchronization status register
• LHSCON0: LIN hardware synchronization control register
• LHSVAL0: LIN hardware synchronization Timer0 (16-bit timer)
• LHSCON1: LIN hardware synchronization edge setup register
• LHSV AL1: LIN hardware synchronization break timer
• LHSCAP: LIN hardware synchronization capture register
• LHSCMP: LIN hardware synchronization compare register
• IRQEN/IRQCLR: enable interrupt register
• FIQEN/FIQCLR: enable fast interrupt register
• GP2DAT: GPIO Port 2 data register
• GP2SET: GPIO Port 2 set register
• GP2CLR: GPIO Port 2 clear register Detailed bit definitions for most of these MMRs have been listed previously. In addition to the registers described in the LIN MMR Description section, LHSCAP and LHSCMP are registers that are required for the operation of the BSD interface. Details of these registers follow. LIN Hardware Synchronization Capture Register Name: LHSCAP Address: 0xFFFF0794 Default Value: 0x0000 Access: Read only Function: This 16-bit, read only register holds the last captured value of the internal LIN synchronization timer (LHSV AL0). In BSD mode, LHSV AL0 is clocked directly from an internal

5 MHz clock, and its value is loaded into the capture register on

every falling edge of the BSD bus. LIN Hardware Synchronization Compare Register Name: LHSCMP Address: 0xFFFF0798 Default Value: 0x0000 Access: Read/write Function: This register is used to time BSD output pulse widths. When enabled through LHSCON0[5], a LIN interrupt is generated when the value in LHSCAP equals the value written in LHSCMP . This functionality allows user code to determine how long a BSD transmission bit (sync, 0, or 1) should be asserted on the bus.

transmissions in the 0 or 1 state. captured in LHSCAP on every falling edge of the BSD bus. The LIN sync timer runs continuously in BSD mode. generates an LHS compare interrupt (LHSSTA[3]). Figure 57. BSD Slave Node State Machine

1 SOFTWARE ASSERTS

section) generates an interrupt on the rising edge of the BSD bus. to determine if the received data bit is a BSD sync pulse, 0, or 1. Figure 59. Master Read, Slave Transmit pin generates an interrupt event and wakes up the MCU core.

1 LHSVAL1 STOPPED

Figure 58. Master Transmit, Slave Read

SYSSER1 MMR (see Table 98 and Table 99 for more information). power-up that can identify the ADuC7036 family member. in the T1LD MMR at power-up. T1LD allows full traceability of each part. Table 97. Branding Example this part to be traced (bottom die only). Table 98. SYSSER0 MMR Bit Designations this device originated). When used in conjunction with SYSSER0[26:0], it provides individual wafer traceability. 26 to 22 Wafer lot fabrication plant. The five bits read from this location reflect the manufacturing plant associated with this wafer lot. When this information is used in conjunction with SYSSER0[21:0], it provides wafer lot traceability. conjunction with SYSSER0[26:22] and SYSSER0[15:0], provide wafer lot traceability. used in conjunction with the value in SYSSER1, that is, the manufacturing lot ID, this number is a unique identifier for the part.

number (bottom die only), as detailed in Table 99. Table 99. SYSSER1 MMR Bit Designations should be interpreted as A, indicating a Revision A kernel is on chip. 19 to 16 Reserved. For prerelease samples, these bits refer to the kernel minor revision number of the device. value in SYSSER0 (that is, the manufacturing lot ID), this number is a unique identifier for the part.

Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEE0CON acts. Note that this MMR is also used to identify the ADuC7036 family member and prerelease silicon revision. Table 100. FEE0ADR System Identification MMR Bit Designations

system meets any EMC and other overvoltage/overcurrent compliance requirements. Figure 60. Simplified Schematic

0.50 BSC

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

0.60 MAX PIN 1

0.25 MIN

Figure 61. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the property of their respective owners.