ADUC7034

ADuC7034 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 136

Technical content

Integrated Precision Battery Sensor for Automotive ADuC7034 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.

FEATURES

Dual channel, simultaneous sampling, 16-bit Σ-Δ ADCs Programmable ADC throughput from 1 Hz to 8 kHz On-chip 5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable gain from 1 to 512 ADC input range: −200 mV to +300 mV Digital comparators with current accumulator feature Voltage channel Buffered, on-chip attenuator for 12 V battery inputs Temperature channel External and on-chip temperature sensor options Microcontroller ARM7TDMI core, 16-/32-bit RISC architecture

20.48 MHz PLL with programmable divider

On-chip precision oscillator On-chip low power oscillator External (32.768 kHz) watch crystal JTAG port supports code download and debug Memory 32 kB Flash/EE memory, 4 kB SRAM 10,000-cycle Flash/EE endurance, 20-year Flash/EE retention In-circuit download via JTAG and LIN On-chip peripherals SAEJ2602/LIN 2.0-compatible (slave) support via UART with hardware synchronization Flexible wake-up I/O pin, master/slave SPI serial I/O 9-pin GPIO port, 3× general-purpose timers Wake-up and watchdog timers Power supply monitor and on-chip power-on reset Power Operates directly from 12 V battery supply Current consumption Normal mode 10 mA at 10 MHz Low power monitor mode Package and temperature range 48-lead, 7 mm × 7 mm LFCSP Fully specified for −40°C to +115°C operation

APPLICATIONS

Battery sensing/management for automotive systems FUNCTIONAL BLOCK DIAGRAM PRECISION ANALOG ACQUISITION BUF RESULT ACCUMULATOR DIGITAL COMPARATOR TEMPERATURE SENSOR VDD VREF VTEMP VBAT IIN– IIN+ PRECISION REFERENCE PGA 2.6V LDO PSM POR ARM7TDMI MCU 20MHz 3× TIMERS WDT WU TIMER MEMORY 32kB FLASH 4kB RAM ADuC7034 PRECISION OSC LOW POWER OSC ON-CHIP PLL GPIO PORT UART PORT SPI PORT LIN MUX BUF 16-BIT Σ-Δ ADC 16-BIT Σ-Δ ADC REG_AVDD REG_DVDD AGND DGND VSS IO_VSS GPIO_2 GPIO_3 GPIO_1 GPIO_0 GPIO_4 TDO NTRST TDI TCK TMS GPIO_5 GPIO_6 GPIO_7 GPIO_8 RESET WU STI LIN/BSD XTAL1 XTAL2 07116-001 Figure 1.

Rev. B | Page 2 of 136 TABLE OF CONTENTS Synchronization of timers Across Asynchronous Clock Handling Interrupts from the High Voltage Peripheral

Rev. B | Page 3 of 136

REVISION HISTORY

5/10—Rev. A to Rev. B 8/09—Rev. 0 to Rev. A 4/08—Revision 0: Initial Version

Rev. B | Page 4 of 136 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.5 V to 18 V , VREF = 1.2 V internal reference, fCORE = 10.24 MHz driven from external 32.768 kHz watch crystal or on-chip precision oscillator, all specifications TA = −40°C to +115°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ADC SPECIFICATIONS Conversion Rate1 Chop off, ADC normal operating mode 4 8000 Hz Chop on, ADC normal operating mode 4 2600 Hz Chop on, ADC low power mode 1 650 Hz Current Channel No Missing Codes1 Valid for all ADC update rates and ADC modes 16 Bits Integral Nonlinearity1, 2 ±10 ±60 ppm of FSR Offset Error2, 3, 4, 5 Chop off, 1 LSB = 36.6 μV/gain −10 ±3 +10 LSB Offset Error1, 3, 6 Chop on −2 ±0.5 +2 μV Offset Error1, 3 Chop on, low power mode or low power plus mode, MCU powered down +100 −50 −300 nV Offset Error1, 3 Chop on, normal mode, CD = 1 +0.5 −1.25 −3 μV Offset Error Drift6 Chop off, valid for ADC gains of 4 to 64, normal mode

0.03 LSB/°C

Offset Error Drift6 Chop off, valid for ADC gains of 128 to 512, normal mode 30 nV/°C Offset Error Drift6 Chop on 10 nV/°C Total Gain Error1, 3, 7, 8, 9, 10 Normal mode −0.5 ±0.1 +0.5 % Total Gain Error1, 3, 7, 9 Low power mode using ADCREF MMR −4 ±0.2 +4 % Total Gain Error1, 3, 7, 9, 11 Low power plus mode, using precision VREF −1 ±0.2 +1 % Gain Drift 3 ppm/°C PGA Gain Mismatch Error ±0.1 % Output Noise1, 12 4 Hz update rate, gain = 512, ADCFLT = 0xBF1D 60 90 nV rms

4 Hz update rate, gain = 512, ADCFLT = 0x3F1D 75 115 nV rms

10 Hz update rate, gain = 512, ADCFLT =

1 kHz update rate, gain ≥ 64, ADCFLT = 0x8101 0.8 1.2 μV rms 1 kHz update rate, gain ≥ 64, ADCFLT = 0x0101 1 1.5 μV rms 1 kHz update rate, gain = 512, ADCFLT = 0x0007 0.6 0.9 μV rms 1 kHz update rate, gain = 32, ADCFLT = 0x0007 0.8 1.2 μV rms 1 kHz update rate, gain = 8, ADCFLT = 0x8101 2.1 4.1 μV rms 1 kHz update rate, gain = 8, ADCFLT = 0x0007 1.6 2.4 μV rms 1 kHz update rate, gain = 8, ADCFLT = 0x0101 2.6 3.9 μV rms 1 kHz update rate, gain = 4, ADCFLT = 0x0007 2.0 2.8 μV rms 8 kHz update rate, gain = 32, ADCFLT = 0x0000 2.5 3.5 μV rms 8 kHz update rate, gain = 4, ADCFLT = 0x0000 14 21 μV rms ADC low power mode, fADC = 10 Hz, gain = 128 1.25 1.9 μV rms ADC low power mode, fADC = 1 Hz, gain = 128 0.35 0.5 μV rms ADC low power plus mode, fADC = 1 Hz, gain = 512 0.1 0.15 μV rms ADC low power plus mode, fADC = 250 Hz, gain = 512, chop enabled 0.6 0.9 μV rms

Rev. B | Page 5 of 136 Parameter Test Conditions/Comments Min Typ Max Unit Voltage Channel13 No Missing Codes1 Valid at all ADC update rates 16 Bits Integral Nonlinearity1 ±10 ±60 ppm of FSR Offset Error3, 5 Chop off, 1 LSB = 439.5 μV −10 ±1 +10 LSB Offset Error1, 3 Chop on 0.3 1 LSB Offset Error Drift Chop off 0.03 LSB/°C Total Gain Error1, 3, 7, 10, 14 Includes resistor mismatch −0.25 ±0.06 +0.25 % Total Gain Error1, 3, 7, 10, 14 Temperature range = −25°C to +65°C −0.15 ±0.03 +0.15 % Gain Drift Includes resistor mismatch drift 3 ppm/°C Output Noise1, 15 4 Hz update rate, ADCFLT = 0xBF1D 60 90 μV rms

10 Hz update rate, ADCFLT = 0x961F 60 90 μV rms

1 kHz update rate, ADCFLT = 0x0007 180 270 μV rms 1 kHz update rate, ADCFLT = 0x8101 240 307 μV rms 1 kHz update rate, ADCFLT = 0x0101 270 405 μV rms 8 kHz update rate, ADCFLT = 0x0000 1600 2400 μV rms Temperature Channel No Missing Codes1 Valid at all ADC update rates 16 Bits Integral Nonlinearity1 ±10 ±60 ppm of FSR Offset Error3, 4, 5, 16 Chop off, 1 LSB = 19.84 μV in unipolar mode −10 ±3 +10 LSB Offset Error1, 3 Chop on −5 +1 +5 LSB Offset Error Drift Chop off 0.03 LSB/°C Total Gain Error1, 3, 14 −0.2 ±0.06 +0.2 % Gain Drift 3 ppm/°C Output Noise1 1 kHz update rate 7.5 11.25 μV rms ADC SPECIFICATIONS ANALOG INPUT Internal VREF = 1.2 V Current Channel Absolute Input Voltage Range Applies to both IIN+ and IIN− −200 +300 mV Input Voltage Range17, 18 Gain = 119 ±1.2 V Gain = 219 ±600 mV Gain = 419 ±300 mV Gain = 8 ±150 mV Gain = 16 ±75 mV Gain = 32 ±37.5 mV Gain = 64 ±18.75 mV Gain = 128 ±9.375 mV Gain = 256 ±4.68 mV Gain = 512 ±2.3 mV Input Leakage Current1 −3 +3 nA Input Offset Current1, 20 0.5 1.5 nA Voltage Channel Absolute Input Voltage Range 4 18 V Input Voltage Range 0 to 28.8 V VBAT Input Current VBAT = 18 V 3 5.5 8 μA Temperature Channel Reference selection: REG_AVDD/2 to GND_SW/2 Absolute Input Voltage Range 100 1300 mV Input Voltage Range 0 to VREF V VTEMP Input Current1 2.5 160 nA

Rev. B | Page 6 of 136 Parameter Test Conditions/Comments Min Typ Max Unit VOLTAGE REFERENCE ADC Precision Reference Internal VREF 1.2 V Power-Up Time1 0.5 ms Initial Accuracy1 Measured at TA = 25°C −0.15 +0.15 % Temperature Coefficient1, 21 −20 ±5 +20 ppm/°C Reference Long-Term Stability22 100 ppm/1000 hr External Reference Input Range23 0.1 1.3 V VREF Divide-by-2 Initial Error1 0.1 0.3 % ADC Low Power Reference Internal VREF 1.2 V Initial Accuracy Measured at TA = 25°C −5 +5 % Initial Accuracy1 Using ADCREF , measured at TA = 25°C 0.1 % Temperature Coefficient1, 21 −300 ±150 +300 ppm/°C ADC DIAGNOSTICS VREF/1361 At any gain settings 8.5 9.4 mV Voltage Attenuator Current Source1 Differential voltage increase on the attenuator when the current source is on, over a range of TA = −40°C to +85°C 3.1 3.8 V RESISTIVE ATTENUATOR Divider Ratio 24 Resistor Mismatch Drift 3 ppm/°C ADC GROUND SWITCH Resistance Direct path to ground 10 Ω 20 kΩ resistor selected1 10 20 30 kΩ Input Current Allowed continuous current through the switch with direct path to ground 6 mA TEMPERATURE SENSOR24 After user calibration Accuracy MCU in power-down or standby mode ±3 °C MCU in power-down or standby mode, temperature range = −25°C to +65°C ±2 °C POWER-ON RESET (POR) POR Trip Level Refers to the voltage at the VDD pin 2.85 3.0 3.15 V POR Hysteresis 300 mV Reset Timeout from POR 20 ms LOW VOLTAGE FLAG (LVF) LVF Level Refers to the voltage at the VDD pin 1.9 2.1 2.3 V POWER SUPPLY MONITOR (PSM) PSM Trip Level Refers to the voltage at the VDD pin 6.0 V WATCHDOG TIMER (WDT) Timeout Period1 32.768 kHz clock, 256 prescale 0.008 512 sec Timeout Step Size 7.8 ms FLASH/EE MEMORY1 Endurance25 10,000 Cycles Data Retention26 20 Years DIGITAL INPUTS All digital inputs except NTRST Input Leakage Current Input high = REG_DVDD ±1 ±10 μA Input Pull-Up Current Input low = 0 V −80 −20 −10 μA Input Capacitance 10 pF Input Leakage Current NTRST only: input low = 0 V ±1 ±10 μA Input Pull-Down Current NTRST only: input high = REG_DVDD 30 55 100 μA

Rev. B | Page 7 of 136 Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS1 All logic inputs Input Low Voltage (VINL) 0.4 V Input High Voltage (VINH) 2.0 V CRYSTAL OSCILLATOR1 Logic Inputs, XTAL1 Only Input Low Voltage (VINL) 0.8 V Input High Voltage (VINH) 1.7 V XTAL1 Capacitance 12 pF XTAL2 Capacitance 12 pF ON-CHIP OSCILLATORS Low Power Oscillator 131.072 kHz Accuracy27 Includes drift data from 1000 hour life test −3 +3 % Precision Oscillator 131.072 kHz Accuracy Includes drift data from 1000 hour life test −1 +1 % MCU CLOCK RATE Eight programmable core clock selections within this range (binary divisions 1, 2, 4, 8, … 64, 128) 0.160 10.24 20.48 MHz MCU START-UP TIME At Power-On Includes kernel power-on execution time 25 ms After Reset Event Includes kernel power-on execution time 5 ms From MCU Power-Down Oscillator Running Wake Up from Interrupt 2 ms Wake Up from LIN 2 ms Crystal Powered Down Wake Up from Interrupt 500 ms Internal PLL Lock Time 1 ms LIN INPUT/OUTPUT GENERAL Baud Rate 1000 20,000 bps VDD Supply voltage range at which the LIN interface is functional 7 18 V Input Capacitance 5.5 pF Input Leakage Current Input low = IO_VSS −800 −400 μA LIN Comparator Response Time1 Using 22 Ω resistor 38 90 μs ILIN_DOM_MAX Current limit for driver when LIN bus is in dominant state, VBAT = VBAT (maximum) 40 200 mA ILIN_PAS_REC Driver off, 7.0 V < VLIN < 18 V, VDD = VLIN − 0.7 V −20 +20 μA ILIN1 VBAT disconnected, VDD = 0 V, 0 < VLIN < 18 V 10 μA ILIN_PAS_DOM1 Input leakage VLIN = 0 V −1 mA ILIN_NO_GND28 Control unit disconnected from ground, GND = VDD; 0 V < V LIN < 18 V; VBAT = 12 V −1 +1 mA VLIN_DOM1 LIN receiver dominant state, VDD > 7.0 V 0.4 VDD V VLIN_REC1 LIN receiver recessive state, VDD > 7.0 V 0.6 VDD V VLIN_CNT1 LIN receiver center voltage, VDD > 7.0 V 0.475 VDD 0.5 VDD 0.525 VDD V VHYS1 LIN receiver hysteresis voltage 0.175 VDD V VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage, VDD = 7 V RLOAD = 500 Ω 1.2 V RLOAD = 1000 Ω 0.6 V VLIN_DOM_DRV_HISUP1 LIN dominant output voltage, VDD = 18 V RLOAD = 500 Ω 2 V RLOAD = 1000 Ω 0.8 V VLIN_RECESSIVE LIN recessive output voltage 0.8 VDD V VBAT Shift28 0 0.1 VDD V GND Shift28 0 0.1 VDD V

Rev. B | Page 8 of 136 Parameter Test Conditions/Comments Min Typ Max Unit RSLAVE Slave termination resistance 20 30 47 kΩ VSERIAL DIODE28 Voltage drop at the internal diode 0.4 0.7 1 V Symmetry of Transmit Propagation Delay1 VDD (minimum) = 7 V −4 +4 μs Receive Propagation Delay1 VDD (minimum) = 7 V 6 μs Symmetry of Receive Propagation Delay1 VDD (minimum) = 7 V −2 +2 μs LIN VERSION1.3 SPECIFICATION Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ ; 6.8 nF||660 Ω; 10 nF||500 Ω dt dV 1 Slew rate Dominant and recessive edges, VBAT = 18 V V/ μs dt dV 1 Slew rate Dominant and recessive edges, VBAT = 7 V 0.5 V/ μs tSYM1 Symmetry of rising and falling edge, VBAT = 18 V −5 +5 μs Symmetry of rising and falling edge, VBAT = 7 V −4 +4 μs LIN VERSION 2.0 SPECIFICATION Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ, 6.8 nF||660 Ω, 10 nF||500 Ω D1 Duty Cycle 1, THREC(MAX) = 0.744 × VBAT, THDOM(MAX) = 0.581 × VBAT, VSUP = 7.0 V … 18 V, tBIT = 50 μs, D1 = tBUS_REC(MIN)/(2 × tBIT) 0.396 D2 Duty Cycle 2, THREC(MIN) = 0.284 × VBAT, THDOM(MIN) = 0.422 × VBAT, VSUP = 7.0 V … 18 V; tBIT = 50 μs, D2 = tBUS_REC(MAX)/(2 × tBIT) 0.581 BSD INPUT/OUTPUT29 Baud Rate 1164 1200 1236 bps Input Leakage Current Input high = VDD, or input low = IO_VSS −50 +50 μA Output Low Voltage (VOL) 1.2 V Output High Voltage (VOH) 0.8 VDD V Short-Circuit Output Current (Io(sc)) V BSD = VDD = 12 V 40 80 200 mA Input Low Voltage (VINL) 1.8 V Input High Voltage (VINH) 0.7 VDD V WAKE-UP R LOAD = 300 Ω, CBUS = 91 nF, RLIMIT = 39 Ω VDD1 Supply voltage range at which the WU pin is functional 7 18 V Input Leakage Current Input high = VDD 0.4 2.1 mA Input low = IO_VSS −50 +50 μA VOH30 Output high level 5 V VOL30 Output low level 2 V VIH Input high level 4.6 V VIL Input low level 1.2 V Monoflop Timeout Timeout period 0.6 1.3 2 sec Short-Circuit Output Current (Io(sc)) 100 140 mA SERIAL TEST INTERFACE RLOAD = 500 Ω, CBUS = 2.4 nF, RLIMIT = 39 Ω Baud Rate 40 kbps Input Leakage Current Input high = VDD, or input low = IO_VSS −50 +70 μA VDD Supply voltage range for which STI is functional 7 18 V VOH Output high level 0.6 VDD V VOL Output low level 0.4 VDD V VIH Input high level 0.6 VDD V VIL Input low level 0.4 VDD V PACKAGE THERMAL SPECIFICATIONS Thermal Shutdown1, 31 140 150 160 °C Thermal Impedance (θJA)32 48-lead LFCSP , stacked die 45 °C/W

Rev. B | Page 9 of 136 Parameter Test Conditions/Comments Min Typ Max Unit POWER REQUIREMENTS Power Supply Voltages VDD (Battery Supply) 3.5 18 V REG_DVDD, REG_AVDD33 2.5 2.6 2.7 V Power Consumption IDD (MCU Normal Mode)34 MCU clock rate = 10.24 MHz, ADC off 10 20 mA MCU clock rate = 20.48 MHz, ADC off 20 mA IDD (MCU Powered Down)1 ADC low power mode, measured over the range of TA = −10°C to +40°C, continuous ADC conversion 300 400 μA ADC low power mode, measured over the range of T A = −40°C to +85°C, continuous ADC conversion 300 500 μA ADC low power plus mode, measured over an ambient temperature range of TA = −10°C to +40°C, continuous ADC conversion 520 700 μA Average current, measured with wake-up and watchdog timer clocked from the low power oscillator, TA = −40°C to +85°C 120 300 μA IDD (MCU Powered Down) Average current, measured with wake-up and watchdog timer clocked from low power oscillator over a range of TA = −10°C to +40°C 120 175 μA IDD (Current ADC) 1.7 mA IDD (Voltage/Temperature ADC) 0.5 mA IDD (Precision Oscillator) 400 μA 1 These numbers are not production tested, but are guaranteed by design and/or characterization data at production release. 2 Valid for a current channel ADC PGA setting of 4 to 64. 3 These numbers include temperature drift. 4 Tested at a gain range of 4; self-offset calibration removes this error. 5 Measured with an internal short after an initial offset calibration. 6 Measured with an internal short. 7 These numbers include internal reference temperature drift. 8 Factory calibrated at a gain of 1. 9 System calibration at a specific gain range (and temperature) removes the error at this gain range (and temperature). 10 Includes an initial system calibration. 11 Using ADC normal mode voltage reference. 12 Typical noise in low power modes is measured with chop enabled. 13 Voltage channel specifications include resistive attenuator input stage. 14 System calibration removes this error at the specified temperature. 15 RMS noise is referred to the voltage attenuator input (for example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 μV) and scaled by the attenuator (divide-by-24) to yield these input-referred noise figures. 16 Valid after an initial self-calibration. 17 In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV. 18 It is possible to extend the ADC input range by up to 10% by modifying the factory-set value of the gain calibration register or by using system calibration. Extending the ADC input range can also be used to reduce the ADC input range (LSB size). 19 Limited by minimum/maximum absolute input voltage range. 20 Valid for a differential input less than 10 mV. 21 Measured using the box method. 22 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. 23 References of up to REG_AVDD can be accommodated for by enabling an internal divide-by-2. 24 Die temperature. 25 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles. 26 Retention lifetime equivalent at a junction temperature (TJ) of 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. 27 Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code. 28 These numbers are not production tested, but are supported by LIN compliance testing. 29 BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and CLoad = 10 nF maximum. 30 This specification does not apply directly to the WU pin but includes an RLIMIT of 39 Ω on the wake-up line. 31 In response to a thermal shutdown event, the MCU core is not shut down but is interrupted, and the high voltage I/O pins are disabled. 32 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature. 33 Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA) and REG_AVDD (ISOURCE = 1 mA). 34 The specification listed is typical; additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.

Table 2. SPI Master Mode Timing—Phase Mode = 1 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 2. SPI Master Mode Timing—PHASE Mode = 1

Table 3. SPI Master Mode Timing—PHASE Mode = 0 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 3. SPI Master Mode Timing—PHASE Mode = 0

Table 4. SPI Slave Mode Timing—PHASE Mode = 1 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 4. SPI Slave Mode Timing—PHASE Mode = 1

Table 5. SPI Slave Mode Timing—PHASE Mode = 0 1 tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 5. SPI Slave Mode Timing—PHASE Mode = 0

Figure 6. LIN 2.0 Timing Specification

Rev. B | Page 15 of 136 ABSOLUTE MAXIMUM RATINGS TA = −40°C to +115°C, unless otherwise noted. Table 6. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Rating AGND to DGND to VSS to IO_VSS −0.3 V to +0.3 V VBAT to AGND −22 V to +40 V VDD to VSS −0.3 V to +33 V VDD to VSS for 1 sec −0.3 V to +40 V LIN to IO_VSS −16 V to +40 V STI and WU to IO_VSS −3 V to +33 V Wake-Up Continuous Current 50 mA Short-Circuit Current of High Voltage I/O Pins 100 mA Digital I/O Voltage to DGND −0.3 V to REG_DVDD + 0.3 V VREF to AGND −0.3 V to REG_AVDD + 0.3 V ADC Inputs to AGND −0.3 V to REG_AVDD + 0.3 V ESD Human Body Model (HBM) Rating HBM-ADI0082 (Based on ANSI/ESD STM5.1-2007). All Pins except LIN and VBAT 1 kV LIN and VBAT ±6KV IEC 61000-4-2 for LIN and VBAT ±7 kV Storage Temperature 125°C Junction Temperature Transient 150°C Continuous 130°C Lead Temperature Soldering Reflow (15 sec) 260°C ESD CAUTION

1. THE EXPOSED PAD SHOULD BE CONNECTED TO DGND.

Figure 7. Pin Configuration Table 7. Pin Function Descriptions that this pin be strapped via a resistor to REG_DVDD. an internal weak pull-up resistor and should be left unconnected when not in use. should be left unconnected when not in use. and should be left unconnected when not in use. and should be left unconnected when not in use. 6 TCK I JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part. unconnected when not in use. unconnected when not in use. 8, 34, 35 DGND S Ground Reference for On-Chip Digital Circuits. not externally connect these pins. These pins can be grounded, if required. externally connect these pins. These pins can be grounded, if required. internal weak pull-up resistor. This pin should be left unconnected when not in use.

Rev. B | Page 17 of 136 Pin No. Mnemonic Type 1 Description 11 NTRST I JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part. NTRST is an input pin only and has an internal weak pull-down resistor. This pin should be left unconnected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN boot load mode. 12 TMS I JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports on the part. TMS is an input pin only and has an internal weak pull-up resistor. This pin should be left unconnected when not in use. 13 VBAT I Battery Voltage Input to Resistor Divider. 14 VREF I External Reference Input Terminal. When this input is not used, connect it directly to the AGND system ground. This pin should be left unconnected when not in use. 15 GND_SW I Switch to Internal Analog Ground Reference. This pin is the negative input for the external temperature channel and the external reference. When this input is not used, connect it directly to the AGND system ground. 18 VTEMP I External Pin for NTC/PTC Temperature Measurement. 19 IIN+ I Positive Differential Input for Current Channel. 20 IIN− I Negative Differential Input for Current Channel. 21, 22 AGND S Ground Reference for On-Chip Precision Analog Circuits. 24 REG_AVDD S Nominal 2.6 V Output from On-Chip Regulator. 27 GPIO_0/IRQ0/SS I/O General-Purpose Digital IO 0/External Interrupt Request 0 (Active High)/Slave Select Input (SPI Interface). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use. 28 GPIO_1/SCLK I/O General-Purpose Digital IO 1/Serial Clock Input (SPI Interface). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use. 29 GPIO_2/MISO I/O General-Purpose Digital IO 2/Master Input, Slave Output (SPI Interface). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use. 30 GPIO_3/MOSI I/O General-Purpose Digital IO 3/Master Output, Slave Input (SPI Interface). By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use. 31 GPIO_4/ECLK I/O General-Purpose Digital IO 4/2.56 MHz Clock Output. By default and after a power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and should be left unconnected when not in use. 33 REG_DVDD S Nominal 2.6 V Output from the On-Chip Regulator. 36 XTAL1 O Crystal Oscillator Output. If an external crystal is not used, this pin should be left unconnected. 37 XTAL2 I Crystal Oscillator Input. If an external crystal is not used, connect this pin to the DGND system ground. 41 WU I/O High Voltage Wake-Up. This high voltage I/O pin has an internal 10 kΩ pull-down resistor and a high-side driver to VDD. If this pin is not being used, it should not be connected externally. 42 VDD S Battery Power Supply to On-Chip Regulator. 44 VSS S Ground Reference. This is the ground reference for the internal voltage regulators. 46 STI I/O High Voltage Serial Test Interface Output. If this pin is not used, externally connect it to the IO_VSS ground reference. 47 IO_VSS S Ground Reference for High Voltage I/O Pins. 48 LIN/BSD I/O Local Interconnect Network IO/Bit Serial Device IO. This is a high voltage pin. EPAD Exposed Pad The exposed pad should be connected to digital ground. 1 I = input, O = output, S = supply.

Rev. B | Page 19 of 136 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC after the ADC has settled. The Σ-Δ conversion techniques used on this part mean that while the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, providing a valid 16-bit data conversion result for output rates from 1 Hz to 8 kHz. Note that when software switches from one input to another on the same ADC, the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this may require multiple conversion cycles. Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end- points of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB The error is expressed as a percentage of full scale. No Missing Codes No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits (as 2 N bits, where N is no missing codes) and specifies the number of codes (ADC results) that are guaranteed to occur through the full ADC input range. Offset Error Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition. Offset Error Drift Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSBs per degrees Celsius. Gain Error Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function. Output Noise The output noise is specified as the standard deviation (that is, 1 × Σ) of the distribution of ADC output codes that are collected when the ADC input voltage is at a dc voltage. It is expressed as μV rms. The output, or rms noise, can be used to calculate the effective resolution of the ADC as defined by the following equation: Effective Resolution = log 2(Full-Scale Range/RMS Noise) where Effective Resolution is expressed in bits. The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × Σ of the distribution of ADC output codes that are collected when the ADC input voltage is at dc. The peak-to- peak noise is therefore calculated as 6.6 times the rms noise. The peak-to-peak noise can be used to calculate the ADC (noise-free code) resolution for which there is no code flicker within a 6.6 × Σ limit as defined by the following equation: Noise-Free Code Resolution = log 2(Full-Scale Range/Peak- to-Peak Noise) where Noise-Free Code Resolution is expressed in bits.

interconnect network (LIN) interface that is integrated on chip. rest (POR) event, or an external serial communication event. generate conversion results to a lower performance specification. nonintrusive emulation is also supported via the JTAG interface. development system supporting the ADuC7034. performance at temperatures from 115°C to 125°C. Table 8. ARM7TDMI

• Relative to ARM, the Thumb code usually requires more instructions to perform a task. Therefore, ARM code is best for maximizing the performance of time-critical code in most applications.
• The Thumb instruction set does not include some instruct- tions that are needed for exception handling; therefore, ARM code may be required for exception handling.
• When an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at that address. The first command is required to be in ARM code. Multiplier (M) The ARM7TDMI instruction set includes an enhanced multiplier with four extra instructions to perform 32-bit × 32-bit multiplication with a 64-bit result, or 32-bit × 32-bit multiplication-accumulation (MAC) with a 64-bit result. EmbeddedICE (I) The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. These registers are con- trolled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. When in the debug state, the processor registers can be interrogated, as can the Flash/EE, SRAM, and memory- mapped registers.

• Normal interrupt (IRQ). This is provided to service general-purpose interrupt handling of internal and external events.
• Fast interrupt (FIQ). This is provided to service a data transfer or a communication channel with low latency. FIQ has priority over IRQ.
• Memory abort (prefetch and data).
• Attempted execution of an undefined instruction.
• Software interrupt (SWI) instruction. This can be used to make a call to an operating system. Typically, the programmer defines interrupts as IRQ, but for higher priority interrupts, the programmer can define interrupts as the FIQ type. The priority of these exceptions and vector address are listed in Table 9.

Table 9. Exception Priorities and Vector Addresses

1 Hardware reset 0x00

2 Memory abort (data) 0x10

3 FIQ 0x1C

4 IRQ 0x18

5 Memory abort (prefetch) 0x0C

6 Software interrupt1 0x08

6 Undefined instruction1 0x04

1 A software interrupt and an undefined instruction exception have the same

priority and are mutually exclusive. The stack pointer contains the current location of the stack. required. A separate stack is defined for each of the exceptions. reducing the response time of the interrupt handling process. Figure 11. Register Organization using a continuous 20.48 MHz processor clock.

the part in Thumb mode, which reduces the time to 22 cycles. synchronizer plus the time to enter the exception mode. for example, when executing interrupt service routines. architecture, sees memory as a linear array of 232 byte locations.

• For the ADuC7034, the first 30 kB of this memory space is used as an area into which the on-chip Flash/EE or SRAM can be remapped.
• The ADuC7034 features a second 4 kB area at the top of the memory map used to locate the MMRs, through which all on-chip peripherals are configured and monitored.
• The ADuC7034 features an SRAM size of 4 kB.
• The ADuC7034 features 32 kB of on-chip Flash/EE memory, 30 kB of which are available to the user and 2 kB of which are reserved for the on-chip kernel. Any access, either a read or a write, to an area not defined in the memory map results in a data abort exception. Memory Format The ADuC7034 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address; the most significant byte, in the highest byte address. BIT 31 BYTE 2 A BYTE 3 B BYTE 1 BYTE 0 BIT 0

32 BITS

Figure 12. Little Endian Format Figure 13. ADuC7034 Memory Map 32 bits, that is, 1024 words located at 0x00040000. array. SRAM is readable/writeable in 8-/16-/32-bit segments. memory array, from Address 0x00000000 to Address 0x00000020. Flash/EE to Address 0x00000000, Bit 0 of SYSMAP0 is cleared.

always be written in Flash/EE. Table 10. SYSMAP0 MMR Bit Designations be written as 0 by user code. the Flash/EE memory to Address 0x00000000.

register can be cleared to 0 by writing to the RSTCLR MMR. The bit designations in RSTCLR mirror those of RSTSTA. all four kinds of reset events are tabulated in Table 12. code to initiate a software reset. corresponding bit in RSTSTA. Table 11. RSTSTA/RSTCLR MMR Bit Designations Set automatically to 1 when an external reset occurs. Cleared by setting the corresponding bit in RSTCLR. Set to 1 by user code to generate a software reset. Cleared by setting the corresponding bit in RSTCLR. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR.

1 If the software reset bit in RSTSTA is set, any write to RSTCLR that does not

clear this bit generates a software reset. Table 12. Device Reset Implications 1 RAM is not valid in the case of a reset following a LIN download. mechanism if the LVF status bit, HVMON[3], is 1. See the Low Voltage Flag (LVF) section for more information.

Rev. B | Page 25 of 136 FLASH/EE MEMORY The ADuC7034 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased, with the erasure being performed in page blocks. Therefore, Flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit program- mability, high density, and low cost. Incorporated within the ADuC7034, Flash/EE memory technology allows the user to update program code space in-circuit without the need to replace one-time programmable (OTP) devices at remote operating nodes. The Flash/EE memory is physically located at Address 0x80000. Upon a hard reset, the Flash/EE memory maps to Address 0x00000000. The factory-set default contents of all Flash/EE memory locations is 0xFF. Flash/EE can be read in 8-/16-/32-bit segments and written in segments of 16 bits. The Flash/EE is rated for 10,000 endurance cycles. This rating is based on the number of times that each byte is cycled, that is, erased and programmed. Implementing a redundancy scheme in the software ensures greater than 10,000 endurance cycles. The user can also write data variables to the Flash/EE memory during run-time code execution, for example, for storing diagnostic battery parameter data. The entire Flash/EE is available to the user as code and non- volatile data memory. There is no distinction between data space and program space during ARM code processing. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. When operating at speeds of less than 20.48 MHz, the Flash/EE memory controller can transparently fetch the second 16-bit halfword (part of the 32-bit ARM operation code) within a single core clock period. Therefore, for speeds less than 20.48 MHz (that is, CD > 0), it is recommended to use ARM mode. For 20.48 MHz operation (that is, CD = 0), it is recommended to operate in Thumb mode. The page size of this Flash/EE memory is 512 bytes. Typically, it takes the Flash/EE controller 20 ms to erase a page, regardless of CD. Writing a 16-bit word at CD = 0, 1, 2, or 3 requires 50 μs; at CD = 4 or 57, 0 μs; at CD = 6, 80 μs; and at CD = 7, 105 μs. It is possible to write to a single 16-bit location only twice between erasures; that is, it is possible to walk bytes, not bits. If a location is written to more than twice, the contents of the Flash/EE page may become corrupt. PROGRAMMING FLASH/EE MEMORY IN-CIRCUIT The Flash/EE memory can be programmed in-circuit, using a serial download mode via the LIN interface or the integrated JTAG port. Serial Downloading (In-Circuit Programming) The ADuC7034 facilitates code download via the LIN pin. JTAG Access The ADuC7034 features an on-chip JTAG debug port to facilitate code downloading and debugging. ADuC7034 Flash/EE Memory The total 32 kB of Flash/EE is organized as 15,000 × 16 bits. Of this total, 30 kB are user space and 2 kB are reserved for boot loader/kernel space. FLASH/EE CONTROL INTERFACE Access to and control of the Flash/EE memory on the ADuC7034 is managed by an on-chip memory controller. The controller manages the Flash/EE memory as a single block of 32 kB. It should be noted that the MCU core is halted until the command completes. User software must ensure that the Flash/EE controller completes any erase or write cycle before the PLL is powered down. If the PLL is powered down before an erase or write cycle is completed, the Flash/EE page may become corrupt. User code, LIN, and JTAG programming use the Flash/EE control interface, consisting of the following MMRs:

• FEE0STA: read only register. Reflects the status of the Flash/EE control interface.
• FEE0MOD: sets the operating mode of the Flash/EE control interface.
• FEE0CON: 8-bit command register. The commands are interpreted as described in Table 13.
• FEE0DAT: 16-bit data register.
• FEE0ADR: 16-bit address register.
• FEE0SIG: holds the 24-bit code signature as a result of the signature command being initiated.
• FEE0HID: protection MMR. Controls read and write protection of the Flash/EE memory code space. If previously configured via the FEE0PRO register, FEE0HID may require a software key to enable access.
• FEE0PRO: a buffer of the FEE0HID register. Stores the FEE0HID value and therefore automatically downloads to the FEE0HID registers on subsequent reset and power-on events. The FEE0CON Register to FEE0DAT Register sections provide detailed descriptions of the bit designations for each of the Flash/EE control MMRs.

Function: This 8-bit register is written by user code to control the operating modes of the Flash/EE memory controller. Table 13. Command Codes in FEE0CON 0x001 Reserved Reserved. This command should not be written by user code. 0x011 Single read Load FEE0DAT with the 16-bit data indexed by FEE0ADR. 0x021 Single write Write FEE0DAT at the address pointed by FEE0ADR. This operation takes 50 μs. the comparison is returned in FEE0STA Bit 1. 0x051 Single erase Erase the page indexed by FEE0ADR. in the Command Sequence for Executing a Mass Erase section. 0x08 Reserved Reserved. This command should not be written by user code. 0x09 Reserved Reserved. This command should not be written by user code. 0x0A Reserved Reserved. This command should not be written by user code. 0x0B Signature This command results in a 24-bit, LFSR-based signature being generated and loaded into FEE0SIG. with a mass erase (0x06) or with the software protection key. 0x0D Reserved Reserved. This command should not be written by user code. 0x0E Reserved Reserved. This command should not be written by user code. 0x0F Ping No operation, interrupt generated. 1 The FEE0CON register reads 0x07 immediately after the execution of this command.

1. Run the mass erase command (Code 0x06) in FEE0CON.

Table 14. FEE0STA MMR Bit Designation 7 to 4 Not used. These bits are not used and always read as 0. 3 Flash/EE interrupt status bit. interrupt enable bit in the FEE0MOD register is set. Set automatically when the Flash/EE controller is busy. Cleared automatically when the controller is not busy. Table 15. FEE0MOD MMR Bit Designation and should be written as 0 by user code. 4 Flash/EE controller command complete interrupt enable. interrupt upon completion of a Flash/EE command. 3 Flash/EE erase/write enable. 1 Flash/EE controller abort enable.

and write protected using the FFE0HID register. The FEE0HID MMR protects the 30 kB of Flash/EE memory. entire Flash/EE from being read through JTAG. keyed permanent protection, and permanent protection. Table 16. FEE0HID MMR and FEE0PRO MMR Bit Designations Set by user code to allow read access to the 32 kB Flash/EE block via JTAG. Cleared by user code to read protect the 32 kB Flash/EE block code. Set by user code to allow writes to Page 59. Cleared by user code to write protect Page 59. Set by user code to allow writes to Page 58. Cleared by user code to write protect Page 58. 28 to 0 Write protection bits. pages and each page consists of 512 bytes. pages and each page consists of 512 bytes.

back to 0xFFFF but also erases the entire user code space.

1. Write in FEE0PRO corresponding to the pages to be
2. Write the new (user-defined) 32-bit software protection

key in FEE0ADR (Bits[31:16]) and FEE0DAT (Bits[15:0]).

1. Write 10 in FEE0MOD (Bits[6:5]) and set FEE0MOD (Bit 3).
2. Run the protect command (Code 0x0C) in FEE0CON.

used with a modified value of FEE0PRO. cycling endurance and Flash/EE memory data retention.

• Initial page erase sequence
• Read/verify sequence
• Byte program sequence
• Second read/verify sequence In reliability qualification, every halfword (16 bits wide) location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in Table 1, the Flash/EE memory endurance qualification of the part is carried out in accordance with JEDEC Retention Lifetime Specification A117. The results allow the specification of a minimum endurance figure over supply and temperature of 10,000 cycles. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the part is qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature J = 85°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for the fully specified retention lifetime every time the Flash/EE memory is reprogrammed. In addition, note that the retention lifetime, based on an activation energy of 0.6 eV , derates with T J as shown in Figure 14. 150 300 450 600 25 40 55 70 85 100 115 130 145 RETENTION (Years) JUNCTION TEMPERATURE (°C) 07116-012

Figure 14. Flash/EE Memory Data Retention

execution for applications where execution time is critical. cycles to fill the pipeline with the new instructions. needed to fetch any instruction. before accessing data for any value of CD bits. then four cycles are needed to fill the pipeline if CD = 0. are more complex and are summarized in Table 17. Table 17. Typical Execution Cycles in ARM/Thumb Mode multiple load/store instruction. takes 20 ms and a write (16 bits) word command takes 50 μs. from SRAM to allow the core to immediately service the interrupt.

Rev. B | Page 31 of 136 ADuC7034 KERNEL The ADuC7034 features an on-chip kernel resident in the top 2 kB of the Flash/EE code space. After any reset event, this kernel copies the factory-calibrated data from the manufacturing data space into the various on-chip peripherals. The peripherals calibrated by the kernel are as follows:

• Power supply monitor (PSM)
• Precision oscillator
• Low power oscillator
• REG_AVDD/REG_DVDD
• Low power voltage reference
• Normal mode voltage reference
• Current ADC (offset and gain)
• Voltage/temperature ADC (offset and gain) User MMRs that can be modified by the kernel and differ from their POR default values are as follows:
• R0 to R15
• GP0CON/GP2CON
• SYSCHK
• ADCMDE/ADC0CON
• FEE0ADR/FEE0CON/FEE0SIG
• HVDAT/HVCON
• HVCFG0/HVCFG1
• T3LD The ADuC7034 also features an on-chip LIN downloader. A flow chart of the execution of the kernel is shown in Figure 15. The current revision of the kernel can be derived from SYSSER1, as described in Table 98. After a POR reset, the watchdog timer is disabled once the kernel code is exited. For the duration of the kernel execution, the watchdog timer is active with a timeout period of 500 ms. This ensures that when an error occurs in the kernel, the ADuC7034 automatically resets. After any other reset, the watchdog timer maintains user code configuration for the period of the kernel and is refreshed just prior to kernel exit. A minimum watchdog period of 30 ms is required to allow correct LIN downloader operation. If LIN download mode is entered, the watchdog is periodically refreshed. Normal kernel execution time, excluding LIN download, is approximately 5 ms. It is only possible to enter and leave LIN download mode through a reset. SRAM is not modified during normal kernel execution; rather, SRAM is modified during a LIN download kernel execution. Note that even with NTRST = 0, user code is not executed unless Address 0x14 contains either 0x27011970 or the checksum of Page 0 excluding Address 0x14. If Address 0x14 does not contain this information, user code is not executed and LIN download mode is entered. During kernel execution, JTAG access is disabled. With NTRST = 1, user code is always executed.

Figure 15. ADuC7034 Kernel Flowchart

register bank for the ADuC7034 is shown in Figure 16. (described in the ARM Registers section) reside in the MMR area. 16 of the MMR bits can be read. Figure 16. Top-Level MMR Map

In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and RW for read and write. Table 18. IRQ Address Base = 0xFFFF0000 0x0000 IRQSTA 4 R 0x00000000 Active IRQ source. See the Interrupt System section and Table 49. System section and Table 49. 0x0008 IRQEN 4 RW 0x00000000 Enabled IRQ sources. See the Interrupt System section and Table 49. 0x000C IRQCLR 4 W N/A MMR to disable IRQ sources. See the Interrupt System section and Table 49. 0x0100 FIQSTA 4 R 0x00000000 Active IRQ source. See the Interrupt System section and Table 49. System section and Table 49. 0x0108 FIQEN 4 RW 0x00000000 Enabled IRQ sources. See the Interrupt System section and Table 49. 0x010C FIQCLR 4 W N/A MMR to disable IRQ sources. See the Interrupt System section and Table 49. 1 Depends on the level on the external interrupt pins (GPIO_0, GPIO_5, GPIO_7, and GPIO_8). Table 19. System Control Address Base = 0xFFFF0200 0x0220 SYSMAP0 1 RW N/A REMAP control register. See the Remap Operation section and Table 10. 0x0230 RSTSTA 1 RW N/A Reset status MMR. See the Reset section and Table 11 and Table 12. 0x0234 RSTCLR 1 W N/A RSTSTA clear MMR. See the Reset section and Table 11 and Table 12. 0x0560 SYSALI 1 4 R N/A System assembly lot ID. See the Part Identification section for details. 0x0240 SYSCHK 1 4 RW N/A Kernel checksum. See the System Kernel Checksum section. Table 20. Timer Address Base = 0xFFFF0300 0x0320 T1LD 4 RW 0x00000000 Timer1 load register. See the Timer1 and Timer1 Load Registers sections. 0x0324 T1VAL 4 R 0xFFFFFFFF Timer1 value register. See the Timer1 and Timer1 Value Register sections. 0x0328 T1CON 4 RW 0x01000000 Timer1 control MMR. See the Timer1 and Timer1 Control Register sections. 0x0330 T1CAP 4 R 0x00000000 Timer1 capture register. See the Timer1 and Timer1 Capture Register sections.

Register sections and Table 54. Register, and Timer3 Control Register sections and Table 55. 0x0390 T4CAP 2 R 0x0000 Timer4 capture register. See the Timer4—STI Timer section and Table 56. Table 21. PLL Base Address = 0xFFFF0400 0x0400 PLLSTA 1 R N/A PLL status MMR. See the PLLSTA Register section and Table 43. 0x0404 POWKEY0 4 W N/A POWCON prewrite key. See the POWCON Prewrite Key section. 0x040C POWKEY1 4 W N/A POWCON postwrite key. See the POWCON Postwrite Key section. 0x0410 PLLKEY0 4 W N/A PLLCON prewrite key. See the PLLCON Prewrite Key section. 0x0414 PLLCON 1 RW 0x00 PLL clock source selection MMR. See the PLLCON Register section. 0x0418 PLLKEY1 4 W N/A PLLCON postwrite key. See the PLLCON Postwrite Key section. 0x042C OSC0TRM 1 RW 0xX8 Low power oscillator trim bits MMR. See the OSC0TRM Register section. 0x0444 OSC0STA 1 R 0x00 Low power oscillator calibration status MMR. See the OSC0STA Register section.

Table 22. ADC Address Base = 0xFFFF0500 0x0500 ADCSTA 2 R 0x0000 ADC status MMR. See the ADC Status Register section and Table 34. 0x0504 ADCMSKI 1 RW 0x00 ADC Interrupt Source Enable MMR. See the ADC Interrupt Mask Register section. 0x0508 ADCMDE 1 RW 0x00 ADC mode register. See the ADC Mode Register section and Table 35. Register section and Table 37. 0x0518 ADCFLT 2 RW 0x0007 ADC filter control MMR. See the ADC Filter Register section and Table 38. 0x0520 ADC0DAT 2 R 0x0000 Current ADC result MMR. See the Current Channel ADC Data Register section. 0x0524 ADC1DAT 2 R 0x0000 V-ADC result MMR. See the Voltage Channel ADC Data Register section. 0x0528 ADC2DAT 2 R 0x0000 T-ADC result MMR. See the Temperature Channel ADC Data Register section. Calibration Register section. Threshold Count Limit Register section. Threshold Count Register section. Reference Scaling Factor section.

Table 23. UART Base Address = 0XFFFF0700 0x0700 COMTX 1 W N/A UART transmit register. See the UART TX Register section. COMRX 1 R 0x00 UART receive register. See the UART RX Register section. 0x070C COMCON0 1 RW 0x00 UART Control Register 0. See the UART Control Register 0 section and Table 80. 0x0710 COMCON1 1 RW 0x00 UART Control Register 1. See the UART Control Register 1 section and Table 81. 0x0714 COMSTA0 1 R 0x60 UART Status Register 0. See the UART Status Register 0 section and Table 82. Table 24. LIN Hardware Sync Base Address = 0XFFFF0780 0x0790 LHSVAL1 2 RW 0x0000 LHS Timer1 MMR. See the LIN Hardware Break Timer1 Register section. Table 25. High Voltage Interface Base Address = 0xFFFF0800 Register section and Table 70 and Table 71.

Table 26. STI Base Address = 0xFFFF0880 0x0880 STIKEY0 4 W N/A STICON prewrite key. See the Serial Test Interface Key0 Register section. 0x088C STIDAT0 2 RW 0x0000 STI Data MMR 0. See the Serial Test Interface Data0 Register section. 0x0890 STIDAT1 2 RW 0x0000 STI Data MMR 1. See the Serial Test Interface Data1 Register section. 0x0894 STIDAT2 2 RW 0x0000 STI Data MMR 2. See the Serial Test Interface Data2 Register section. Table 27. SPI Base Address = 0xFFFF0A00 0x0A00 SPISTA 1 R 0x00 SPI status MMR. See the SPI Status Register section and Table 89. 0x0A04 SPIRX 1 R 0x00 SPI receive MMR. See the SPI Receive Register section. 0x0A08 SPITX 1 W SPI transmit MMR. See the SPI Transmit Register section. 0x0A0C SPIDIV 1 RW 0x1B SPI baud rate select MMR. See the SPI Divider Register section. 0x0A10 SPICON 2 RW 0x00 SPI control MMR. See the SPI Control Register section and Table 88. Table 28. GPIO Base Address = 0xFFFF0D00 1 Depends on the level on the external GPIO pins.

Table 29. Flash/EE Base Address = 0xFFFF0E00 0x0E00 FEE0STA 1 R 0x20 Flash/EE status MMR and Table 14. 0x0E04 FEE0MOD 1 RW 0x00 Flash/EE control MMR and Table 15. 0x0E08 FEE0CON 1 RW 0x07 Flash/EE control MMR. See Table 13. 0x0E0C FEE0DAT 2 RW 0x0000 Flash/EE data MMR. 0x0E10 FEE0ADR 2 RW Flash/EE address MMR. 0x0E18 FEE0SIG 3 R 0xFFFFFF Flash/EE LFSR MMR.

Rev. B | Page 40 of 136 16-BIT SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS The ADuC7034 incorporates two independent sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), namely, the current channel ADC (I-ADC) and the voltage/temperature channel ADC (V-/T-ADC). These precision measurement channels integrate on-chip buffering, a programmable gain amplifier, 16-bit Σ-Δ modulators, and digital filtering for precise measurement of current, voltage, and temperature variables in 12 V automotive battery systems. CURRENT CHANNEL ADC (I-ADC) The I-ADC converts battery current sensed through an external 100 μΩ shunt resistor. On-chip programmable gain means that the I-ADC can be configured to accommodate battery current levels from ±1 A to ±1500 A. As shown in Figure 17, the I-ADC employs a Σ-Δ conversion technique to attain 16 bits of no missing codes performance. The Σ-Δ modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital infor- mation. A modified sinc3 programmable low-pass filter is then employed to decimate the modulator output data stream to provide a valid 16-bit data conversion result at programmable output rates from 4 Hz to 8 kHz in normal mode and from 1 Hz to 2 kHz in low power mode. The I-ADC also incorporates counter, comparator, and accumulator logic. This allows the I-ADC result to generate an interrupt after a predefined number of conversions has elapsed or a programmable threshold value has been exceeded. A fast ADC overrange feature is also supported. Once enabled, a 32-bit accumulator automatically sums the 16-bit I-ADC results. The time to a first valid (fully settled) result on the current channel is three ADC conversion cycles with chop mode disabled and two ADC conversion cycles with chop mode enabled.

Figure 17. Current ADC, Top-Level Overview

additional battery parameters, such as voltage and temperature. ture sensor circuit, or an on-chip temperature sensor. is internally implemented in the voltage channel. via an on-chip high voltage (divide-by-24) resistive attenuator. the voltage attenuator input is selected. temperature sensor or an external temperature sensor input. ADC conversion cycles with chop mode disabled. level overview of this ADC signal chain is shown in Figure 18. Figure 18. Voltage/Temperature ADC, Top-Level Overview

Power Voltage Reference Scaling Factor Registersections. the ADC1DAT MMR and then read the ADC0DAT MMR. MMRs unless the respective ADC result ready bits are first cleared. conversion result, even if the ready bits have not been cleared. or current status of the ADuC7034 ADCs. Table 34. ADCSTA MMR Bit Designations Set automatically in hardware to indicate that an ADC calibration cycle has been completed. Cleared after ADCMDE is written to. 14 ADC temperature conversion error. conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. Cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register. 13 ADC voltage conversion error. result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. Cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register. 12 ADC current conversion error. result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. Cleared when a valid (in-range) current conversion result is written to the ADC0DAT register. 11 to 5 Not used. These bits are reserved for future functionality and should not be monitored by user code. conversions equals the value in the ADC0THV MMR. Cleared by a reconfiguration of the ADC or if the comparator threshold is disabled. 3 Current channel ADC overrange bit. This bit is updated every 125 μs. 2 Temperature conversion result ready bit. if the temperature channel ADC is enabled. It is also set at the end of a calibration. Cleared by reading either ADC2DAT or ADC0DAT.

Rev. B | Page 45 of 136 Bit Description 1 Voltage conversion result ready bit. Set by hardware as soon as a valid voltage conversion result is written in the voltage data register (ADC1DAT MMR) if the voltage channel ADC is enabled. It is also set at the end of a calibration. Cleared by reading either ADC1DAT or ADC0DAT. 0 Current conversion result ready bit. Set by hardware as soon as a valid current conversion result is written in the current data register (ADC0DAT MMR) if the current channel ADC is enabled. It is also set at the end of a calibration. Cleared by reading ADC0DAT. ADC Interrupt Mask Register Name: ADCMSKI Address: 0xFFFF0504 Default Value: 0x00 Access: Read/write Function: This register allows the ADC interrupt sources to be individually enabled. The bit positions in this register are the same as the lower eight bits in the ADCSTA MMR. If a bit is set to 1 by user code, the respective interrupt is enabled. By default, all bits are 0, meaning all ADC interrupt sources are disabled.

Function: The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 35. ADCMDE MMR Bit Designations 7 Not used. This bit is reserved for future functionality and should be written as 0 by user code. 1 = selects the 20 kΩ resistor shown in Figure 20. 0 = selects the direct path to ground shown in Figure 20 (default). 5 Low power mode reference select. voltage reference in low power modes requires additional current and therefore results in increased current consumption. 0 = enables the low power voltage reference in either low power mode or low power plus mode (default). 4 to 3 ADC power mode configuration. the on-chip low power 131 kHz oscillator to directly drive the ADC circuits. mode, the gain is fixed to 512 and the current consumed is approximately 200 μA more than the ADC low power mode. 2 to 0 ADC operation mode configuration. 000 = ADC power-down mode. All ADC circuits, including the internal reference, are powered down. 001 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts. 011 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. conversion ready status bits are set at the end of an offset calibration cycle. calibration should be performed on the temperature channel. calibration result is available. an external full-scale voltage driven at the ADC input pins.

Function: The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC. Note: If the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ADC are also reset. Table 36. ADC0CON MMR Bit Designations 15 Current channel ADC enable. Set to 1 by user code to enable the I-ADC. Clearing this bit to 0 powers down the I-ADC and resets the respective ADC ready bit in the ADCSTA MMR to 0. 14 to 13 IIN current source enable. 00 = disables current sources. 01 = enables 50 μA current source on IIN+. 10 = enables 50 μA current source on IIN−. 11 = enables 50 μA current source on both IIN− and IIN+. 12 to 10 Not used. These bits are reserved for future functionality and should be written as 0. 9 Current channel ADC output coding. Set to 1 by user code to configure I-ADC output coding as unipolar. Cleared to 0 by user code to configure I-ADC output coding as twos complement. 8 Not used. This bit is reserved for future functionality and should be written as 0. 7 to 6 Current channel ADC inputs select. 00 = IIN+ and IIN− are selected. 01 = IIN− and IIN− are selected. Diagnostic, internal short configuration. AGND divided by 2 is selected, REG_AVDD is used for VREF. This leads to ADC0DAT being scaled by 2. 5 to 4 Current channel ADC reference select. 01 = external reference inputs VREF and GND_SW are selected. external reference up to REG_AVDD. 11 = the reference REG_AVDD and AGND divided by 2 is selected. 3 to 0 Current channel ADC gain select. The nominal I-ADC full-scale input voltage is VREF/gain. 1010 = I-ADC gain is undefined. 1011 = I-ADC gain is undefined. 1100 = I-ADC gain is undefined. 1101 = I-ADC gain is undefined. 1110 = I-ADC gain is undefined. 1111 = I-ADC gain is undefined.

Function: The voltage/temperature channel ADC control MMR is a 16-bit register that is used to configure the V-/T-ADC. Note: If the VBAT attenuator input is selected, the voltage attenuator buffers are automatically enabled. Table 37. ADC1CON MMR Bit Designations 15 Voltage/temperature channel ADC enable. Set to 1 by user code to enable the V-/T-ADC. Clearing this bit to 0 powers down the V-/T-ADC. 14 to 13 VTEMP current source enable. 00 = disables current sources. 01 = enables 50 μA current source on VTEMP . 10 = enables 50 μA current source on GND_SW. 11 = enables 50 μA current source on both VTEMP and GND_SW. 12 to 10 Not used. These bits are reserved for future functionality and should not be modified by user code. 9 Voltage/temperature channel ADC output coding. Set to 1 by user code to configure V-/T-ADC output coding as unipolar. Cleared to 0 by user code to configure V-/T-ADC output coding as twos complement. 8 Not used. This bit is reserved for future functionality and should be written as 0 by user code. 7 to 6 Voltage/temperature channel ADC input select. configuration. The conversion result is written to ADC1DAT. 01 = external temperature inputs (VTEMP and GND_SW) are selected. The conversion result is written to ADC2DAT. temperature gradient is 0.33 mV/°C; this is only applicable to the internal temperature sensor. 11 = internal short is selected. Shorted input. The conversion result is written to ADC1DAT. 5 to 4 Voltage/temperature channel ADC reference select. 00 = internal 1.2 V precision reference is selected. 01 = external reference inputs VREF and GND_SW are selected. 11 = the reference input REG_AVDD and AGND divided by 2 are selected for the voltage channel. The reference inputs REG_AVDD and GND_SW divided by 2 are selected for the temperature channel. 3 to 0 Not used. These bits are reserved for future functionality and should not be written as 0 by user code.

Function: The ADC filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs. Note: If ADCFLT is modified, the current and voltage/temperature ADCs are reset. Table 38. ADCFLT MMR Bit Designations Cleared by user code to disable system chopping. Cleared by the user to disable the running average function. 13 to 8 Averaging factor (AF). The values written to these bits are used to implement a programmable first-order sinc3 postfilter. factor, Bits[6:0], in this table. fNOTCH is the location of the first notch in the response. and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125. For SF = 126, fADC is forced to 60 Hz. For SF = 127, fADC is forced to 50 Hz. For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 39. that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.

Table 39. ADC Conversion Rates and Settling Times 1 An additional time of approximately 60 μs per ADC is required before the first ADC is available. Table 40. Allowable Combinations of SF and AF

Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 41. ADCCFG MMR Bit Designations 7 Analog ground switch enable. Set to 1 by user software to connect the external GND_SW pin (Pin 15) to an internal analog ground reference point. conjunction with ADCMDE[6] to select a 20 kΩ resistor to ground. Cleared by user code to disconnect the external GND_SW pin. 6 to 5 Current channel (32-bit) accumulator enable. twice) before the accumulator can be re-enabled to ensure the accumulator is reset. Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum value of 0. continues to subtract current even after 0 is reached. 4 to 3 Current channel ADC comparator enable. 01 = comparator active. An interrupt is asserted if the absolute value of the I-ADC conversion result is |I| ≥ ADC0TH. threshold counter value (ADC0THV) toward 0. 2 Current channel ADC overrange enable. set range for more than 125 μs for the flag to be set. This feature should not be used in ADC low power mode. Cleared by user code to disable the overrange feature. 1 Not used. This bit is reserved for future functionality and should be written as 0 by user code. 0 Current channel ADC, result counter enable. Set by user to enable the result count mode. In this mode, an I-ADC interrupt is generated only when ADC0RCV = ADC0RCL. available (intermediate V-/T-ADC conversion results are not stored) when the ADC counter interrupt occurs.

Rev. B | Page 52 of 136 Current Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF0520 Default Value: 0x0000 Access: Read only Function: This ADC data MMR holds the 16-bit conversion result from the I-ADC. The ADC does not update this MMR if the ADC0 conversion result ready bit (ADCSTA[0]) is set. A read of this MMR by the MCU clears all asserted ready flags (ADCSTA[2:0]). Voltage Channel ADC Data Register Name: ADC1DAT Address: 0xFFFF0524 Default Value: 0x0000 Access: Read only Function: This ADC data MMR holds the 16-bit voltage conversion result from the V-/T-ADC. The ADC does not update this MMR if the voltage conversion result ready bit (ADCSTA[1]) is set. If I-ADC is not active, a read of this MMR by the MCU clears all asserted ready flags (ADCSTA[2:1]). Temperature Channel ADC Data Register Name: ADC2DAT Address: 0xFFFF0528 Default Value: 0x0000 Access: Read only Function: This ADC data MMR holds the 16-bit temperature conversion result from the V-/T- ADC. The ADC does not update this MMR if the temperature conversion result ready bit (ADCSTA[2]) is set. A read of this MMR clears ADCSTA[2]. Current Channel ADC Offset Calibration Register Name: ADC0OF Address: 0xFFFF0530 Default Value: Part specific, factory programmed Access: Read/write access Function: This ADC offset MMR holds a 16-bit offset calibration coefficient for the I-ADC. The register is configured at power-on with a factory-set default value. However, the value of this register is automatically overwritten if an offset calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register after the ADC is in idle mode for at least 23 μs. Therefore, the ADC must be enabled and in idle mode for at least 23 μs before an offset or gain register can be written to. Voltage Channel ADC Offset Calibration Register Name: ADC1OF Address: 0xFFFF0534 Default Value: Part specific, factory programmed Access: Read/write access Function: This offset MMR holds a 16-bit offset calibration coefficient for the voltage channel. The register is configured at power-on with a factory-set default value. However, the value of this register is automatically overwritten if an offset calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register after the ADC is in idle mode for at least 23 μs. Therefore, the ADC must be enabled and in idle mode for at least 23 μs before an offset or gain register can be written to.

Rev. B | Page 53 of 136 Temperature Channel ADC Offset Calibration Register Name: ADC2OF Address: 0xFFFF0538 Default Value: Part specific, factory programmed Access: Read/write Function: This ADC offset MMR holds a 16-bit offset calibration coefficient for the temperature channel. The register is configured at power-on with a factory-set default value. However, the value of this register is automatically overwritten if an offset calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register after the ADC is in idle mode for at least 23 μs. Therefore, the ADC must be enabled and in idle mode for at least 23 μs before an offset or gain register can be written to. Current Channel ADC Gain Calibration Register Name: ADC0GN Address: 0xFFFF053C Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling the I-ADC conversion result. The register is configured at power-on with a factory-set default value. However, the value of this register is automatically overwritten if a gain calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register after the ADC is in idle mode for at least 23 μs. Therefore, the ADC must be enabled and in idle mode for at least 23 μs before an offset or gain register can be written to. Voltage Channel Gain Calibration Register Name: ADC1GN Address: 0xFFFF0540 Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling a voltage channel conversion result. The register is configured at power-on with a factory-set default value. However, the value of this register is automatically overwritten if a gain calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register after the ADC is in idle mode for at least 23 μs. Therefore, the ADC must be enabled and in idle mode for at least 23 μs before an offset or gain register can be written to. Temperature Channel Gain Calibration Register Name: ADC2GN Address: 0xFFFF0544 Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling a temperature channel conversion result. The register is configured at power-on with a factory-set default value. However, the value of this register is automatically overwritten if a gain calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register after the ADC is in idle mode for at least 23 μs. Therefore, the ADC must be enabled and in idle mode for at least 23 μs before an offset or gain register can be written to.

Rev. B | Page 54 of 136 Current Channel ADC Result Counter Limit Register Name: ADC0RCL Address: 0xFFFF0548 Default Value: 0x0001 Access: Read/write Function: This 16-bit MMR sets the number of conversions required before an ADC interrupt can be generated. By default, this register is set to 0x01. The ADC counter function must be enabled via the ADC result counter enable bit in the ADCCFG MMR. Current Channel ADC Result Count Register Name: ADC0RCV Address: 0xFFFF054C Default Value: 0x0000 Access: Read only Function: This 16-bit, read only MMR holds the current number of I-ADC conversion results. It can be used in conjunction with the ADC0RCL register to mask I-ADC interrupts and therefore generate a lower interrupt rate. Alternatively, the ADC0RCV register can be used in conjunction with the accumulator (ADC0ACC) to calculate the average current. In either case, the result counter must be enabled via ADCCFG[0]. When ADC0RCV = ADC0RCL, the value in ADC0RCV resets to 0 and resumes counting. In addition, the value in ADC0RCV resets to 0 when the I-ADC is reconfigured, that is, when the ADC0CON or ADCMDE are written. Current Channel ADC Threshold Register Name: ADC0TH Address: 0xFFFF0550 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR sets the threshold that is compared with the absolute value of the I-ADC conversion result. In unipolar mode, this threshold is compared with ADC0TH[15:0]; in twos complement mode, this threshold is compared with ADC0TH[14:0]. Current Channel ADC Threshold Count Limit Register Name: ADC0TCL Address: 0xFFFF0554 Default Value: 0x01 Access: Read/write Function: This 8-bit MMR determines how many cumulative I-ADC conversion result readings above ADC0TH (that is, values that are below the threshold decrement or that reset the count to 0) must occur before the I-ADC comparator threshold bit is set in the ADCSTA MMR, generating an ADC interrupt. The I-ADC comparator threshold bit is asserted as soon as ADC0THV = ADC0TCL. Current Channel ADC Threshold Count Register Name: ADC0THV Address: 0xFFFF0558 Default Value: 0x00 Access: Read only Function: This 8-bit MMR is incremented every time the absolute value of an I-ADC conversion result is |I| ≥ ADC0TH. This register is decremented or reset to 0 every time the absolute value of an I- ADC conversion result is |I| < ADC0TH. The configuration of this function is enabled via the current channel ADC comparator bits in the ADCCFG MMR. Current Channel ADC Accumulator Register Name: ADC0ACC Address: 0xFFFF055C Default Value: 0x00000000 Access: Read only Function: This 32-bit MMR holds the current accumulator value. The I-ADC ready bit in the ADCSTA MMR should be used to determine when to read this MMR. The MMR value is reset to 0 by disabling the accumulator in the ADCCFG MMR or by reconfiguring the current channel ADC.

Rev. B | Page 55 of 136 Low Power Voltage Reference Scaling Factor Register Name: ADCREF Address: 0xFFFF057C Default Value: Part specific, factory programmed Access: Read/write. Care should be taken not to write to this register. Function: This MMR allows user code to correct for the initial error of the LPM reference. Value 0x8000 corresponds to no error when compared with the normal mode reference. The magnitude of the ADC result should be multiplied by the value in ADCREF and divided by 0x8000 to compensate for the actual value of the low power reference. If the LPM voltage reference is 1% below 1.200 V, the value of ADCREF is approximately 0x7EB9. If the LPM voltage reference is 1% above 1.200 V, the value of ADCREF is approximately 0x8147. This register corrects the effective value of the LPM reference at the temperature at which the reference is measured during the Analog Devices, Inc., production flow, which is 25°C. There is no change to the temperature coefficient of the LPM reference when using the ADCREF MMR. This register should not be used if the precision reference is being used in low power mode (if ADCMDE[5] is set). ADC POWER MODES OF OPERATION The ADCs can be configured into various reduced or full power modes of operation by changing the configuration of ADCMDE[4:3], and the ARM7 MCU can be configured in low power modes of operation (POWCON[5:3]). Note that the core power modes are independently controlled and are not related to the ADC power modes. ADC Normal Power Mode In normal mode, the current and voltage/temperature channels are fully enabled. The ADC modulator clock is 512 kHz and enables the ADCs to provide regular conversion results at a rate between 4 Hz and 8 kHz (see the ADC Filter Register section). Both channels are under full control of the MCU and can be reconfigured at any time. The default ADC update rate for all channels in this mode is 1.0 kHz. Note that I-ADC and V-/T-ADC channels can be configured to initiate periodic single conversion cycles in normal power mode with high accuracy before returning to ADC full power-down mode. This flexibility is facilitated by the full MCU control via the ADCMDE MMR, which ensures the feasibility of continuous periodic monitoring of battery current, voltage, and temperature settings while minimizing the average dc current consumption. In ADC normal mode, the PLL must not be powered down. ADC Low Power Mode In ADC low power mode, the I-ADC is enabled in a reduced power and reduced accuracy configuration. In this mode, the ADC modulator clock is driven directly from the on-chip 131 kHz low power oscillator, which allows the ADC to be configured at update rates as low as 1 Hz (ADCFLT). The gain of the ADC in this mode is fixed at 128. All ADC peripheral functions (result counter, digital comparator, and accumulator) described in the ADC Normal Power Mode section can also be enabled in low power mode. Typically, in low power mode only the I-ADC is configured to run at a low update rate and to continuously monitor battery current. The MCU is in power-down mode and wakes up when the I-ADC interrupts the MCU. Such an interrupt occurs after the I-ADC detects a current conversion that exceeds a preprogrammed threshold, a setpoint, or a set number of conversions. It is also possible to select either the ADC precision voltage reference or the ADC low power mode voltage reference via ADCMDE[5].

mode almost identical to low power mode (ADCMDE[4:3]). section can also be enabled in low power plus mode. low update rate and to continuously monitor battery current. a setpoint, or a set number of conversions. preset value that is set via ADC0TCL. further software processing. and is configured via the 16-bit ADC filter register (ADCFLT). This register determines the overall throughput rate of the ADCs. values are outlined in Table 40. running average, averaging factor, and sinc3 modify) disabled. Figure 21. Typical Digital Filter Response at fADC = 1 kHz where fNOTCH is the location of the first notch in the response. compared with the standard 1 kHz response.

Figure 26. Typical Digital Filter Response at fADC = 4 Hz (ADCFLT = 0xBF1D) Figure 27. Typical Digital Filter Response at fADC = 1 Hz (ADCFLT = 0xBD1F) some common ADCFLT configurations. Table 42. Common ADCFLT Configurations

Rev. B | Page 59 of 136 ADC CALIBRATION As shown in detail in the top-level diagrams (Figure 17 and Figure 18), the signal flow through all ADC channels can be described in as follows: 1. An input voltage is applied through an input buffer (and through PGA in the case of the I-ADC) to the Σ-Δ modulator. 2. The modulator output is applied to a programmable digital decimation filter. 3. The filter output result is averaged if chopping is used. 4. An offset value (ADCxOF) is subtracted from the result. 5. The result is scaled by a gain value (ADCxGN). 6. The result is formatted as twos complement/offset binary, rounded to 16 bits, or clamped to ±full scale. Each ADC has a specific offset and gain correction or calibra- tion coefficient associated with it that is stored in MMR-based offset and gain registers (ADCxOF and ADCxGN). The offset and gain registers can be used to remove offsets and gain errors within the part as well as system-level offset and gain errors external to the part. These registers are configured at power-on with a factory- programmed calibration value. These factory-set calibration values vary from part to part, reflecting the manufacturing variability of internal ADC circuits. However, these registers can also be overwritten by user code if the ADC is in idle mode and are automatically overwritten if an offset or gain calibration cycle is initiated by the user through the mode bits in the ADCMDE[2:0] MMR. Two types of automatic calibration are available to the user, namely, self-calibration or system calibration. Self-Calibration In self-calibration of offset errors, the ADC generates its calibration coefficient based on an internally generated 0 V , whereas in self-calibration of gain errors the coefficient is based on the full-scale voltage. Although self-calibration can correct offset and gain errors within the ADC, it cannot compensate for external errors in the system, such as shunt resistor tolerance/drift and external offset voltages. Note that in self-calibration mode, ADC0GN must contain the values for PGA = 1 before a calibration scheme is started. System Calibration In system calibration of offset errors, the ADC generates its calibration coefficient based on an externally generated zero-scale voltage, whereas in system calibration of gain errors the coefficient is based on the full-scale voltage. The calibration coefficient is applied to the external ADC input for the duration of the calibration cycle. The duration of an offset calibration is a single conversion cycle (3/f ADC chop off, 2/fADC chop on) before returning the ADC to idle mode. A gain calibration is a two-stage process and, there- fore, takes twice as long as an offset calibration cycle. When a calibration cycle is initiated, any ongoing ADC conversion is immediately halted, the calibration is automatically performed at the ADC update rate programmed in ADCFLT, and the ADC is always returned to idle after any calibration cycle. It is strongly recommended that ADC calibration be initiated at as low an ADC update rate as possible (and therefore requires a high SF value in ADCFLT) to minimize the impact of ADC noise during calibration. Using the Offset and Gain Calibration If the chop enable bit (ADCFLT[15]) is enabled, internal ADC offset errors are minimized and an offset calibration may not be required. If chopping is disabled, however, an initial offset calibration is required and may need to be repeated, particularly after a large change in temperature. Depending on system accuracy requirements, a gain calibration, especially in the context of the I-ADC (with internal PGA), may need to be performed at all relevant system gain ranges. If it is not possible to apply an external full-scale current on all gain ranges, apply a lower current and then scale the result produced by the calibration. For example, apply a 50% current and then divide the ADC0GN value produced by 2 and write this value back into ADC0GN. Note that there is a lower limit for the input signal that can be applied during a system calibration because ADC0GN is only a 16-bit register. The input span (that is, the difference between the system zero-scale value and the system full-scale value) should be greater than 40% of the nominal full-scale input range (that is, >40% of VREF/gain). The on-chip Flash/EE memory can be used to store multiple calibration coefficients. These calibration coefficients can be copied directly into the relevant calibration registers by user code and are based on the system configuration. In general, the simplest way to use the calibration registers is to let the ADC calculate the values required as part of the ADC automatic calibration modes. A factory-programmed or end-of-line calibration for the I-ADC is a two-step procedure: 1. Apply 0 A current. Configure the ADC in the required PGA setting and write to ADCMDE[2:0] to perform a system zero-scale calibration. This writes a new offset calibration value into ADC0OF. 2. Apply a full-scale current for the selected PGA setting. Write to ADCMDE to perform a system full-scale calibration. This writes a new gain calibration value into ADC0GN.

Rev. B | Page 60 of 136 Understanding the Offset and Gain Calibration Registers The simplified ADC transfer function can be described as The output of a typical block in the ADC signal flow (described in the ADC Sinc3 Digital Filter Response section through the Using the Offset and Gain Calibration section) can be consid- ered a fractional number with a span for a ±full-scale input of approximately ±0.75. The span is less than ±1.0 because there is attenuation in the modulator to accommodate some overrange capacity on the input signal. The exact value of the attenuation varies slightly from part to part because of manufacturing tolerances. NOMREF IN OUT ADCGN ADCGNADCOFV PGA VADC ×⎥ ⎡ × −= where the equation is valid for the voltage/temperature channel ADC. For the current channel ADC, NOMREF IN OUT ADCGN ADCGNADCOF KV PGA VADC ×−= ⎥ ⎡ ×× The offset coefficient is read from the ADC0OF calibration register and is a 16-bit, twos complement number. The range of this number in terms of the signal chain is effectively ±1.0. Therefore, 1 LSB of the ADC0OF register is not the same as 1 LSB of ADC0DAT. where K is dependent on the PGA gain setting and ADC mode. Normal Mode In normal mode, K = 1 for PGA gains of 1, 4, 8, 16, 32, and 64; K = 2 for PGA gains of 2 and 128; K = 4 for a PGA gain of 256; and K = 8 for a PGA gain of 512. A positive value of ADC0OF indicates that when offset is subtracted from the output of the filter, a negative value is added. The nominal value of this register is 0x0000, indicating zero offset is to be removed. The actual offset of the ADC can vary slightly from part to part and at different PGA gains. The offset within the ADC is minimized if the chopping mode is enabled (that is, ADCFLT[15] = 1). Low Power Mode In low power mode, K = 32 for a PGA gain of 128. In addition, if the REG_AVDD/2 reference is used, the K factor doubles. Low Power Plus Mode In low power plus mode, K = 8 for a PGA gain of 512. In addition, if the REG_AVDD/2 reference is used, the K factor doubles. The gain coefficient is read from the AD0GN register and is a unitless scaling factor. The 16-bit value in this register is divided by 16,384 and then multiplied by the offset-corrected value. The nominal value of this register equals 0x5555, corresponding to a multiplication factor of 1.3333, and scales the nominal ±0.75 signal to produce a full-scale output signal of ±1.0. The resulting output signal is checked for overflow/underflow and converted to twos complement or unipolar mode before being output to the data register. ADC DIAGNOSTICS The ADuC7034 features diagnostic capability on both ADCs. Current ADC Diagnostics The ADuC7034 features the capability to detect open-circuit conditions on the application board. This is accomplished using the two current sources on IIN+ and IIN−, which are controlled via ADC0CON[14:13]. The actual gain and the required scaling coefficient for zero gain error varies slightly from part to part at different PGA settings in normal and low power modes. The value downloaded into ADC0GN at a power-on reset represents the scaling factor for a PGA gain of 1. If a different PGA setting is used, however, some gain error may be present. To correct this error, overwrite the calibration coefficients via user code or perform an ADC calibration. Note that the IIN+ and IIN− current sources have a tolerance of ±30%. Therefore, a PGA gain ≥ 2 (ADC0CON[3:0] ≥ 0001) must be used when current sources are enabled. Voltage/Temperature ADC Diagnostics The ADuC7034 features the capability to detect open-circuit conditions on the voltage and temperature channel inputs. This is accomplished using the two current sources on VTEMP and GND_SW , which are controlled via ADC1CON[14:13].

status and the PLL interrupt. core begins executing code as soon as the PLL starts oscillating. divide-by-8 to the locked PLL output. resuming normal code execution. Table 43. PLLSTA MMR Bit Designations between high and low at a frequency of 32.768 kHz. 1 PLL lock status bit. This is a read only bit. Set when the PLL is locked and outputting 20.48 MHz. an fCORE divide-by-8 clock source. Set if the PLL lock status bit signal goes low. Cleared by writing 1 to this bit.

written before and after PLLCON. be written before and after PLLCON. sources as the PLL source clock. Table 44. PLLCON MMR Bit Designations1 7 to 2 Reserved. These bits should be written as 0 by user code. 00 = low power 131 kHz oscillator. 01 = precision 131 kHz oscillator. 10 = external 32.768 kHz crystal.

1 If the user code switches MCU clock sources, a dummy MCU cycle should be

included after the clock switch is written to PLLCON. Function: POWKEY0 is the POWCON prewrite key. key value to be written before and after POWCON. Function: POWKEY1 is the POWCON postwrite key. key value to be written before and after POWCON.

controls the speed of the ARM7TDMI core. Table 45. POWCON MMR Bit Designations 7 Precision 131 kHz input enable. Cleared by the user to power down the precision 131 kHz input enable. Set by the user to enable the external crystal circuitry. Cleared by the user to power down the external crystal circuitry. source remain in normal power mode. Set by default, or set by hardware upon a wake-up event. therefore, Bit 3, Bit 4, and Bit 5 must be cleared simultaneously. GPIO interfaces, and SPI and UART serial ports. driven from the low power oscillator even if this bit is set. and Bit 4 must be cleared simultaneously. LIN can respond to wake-up events even if this bit is cleared. Set by default, or set by hardware on a wake-up event. Cleared to power down the ARM core. 2 to 0 Core clock divider (CD) bits.

trim register are used to implement this feature. at 131 kHz or through a divide-by-4 block generating 32.768 kHz. typical trim range is between 127 kHz and 135 kHz.

• OSC0CON: control bits for calibration.
• OSC0STA: calibration status register.
• OSC0V AL0: 9-bit counter, Counter 0.
• OSC0V AL1: 10-bit counter, Counter 1.
• OSC0TRM: oscillator trim register. A calibration routine flowchart is shown in Figure 30. User code configures and enables the calibration sequence using OSC0CON. When the OSC0V AL0 low power oscillator calibration counter reaches 0x1FF, both counters are disabled. User code then reads back the value of the low power oscillator calibration counter. There are three possible scenarios:
• OSC0V AL0 = OSC0V AL1. No further action is required.
• OSC0V AL0 > OSC0V AL1. The low power oscillator is running slow. OSC0TRM must be decreased.
• OSC0V AL0 < OSC0V AL1. The low power oscillator is running fast. OSC0TRM must be increased. When the value in OSC0TRM is changed, the routine should be run again and the new frequency should be checked. Using the internal precision 131 kHz oscillator requires approximately 4 ms to execute the calibration routine. If the external 32.768 kHz crystal is used, the time increases to 16 ms. Prior to the start of the clock calibration routine, the user must switch the clock source to either the precision 131 kHz oscillator or the external 32.768 kHz watch crystal. If this is not done, the PLL may lose lock each time OSC0TRM is modified, thereby increasing the time required to calibrate the low power oscillator. BEGIN CALIBRATION ROUTINE WHILE OSC0STA[0] = 1 INCREASE OSC0TRM DECREASE OSC0TRM OSC0VAL0 < OSC0VAL1 OSC0VAL0 > OSC0VAL1 END CALIBRATION ROUTINE IS ERROR WITHIN DESIRED LEVEL? OSC0VAL0 = OSC0VAL1 NO YES 07116-028

Figure 30. OSC0TRM Calibration Routine Flowchart

Table 46. OSC0TRM MMR Bit Designations 7 to 4 Reserved. Should be written as 0s. 3 to 0 User-defined trim bits. oscillator calibration routine. Table 47. OSC0CON MMR Bit Designations 7 to 5 Reserved. Should be written as 0. Set to select external 32.768 kHz crystal. Cleared to select internal precision 131 kHz oscillator. Cleared by user code after a calibration reset. Set by user code to clear OSC0VAL1. Cleared by user code after an OSC0VAL1 reset. Set by user code to clear OSC0VAL0. Cleared by user code after an OSC0VAL0 reset. Cleared to abort calibration. low power oscillator calibration routine. Table 48. OSC0STA MMR Bit Designations Set by hardware upon completion of a calibration cycle. Cleared by a read of OSC0VAL1. Set by hardware if calibration is in progress. Cleared by hardware if calibration is completed.

interrupt sources are serviced. IRQSIG[2] is set and can only be cleared by writing to T0CLRI. FIQSTA/IRQSTA[2] is set or an interrupt (FIQ or IRQ) occurs. ARM core can then only be powered up by a reset event. Table 49. IRQ/FIQ MMRs Bit Designations

0 All interrupts OR’ed (FIQ only)

1 SWI: not used in IRQEN/CLR and FIQEN/CLR

2 Timer0 See the Timer0—Lifetime Timer section. 3 Timer1 See the Timer1 section. 4 Timer2 or wake-up timer See the Timer2—Wake-Up Timer section. 5 Timer3 or watchdog timer See the Timer3—Watchdog Timer section. 6 Timer4 or STI timer See the Timer4—STI Timer section. 7 LIN hardware See the LIN (Local Interconnect Network) Interface section. 8 Flash/EE interrupt See the Flash/EE Control Interface section. 9 PLL lock See the ADuC7034 System Clocks section. 10 ADC See the 16-Bit Sigma-Delta Analog-to-Digital Converters section. 11 UART See the UART Serial Interface section. 12 SPI master See the Serial Peripheral Interface section. 13 XIRQ0 (GPIO IRQ0 ) See the General-Purpose I/O section. 14 XIRQ1 (GPIO IRQ1) See the General-Purpose I/O section.

15 Reserved

16 IRQ3 high voltage IRQ High voltage interrupt; see the High Voltage Peripheral Control

17 SPI slave See the Serial Peripheral Interface section. 18 XIRQ4 (GPIO IRQ4) See the General-Purpose I/O section. 19 XIRQ5 (GPIO IRQ5) See the General-Purpose I/O section.

Rev. B | Page 69 of 136 Normal Interrupt (IRQ) Request The IRQ request is the exception signal allowed to enter the processor in IRQ mode. It is used to service general-purpose interrupt handling of internal and external events. All 32 bits of the IRQSTA MMR are OR’ ed to create a single IRQ signal to the ARM7TDMI core. The four 32-bit registers dedicated to IRQ are described in the IRQSIG to IRQSTA sections. IRQSIG Register Name: IRQSIG Address: 0xFFFF0004 Default Value: 0x00000000 Access: Read access only Function: This 32-bit register reflects the current state of all IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, the corresponding bit is cleared. The IRQSIG bits are cleared when the interrupt in the peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSTA Register Name: IRQSTA Address: 0xFFFF0000 Default Value: 0x00000000 Access: Read only Function: IRQSTA provides the status of the IRQ source that is currently enabled (that is, a logic AND of the IRQSIG and IRQEN bits). When a bit in this register is set to 1, the corresponding source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. IRQEN Register Name: IRQEN Address: 0xFFFF0008 Default Value: 0x00000000 Access: Read/write Function: IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception signal. When a bit is set to 0, the corresponding source request is disabled or masked and does not create an IRQ exception signal. The IRQEN register cannot be used to disable an interrupt. IRQCLR Register Name: IRQCLR Address: 0xFFFF000C Access: Write only Function: IRQCLR allows the IRQEN register to clear in order to mask an interrupt source. Each bit set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. When used as a pair of registers, IRQEN and IRQCLR allow independent manipulation of the enable mask without requiring an atomic read-modify-write instruction. Fast Interrupt (FIQ) Request The FIQ request is the exception signal allowed to enter the processor in FIQ mode. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second-level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. All 32 bits of the FIQSTA MMR are OR’ ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. As a side effect, a bit set to 1 in FIQEN clears the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks.

controller and by the user in the IRQSTA/FIQSTA register. programmed source interrupt. Table 50. SWICFG MMR Bit Designations setting/clearing Bit 1 of FIQSTA and FIQSIG. setting/clearing Bit 1 of IRQSTA and IRQSIG. Figure 31. Interrupt Structure

The ADuC7034 features five general-purpose timer/counters.

• Timer0, or the lifetime timer
• Timer1, or general-purpose timer
• Timer2, or the wake-up timer
• Timer3, or the watchdog timer
• Timer4, or the STI timer The five timers in their normal mode of operation can be in either free running mode or periodic mode. Timers are started by writing data to the control register of the corresponding timer (TxCON). The counting mode and speed depend on the configuration chosen in TxCON. In normal mode, an IRQ is generated each time the value of the counter reaches 0 when counting down, or each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing any value to clear the register of that particular timer (TxCLRI). The three timers in their normal mode of operation can be either free-running or periodic. In free-running mode, starting with the value in the TxLD register, the counter decrements/increments from the maximum/ minimum value until zero/full scale and starts again at the maximum/minimum value. This means that, in free-running mode, TxV AL is not reloaded when the relevant interrupt bit is set but the count simply rolls over as the counter underflows or overflows. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero/full scale starts again from this value. This means when the relevant interrupt bit is set, TxV AL is reloaded with TxLD and counting starts again from this value. Loading the TxLD register with zero is not recommended. The value of a counter can be read at any time by accessing its value register (TxV AL). In addition, Timer0, Timer1, and Timer4 each have a capture register (T0CAP , T1CAP , and T4CAP , respectively) that can hold the value captured by an enabled IRQ event. The IRQ events are described in Table 51.

Table 51. Timer Event Capture

0 Timer0, or the lifetime timer

1 Timer1, or general-purpose timer

2 Timer2, or the wake-up timer

3 Timer3, or the watchdog timer

4 Timer4, or the STI timer

5 LIN hardware

6 Flash/EE interrupt

7 PLL lock

8 ADC

9 UART

10 SPI master

11 XIRQ0 (GPIO_0)

12 XIRQ1 (GPIO_5)

13 Reserved

14 IRQ3 high voltage interrupt

15 SPI slave

16 XIRQ4 (GPIO_7); see the General-Purpose I/O section

17 XIRQ5 (GPIO_8); see the General-Purpose I/O section

user MMR interface by the synchronization (SYNC) block.

Rev. B | Page 73 of 136 Starting Timer2 When starting Timer2, it is recommended to first load Timer2 with the required TxLD value. Next, start the timer by setting the T2CON bits as required. This enables the timer, but only once the T2CON bits have been latched internally in the Timer2 clock domain. Therefore, it is advised that a delay of more than three clock periods (that is, 100 μs for a 32 kHz timer clock source) is inserted to allow both the T2LD value and the T2CON value to be latched through the synchronization logic and reach the Timer2 domain. After the delay, it is recommended that any (inadvertent) Timer2 interrupts are now cleared using T2CLRI=0x00. Finally, the Timer2 system interrupt can be unmasked by setting the appro-priate bit in the IRQEN MMR. An example of this code is as follows, where the assumption is that Timer2 is halted: Example Code T2LD = 0x1; //Reload Timer T2CON = 0x02CF; //Enable T2—Low Power Osc, 32768 prescaler Delay(100us); //Include Delay to ensure T2CON bits take effect T2CLRI = 0 ; //*ClearTimerIrq IRQEN = WAKEUP_TIMER_BIT; //Unmask Timer2

Rev. B | Page 74 of 136 TIMER0—LIFETIME TIMER Timer0 is a general-purpose, 48-bit up counter or a 16-bit up/down counter timer with a programmable prescaler. Timer0 can be clocked from either the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. When the core is operating at 20.48 MHz with a prescaler of 1, a minimum resolution of 48.83 ns results. In 48-bit mode, Timer0 counts up from 0. The current counter value can be read from T0V AL0 and T0V AL1. In 16-bit mode, Timer0 can count up or down. A 16-bit value can be written to T0LD to load into the counter. The current counter value is read from T0V AL0. Timer0 has a capture register (T0CAP) that is triggered by a selected IRQ source initial assertion. When the capture register is triggered, the current timer value is copied to T0CAP and the timer continues running. This feature can be used to determine the assertion of an event with more accuracy than would be provided by servicing an interrupt alone. Timer0 reloads the value from T0LD when Timer0 overflows. The Timer0 interface consists of six MMRS.

• T0LD is a 16-bit register holding the 16-bit value that is loaded into the counter. T0LD is only available in 16-bit mode.
• T0CAP is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event. T0CAP is only available in 16-bit mode.
• T0V AL0/T0V AL1 are 16-bit and 32-bit registers that hold the 16 LSBs and 32 MSBs, respectively. T0V AL0 and T0V AL1 are read only registers. In 16-bit mode, 16-bit T0V AL0 is used. In 48-bit mode, both 16-bit T0V AL0 and 32-bit T0V AL1 are used.
• T0CLRI is an 8-bit register. Writing any value to this register clears the interrupt. T0CLRI is only available in 16-bit mode.
• T0CON is a configuration MMR and is described in Table 52. Timer0 Load Register Name: T0LD Address: 0xFFFF0300 Default Value: 0x0000 Access: Read/write Function: T0LD0 is the 16-bit register holding the 16-bit value that is loaded into the counter. This register is only available in 16-bit mode. Timer0 Clear Register Name: T0CLRI Address: 0xFFFF0310 Access: Write only Function: This 8-bit, write only MMR is written (with any value) by user code to clear the interrupt. Timer0 Value Registers Name: T0V AL0, T0V AL1 Address: 0xFFFF0304, 0xFFFF0308 Default Value: 0x0000, 0x00000000 Access: Read access only Function: T0V AL0 and T0V AL1 are 16-bit and 32-bit registers that hold the 16 LSBs and 32 MSBs, respectively. T0V AL0 and T0V AL1 are read only registers. In 16-bit mode, 16-bit T0V AL0 is used. In 48-bit mode, both 16-bit T0V AL0 and 32-bit T0V AL1 are used. Timer0 Capture Register Name: T0CAP Address: 0xFFFF0314 Default Value: 0x0000 Access: Read access only Function: This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event. This register is only available in 16-bit mode.

Figure 34. Timer0 Block Diagram Function: This 32-bit MMR configures the mode of operation for Timer0. Table 52. T0CON MMR Bit Designations Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event number (0 to 17). The events are defined in Table 51. 01 = low power 32.768 kHz oscillator. 10 = external 32.768 kHz watch crystal. 11 = precision 32.768 kHz oscillator. 8 Count up. Available in 16-bit mode only. Set by user for Timer0 to count up. Cleared by user for Timer0 to countdown (default). Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 0 = 16-bit operation (default). 0000 = source clock/1 (default).

minimum resolution of 48.83 ns results. time expressed as hours:minutes:seconds:hundredths. The Timer1 interface consists of five MMRS.

• T1LD, T1V AL, and T1CAP are 32-bit registers and hold 32-bit unsigned integers. T1V AL and T1CAP are read only.
• T1CLRI is an 8-bit register. Writing any value to this register clears the Timer1 interrupt.
• T1CON is a configuration MMR and is described in Table 53. Timer1 features a postscaler that allows the user to count the number of Timer1 timeouts between 1 and 256. To activate the postscaler, the user sets Bit 23 and writes the desired number to count into Bits[24:31] of T1CON. When this number of timeouts is reached, Timer1 generates an interrupt if T1CON[18] is set. Note that if the part is in a low power mode and Timer1 is clocked from the GPIO or low power oscillator source, then Timer1 continues to operate. Timer1 reloads the value from T1LD when Timer1 overflows. Timer1 Load Registers Name: T1LD Address: 0xFFFF0320 Default Value: After a reset, this register contains the upper half of the assembly lot ID. Access: Read/write Function: T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Timer1 Clear Register Name: T1CLRI Address: 0xFFFF032C Access: Write only Function: This 8-bit, write only MMR is written (with any value) by user code to clear the interrupt. Timer1 Value Register Name: T1VAL Address: 0xFFFF0324 Default Value: 0xFFFFFFFF Access: Read only Function: T1V AL is a 32-bit register that holds the current value of Timer1. TIMER1 VALUE LOW POWER 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY GPIO GPIO 32-BIT LOAD 32-BIT UP/DOWN COUNTER 8-BIT POSTSCALER PRESCALER 1, 16, 256, OR 32,768 TIMER1 IRQ 07116-031 CAPTUREIRQ[31:0]

Figure 35. Timer1 Block Diagram

captured by an enabled IRQ event. Table 53. T1CON MMR Bit Designations By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1. By reading these eight bits, the current value of the counter is read. 23 Timer1 enable postscaler. Set to enable the Timer1 postscaler. Cleared to disable the Timer1 postscaler. 22 to 20 Reserved. These bits are reserved and should be written as 0 by user code. 19 Postscaler compare flag. Read only. Set if the number of Timer1 overflows is equal to the number written to the postscaler. Set to select interrupt generation from the postscaler counter. Cleared to select interrupt generation directly from Timer1. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event number (0 to 17). The events are defined in Table 51. 001 = low power 32.768 kHz oscillator. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down (default). Set by user to enable Timer1. Cleared by user to disable Timer1 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). 0000 = source clock/1 (default).

expressed as hours:minutes:seconds:hundredths. Timer2 reloads the value from T2LD when Timer2 overflows. The Timer2 interface consists of four MMRS.

• T2LD and T2V AL are 32-bit registers and hold 32-bit unsigned integers. T2V AL is a read only register.
• T2CLRI is an 8-bit register. Writing any value to this register clears the Timer2 interrupt.
• T2CON is a configuration MMR and is described in Table 54. Timer2 Load Register Name: T2LD Address: 0xFFFF0340 Default Value: 0x00000000 Access: Read/write Function: T2LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Timer2 Clear Register Name: T2CLRI Address: 0xFFFF034C Access: Write only Function: This 8-bit, write only MMR is written (with any value) by user code to clear the interrupt. Timer2 Value Register Name: T2VAL Address: 0xFFFF0344 Default Value: 0xFFFFFFFF Access: Read only Function: T2V AL is a 32-bit register that holds the current value of Timer2. TIMER2 IRQ32-BIT UP/DOWN COUNTER PRECISION 32.768kHz OSCILLATOR LOW POWER 32.768kHz OSCILLATOR CORE CLOCK 32-BIT LOAD PRESCALER 1, 16, 256, OR 32,768 EXTERNAL 32.768kHz WATCH CRYSTAL TIMER2 VALUE 07116-032

Figure 36. Timer2 Block Diagram

Function: This 16-bit MMR configures the mode of operation of Timer2. Table 54. T2CON MMR Bit Designations 10 to 9 Clock source select. 01 = low power 32.768 kHz oscillator. 10 = external 32.768 kHz watch crystal. 11 = precision 32.768 kHz oscillator. Set by user for Timer2 to count up. Cleared by user for Timer2 to count down (default). Set by user to enable Timer2. Cleared by user to disable Timer2 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). These bits are only valid with a 32 kHz clock. 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). These bits are only valid with a 32 kHz clock. 0000 = source clock/1 (default). format. See the formats listed for the 10 and 11 settings of Bits[5:4] in this table.

Timer3 reloads the value from T3LD when Timer3 overflows. maximum prescaler/256 and full scale in T3LD. reloads the counter with T3LD and begins a new timeout period. should only configure a minimum timeout period of 30 ms. power-down. This can be disabled by setting Bit 0 in T3CON. the watchdog timer continues to count during power-down.

• T3CON is a configuration MMR and is described in Table 55.
• T3LD and T3V AL are 16-bit registers and hold 16-bit unsigned integers. T3V AL is a read only register.
• T3CLRI is an 8-bit register. Writing any value to this register clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode. Timer3 Load Register Name: T3LD Address: 0xFFFF0360 Default Value: 0x0040 Access: Read/write Function: This 16-bit MMR holds the Timer3 reload value. Timer3 Clear Register Name: T3CLRI Address: 0xFFFF036C Access: Write only Function: This 8-bit, write only MMR is written (with any value) by user code to refresh (reload) Timer3 in watchdog mode to prevent a watchdog timer reset event. Timer3 Value Register Name: T3VAL Address: 0xFFFF0364 Default Value: 0x0040 Access: Read only Function: This 16-bit, read only MMR holds the current Timer3 count value. PRESCALER 1, 16, 256 TIMER3 IRQ WATCHDOG RESET16-BIT UP/DOWN COUNTER LOW POWER 32.768kHz 16-BIT LOAD TIMER3 VALUE 07116-033

Figure 37. Timer3 Block Diagram

Function: This 16-bit MMR configures the mode of operation of Timer3 as described in Table 55. Table 55. T3CON MMR Bit Designations 15 to 9 Reserved. These bits are reserved and should be written as 0 by user code. 8 Count up/count down enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. Set by user code to enable Timer3. Cleared by user code to disable Timer3. Set by user code to configure Timer3 to operate in periodic mode. Cleared by user to configure Timer3 to operate in free running mode. 5 Watchdog timer mode enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. 4 Reserved. This bit is reserved and should be written as 0 by user code. 3 to 2 Timer3 clock (32.768 kHz) prescaler. 00 = source clock/1 (default). 1 Watchdog timer IRQ enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. Set by user code to stop Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR. Cleared by user code to enable Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR.

determine the assertion of an event with increased accuracy.

• T4LD, T4V AL, and T4CAP are 16-bit registers and hold 16-bit unsigned integers. T4V AL and T4CAP are read only registers.
• T4CLRI is an 8-bit register. Writing any value to this register clears the interrupt.
• T4CON is a configuration MMR and is described in Table 56. Timer4 Load Register Name: T4LD Address: 0xFFFF0380 Default Value: 0x00000 Access: Read/write Function: This 16-bit register holds the 16-bit value that is loaded into the counter. Timer4 Clear Register Name: T4CLRI Address: 0xFFFF038C Access: Write only Function: This 8-bit, write only MMR is written (with any value) by user code to clear the interrupt. Timer4 Value Register Name: T4VAL Address: 0xFFFF0384 Default Value: 0xFFFF Access: Read only Function: This 16-bit register holds the current value of Timer4. Time4 Capture Register Name: T4CAP Address: 0xFFFF0390 Default Value: 0x0000 Access: Read only Function: This 16-bit register holds the 32-bit value captured by an enabled IRQ event. Timer4 Control Register Name: T4CON Address: 0xFFFF0388 Default Value: 0x00000000 Access: Read/write Function: This 32-bit MMR configures the mode of operation of Timer4. PRESCALER 1, 16, 256, OR 32768 STI TIMER4 IRQ 16-BIT LOAD LOW POWER 32.768kHz OSCILLATOR 16-BIT UP/DOWN COUNTERCORE CLOCK FREQUENCY TIMER4 VALUE CAPTUREIRQ[31:0] 07116-034

Figure 38. Timer4 Block Diagram

Table 56. T4CON MMR Bit Designations Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event number (0 to 17). The events are defined in Table 51. 1 = low power 32.768 kHz oscillator. Set by user for Timer4 to count up. Cleared by user for Timer4 to count down (default). Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 0000 = source clock/1 (default).

and a source capability of 0.1 mA. Table 57. A typical GPIO structure is shown Figure 39. one CD-divided core clock to guarantee recognition.

• GPxCON: Portx control register
• GPxDAT: Portx configuration and data register
• GPxSET: Data set Portx
• GPxCLR: Data clear Portx where x corresponds to the port number (0, 1, or 2). During normal operation, user code can control the function and state of the external GPIO pins by these general-purpose registers. All GPIO pins retain their external level (high or low) during power-down (POWCON) mode. 1ONLY AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8. GPIO REG_DVDD OUTPUT DRIVE ENABLE GPxDAT[31:24] OUTPUT DATA GPxDAT[23:16] INPUT DATA GPxDAT[7:0] GPIO IRQ1 07116-035

Figure 39. ADuC7034 GPIO

Table 57. External GPIO Pin to Internal Port Signal Assignments Port0 GPIO_0 P0.0 General-purpose I/O. SS Slave select I/O for SPI. GPIO_1 P0.1 General-purpose I/O. SCLK Serial clock I/O for SPI. GPIO_2 P0.2 General-purpose I/O. MISO Master input, slave output for SPI. GPIO_3 P0.3 General-purpose I/O. MOSI Master output, slave input for SPI. P 0.51 High voltage serial interface. P 0.61 High voltage serial interface. Port1 GPIO_5 P1.0 General-purpose I/O. GPIO_6 P1.1 General-purpose I/O. Port2 GPIO_7 P2.0 General-purpose I/O. IRQ4 External Interrupt Request 4. LIN Output Pin. Used to read directly from LIN pin for conformance testing. GPIO_8 P2.1 General-purpose I/O. IRQ5 External Interrupt Request 5. LIN HV Input Pin. Used to directly drive LIN pin for conformance testing. GPIO_11 2 P2.42 General-purpose I/O. GPIO_12 2 P2.52 General-purpose I/O. GPIO_13 1 P2.6 1 General-purpose I/O, STI data output. readback (GPIO_11) capability.

Function: This 32-bit MMR selects the pin function for each Port0 pin. Table 58. GP0CON MMR Bit Designations 31 to 29 Reserved. These bits are reserved and should be written as 0 by user code. 28 Reserved. This bit is reserved and should be written as 1 by user code. 27 to 25 Reserved. These bits are reserved and should be written as 0 by user code. indirectly access the high voltage serial interface. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. indirectly access the high voltage serial interface. 19 to 17 Reserved. These bits are reserved and should be written as 0 by user code. 16 GPIO_4 function select bit. Set to 1 by user code to configure the GPIO_4 pin as ECLK, enabling a 2.56 MHz clock output on this pin. Cleared by user code to 0 to configure the GPIO_4 pin as a general-purpose I/O (GPIO) pin. 15 to 13 Reserved. These bits are reserved and should be written as 0 by user code. 12 GPIO_3 function select bit. Set to 1 by user code to configure the GPIO_3 pin as MOSI (master output, slave input) data for the SPI port. Cleared by user code to 0 to configure the GPIO_3 pin as a general-purpose I/O (GPIO) pin. 11 to 9 Reserved. These bits are reserved and should be written as 0 by user code. 8 GPIO_2 Function Select Bit. Set to 1 by user code to configure the GPIO_2 pin as MISO (master input, slave output) data for the SPI port. Cleared to 0 by user code to configure the GPIO_2 pin as a general-purpose I/O (GPIO) pin. 7 to 5 Reserved. These bits are reserved and should be written as 0 by user code. 4 GPIO_1 function select bit. Set to 1 by user code to configure the GPIO_1 pin as SCLK I/O for the SPI port. Cleared to 0 by user code to configure the GPIO_1 pin as a general-purpose I/O (GPIO) pin. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_0 function select bit. Set to 1 by user code to configure the GPIO_0 pin as SS I/O for the SPI port. Cleared to 0 by user code to configure the GPIO_0 pin as a general-purpose I/O (GPIO) pin.

Function: This 32-bit MMR selects the pin function for each Port1 pin. Table 59. GP1CON MMR Bit Designations 31 to 5 Reserved. These bits are reserved and should be written as 0 by user code. 4 GPIO_6 function select bit. Set to 1 by user code to configure the GPIO_6 pin as TxD, the transmit data for the UART serial port. Cleared by user code to 0 to configure the GPIO_6 pin as a general-purpose I/O (GPIO) pin. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_5 function select bit. Set by user code to 1 to configure the GPIO_5 pin as RxD, the receive data for the UART serial port. Cleared by user code to 0 to configure the GPIO_5 pin as a general-purpose I/O (GPIO) pin.

Function: This 32-bit MMR selects the pin function for each Port2 pin. Table 60. GP2CON MMR Bit Designations 31 to 25 Reserved. These bits are reserved and should be written as 0 by user code. 24 GPIO_13 function select bit. Set to 1 by user code to route the STI data output to the STI pin. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. 20 GPIO_12 function select bit. Set to 1 by user code to route the UART TxD (transmit data) to the LIN/BSD data pin. This configuration is used in LIN mode. 19 to 17 Reserved. These bits are reserved and should be written as 0 by user code. 16 GPIO_11 function select bit. logic and to the UART RxD (receive data). This mode must be configured by user code when using LIN or BSD modes. support diagnostic readback on all external high voltage I/O pins (see HVCFG1[2:0]). 15 to 5 Reserved. These bits are reserved and should be written as 0 by user code. 4 GPIO_8 function select bit. transceiver interface as a standalone component without any interaction from MCU or UART. Cleared to 0 by user code to configure the GPIO_8 pin as a general-purpose I/O (GPIO) pin. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_7 function select bit. interaction from MCU or UART. Cleared to 0 by user code to configure the GPIO_7 pin as a general-purpose I/O (GPIO) pin.

output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 61. GP0DAT MMR Bit Designations 31 to 29 Reserved. These bits are reserved and should be written as 0 by user code. 28 Port0.4 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port0.4 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.4 as an input. 27 Port0.3 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port0.3 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.3 as an input. 26 Port0.2 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port0.2 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.2 as an input. 25 Port0.1 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port0.1 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.1 as an input. 24 Port0.0 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port0.0 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.0 as an input. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. 20 Port0.4 data output. The value written to this bit appears directly on the GPIO pin assigned to Port0.4. 19 Port0.3 data output. The value written to this bit appears directly on the GPIO pin assigned to Port0.3. 18 Port0.2 data output. The value written to this bit appears directly on the GPIO pin assigned to Port0.2. 17 Port0.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port0.1. 16 Port0.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port0.0. 15 to 5 Reserved. These bits are reserved and should be written as 0 by user code.

output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 62. GP1DAT MMR Bit Designations 31 to 26 Reserved. These bits are reserved and should be written as 0 by user code. 25 Port1.1 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port1.1 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port1.1 as an input. 24 Port1.0 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port1.0 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port1.0 as an input. 23 to 18 Reserved. These bits are reserved and should be written as 0 by user code. 17 Port1.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port1.1. 16 Port1.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port1.0. 15 to 2 Reserved. These bits are reserved and should be written as 0 by user code.

output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 63. GP2DAT MMR Bit Designations 31 Reserved. This bit is reserved and should be written as 0 by user code. 30 Port2.6 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port2.6 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port2.6 as an input. 29 Port2.5 direction select bit. diagnostic write capability to the high voltage I/O pins. Cleared to 0 by user code to configure the GPIO pin assigned to Port2.5 as an input. 28 Port2.4 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port2.4 as an output. diagnostic readback capability from the high voltage I/O pins (see HVCFG1[2:0]). 27 to 26 Reserved. These bits are reserved and should be written as 0 by user code. 25 Port2.1 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port2.1 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port2.1 as an input. 24 Port2.0 direction select bit. Set to 1 by user code to configure the GPIO pin assigned to Port2.0 as an output. Cleared to 0 by user code to configure the GPIO pin assigned to Port2.0 as an input. 23 Reserved. This bit is reserved and should be written as 0 by user code. 22 Port2.6 data output. The value written to this bit appears directly on the GPIO pin assigned to Port2.6. 21 Port2.5 data output. The value written to this bit appears directly on the GPIO pin assigned to Port2.5. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. 17 Port2.1 data output. The value written to this bit appears directly on the GPIO pin assigned to Port2.1. 16 Port2.0 data output. The value written to this bit appears directly on the GPIO pin assigned to Port2.0. 15 to 7 Reserved. These bits are reserved and should be written as 0 by user code. 3 to 2 Reserved. These bits are reserved and should be written as 0 by user code.

code requires when using GP0DAT). Table 64. GP0SET MMR Bit Designations 31 to 21 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_4 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_4 pin. Set to 1 by user code to set the external GPIO_3 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_3 pin. Set to 1 by user code to set the external GPIO_2 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_2 pin. Set to 1 by user code to set the external GPIO_1 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_1 pin. Set to 1 by user code to set the external GPIO_0 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_0 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. code requires when using GP1DAT). Table 65. GP1SET MMR Bit Designations 31 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_6 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin. Set to 1 by user code to set the external GPIO_5 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

requires when using GP2DAT). Table 66. GP2SET MMR Bit Designations 31 to 23 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_13 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_13 pin. Set to 1 by user code to set the external GPIO_12 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_12 pin. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_8 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin. Set to 1 by user code to set the external GPIO_7 pin high. Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. requires when using GP0DAT). Table 67. GP0CLR MMR Bit Designations 31 to 21 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_4 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_4 pin. Set to 1 by user code to clear the external GPIO_3 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_3 pin. Set to 1 by user code to clear the external GPIO_2 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_2 pin. Set to 1 by user code to clear the external GPIO_1 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_1 pin. Set to 1 by user code to clear the external GPIO_0 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_0 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

requires when using GP1DAT). Table 68. GP1CLR MMR Bit Designations 31 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_6 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin. Set to 1 by user code to clear the external GPIO_5 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. requires when using GP2DAT). Table 69. GP2CLR MMR Bit Designations 31 to 23 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_13 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin. Set to 1 by user code to clear the external GPIO_12 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_8 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin. Set to 1 by user code to clear the external GPIO_7 pin low. Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

name suggests) indirectly via the HVCON and HVDAT MMRs. read/write command is complete.

• Precision os
• Wa ke-up ( WU) pin f
• Power supply monitor (PSM)
• Low voltage flag (LVF)
• LIN operating modes
• STI diagnostics
• High voltage dia
• High voltage attenuator-b
• High voltage (HV) temperature monitor ARM7 MCU AND PERIPHERALS HIGH VOLTAGE INTERFACE MMRs HVCON HVDAT PRECISION OSCILLATORHVCFG0[6] LVFHVCFG0[2] LIN MODES PSMHVCFG0[3] ATTENUATOR AND BUFFERHVCFG1[5] HVCFG1[7] HV TEMP MONITOR HVCFG1[6] HVCFG1[3] HVCFG0 (INDIRECT) HIGH VOLTAGE REGISTERS HVCFG1 HVSTA HVMON SERIAL INTERFACE CONTROLLER SERIAL DATA SERIAL CLOCK HIGH VOLTAGE INTERRUPT CONTROLLER PSM—HVSTA[5] WU—HVSTA[4] OVER TEMP—HVSTA[3] LIN S-SCT—HVSTA[2] STI S-SCT—HVSTA[1] WU S-SCT—HVSTA[0] IRQ3 (IRQEN[16]) HIGH VOLTAGE DIAGNOSTIC CONTROLLER WU DIAGNOSTIC INPUT HVCFG0[4] STI DIAGNOSTIC INPUT P2.6 LIN DIAGNOSTIC INPUT P2.5 WU DIAGNOSTIC OUTPUT HVMON[7] STI DIAGNOSTIC OUTPUT HVMON[5] LIN DIAGNOSTIC OUTPUT P2.4 HVCFG0[5] HVCFG0[1:0] WU I/O CONTROL HVCFG0[4] HVCFG1[4] HVCFG1[4] STI I/O CONTROL HVCFG1[3] 07116-036

Figure 40. High Voltage Interface, Top-Level Block Diagram

HVDAT register is used to store data to be written to or read back from the indirect registers. Table 70. HVCON MMR Write Bit Designations 0x00 = read back the HVCFG0 high voltage register into HVDAT. 0x01 = read back the HVCFG1 high voltage register into HVDAT. 0x02 = read back the HVSTA high voltage status register into HVDAT. 0x03 = read back the HVMON high voltage status register into HVDAT. 0x08 = write the value in HVDAT to the HVCFG0 high voltage register. 0x09 = write the value in HVDAT to the HVCFG1 high voltage register. Table 71. HVCON MMR Read Bit Designations 2 Transmit command to high voltage die status. 1 = command completed successfully. 1 Read command from high voltage die status. 1 = command completed successfully. as described in this table, should not be written to HVCON unless busy = 0. 1 = high voltage interface is busy and has not completed the previous command written to HVCON. Bit 1 and Bit 2 are not valid. 0 = high voltage interface is not busy and has completed the command written to HVCON. Bit 1 and Bit 2 are valid.

high voltage interface registers. Table 72. HVDAT MMR Bit Designations 11 to 8 Command with which HVDAT[7:0] high voltage data is associated. These bits are read only and should be written as 0s. 0x00 = read back the HVCFG0 high voltage register into HVDAT. 0x01 = read back the HVCFG1 high voltage register into HVDAT. 0x02 = read back the HVSTA high voltage status register into HVDAT. 0x03 = read back the HVMON high voltage status register into HVDAT. 0x08 = write the value in HVDAT to the HVCFG0 high voltage register. 0x09 = write the value in HVDAT to the HVCFG1 high voltage register. 7 to 0 High voltage data to read/write.

written to or read from this register via the HVDAT MMR. Table 73. HVCFG0 Bit Designations 7 Wake-up/STI thermal shutdown disable. Set to 1 to disable the automatic shutdown of the wake/STI driver when a thermal event occurs. Cleared to 0 to enable the automatic shutdown of the wake/STI driver when a thermal event occurs. 6 Precision oscillator enable bit. voltage interface latency of 10 μs). Cleared to 0 to power down the precision 131 kHz oscillator. 5 Bit serial device (BSD) mode enable bit. Set to 1 to disable the internal (LIN) pull-up and to configure the LIN/BSD pin for BSD operation. Cleared to 0 to enable an internal (LIN) pull-up resistor on the LIN/BSD pin. Set to 1 to assert the external WU pin high. Cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor. 3 Power supply monitor (PSM) enable bit. generates an interrupt if the voltage at the VDD pin drops below 6.0 V. Cleared to 0 to disable the power supply (voltage at the VDD pin) monitor. 2 Low voltage flag (LVF) enable bit. determine if the REG_DVDD voltage previously dropped below 2.1 V. Cleared to 0 to disable the LVF function. 1 to 0 LIN operating mode. These bits enable/disable the LIN driver. 01 = reserved (not LIN V2.0 compliant).

written to or read from this register via the HVDAT MMR. Table 74. HVCFG1 Bit Designations 7 Voltage attenuator diagnostic enable bit. Set to 1 to turn on a 1.29 μA current source, which adds 170 mV differential voltage to the voltage channel measurement. Cleared to 0 to disable the voltage attenuator diagnostic. negative temperature coefficient of typically −2.1 mV/°C. monitor is routed directly to the voltage channel ADC. Cleared to 0 to disable the on-chip high voltage temperature monitor. 5 Voltage channel short enable bit. allows noise to be measured as a self-diagnostic test. Cleared to 0 to disable an internal short on the voltage channel. 4 WU and STI readback enable bit. monitored via the HVMON register (HVMON[7] and HVMON[5]). Cleared to 0 to disable input capability on the external WU/STI pins. 3 High voltage I/O driver enable bit. to clear any pending interrupt generated by the short-circuit event and to re-enable the high voltage I/O pins. 2 Enable/disable short-circuit protection (LIN/BSD and STI). does not disable the short-circuiting pin. circuiting pin. When disabled, the I/O pin can only be re-enabled by writing to HVCFG1[3]. 1 WU pin timeout (monoflop) counter enable/disable. Set to disable the WU I/O timeout counter. 0 WU open-circuit diagnostic enable. Cleared to disable an internal WU I/O diagnostic pull-up resistor.

back from this register via the HVDAT MMR. Table 75. HVMON Bit Designations 7 WU pin diagnostic readback. When enabled via HVCFG1[4], this read only bit reflects the state of the external WU pin. 0 = a thermal shutdown event has not occurred. 1 = a thermal shutdown event has occurred. 5 STI pin diagnostic readback. When enabled via HVCFG1[4], this read only bit reflects the state of the external STI pin. 0 = the voltage channel ADC input buffer is disabled. 1 = the voltage channel ADC input buffer is enabled. 3 Low voltage flag status bit. Only valid if enabled via HVCFG0[2]. 0 (on power-on) = REG_DVDD has dropped below 2.1 V. In this state, RAM contents can be deemed corrupt. cleared by re-enabling the low voltage flag in HVCFG0[2]. 2 LIN/BSD short-circuit status flag. 0 = the LIN/BSD driver is operating normally. 1 = the LIN/BSD driver has experienced a short-circuit condition and is cleared automatically by writing to HVCFG1[3]. 1 STI short-circuit status flag. 0 = the STI driver is operating normally. 1 = the STI driver has experienced a short-circuit condition, and it is cleared automatically by writing to HVCFG1[3]. 0 Wake-up short-circuit status flag. 0 = the wake-up driver is operating normally. 1 = the wake-up driver has experienced a short-circuit condition.

high voltage status register (HVSTA) into the HVDAT register. Table 76. HVSTA Bit Designations 7 to 6 Reserved. These bits should not be used and are reserved for future use. 5 PSM status. Only valid if enabled via HVCFG0[3]. This bit is not latched and the IRQ needs to be enabled to detect it. 0 = the voltage at the VDD pin stays above 6.0 V. 1 = the voltage at the VDD pin drops below 6.0 V. that a rising or falling edge transition on the WU pin generated a high voltage interrupt. 3 Overtemperature. This bit is always enabled. 0 = a thermal shutdown event has not occurred. disabled after a thermal shutdown occurs. 2 LIN/BSD short-circuit status flag. 0 = normal LIN/BSD operation. This bit is cleared automatically by reading the HVSTA register. 1 = a LIN/BSD short circuit is detected. In this condition, the LIN driver is automatically disabled. 1 STI short-circuit status flag. 0 = the STI driver is operating normally and is cleared automatically by reading the HVSTA register. 1 = the STI driver has experienced a short-circuit condition. 0 Wake-up short-circuit status flag. 0 = normal wake-up operation. 1 = a wake-up short circuit is detected.

internal 10 kΩ pull-down resistor and high-side FET driver. output by writing directly to HVCFG0[4]. the High Voltage Peripheral Control Interface section). the wake-up driver should be disabled after 1.3 sec. a high voltage interrupt is generated and HVMON[0] is set. is above or below a typical voltage of 3 V. Figure 41. WU Circuit, Block Diagram

An interrupt controller is integrated in the high voltage circuits. (IRQ3) signal and interrupt the MCU core. 10 μs to indicate that the HVSTA contents are available in HVDAT. the appropriate action can be taken. or by disabling the LVF functionality using HVCFG0[2]. STI pin, as described in Table 77. Table 77. High Voltage Diagnostics more than 100 mA is continuously drawn. Drive LIN or STI high LIN or STI readback is low. Drive WU low Readback high in HVMON[7]. than 100 mA typically is sourced.

conversion on data characters received from the ARM7TDMI. accuracy baud rate generation and a network addressable mode. GPIO_6/TxD pins of the ADuC7034. options selectable in the configuration register. fractional divider baud rate generation. Table 78 lists common baud rate values. Table 78. Baud Rate Using the Standard Baud Rate Generator erator allows the generation of accurate, high speed baud rates. Figure 42. Fractional Divider Baud Rate Generation an input by a nonwhole number M.N. divides an input by a nonwhole number M.N. Table 79 lists common baud rate values. Table 79. Baud Rate Using the Fractional Baud Rate Generator

Rev. B | Page 105 of 136 UART REGISTER DEFINITION The UART interface consists of the following nine registers:

• COMTX: 8-bit transmit register
• COMRX: 8-bit receive register
• COMDIV0: divisor latch (low byte)
• COMDIV1: divisor latch (high byte)
• COMCON0: line control register
• COMSTA0: line status register
• COMIEN0: interrupt enable register
• COMIID0: interrupt identification register
• COMDIV2: 16-bit fractional baud divider register COMTX, COMRX, and COMDIV0 share the same address location. COMTX and COMRX can be accessed when Bit 7 in the COMCON0 register is cleared, and COMDIV0 can be accessed when Bit 7 of COMCON0 is set. UART TX Register Name: COMTX Address: 0xFFFF0700 Access: Write only Function: Write to this 8-bit register to transmit data using the UART . UART RX Register Name: COMRX Address: 0xFFFF0700 Default Value: 0x00 Access: Read only Function: This 8-bit register is read from to receive data transmitted using the UART . UART Divisor Latch Register 0 Name: COMDIV0 Address: 0xFFFF0700 Default Value: 0x00 Access: Read/write Function: This 8-bit register contains the LSB of the divisor latch that controls the baud rate at which the UART operates. UART Divisor Latch Register 1 Name: COMDIV1 Address: 0xFFFF0704 Default Value: 0x00 Access: Read/write Function: This 8-bit register contains the MSB of the divisor latch that controls the baud rate at which the UART operates. UART Control Register 0 Name: COMCON0 Address: 0xFFFF070C Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the operation of the UART in conjunction with COMCON1.

Table 80. COMCON0 MMR Bit Designations 7 DLAB Divisor latch access. Set by user to enable access to COMDIV0 and COMDIV1. Set by user to force TxD to 0. Cleared to operate in normal mode. 5 SP Stick parity. Set by user to force parity to defined values. 4 EPS Even parity select bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. number of stop bits selected. Cleared by the user to generate 1 stop bit in the transmitted data. 1 to 0 WLS Word length select. Function: This 8-bit register controls the operation of the UART in conjunction with COMCON0. Table 81. COMCON1 MMR Bit Designations 00 = RxD driven by LIN input; required for LIN communications using the LIN pin. 10 = RxD driven by GP5; required for serial communication using GPIO_5 pin (RxD). 4 LOOPBACK Loopback. Set by user to enable loopback mode. In loopback mode, the TxD is forced high. 3 to 0 N/A Reserved. Not used.

Function: This 8-bit read only register reflects the current status of UART. Table 82. COMSTA0 MMR Bit Designations 6 TEMT COMTX and shift register empty status bit. transmitted, that is, no more data is present in the shift register. Cleared automatically by writing to COMTX. 5 THRE COMTX empty status bit. previous data might not have been transmitted yet and may still be present in the shift register. Cleared automatically by writing to COMTX. Set when SIN is held low for more than the maximum word length. Set when the stop bit is invalid. Set when a parity error occurs. Set automatically if data is overwritten before being read. Set automatically when COMRX is full.

Function: The 8-bit register enables and disables the individual UART interrupt sources. Table 83. COMIEN0 MMR Bit Designations 7 to 4 N/A Reserved. Not used. 3 N/A Reserved. This bit should be written as 0. 2 ELSI RxD status interrupt enable bit. Set by the user to enable generation of an interrupt if any of the COMSTA0[3:1] register bits are set. 1 ETBEI Enable transmit buffer empty interrupt. 0 ERBFI Enable receive buffer full interrupt. Set by the user to enable an interrupt when the buffer is full during a reception. Function: This 8-bit register reflects the source of the UART interrupt. Table 84. COMIID0 MMR Bit Designations

Function: This 16-bit register controls the operation of the fractional divider for the ADuC7034. Table 85. COMDIV2 MMR Bit Designations 15 FBEN Fractional baud rate generator enable bit. Set by the user to enable the fractional baud rate generator. Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator. the M fractional divider and Table 79 for common baud rate values. divider and Table 79 for common baud rate values.

Rev. B | Page 110 of 136 SERIAL PERIPHERAL INTERFACE The ADuC7034 features a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. In master mode, polarity and phase of the clock is controlled by the SPICON register, and the bit rate is defined in the SPIDIV register using the SPI baud rate calculation as follows: ) 1 ( 2 MHz 48 . 20 SPIDIVf CLOCKSERIAL + ×= (3) The SPI interface is only operational with core clock divider bits (POWCON[2:0] = 0 or 1). The maximum speed of the SPI clock is dependent on the clock divider bits and is summarized in Table 87. The SPI port can be configured for master or slave operation and consists of four pins that are multiplexed with four GPIOs. The four SPI pins are MISO, MOSI, SCLK, and SS (see ). Table 86 Table 87. SPI Speed vs. Clock Divider Bits in Master Mode Setting of CD Bits SPIDIV Maximum SCLK (MHz) Table 86. SPI Output Pins

Description

1 0x0B 0.833 GPIO_0 SS Slave select In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data of up to 5.12 Mb from an external master when CD = 0. The formula to determine the maximum speed is as follows: GPIO_1 SCLK Serial clock GPIO_2 MISO Master input, slave output GPIO_3 MOSI Master output, slave input HCLK CLOCKSERIAL ff = 1 The GPIO pins have multiple functions that can be configured by user code. By default, however, the GPIO pins are configured in GPIO mode. In both master and slave modes, data is transmitted on one edge of the SCL signal and sampled on the other. Therefore, it is important to use the same polarity and phase configurations for the master and slave devices. MISO PIN The MISO (master input, slave output) pin is configured as an input line in master mode and as an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first. SS PIN In SPI slave mode, a transfer is initiated by the assertion of SS, an active low input signal. The SPI port transmits and receives eight bits of data, and then the transfer is concluded by the deassertion of SS. In slave mode, SS is always an input. MOSI PIN The MOSI (master output, slave input) pin is configured as an output line in master mode and as an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first. SPI REGISTER DEFINITIONS The following MMR registers are used to control the SPI interface:

• SPICON: 16-bit control register SCLK PIN • SPISTA: 8-bit, read only status register The SCLK (master serial clock) pin is used to synchronize the data being transmitted and received through the MOSI SCLK period. Therefore, a byte is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output in master mode and as an input in slave mode.
• SPIDIV: 8-bit, serial clock divider register
• SPITX: 8-bit, write only transmit register
• SPIRX: 8-bit, read only receive register

Function: The 16-bit MMR configures the serial peripheral interface. Table 88. SPICON MMR Bit Designations 12 Continuous transfer enable. the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty. exists in the SPITX register, a new transfer is initiated after a stall period. Set by the user to connect MISO to MOSI and test software. Cleared by the user to be in normal mode. Set by the user to enable the slave output. Cleared by the user to disable slave output. 9 Slave select input enable. Set by the user in master mode to enable the output. Cleared by user code to disable the output. 8 SPIRX overflow overwrite enable. Set by the user; the valid data in the SPIRX register is overwritten by the new serial byte received. Cleared by the user; the new serial byte received is discarded. Set by the user to transmit the previous data. Cleared by the user to transmit 0. 6 Transfer and interrupt mode (master mode). Set by the user to initiate a transfer with a write to the SPITX register. An interrupt occurs when SPITX is empty. Cleared by the user to initiate a transfer with a read of the SPIRX register. An interrupt occurs when SPIRX is full. 5 LSB first transfer enable bit. Set by the user; the LSB is transmitted first. Cleared by the user; the MSB is transmitted first. 3 Serial clock polarity mode bit. Set by the user; the serial clock idles high. Cleared by the user; the serial clock idles low. 2 Serial clock phase mode bit. Set by the user; the serial clock pulses at the beginning of each serial bit transfer. Cleared by the user; the serial clock pulses at the end of each serial bit transfer. Set by the user to enable master mode. Cleared by the user to enable slave mode. Set by the user to enable the SPI. Cleared by the user to disable the SPI.

Function: The 8-bit MMR represents the current status of the serial peripheral interface. Table 89. SPISTA MMR Bit Designations 5 SPIRX data register overflow status bit. Set if SPIRX is overflowing. Cleared by reading the SPIRX register. Set automatically if Bit 3 or Bit 5 is set. Cleared by reading the SPIRX register. 3 SPIRX data register full status bit. Set automatically if valid data is present in the SPIRX register. Cleared by reading the SPIRX register. 2 SPITX data register underflow status bit. Set automatically if SPITX is underflowing. Cleared by writing in the SPITX register. Set automatically if Bit 0 is cleared or Bit 2 is set. Cleared by either writing in the SPITX register or, if the transmission is finished, by disabling the SPI. 0 SPITX data register empty status bit. Set by writing to SPITX to send data. This bit is set during transmission of data. Cleared when SPITX is empty.

Rev. B | Page 113 of 136 SPI Receive Register Name: SPIRX Address: 0xFFFF0A04 Default Value: 0x00 Access: Read only Function: This 8-bit MMR contains the data received using the serial peripheral interface. SPI Transmit Register Name: SPITX Address: 0xFFFF0A08 Access: Write only Function: Write to this 8-bit MMR to transmit data using the serial peripheral interface. SPI Divider Register Name: SPIDIV Address: 0xFFFF0A0C Default Value: 0x1B Access: Read/write Function: The 8-bit MMR represents the frequency at which the serial peripheral interface is oper- ating. For more information on the calculation of the baud rate, refer to Equation 3.

diagnostics of finished production units. The STI port transmits from 1 to 6 bytes of data in 12-bit packets. baud rate is determined by the overflow rate of Timer4. The STI port is configured and controlled via six MMRs.

• STIKEY0: Serial Test Interface Key 0
• STIKEY1: Serial Test Interface Key 1
• STIDAT0: Data0 (16-bit) holds two bytes
• STIDAT1: Data1 (16-bit) holds two bytes
• STIDAT2: Data2 (16-bit) holds two bytes
• STICON: Controls the serial test interface SERIAL TEST INTERFACE REGISTERS Serial Test Interface Key0 Register Name: STIKEY0 Address: 0xFFFF0880 Access: Write only Function: The STIKEY0 MMR is used in conjunction with the STIKEY1 MMR to protect the STICON MMR. STIKEY0 must be written with 0x0007 immediately before any attempt is made to write to STICON. STIKEY1 must be written with 0x00B9 immediately after STICON is written to ensure that the STICON write sequence has completed successfully. If STIKEY0 is not written, is written out of sequence, or is written incorrectly, any subsequent write to the STICON MMR is ignored. Serial Test Interface Key1 Register Name: STIKEY1 Address: 0xFFFF0888 Access: Write only Function: The STIKEY1 MMR is used in conjunction with the STIKEY0 MMR to protect the STICON MMR. STIKEY1 must be written with 0x00B9 immediately after any attempt is made to write to STICON. STIKEY0 must be written with 0x0007 immediately before STICON is written to ensure that the STICON write sequence has completed successfully. If STIKEY1 is not written, is written out of sequence, or is written incorrectly, any previous write to the STICO Serial T rface Data N Address: 0xFFFF0 Default V 0x0000 Access: Read/write The STIDAT0 MMR is a 16-bit register that holds the first and second data bytes that are to be transmitted on the STI pin as soon as the STI port is enabled. The first byte to be transm occupies Bits[7:0], an occupies Bits[15:8]. Serial T rface Data Name: STIDAT1 Address: 0xFFFF0 Default V 0x0000 Access: Read/write The STIDAT1 MMR is a 16-bit register that holds the third and fourth data bytes that are to be transmitted on the STI pin when the STI po is enabled. The third byte to be transmit occupies Bits[7:0], an occupies Bits[15:8]. Serial T rface Data Name: STIDAT2 Address: 0xFFFF0 Default V 0x0000 Access: Read/write The STIDAT2 MMR is a 16-bit register that is used to hold the fifth and sixth data bytes that are to be transmitted on the STI pin whe STI port is enabled. The fifth byte to be transmitted occupies Bits PARITY BIT START BIT STI BYTE0 STI BYTE1 STI BYTE2 PARITY BIT WITH TWO STOP BITS 07116-039

Figure 43. Serial ADC Test Interface Example, 3-Byte Transmission

1. STIKEY0 MMR is written with 0x0007.
2. The sequence is completed by writing 0x00B9 to STIKEY1.

Function: The STI control MMR is a 16-bit register that configures the mode of operation of the serial test interface. Note: GPIO_13 must be configured for STI operation in GP2CON for STI communications. Table 90. STICON MMR Bit Designations 15 to 9 Reserved. These bits are reserved for future use and should be written as 0 by user code. 8 to 5 State bits. Read only. If the interface is in the middle of a transmission, these bits are not 0. write the bytes to be transmitted into the STIDAT0, STIDAT1, and STIDAT2 MMRs. 1 Reset serial test interface. 1 = resets the serial test interface. A subsequent read of STICON returns all 0s. 0 = operates in normal mode (default). 0 Serial test interface enable. This bit is set by user code. 1 = enables the serial test interface. 0 = disables the serial test interface.

Figure 44. STI Output Structure

1. Configure Timer4 for baud rate generation.
2. Correctly enable STICON using STIKEY0 and STIKEY1
3. Write the required bytes to be transmitted into STIDAT0,

ADC conversion result is available. STIKEY1 MMRs as described in the previous sections.

the PLL is used for the synchronous byte timing.

• LHSSTA: LHS status register. This MMR contains information flags that describe the current status on the interface.
• LHSCON0: LHS Control Register 0. This MMR controls the configuration of the LHS timer.
• LHSCON1: LHS start and stop edge control register. This MMR dictates on which edge of the LIN synchronization byte the LHS starts/stops counting.
• LHSV AL0: LHS synchronization 16-bit timer. This MMR is controlled by LHSCON0.
• LHSV AL1: LHS break timer register. GPIO12 FUNCTION SELECT GP2CON[20] GPIO12 GP2DAT[29] AND GPSDAT[21] UART LHS HARDWARE RxD TxD BPF INTERNAL SHORT-CIRCUIT TRIP REFERENCE INTERNAL SHORT-CIRCUIT SENSE RESISTORSHORT-CIRCUIT CONTROL HVCFG1[2] OUTPUT DISABLE LIN MODE HVCFG0[1:0] INPUT VOLTAGE THRESHOLD REFERENCE LIN ENABLE (INTERNAL PULL-UP) HVCFG0[5] FOUR LIN INTERRUPT SOURCES: BREAK LHSSTA[0] START LHSSTA[1] STOP LHSSTA[2] BREAK ERROR LHSSTA[4] VDD RxD ENABLE LHSCON0[8] LHSVAL0 LHSVAL1 LHS INTERRUPT IRQEN[7] 5MHz 131kHz LHS INTERRUPT LOGIC VDD SCR IO_VSS OVERVOLTAGE PROTECTION EXTERNAL LIN PIN MASTER ECU PROTECTION DIODE MASTER ECU PULL-UP C LOAD 07116-041

Figure 45. LIN I/O Block Diagram

Function: The LHS status register is an 8-bit register whose bits reflect the current operating status of the LIN interface. Table 91. LHSSTA MMR Bit Designations 7 Reserved. These read only bits are reserved for future use. 6 Rising edge detected (BSD mode only). Set to 1 by hardware to indicate a rising edge has been detected on the BSD bus. Cleared to 0 after user code reads the LHSSTA MMR. Set to 1 by hardware to indicate a LHS reset command has completed successfully. Cleared to 0, after user code reads the LHSSTA MMR. overflows to indicate the LIN bus has stayed low too long, thus suggesting a possible LIN bus error. Cleared to 0 after user code reads the LHSSTA MMR. Set to 1 by hardware when the value in LHSVAL0 (LIN synchronization bit timer) equals the value in the LHSCMP register. Cleared to 0 after user code reads the LHSSTA MMR. Set to 1 by hardware when a stop condition is detected. Cleared to 0 after user code reads LHSSTA MMR. 1 Start condition interrupt. Set to 1 by hardware when a start condition is detected. Cleared to 0 after user code reads LHSSTA MMR. 0 Break timer compare interrupt. section for more information). Cleared to 0 after user code reads the LHSSTA MMR.

Table 92. LHSCON0 MMR Bit Designations 16 to 13 Reserved. These bits are reserved for future use and should be written as 0 by user software. 12 Rising edge detected interrupt disable. BSD Mode Set to 1 to disable the rising edge detected interrupt. Cleared to 0 to enable the break rising edge detected interrupt. LIN Mode Set to 1 to enable the rising edge detected interrupt. Cleared to 0 to disable the break rising edge detected interrupt. 11 Break timer compare interrupt disable. Set to 1 to disable the break timer compare interrupt. Cleared to 0 to enable the break timer compare interrupt. 10 Break timer error interrupt disable. Set to 1 to disable the break timer error interrupt. Cleared to 0 to enable the break timer error interrupt. 9 LIN transceiver, standalone test mode. Function Select Bit 0 and GPIO Function Select Bit 4 in the GP2CON register. Cleared to 0 by user code to operate the LIN in normal mode; it is driven directly from the on-chip UART. UART before valid data fields could be received. subsequent LIN sync byte have been detected so that the UART can receive the subsequent LIN data fields. overflows. This configuration can be used in BSD read mode to detect fault conditions on the BSD bus. pulse width in transmitted data bits. 7 Sync timer stop edge type bit. Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register. Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4] register.

Set to 1 by user code to select BSD mode of operation. Cleared to 0 by user code to select LIN mode of operation. 5 Enable compare interrupt bit. is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be transmitted. Cleared to 0 by user code to disable compare interrupts. Set to 1 by user code to generate an interrupt when a stop condition occurs. Cleared to 0 by user code to disable interrupts when a stop condition occurs. Set to 1 by user code to generate an interrupt when a start condition occurs. Cleared to 0 by user code to disable interrupts when a start condition occurs. Set to 1 by user code to enable LHS functionality. Cleared to 0 by user code to disable LHS functionality. Set to 1 by user code to clear the internal edge counters in the LHS peripheral. Cleared automatically to 0 after a 15 μs delay. Set to 1 by user code to reset all LHS logic to default conditions. Cleared automatically to 0 after a 15 μs delay. condition interrupt can be used to ensure that this scenario is avoided. Table 93. LHSCON1 MMR Bit Designations falling edge at the start of the LIN break pulse. internal LIN synchronization timer starts counting. The stop value of this counter can be read by user code via LHSVAL0. that the first falling edge is considered to be the falling edge at the start of the LIN break pulse.

ADuC7034 slave to the LIN master node. break symbol, sync byte, protected identifier, and data bytes. support and manage LIN-based transmissions and receptions. Synchronization Status Register section. Figure 49. The protected identifier consists of two subfields: the number of bytes is user configurable at the system-level design. the revision of LIN for which the system is designed.

Rev. B | Page 123 of 136 Example LIN Hardware Synchronization Routine Consider the following C-source code LIN initialization routine. void LIN_INIT(void ) char HVstatus; GP2CON = 0x110000; // Enable LHS on GPIO pins LHSCON0 = 0x1; // Reset LHS interface do{ HVDAT = 0x02; // Enable normal LIN TX mode HVCON = 0x08; // Write to HVCFG0 do{ HVstatus = HVCON; while(HVstatus & 0x1); // Wait until command is finished while (!(HVstatus & 0x4)); // Transmit command is correct while((LHSSTA & 0x20) == 0 ) { // Wait until the LHS hardware is reset LHSCON1 = 0x062; // Sets stop edge as the fifth falling edge // and the start edge as the first falling // edge in the sync byte LHSCON0 = 0x0114; // Gates UART RX line, ensuring no interference // from the LIN into the UART // Selects the stop condition as a falling edge // Enables generation of an interrupt on the // stop condition // Enables the interface LHSVAL1 = 0x03F; // Sets number of 131 kHz periods to generate a break // interrupt // 0x3F/131 kHz~480 •s, which is just over 9.5 t BIT

Figure 51. Example LIN Configuration

Rev. B | Page 125 of 136 LIN Diagnostics The ADuC7034 features the capability to nonintrusively monitor the current state of the LIN pin. This readback functionality is implemented using GPIO_11. The current state of the LIN pin is contained in GP2DAT[4]. It is also possible to drive the LIN pin high and low through user software, allowing the user to detect open-circuit conditions. This functionality is implemented via GPIO_12. First, GPIO must be configured as a GPIO through GP2CON[20], and then the LIN pin can be pulled high or low using GP2DAT. The ADuC7034 also features short-circuit protection on the LIN pin. If a short-circuit condition is detected on the LIN pin, HVSTA[2] is set. This bit is cleared by re-enabling the LIN driver using HVCFG1[3]. It is possible to disable this feature through HVCFG1[2]. LIN Operation During Thermal Shutdown When a thermal event occurs (that is, when HVSTA[3] is set), LIN communication continues uninterrupted.

and communication occurs at 1200 bps ± 3%. Table 94. BSD Bit Level Description all of which are under software control. Figure 52. BSD I/O Hardware Interface

Rev. B | Page 127 of 136 BSD RELATED MMRS The ADuC7034 emulates the BSD communication protocol using a software (bit bang) interface with some hardware assis- tance from the LIN hardware synchronization logic. In effect, the ADuC7034 BSD interface uses the following protocols:

• An internal GPIO signal (GPIO_12) that is routed to the external LIN/BSD pin and is controlled directly by software to generate 0s and 1s.
• When reading bits, the LIN synchronization hardware uses LHSV AL1 to count the width of the incoming pulses so that user code can interpret the bits as sync, 0, or 1.
• When writing bits, user code toggles a GPIO pin and uses the LHSCAP and LHSCMP registers to time pulse widths and generate an interrupt when the BSD output pulse width has reached its required width. The ADuC7034 MMRs required for BSD communication are as follows:
• LHSSTA: LIN hardware sync status register.
• LHSCON0: LIN hardware sync control register.
• LHSV AL0: LIN Hardware Sync Timer0 (16-bit timer).
• LHSCON1: LIN hardware sync edge setup register.
• LHSV AL1: LIN sync break timer.
• LHSCAP: LIN sync capture register.
• LHSCMP: LIN sync compare register.
• IRQEN/CLR: Enable interrupt register.
• FIQEN/CLR: Enable fast interrupt register.
• GP2DAT: GPIO data register.
• GP2SET: GPIO set register.
• GP2CLR: GPIO clear register. Detailed bit definitions for most of these MMRs have been listed previously. In addition to the registers described in the LIN MMR Description section, LHSCAP and LHSCMP are new registers that are required for the operation of the BSD interface. Details of these registers are included in the LIN Hardware Synchronization Capture Register and LIN Hardware Synchronization Compare Register sections. LIN Hardware Synchronization Capture Register Name: LHSCAP Address: 0xFFFF0794 Default Value: 0x0000 Access: Read only Function: This 16-bit, read only LHSCAP register holds the last captured value of the internal LIN synchronization timer (LHSV AL0). In BSD mode, the LHSV AL0 is clocked directly from an internal 5 MHz clock, and its value is loaded into the capture register on every falling edge of the BSD bus. LIN Hardware Synchronization Compare Register Name: LHSCMP Address: 0xFFFF0798 Default Value: 0x0000 Access: Read/write Function: The LHSCMP register is used to time BSD output pulse widths. When enabled through LHSCON0[5], a LIN interrupt is generated when the value in LHSCAP equals the value written in LHSCMP . This functionality allows user code to determine how long a BSD transmission bit (sync, 0, or 1) should be asserted on the bus.

is captured in LHSCAP on every falling edge of the BSD bus. The LIN sync timer runs continuously in BSD mode. the GPIO_12 is driven high for a pulse width in the 0 or 1 state. compare interrupt (LHSSTA[3]). Figure 56. BSD Slave Node State Machine

1 SOFTWARE ASSERTS

an interrupt on the rising edge of the BSD bus. to determine if the received data bit is a BSD sync pulse, 0, or 1. Figure 58. Master Read, Slave Transmit code should enable the start condition interrupt (LHSCON0[3]).

1 LHSVAL1 STOPPED

Figure 57. Master Transmit, Slave Read

SYSSER1 MMR (see Table 97 and Table 98 for details). power-up that can identify the ADuC7034 family member. contained in the T1LD MMR at power-up. T1LD allows full traceability of each part. Table 96. Branding Example unit was manufactured (bottom die only). this part to be traced (bottom die only). Table 97. SYSSER0 MMR Bit Designations device originated). When used in conjunction with SYSSER0[26:0], these bits provide individual wafer traceability. conjunction with SYSSER0[21:0], these bits provide wafer lot traceability. SYSSER0[26:22] and SYSSER0[15:0], these bits provide wafer lot traceability. 15 to 0 Wafer lot fabrication ID. These 16 LSBs hold a 16-bit number that is interpreted as the wafer fabrication lot ID number.

number (bottom die only) as detailed in Table 98. Table 98. SYSSER1 MMR Bit Designations should be interpreted as ASCII Character A, indicating a Revision A kernel is on chip. 19 to 16 Reserved. For prerelease samples, these bits refer to the kernel minor revision number of the device. value in SYSSER0 (that is, the manufacturing lot ID), this number is a unique identifier of the part.

lower half of the assembly lot ID. 0x38363430, and T1LD contains 0x30313330 at power-up. Table 99. FEE0ADR System Identification MMR Bit Designations

system meets any EMC and other overvoltage/overcurrent compliance requirements. Figure 59. Schematic

Rev. B | 134 of 136 Package Drawing (Option) CP-48-1 Package Type LFCSP Package Description 48-Lead Lead Frame Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADuC7034BCPZ −40°C to +115°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-1 ADuC7034BCPZ-RL −40°C to +115°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-1 1 Z = RoHS Compliant Part.

Rev. B | Page 135 of 136 NOTES

Rev. B | Page 136 of 136 NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D07116-0-5/10(B)