ADUC7033

ADuC7033 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 140

Technical content

Integrated, Precision Battery Sensor for Automotive ADuC7033 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.

FEATURES

Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs Programmable ADC throughput from 1 Hz to 8 kHz On-chip 5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable gain from 1 to 512 ADC input range: −200 mV to +300 mV Digital comparators, with current accumulator feature Voltage channel Buffered, on-chip attenuator for 12 V battery inputs Temperature channel External and on-chip temperature sensor options Microcontroller ARM7TDMI core, 16-/32-bit RISC architecture

20.48 MHz PLL with programmable divider

On-chip precision oscillator On-chip low power oscillator External (32.768 kHz) watch crystal JTAG port supports code download and debug Memory 96 kB Flash/EE memory, 6 kB SRAM 10,000-cycle Flash/EE endurance, 20-year Flash/EE retention In-circuit download via JTAG and LIN On-chip peripherals LIN 2.0-compatible (slave) support via UART with hardware synchronization Flexible wake-up I/O pin, master/slave SPI serial I/O 9-pin GPIO port, 3× general-purpose timers Wake-up and watchdog timers Power supply monitor and on-chip power-on reset Power Operates directly from 12 V battery supply Current consumption Normal mode: 10 mA at 10 MHz Low power monitor mode Package and temperature range 48-lead, 7 mm × 7 mm LQFP Fully specified for −40°C to +115°C operation

APPLICATIONS

Battery sensing/management for automotive systems FUNCTIONAL BLOCK DIAGRAM 16-BIT Σ-Δ ADCBUF PGA IIN+ IIN– RESULT ACCUMULATOR DIGITAL COMPARATOR 16-BIT Σ-Δ ADCMUX BUF TCK TDI TDO NTRST TMS VDD REG_AVDD REG_DVDD AGND DGND VSS IO_VSS GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 VBAT VTEMP VREF PRECISION ANALOG ACQUISITION ARM7TDMI MCU 20MHz PRECISION OSC LOW POWER OSC ON-CHIP PLL XTAL1 XTAL2 3 × TIMERS WDT W/U TIMER GPIO PORT UART PORT SPI PORT LIN WU STI LIN/BSD 2.6V LDO PSM POR MEMORY 96KB FLASH 6KB RAM RESET TEMPERATURE SENSOR PRECISION REFERENCE ADuC7033 06847-001 Figure 1.

Rev. B | Page 2 of 140 TABLE OF CONTENTS Synchronization of Timers Across Asynchronous Clock Handling Interrupts from the High Voltage Peripheral

Rev. B | Page 3 of 140

REVISION HISTORY

10/10—Rev. A to Rev. B Added Synchronization of Timers across Asynchronous Clock 11/09—Rev. 0 to Rev. A 11/07—Revision 0: Initial Version

precision oscillator, all specifications TA = −40°C to +115°C, unless otherwise noted. Table 1. ADuC7033 Electrical Specifications

4 Hz update rate, gain = 512, chop disabled 75 115 nV rms

10 Hz update rate, gain = 512, chop enabled 100 150 nV rms

10 Hz update rate, gain = 512, chop disabled 120 180 nV rms

Rev. B | Page 5 of 140 Parameter Test Conditions/Comments Min Typ Max Unit Total Gain Error1, 3, 7, 13, 14 Includes resistor mismatch −0.25 ±0.06 +0.25 % Temperature range = −25°C to +65°C −0.15 ±0.03 +0.15 % Gain Drift Includes resistor mismatch drift ±3 ppm/°C Output Noise1, 10, 15 4 Hz update rate, chop enabled 60 90 μV rms

10 Hz update rate, chop enabled 60 90 μV rms

1 kHz update rate, chop disabled 180 270 μV rms 1 kHz update rate, chop enabled 240 307 μV rms 1 kHz update rate (ADCFLT = 0x0101) 270 405 μV rms 8 kHz update rate 1600 2400 μV rms Temperature Channel No Missing Codes1 Valid at all ADC update rates 16 Bits Integral Nonlinearity1 ±10 ±60 ppm of FSR Offset Error3, 5, 16, 17 Chop off, 1 LSB = 19.84 μV (in unipolar mode) −10 ±3 +10 LSB Offset Error1, 3 Chop on −5 ±1 +5 LSB Offset Error Drift Chop off ±0.03 LSB/°C Total Gain Error1, 3, 13 Using AVDD/2 for reference −0.2 ±0.06 +0.2 % Gain Drift ±3 ppm/°C Output Noise1 1 kHz update rate 7.5 11.25 μV rms ADC SPECIFICATIONS ANALOG INPUT Internal VREF = 1.2 V Current Channel Absolute Input Voltage Range Applies to both IIN+ and IIN− −200 +300 mV Input Voltage Range18, 19 Gain = 1 20 ±1.2 V Gain = 220 ±600 mV Gain = 420 ±300 mV Gain = 8 ±150 mV Gain = 16 ±75 mV Gain = 32 ±37.5 mV Gain = 64 ±18.75 mV Gain = 128 ±9.375 mV Gain = 256 ±4.68 mV Gain = 512 ±2.3 mV Input Leakage Current1 −3 +3 nA Input Offset Current1, 21 0.5 1.5 nA Voltage Channel Absolute Input Voltage Range 4 18 V Input Voltage Range 0 to 28.8 V VBAT Input Current VBAT = 18 V 3 5.5 8 μA Temperature Channel VREF = (REG_AVDD, GND_SW)/2 Absolute Input Voltage Range 100 1300 mV Input Voltage Range 0 to V REF V VTEMP Input Current1 2.5 100 nA VOLTAGE REFERENCE ADC Precision Reference Internal VREF 1.2 V Power-Up Time1 0.5 Ms Initial Accuracy1 Measured at TA = 25°C −0.15 +0.15 % Temperature Coefficient1, 22 −20 ±5 +20 ppm/°C Reference Long-Term Stability23 100 ppm/1000 hr External Reference Input Range24 0.1 1.3 V VREF Divide-by-2 Initial Error1 0.1 0.3 %

Rev. B | Page 6 of 140 Parameter Test Conditions/Comments Min Typ Max Unit ADC Low Power Reference Internal VREF 1.2 V Initial Accuracy Measured at TA = 25°C −5 +5 % Initial Accuracy1 Using ADCREF , measured at TA = 25°C 0.1 % Temperature Coefficient1, 22 −300 ±150 +300 ppm/°C RESISTIVE ATTENUATOR Divider Ratio 24 Resistor Mismatch Drift 3 ppm/°C ADC GROUND SWITCH Resistance Direct path to ground 10 Ω 20 kΩ resistor selected 10 20 30 kΩ Input Current 6 mA TEMPERATURE SENSOR25 After user calibration Accuracy MCU in power-down or standby mode ±3 °C MCU in power-down or standby mode, temperature range = −25°C to +65°C ±2 °C POWER-ON RESET (POR) POR Trip Level Refers to voltage at VDD pin 2.85 3.0 3.15 V POR Hysteresis 300 mV RESET Timeout from POR 20 ms LOW VOLTAGE FLAG (LVF) LVF Level Refers to voltage at VDD pin 1.9 2.1 2.3 V POWER SUPPLY MONITOR (PSM) PSM Trip Level Refers to voltage at VDD pin 6.0 V WATCHDOG TIMER (WDT) Timeout Period1 32.768 kHz clock, 256 prescale 0.008 512 sec Timeout Step Size 7.8 ms FLASH/EE MEMORY1 Endurance26 10,000 Cycles Data Retention27 20 Years DIGITAL INPUTS All digital inputs except NTRST Input Leakage Current Input (high) = REG_DVDD −10 ±1 +10 μA Input Pull-up Current Input (low) = 0 V −80 −20 −10 μA Input Capacitance 10 pF Input Leakage Current NTRST only: input (low) = 0 V −10 ±1 +10 μA Input Pull-Down Current NTRST only: input (high) = REG_DVDD 30 55 100 μA LOGIC INPUTS1 All logic inputs VINL, Input Low Voltage 0.4 V VINH, Input High Voltage 2.0 V CRYSTAL OSCILLATOR1 Logic Inputs, XTAL1 Only VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 1.7 V XTAL1 Capacitance 12 pF XTAL2 Capacitance 12 pF ON-CHIP OSCILLATORS Low Power Oscillator 131.072 kHz Accuracy28 Includes drift data from 1000-hour life test −3 +3 % Precision Oscillator 131.072 kHz Accuracy Includes drift data from 1000-hour life test −1 +1 % MCU CLOCK RATE 8 programmable core clock selections within this range (binary divisions 1, 2, 4, 8 . . . 64, 128) 0.160 10.24 20.48 MHz

Rev. B | Page 7 of 140 Parameter Test Conditions/Comments Min Typ Max Unit MCU START-UP TIME At Power-On Includes kernel power-on execution time 25 ms After Reset Event Includes kernel power-on execution time 5 ms From MCU Power-Down Oscillator Running Wake Up from Interrupt 2 ms Wake Up from LIN 2 ms Crystal Powered Down Wake Up from Interrupt 500 ms Internal PLL Lock Time 1 ms LIN INPUT/OUTPUT GENERAL Bus load conditions (CBUS||RBU): 1 nF||1 kΩ, 6.8 nF||660 Ω; 10 nF||500 Ω Baud Rate 1000 20,000 Bits/sec VDD Supply voltage range at which the LIN interface is functional 7 18 V Input Capacitance 5.5 pF Input Leakage Current Input (low) = IO_VSS −800 −400 μA LIN Comparator Response Time1 Using 22 Ω resistor 38 90 μs ILIN DOM MAX Current limit for driver when LIN bus is in dominant state, VBAT = VBAT (MAX) 40 200 mA ILIN_PAS_REC Driver off, 7.0 V < VLIN < 18 V, VDD = VLIN − 0.7 V −20 +20 μA ILIN1 VBAT disconnected, VDD = 0 V, 0 < VLIN < 18 V 10 μA ILIN_PAS_DOM1 Input leakage VLIN = 0 V −1 mA ILIN_NO_GND29 Control unit disconnected from ground, GND = VDD, 0 V < VLIN < 18 V, VBAT = 12 V −1 +1 mA VLIN_DOM1 LIN receiver dominant state, VDD > 7.0 V 0.4 V DD V VLIN_REC1 LIN receiver recessive state, VDD > 7.0 V 0.6 VDD V VLIN_CNT1 LIN receiver center voltage, VDD > 7.0 V 0.475 VDD 0.5 V DD 0.525 V DD V VHYS1 LIN receiver hysteresis voltage 0.175 V DD V VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage, VDD = 7 V RL 500 Ω 1.2 V RL 1000 Ω 0.6 V VLIN_DOM_DRV_HISUP1 LIN dominant output voltage, VDD = 18 V RL 500 Ω 2 V RL 1000 Ω 0.8 V VLIN_RECESSIVE LIN recessive output voltage 0.8 VDD V VBAT Shift29 0 0.1 VDD V GND Shift29 0 0.1 VDD V RSLAVE Slave termination resistance 20 30 47 kΩ VSERIAL DIODE29 Voltage drop at the Serial Diode DSer_Int 0.4 0.7 1 V Symmetry of Transmit Propagation Delay1 VDD (MIN) = 7 V −2 +2 μs Receive Propagation Delay1 V DD (MIN) = 7 V 6 μs Symmetry of Receive Propagation Delay1 VDD (MIN) = 7 V −2 +2 μs LIN VERSION 2.0 SPECIFICATION Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ, 6.8 nF||660 Ω; 10 nF||500 Ω D1 Duty Cycle 1, THREC(MAX) = 0.744 × VBAT, THDOM(MAX) = 0.581 × VBAT, VSUP = 7.0 V . . . 18 V, tBIT = 50 μs, D1 = tBUS_REC(MIN)/(2 × tBIT) 0.396

Rev. B | Page 8 of 140 Parameter Test Conditions/Comments Min Typ Max Unit D2 Duty Cycle 2, THREC(MIN) = 0.284 × VBAT, THDOM(MIN) = 0.422 × VBAT, VSUP = 7.0 V . . . 18 V, tBIT = 50 μs, D2 = tBUS_REC(MAX)/(2 × tBIT) 0.581 BSD INPUT/OUTPUT30 Baud Rate 1164 1200 1236 Bits/sec Input Leakage Current Input (high) = VDD or input (low) = IO_VSS −50 +50 μA VOL, Output Low Voltage 1.2 V VOH, Output High Voltage 0.8 VDD V DD V Io(sc), Short-Circuit Output Current V BSD = VDD = 12 V 50 80 120 mA VINL, Input Low Voltage 1.8 V VINH, Input High Voltage 0.7 VDD V WAKE R L = 300 Ω, CBUS = 91 nF, RLIMIT = 39 Ω VDD1 Supply voltage range at which the WU pin is functional 7 18 V Input Leakage Current Input (high) = VDD 0.4 2.1 mA Input (low) = IO_VSS −50 +50 μA VOH31 Output high level 5 V VOL31 Output low level 2 V VIH Input high level 4.6 V VIL Input low level 1.2 V Monoflop Timeout Timeout period 0.6 1.3 2 sec Io(sc), Short-Circuit Output Current 65 100 mA SERIAL TEST INTERFACE RL = 500 Ω, CBUS = 2.4 nF, RLIMIT = 39 Ω Baud Rate 40 kbps Input Leakage Current Input (high) = VDD or input (low) = IO_VSS −50 +70 μA VDD Supply voltage range for which STI is functional 7 18 V VOH Output high level 0.6 VDD VOL Output low level 0.4 V DD VIH Input high level 0.6 VDD VIL Input low level 0.4 V DD PACKAGE THERMAL SPECIFICATIONS Thermal Shutdown1, 32 140 150 160 °C θJA, Thermal Impedance33 48-lead LFCSP, stacked die 45 °C/W 48-lead LQFP, stacked die 75 °C/W POWER REQUIREMENTS Power Supply Voltages VDD (Battery Supply) 3.5 18 V REG_DVDD, REG_AVDD34 2.5 2.6 2.7 V Power Consumption IDD (MCU Normal Mode)35 MCU clock rate = 10.24 MHz, ADC off 10 20 mA MCU clock rate = 20.48 MHz, ADC off 20 mA IDD (MCU Powered Down)1 ADC low power mode, measured over the range of TA = −10°C to +40°C, continuous ADC conversion 300 400 μA ADC low power mode, measured over the range of T A = −40°C to +85°C, continuous ADC conversion 300 500 μA ADC low power plus mode, measured over an ambient temperature range of TA = −10°C to +40°C, continuous ADC conversion 520 700 μA Average current, measured with wake and watchdog timer clocked from the low power oscillator, T A = −40°C to +85°C 120 300 μA IDD (MCU Powered Down) Average current, measured with wake and watchdog timer clocked from low power oscillator over a range of TA = −10°C to +40°C 120 175 μA IDD (Current ADC) 1.7 mA IDD (Voltage/Temperature ADC) 0.5 mA IDD (Precision Oscillator) 400 μA

Rev. B | Page 9 of 140 1 Not guaranteed by production test, but by design and/or characterization data at production release. 2 Valid for current ADC gain setting of PGA = 4 to 64. 3 These numbers include temperature drift. 4 Tested at gain range = 4; self-offset calibration removes this error at the operating temperature. 5 Measured with an internal short after an initial offset calibration. 6 Measured with an internal short. 7 These numbers include internal reference temperature drift. 8 Factory calibrated at gain = 1. 9 System calibration at a specific gain range removes the error at this gain range at that temperature. 10 1 kHz update rate chop enable is achieved with ADCFLT = 0x8101; yet with chop off, ADCFLT = 0x0007, unless otherwise stated. 11 Typical noise in low power modes is measured with chop enabled. 12 Voltage channel specifications include resistive attenuator input stage. 13 Includes an initial system calibration. 14 System calibration removes this error. 15 RMS noise is referred to voltage attenuator input, for example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 μV, scaled by the attenuator (24) yields these input referred noise figures. 16 ADC self-offset calibration removes this error at the operating temperature. 17 Valid after an initial self calibration. 18 In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV. 19 It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach can also be used to reduce the ADC input range (LSB size). 20 Limited by minimum/maximum absolute input voltage range. 21 Valid for a differential input less than 10 mV. 22 Measured using box method. 23 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000-hour period. 24 References of up to REG_AVDD can be accommodated by enabling an internal divide-by-2. 25 Die temperature. 26 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles. 27 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. 28 Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code. 29 These numbers are not production tested, but are supported by LIN compliance testing. 30 BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and CLoad = 10 nF maximum. 31 Specified after RLIMIT of 39 Ω. 32 The MCU core is not shut down but interrupted, and high voltage I/O pins are disabled in response to a thermal shutdown event. 33 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature. 34 Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA), and REG_AVDD (ISOURCE = 1 mA). 35 Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.

Table 2. SPI Master Mode Timing (PHASE Mode = 1) 1 tHCLK depends on the clock divider (CD) bits in POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 2. SPI Master Mode Timing (PHASE Mode = 1)

Table 3. SPI Master Mode Timing (PHASE Mode = 0) 1 tHCLK depends on the clock divider (CD) bits in POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 3. SPI Master Mode Timing (PHASE Mode = 0)

Table 4. SPI Slave Mode Timing (PHASE Mode = 1) 1 tHCLK depends on the clock divider (CD) bits in POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 4. SPI Slave Mode Timing (PHASE Mode = 1)

Table 5. SPI Slave Mode Timing (PHASE Mode = 0) 1 tHCLK depends on the clock divider (CD) bits in POWCON MMR. tHCLK = tUCLK/2CD. 2 tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. Figure 5. SPI Slave Mode Timing (PHASE Mode = 0)

Figure 6. LIN 2.0 Timing Specification

Rev. B | Page 15 of 140 ABSOLUTE MAXIMUM RATINGS TA = −40°C to +115°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Parameter Rating AGND to DGND to VSS to IO_VSS −0.3 V to +0.3 V VBAT to AGND −22 V to +40 V VDD to VSS −0.3 V to +33 V VDD to VSS for 1 sec −0.3 V to +40 V LIN to IO_VSS −16 V to +40 V STI/WU to IO_VSS −3 V to +33 V WU Continuous Current 50 mA High Voltage I/O Pins Short-Circuit Current 100 mA Digital I/O Voltage to DGND −0.3 V to REG_DVDD + 0.3 V VREF to AGND −0.3 V to REG_AVDD + 0.3 V ADC Inputs to AGND −0.3 V to REG_AVDD + 0.3 V Storage Temperature 125°C Junction Temperature Transient 150°C Continuous 130°C Lead Temperature Soldering Reflow (15 sec) 260°C ESD CAUTION

Figure 7. Pin Configuration Table 7. Pin Function Descriptions recommended that this pin be strapped via a resistor to REG_DVDD. General-Purpose Digital I/O 5. External Interrupt Request 1, active high. Receive data for UART serial port. General-Purpose Digital I/O 6. Transmit data for UART serial port. General-Purpose Digital I/O 7. External Interrupt Request 4, active high. General-Purpose Digital I/O 8. External Interrupt Request 5, active high. 6 TCK I JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part. unconnected when not in use.

Rev. B | Page 17 of 140 Pin No. Mnemonic Type 1 Description 7 TDI I JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the part. TDI is an input pin only and has an internal weak pull-up resistor. This pin remains unconnected when not in use. 8, 34, 35 DGND S Ground Reference for On-Chip Digital Circuits. 9, 16, 17, 23, 25, 26, 32, 38 to 40, 43, 45 NC No Connect. These pins are not internally connected, but are reserved for possible future use. Therefore, do not externally connect these pins. These pins can be grounded, if required. 10 TDO O JTAG Test Data Output. This data output pin is one of the standard 5-pin JTAG debug ports on the part. TDO is an output pin only. At power-on, this output is disabled and pulled high via an internal weak pull-up resistor. This pin remains unconnected when not in use. 11 NTRST I JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part. NTRST is an input pin only and has an internal, weak, pull-down resistor. This pin remains unconnected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN boot load mode. 12 TMS I JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports on the part. TMS is an input pin only and has an internal weak pull-up resistor. This pin remains unconnected when not in use. 13 VBAT I Battery Voltage Input to Resistor Divider. 14 VREF I External Reference Input Terminal. When this input is not used, connect it directly to the AGND system ground. It can also remain unconnected. 15 GND_SW I Switch to Internal Analog Ground Reference. This pin is the negative input for the external temperature channel and external reference. When this input is not used, connect it directly to the AGND system ground. 18 VTEMP I External Pin for NTC/PTC Temperature Measurement. 19 IIN+ I Positive Differential Input for Current Channel. 20 IIN− I Negative Differential Input for Current Channel. 21, 22 AGND S Ground Reference for On-Chip Precision Analog Circuits. 24 REG_AVDD S Nominal 2.6 V Output from On-Chip Regulator. 27 GPIO_0/IRQ0/SS I/O General-Purpose Digital Input/Output 0, External Interrupt Request 0, or SPI Interface. This is a multifunction pin. By default and after power-on-reset, this pin is configured as an input. The pin has an internal weak pull-up resistor. This pin remains unconnected when not in use. This multifunction pin can be configured in one of three states, namely General-Purpose Digital I/O 0. External Interrupt Request 0, active high. SPI interface, slave select input. 28 GPIO_1/SCLK I/O General-Purpose Digital Input/Output 1, SPI Interface. This is a multifunction pin. By default and after power-on-reset, this pin is configured as an input. The pin has an internal weak pull- up resistor. This pin remains unconnected when not in use. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 1. SPI interface, serial clock input. 29 GPIO_2/MIS0 I/O General-Purpose Digital Input/Output 2, SPI Interface. This is a multifunction pin. By default and after power-on-reset, this pin is configured as an input. The pin has an internal weak pull- up resistor. This pin remains unconnected when not in use. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 2. SPI interface, master input/slave output pin. 30 GPIO_3/MOSI I/O General-Purpose Digital Input/Output 3, SPI Interface. This is a multifunction pin. By default and after power-on reset, this pin is configured as an input. The pin has an internal weak pull- up resistor. This pin remains unconnected when not in use. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 3. SPI interface, master output/slave input pin.

Rev. B | Page 18 of 140 Pin No. Mnemonic Type 1 Description 31 GPIO_4/ECLK I/O General-Purpose Digital Input/Output 4, Clock. This is a multifunction pin. By default and after power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor. This pin remains unconnected when not in use. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 4. Output a 2.56 MHz clock. 33 REG_DVDD S Nominal 2.6 V Output from On-Chip Regulator. 36 XTAL1 O Crystal Oscillator Output. If an external crystal is not used, this pin is left unconnected. 37 XTAL2 I Crystal Oscillator Input. If an external crystal is not used, connect this pin to the DGND system ground. 41 WU I/O High Voltage Wake-Up Pin. This high voltage I/O pin has an internal 10 kΩ pull-down resistor and a high-side driver to VDD. If this pin is not used, do not externally connect it. 42 VDD S Battery Power Supply to On-Chip Regulator. 44 VSS S Ground Reference. This is the ground reference for the internal voltage regulators. 46 STI I/O High Voltage Serial Test Interface Output Pin. If this pin is not used, externally connect it to the IO_VSS ground reference. 47 IO_VSS S Ground Reference for High Voltage I/O Pins. 48 LIN/BSD I/O LIN Serial Interface Input/Output Pin. This is a high voltage pin. 1 I = input, O = output, S = supply.

Rev. B | Page 20 of 140 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, after the ADC settles. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that while the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output giving a valid 16-bit data conversion result at output rates from 1 Hz to 8 kHz. Note that when software switches from one input to another on the same ADC, the digital filter must first be cleared and then allowed to average a new result. Depending on the con- figuration of the ADC and the type of filter, this may require multiple conversion cycles. Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end- points of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB The error is expressed as a percentage of full scale. No Missing Codes No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits and specifies the number of codes (ADC results) as 2 N bits, where N = no missing codes, guaranteed to occur through the full ADC input range. Offset Error Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition. Offset Error Drift Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSBs per °C. Gain Error Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function. Output Noise The output noise is specified as the standard deviation (or 1 × Σ) of ADC output codes distribution collected when the ADC input voltage is at a dc voltage. It is expressed as μ rms. The output, or rms noise, can be used to calculate the effective resolution of the ADC as defined by the following equation: Effective Resolution = log 2(Full-Scale Range/rms Noise) where Effective Resolution is expressed in bits. The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × Σ of the distribution of ADC output codes collected when the ADC input voltage is at dc. The peak-to- peak noise is therefore calculated as 6.6 × the rms noise. The peak-to-peak noise can be used to calculate the ADC (noise-free code) resolution for which there is no code flicker within a 6.6-Σ limit as defined by the following equation: Noise-Free Code Resolution = log 2(Full-Scale Range/Peak- to-Peak Noise) where Noise-Free Code Resolution is expressed in bits. Data Sheet Acronyms ADC analog-to-digital converter ARM advanced RISC machine JTAG joint test action group LIN local interconnect network LSB least significant byte/bit LVF low voltage flag MCU microcontroller MMR memory mapped register MSB most significant byte/bit OTP one time programmable PID protected identifier POR power-on reset PSM power supply monitor rms root mean square STI serial test interface

range of operating conditions. generates the supply voltage for two integrated, 16-bit, Σ-Δ ADCs. results to a lower performance specification. nonintrusive emulation is also supported via the JTAG interface. development system supporting the ADuC7033. performance, at temperatures from 115°C to 125°C. Table 8. ARM7TDMI core particularly suited for embedded applications.

• Relative to ARM, the Thumb code usually requires more instructions to perform that same task. Therefore, ARM code is best for maximizing the performance of time- critical code in most applications.
• The Thumb instruction set does not include some instructions that are needed for exception handling, therefore, ARM code can be required for exception handling.
• When an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at that address. The first command is required to be in ARM code. Multiplier (M) The ARM7TDMI instruction set includes an enhanced multiplier, with four extra instructions to perform 32-bit × 32-bit multiplication with a 64-bit result, and 32-bit × 32-bit multiplication accumulation (MAC) with a 64-bit result. EmbeddedICE (I) The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. These registers are con- trolled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. Once in a debug state, the processor registers can be interrogated, as can the Flash/EE memory, SRAM, and memory mapped registers. ARM7 Exceptions The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are as follows:

• Normal interrupt (IRQ). This is provided to service general-purpose interrupt handling of internal and external events.
• Fast interrupt (FIQ). This is provided to service data transfer or a communication channel with low latency. FIQ has priority over IRQ.
• Memory abort (prefetch and data).
• Attempted execution of an undefined instruction.
• Software interrupt (SWI) instruction that can be used to make a call to an operating system. Typically, the programmer defines interrupts as IRQ, but for higher priority interrupts, the programmer can define interrupts as the FIQ type. The priority of these exceptions and vector addresses are listed in Table 9.

Table 9. Exception Priorities and Vector Addresses

1 Hardware Reset 0x00

2 Memory Abort (Data) 0x10

3 FIQ 0x1C

4 IRQ 0x18

5 Memory Abort (Prefetch) 0x0C

6 Software Interrupt1 0x08

6 Undefined Instruction1 0x04

1 A software interrupt and an undefined instruction exception have the same

priority and are mutually exclusive. and LIN download mode is entered. The stack pointer contains the current location of the stack. such as C, it is necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used. reducing the response time of the interrupt handling process. Figure 11. Register Organization The minimum latency for FIQ or IRQ interrupts is five cycles. the synchronizer plus the time to enter the exception mode.

Flash/EE area, and a memory mapped register (MMR) area.

• The first 94 kB of this memory space is used as an area into which the on-chip Flash/EE memory or SRAM can be remapped.
• The ADuC7033 features a second 4-kB area at the top of the memory map used to locate the MMRs, through which all on-chip peripherals are configured and monitored.
• The ADuC7033 features a SRAM size of 6 kB.
• The ADuC7033 features 96 kB of on-chip Flash/EE memory. 94 kB of on-chip Flash/EE memory are available to the user. In addition, 2 kB are reserved for the on-chip kernel. Any access, either reading or writing, to an area not defined in the memory map results in a data abort exception. Memory Format The ADuC7033 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. BIT 31 BYTE 2 A BYTE 3 B BYTE 1 BYTE 0 BIT 0

32 BITS

Figure 12. Little Endian Format Figure 13. ADuC7033 Memory Map memory array, from Address 0x00000000 to Address 0x00000020. mapped to Address 0x00000000. It is possible to logically remap the SRAM to Address 0x00000000. 0x00000000, Bit 0 of SYSMAP0 is cleared.

always be written in Flash/EE memory. the user can observe abnormal program operation. Table 10. SYSMAP0 MMR Bit Designations be written as 0 by user code. Flash/EE memory to 0x00000000.

tions of all four kinds of reset event are tabulated in Table 12. user code to initiate a software reset. corresponding bit in RSTSTA. Table 11. RSTSTA/RSTCLR MMR Bit Designations Automatically set to 1 when an external reset occurs. Cleared by setting the corresponding bit in RSTCLR. Cleared by setting the corresponding bit in RSTCLR. Automatically set when a power-on-reset occurs. Cleared by setting the corresponding bit in RSTCLR.

1 If the software reset bit in RSTSTA is set, any write to RSTCLR that does not

clear this bit generates a software reset. Table 12. Device Reset Implications 1 RAM is not valid in the case of a reset following LIN download. mechanism if the LVF Status Bit HVSTA[6] is 1. See the Low Voltage Flag (LVF) section for more information.

Rev. B | Page 26 of 140 FLASH/EE MEMORY The ADuC7033 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit repro- grammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased, the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit program- mability, high density, and low cost. Incorporated within the ADuC7033, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes. The Flash/EE memory is physically located at 0x80000. Upon a hard reset, it logically maps to 0x00000000. The factory default contents of all Flash/EE memory locations is 0xFF. Flash/EE memory can be read in 8-/16-/32-bit segments, and written in segments of 16 bits. The Flash/EE memory is rated for 10,000 endurance cycles. This rating is based on the number of times that each individual byte is cycled, that is, erased and programmed. Implementing a redundancy scheme in the software ensures a greater than 10,000-cycle endurance. The user can also write data variables to the Flash/EE memory during run-time code execution, for example, for storing diagnostic battery parameter data. The entire Flash/EE memory is available to the user as code and nonvolatile data memory. There is no distinction between data and program, because ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE memory are necessary for each instruction fetch. When operating at speeds of less than 20.48 MHz, the Flash/EE memory controller can transparently fetch the second 16-bit halfword (part of the 32-bit ARM operation code) within a single core clock period. Therefore, it is recommended that for speeds less than 20.48 MHz, that is, CD > 0, use ARM mode. For 20.48MHz operation, that is, CD = 0, it is recommended to operate in Thumb mode. The page size of this Flash/EE memory is 512 bytes. Typically, it takes the Flash/EE memory controller 20 ms to erase a page, regardless of CD. To write a 16-bit word at CD = 0, 1, 2, 3 requires 50 μs; 70 μs at CD = 4, 5; 80 μs at CD = 6; and 105 μs at CD = 7. It is possible to write to a single, 16-bit location only twice between erases, that is, it is possible to walk bytes, not bits. If a location is written to more than twice, then it is possible to corrupt the contents of the Flash/EE memory page. PROGRAMMING FLASH/EE MEMORY IN-CIRCUIT The Flash/EE memory can be programmed in-circuit, using a serial download mode via the LIN interface or the integrated JTAG port. Serial Downloading (In-Circuit Programming) The ADuC7033 facilitates code download via the LIN pin. JTAG Access The ADuC7033 features an on-chip JTAG debug port to facilitate code download and debug. ADuC7033 Flash/EE Memory The total 96 kB of Flash/EE memory are organized as 47,000 × 16 bits. Of the 96 kB, 94 kB is user space and 2 kB is reserved for boot loader/kernel space. FLASH/EE MEMORY CONTROL INTERFACE The access to and control of the Flash/EE memory on the ADuC7033 is managed by an on-chip memory controller. The controller manages the Flash/EE memory as two separate blocks (0 and 1). Block0 consists of the 32 kB Flash/EE memory mapped from 0x00090000 to 0x00097FFF (including the 2 kB kernel space which is reserved at the top of this block). Block1 consists of the 64 kB Flash/EE memory mapped from 0x00080000 to 0x0008FFFF. Note that the MCU core can continue to execute code from one memory block while an active erase or program cycle is being carried out on the other block. If a command operates on the same block as the code currently executing, the core halts until the command is completed; this also applies to code execution. User code, LIN, and JTAG programming use the Flash/EE memory control interface, consisting of the following MMRs:

• FEExSTA (x = 0 or 1): read only register, reflects the status of the Flash/EE memory control interface.
• FEExMOD (x = 0 or 1): sets the operating mode of the Flash/EE memory control interface.
• FEExCON (x = 0 or 1): 8-bit command register. The commands are interpreted as described in Table 13.
• FEExDAT (x = 0 or 1): 16-bit data register.
• FEExADR (x= 0 or 1): 16-bit address register.
• FEExSIG (x = 0 or 1): Holds the 24-bit code signature as a result of the signature command being initiated.
• FEExHID (x = 0 or 1): Protection MMR. Controls read and write protection of the Flash/EE memory code space. If previously configured via the FEExPRO register, FEExHID may require a software key to enable access.
• FEExPRO (x = 0 or 1): A buffer of the FEExHID register, which is used to store the FEExHID value; therefore, it is automatically downloaded to the FEExHID registers on subsequent reset and power-on events.

designations for each of the Flash/EE memory control MMRs. Block0 (32 kB) and Block1 (64 kB). Table 13. Command Codes in FEE0CON and FEE1CON 0x002 Reserved Reserved, this command should not be written by user code. 0x012 Single Read Load FEExDAT with the 16-bit data indexed by FEExADR. 0x022 Single Write Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs. is returned in FEExSTA Bit 1. 0x052 Single Erase Erase the page indexed by FEExADR. the following command codes. 0x08 Reserved Reserved, this command should not be written by user code. 0x09 Reserved Reserved, this command should not be written by user code. 0x0A Reserved Reserved, this command should not be written by user code. 0x0B Signature FEE0CON: This command results in a 24-bit LFSR-based signature being generated and loaded into FEE0SIG. from the page specified in FEE0ADR upwards, including the kernel, security bits, and the Flash/EE memory key. If FEE0ADR is greater than 0x97800, the kernel and manufacturing data is signed. This operation takes 120 μs. erase (0x06) or with the key. 0x0D Reserved Reserved, this command should not be written by user code. 0x0E Reserved Reserved, this command should not be written by user code. 0x0F Ping No operation, interrupt generated. 1 x is 0 or 1 to designate Flash/EE memory Block0 or Block1. 2 The FEExCON always reads 0x07 immediately after execution of any of these commands.

code sequence must be executed to initiate this operation.

1. Run the Mass Erase Command 0x06 in FEExCON

Table 14. FEE0STA and FEE1STA MMR Bit Designations 7 to 4 Not Used. These bits are not used and always read as 0. 3 Flash/EE Memory Interrupt Status Bit. bit in the FEExMOD register is set. Cleared automatically when the FEExSTA register is read by user code. 2 Flash/EE Memory Controller Busy. Set automatically when the Flash/EE memory controller is busy. Cleared automatically when the controller is not busy. Set automatically when a command written to FEExCON completes unsuccessfully. Cleared automatically when the FEExSTA register is read by user code. Set automatically by MCU when a command is completed successfully. Cleared automatically when the FEE0STA register is read by user code. 1 x is 0 or 1 to designate Flash/EE memory Block0 or Block1.

System Identification FEE0ADR section. Function: These registers are written by user code to configure the mode of operation of the Flash/EE memory controllers. Table 15. FEE0MOD and FEE1MOD MMR Bit Designations 15 to 7 Not Used. These bits are reserved for future functionality and should be written as 0 by user code. 6, 5 Flash/EE Security Lock Bits. These bits must be written as [6,5] = 1, 0 to complete the Flash/EE security protect sequence. 4 Flash/EE Controller Command Complete Interrupt Enable. Set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command. Cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command. 3 Flash/EE Erase/Write Enable. Set by user code to enable the Flash/EE erase and write access via FEExCON. Cleared by user code to disable the Flash/EE erase and write access via FEExCON. 2 Reserved and should be written as zero. 1 Flash/EE Controller Abort Enable. Set to 1 by user code to enable the Flash/EE controller abort functionality. 0 Reserved and should be written as zero. 1 x is 0 or 1 to designate Flash/EE memory Block0 or Block1.

register (Bit 31) protects Block0 from been read via JTAG. protection systems into the field. (Bit 31) protects Flash/EE Block1, from been read via JTAG. loaded on subsequent power-on or reset events. Function: These registers are written by user code to configure the protection of the Flash/EE memory. Table 16. FEE0HID and FEE0PRO MMR Bit Designations Cleared by user to protect the 32 kB Flash/EE block code through JTAG read access. Set by user to allow reading of the 32 kB Flash/EE block code through JTAG read access. Set by user code to unprotect Page 59. Cleared by user code to write protect Page 59. Set by user code to unprotect Page 58. Cleared by user code to write protect Page 58. 28 to 0 Write Protection Bits. pages and each page consists of 512 bytes. two pages and each page consists of 512 bytes.

Function: These registers are written by user code to configure the protection of the Flash/EE memory. Table 17. FEE1HID and FEE1PRO MMR Bit Designations Cleared by user to protect the 64 kB Flash/EE Block code via JTAG read access. Set by user to allow reading the 64 kB Flash/EE Block code via JTAG read access. 30 Read Protection. This bit write protects eight pages and each page consists of 512 bytes. When set by user code, these bits unprotect Page 120 to Page 127 of the 64 kB Flash/EE code memory. When cleared by user code, these bits write protect Page 120 to Page 127 of the 64 kB Flash/EE code memory. 29 to 0 Write Protection Bits. pages and each page consists of 512 bytes. two pages and each page consists of 512 bytes.

Rev. B | Page 32 of 140 In summary, there are three levels of protection. Temporary Protection Set and remove temporary protection by writing directly into the FEExHID MMR. This register is volatile and therefore protection is only in place while the part remains powered on. This protection is not reloaded after a power cycle. Keyed Permanent Protection Set keyed permanent protection via FEExPRO to lock the protection configuration. The software key used at the start of the required FEExPRO write sequence is saved one time only and thereafter must be used for any subsequent access of the FEExHID or FEExPRO MMRs. A mass erase resets the key to 0xFFFF but also erases the entire user code space. Permanent Protection Set permanent protection via FEExPRO, similarly to keyed permanent protection, the only difference is that the Software Key 0xDEADDEAD is used. Once the FEExPRO write sequence is saved, only a mass erase resets the key to 0xFFFFFFFF. This also erases the entire user code space. Sequence to Write the Key and Set Permanent Protection 1. Write in FEExPRO corresponding to the pages to be protected. 2. Write the new (user defined) 32-bit key in FEExADR (Bits[31:16]) and FEExDAT (Bits[15:0]). 3. Write 1, 0 in FEExMOD[6:5] and set FEExMOD[3]. 4. Run the Write Key Command 0x0C in FEExCON. To remove or modify the protection, the same sequence can be used with a modified value of FEExPRO. Sequence Example The sequence to write the key and set permanent protection is illustrated in the following example; this protects writing Page 4 and Page 5 of the Flash/EE memory: Int a = FEExSTA; // Ensure FEExSTA is cleared FEExPRO = 0xFFFFFFFB; //Protect Pages[4:5] FEExADR = 0x66BB; //32 bit key value (Bits[31:16]) FEExDAT = 0xAA55; //32 bit key value (Bits[15:0]) FEExMOD = 0x0048; //Lock security sequence FEExCON = 0x0C; //Write key command while (FEExSTA & 0x04){} //Wait for command to finish

cycling endurance and Flash/EE memory data retention.

1. Initial page erase sequence.
2. Second read/verify sequence.

and temperature of 10,000 cycles. described previously, before data retention is characterized. Figure 14. Flash/EE Memory Data Retention execution for applications where execution time is critical. needed to retrieve the 32-bit data from Flash/EE. needed to fetch any instruction. before accessing data for any value of CD bits. then four cycles are needed to fill the pipeline if CD = 0. are more complex and are summarized in Table 18. Table 18. Typical Execution Cycles in ARM/Thumb Mode multiple load/store instruction. takes 20 ms and a write (16 bits) word command takes 50 μs.

Rev. B | Page 34 of 140 ADuC7033 KERNEL The ADuC7033 features an on-chip kernel resident in the top 2 kB of the Flash/EE code space. After any reset event, this kernel copies the factory calibrated data from the manufacturing data space into the various on-chip peripherals. The peripherals calibrated by the kernel are as follows:

• Power supply monitor (PSM)
• Precision oscillator
• Low power oscillator
• REG_AVDD/REG_DVDD
• Low power voltage reference
• Normal mode voltage reference
• Current ADC (offset and gain)
• Voltage/temperature ADC (offset and gain) User MMRs that can be modified by the kernel and differ from their POR default values are as follows:
• R0 to R15
• GP0CON/GP2CON
• SYSCHK
• ADCMDE/ADC0CON
• FEE0ADR/FEE0CON/FEE0SIG
• HVDAT/HVCON
• HVCFG0/HVCFG1
• T3LD The ADuC7033 also features an on-chip LIN downloader. A flowchart of the execution of the kernel is shown in Figure 15. The current revision of the kernel can be derived from SYSSER1, as described in Table 100. For the duration of the kernel execution, the watchdog timer is active with a timeout period of 30 ms. This ensures that when an error occurs in the kernel, the ADuC7033 automatically resets. After a POR reset, the watchdog timer is disabled once the kernel code is exited. After any other reset, the watchdog timer maintains user code configuration for the period of the kernel, and is refreshed just prior to kernel exit. A minimum watchdog period of 30 ms is required. If LIN download mode is entered, the watchdog is periodically refreshed. Normal kernel execution time, excluding LIN download, is approximately 5 ms. It is only possible to enter and leave LIN download mode through a reset. SRAM is not modified during normal kernel execution; rather, SRAM is modified during a LIN download kernel execution. Note that even with NTRST = 0, user code is not executed unless Address 0x14 contains either 0x27011970 or the checksum of Page 0, excluding Address 0x14. If Address 0x14 does not contain this information, user code is not executed and LIN download mode is entered. With NTRST = 1, user code is always executed. During kernel execution, JTAG access is disabled.

Figure 15. ADuC7033 Kernel Flowchart

bank for the ADuC7033 is shown in Figure 16. (described in the ARM Registers section) reside in the MMR area. with a 32-bit read or write access. Figure 16. Top Level MMR Map

In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write. Table 19. IRQ Address Base = 0xFFFF0000 0x0000 IRQSTA 4 R 0x00000000 Active IRQ Source. See the Interrupt System section and Table 50. System section and Table 50. 0x0008 IRQEN 4 RW 0x00000000 Enabled IRQ Sources. See the Interrupt System section and Table 50. 0x000C IRQCLR 4 W MMR to Disable IRQ Sources. See the Interrupt System section and Table 50. 0x0100 FIQSTA 4 R 0x00000000 Active IRQ Source. See the Interrupt System section and Table 50. System section and Table 50. 0x0108 FIQEN 4 RW 0x00000000 Enabled IRQ Sources. See the Interrupt System section and Table 50. 0x010C FIQCLR 4 W MMR to Disable IRQ Sources. See the Interrupt System section and Table 50. 1 Depends on the level on the external interrupt pins (GPIO_0, GPIO_5, GPIO_7, and GPIO_8). Table 20. System Control Address Base = 0xFFFF0200 0x0220 SYSMAP0 1 RW N/A REMAP Control Register. See the Remap Operation section and Table 10. 0x0230 RSTSTA 1 RW N/A Reset Status MMR. See the Reset section and Table 11 and Table 12. 0x0234 RSTCLR 1 W N/A RSTSTA Clear MMR. See the Reset section and Table 11 and Table 12. 0x0240 SYSCHK 1 4 RW N/A Kernel Checksum. See the System Kernel Checksum section. Table 21. Timer Address Base = 0xFFFF0300 Registers (T0VAL0/T0VAL1) sections. Registers (T0VAL0/T0VAL1) sections. 0x0320 T1LD 4 RW 0x00000000 Timer1 Load Register. See th e Timer1 and Timer1 Load Registers sections. 0x0324 T1VAL 4 R 0xFFFFFFFF Timer1 Value Register. See the Timer1 and Timer1 Value Register sections. 0x0328 T1CON 4 RW 0x01000000 Timer1 Control MMR. See the Timer1 and Timer1 Control Register sections. 0x0330 T1CAP 4 R 0x00000000 Timer1 Capture Register. See th e Timer1 and Timer1 Capture Register sections.

Register sections and Table 55. Register, and Timer3 Control Register sections and Table 56. 0x0390 T4CAP 2 R 0x0000 Timer4 Capture Register. See the Timer4 or STI Timer section and Table 57. Table 22. PLL Base Address = 0xFFFF0400 0x0400 PLLSTA 4 R N/A PLL Status MMR. See the PLLSTA Register section. 0x0404 POWKEY0 4 W N/A POWCON Prewrite Key. See the POWCON Prewrite Key POWKEY0 section. 0x040C POWKEY1 4 W N/A POWCON Postwrite Key. See the POWCON Postwrite Key POWKEY1 section. 0x0410 PLLKEY0 4 W N/A PLLCON Prewrite Key. See the PLLCON Prewrite Key PLLKEY0 section. 0x0414 PLLCON 1 RW 0x00 PLL Clock Source Selection MMR. See the PLLCON Register section. 0x0418 PLLKEY1 4 W N/A PLLCON Postwrite Key. See the PLLCON Postwrite Key PLLKEY1 section. 0x042C OSC0TRM 1 RW 0xX8 Low Power Oscillator Trim Bits MMR. See the OSC0TRM Register section.

Table 23. ADC Address Base = 0xFFFF0500 0x0500 ADCSTA 2 R 0x0000 ADC Status MMR. See the ADC Status Register section and Table 35. 0x0508 ADCMDE 1 RW 0x00 ADC Mode Register. See the ADC Mode Register section and Table 36. Channel ADC Control Register section and Table 38. 0x0518 ADCFLT 2 RW 0x0007 ADC Filter Control MMR. See the ADC Filter Register section and Table 39. 0x0520 ADC0DAT 2 R 0x0000 Current ADC Result MMR. See the Current Channel ADC Data Register section. 0x0524 ADC1DAT 2 R 0x0000 Voltage ADC Result MMR. See the Voltage Channel ADC Data Register section. Calibration Register section. Threshold Count Limit Register section. ADC Threshold Count Register section. Voltage Reference Scaling Factor section.

Table 24. UART Base Address = 0xFFFF0700 0x0700 COMTX 1 W N/A UART Transmit Register. See the UART TX Register section. 0x0700 COMRX 1 R 0x00 UART Receive Register. See the UART RX Register section. Register 0 section and Table 85. 0x070C COMCON0 1 RW 0x00 UART Control Register 0. See the UART Control Register 0 section and Table 81. 0x0710 COMCON1 1 RW 0x00 UART Control Register 1. See the UART Control Register 1 section and Table 82. 0x0714 COMSTA0 1 R 0x60 UART Status Register 0. See the UART Status Register 0 section and Table 83. Table 25. LIN Hardware Sync Base Address = 0xFFFF0780 Register 0 section and Table 94. Register 1 section and Table 95. 0x0790 LHSVAL1 2 RW 0x0000 LHS Timer1 MMR. See the LIN Hardware Break Timer1 Register section. Table 26. High Voltage Interface Base Address = 0xFFFF0800 Control Register section and Table 71 and Table 72.

Table 27. STI Base Address = 0xFFFF0880 0x0880 STIKEY0 4 W N/A STICON Prewrite Key. See the Serial Test Interface Key0 Register section. 0x088C STIDAT0 2 RW 0x0000 STI Data MMR 0. See the Serial Test Interface Data0 Register section. 0x0890 STIDAT1 2 RW 0x0000 STI Data MMR 1. See the Serial Test Interface Data1 Register section. 0x0894 STIDAT2 2 RW 0x0000 STI Data MMR 2. See the Serial Test Interface Data2 Register section. Table 28. SPI Base Address = 0xFFFF0A00 0x0A00 SPISTA 1 R 0x00 SPI Status MMR. See the SPI Status Register section and Table 90. 0x0A04 SPIRX 1 R 0x00 SPI Receive MMR. See the SPI Receive Register section. 0x0A08 SPITX 1 W SPI Transmit MMR. See the SPI Transmit Register section. 0x0A0C SPIDIV 1 RW 0x1B SPI Baud Rate Select MMR. See the SPI Divider Register section. 0x0A10 SPICON 2 RW 0x0000 SPI Control MMR. See the SPI Control Register section and Table 89. Table 29. GPIO Base Address = 0xFFFF0D00 1 Depends on the level on the external GPIO pins.

Table 30. Flash/EE Base Address = 0xFFFF0E00 0x0E00 FEE0STA 1 R 0x20 Flash/EE Status MMR. 0x0E04 FEE0MOD 1 RW 0x00 Flash/EE Control MMR. 0x0E08 FEE0CON 1 RW 0x07 Flash/EE Control MMR. See Table 13. 0x0E0C FEE0DAT 2 RW 0x0000 Flash/EE Data MMR. 0x0E10 FEE0ADR 2 RW Flash/EE Address MMR. 0x0E18 FEE0SIG 3 R 0xFFFFFF Flash/EE LFSR MMR. 0x0E20 FEE0HID 4 RW 0xFFFFFFFF Flash/EE Protection MMR. See the Flash/EE Memory Security and Table 16. 0x0E80 FEE1STA 1 R 0x20 Flash/EE Status MMR. 0x0E84 FEE1MOD 1 RW 0x00 Flash/EE Control MMR. 0x0E88 FEE1CON 1 RW 0x07 Flash/EE Control MMR. See Table 13. 0x0E8C FEE1DAT 2 RW 0x0000 Flash/EE Data MMR. 0x0E90 FEE1ADR 2 RW 0x0000 Flash/EE Address MMR. 0x0E98 FEE1SIG 3 R 0xFFFFFF Flash/EE LFSR MMR. 0x0EA0 FEE1HID 4 RW 0xFFFFFFFF Flash/EE Protection MMR. See the Flash/EE Memory Security and Table 17.

Rev. B | Page 43 of 140 16-BIT, Σ-Δ ANALOG-TO-DIGITAL CONVERTERS The ADuC7033 incorporates two independent sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), namely: the current channel ADC (I-ADC) and the voltage/temperature channel ADC (V/T-ADC). These precision measurement channels integrate on-chip buffering, a programmable gain amplifier, 16-bit, Σ-Δ modulators, and digital filtering for precise measurement of current, voltage, and temperature variables in 12 V automotive battery systems. CURRENT CHANNEL ADC (I-ADC) The I-ADC converts battery current sensed through an external 100 μΩ shunt resistor. On-chip programmable gain means that the I-ADC can be configured to accommodate battery current levels from ±1 A to ±1500 A. As shown in Figure 17, the I-ADC employs a Σ-Δ conversion technique to realize 16 bits of no missing codes performance. The Σ-Δ modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital infor- mation. A modified Sinc3, programmable, low-pass filter is then employed to decimate the modulator output data stream to give a valid 16-bit data conversion result at programmable output rates from 4 Hz to 8 kHz in normal mode, and 1 Hz to 2 kHz in low power mode. The I-ADC also incorporates counter, comparator, and accumulator logic. This allows the I-ADC result to generate an interrupt after a predefined number of conversions have elapsed or if the I-ADC result exceeds a programmable threshold value. A fast ADC overrange feature is also supported. When enabled, a 32-bit accumulator automatically sums the 16-bit I-ADC results. The time to a first valid (fully settled) result on the current channel is three ADC conversion cycles with chop mode turned off and two ADC conversion cycles with chop mode turned on.

Figure 17. Current ADC, Top Level Overview

additional battery parameters such as voltage and temperature. ture sensor circuit, and an on-chip temperature sensor. mented in the voltage channel. via an on-chip, high voltage (divide-by-24), resistive attenuator. This must be enabled/disabled through HVCFG1[7]. temperature sensor or an external temperature sensor input. ADC conversion cycles with chop mode turned off. level overview of this ADC signal chain is shown in Figure 18. Figure 18. Voltage/Temperature ADC, Top Level Overview

(or 1 sigma) of the distribution of ADC output codes collected when the ADC input voltage is at a dc voltage. It is expressed as μV rms. Table 32. Current Channel ADC, Normal Power Mode, Typical Output RMS Noise 1 The maximum absolute input voltage allowed is −200 mV to +300 mV relative to ground. Table 33. Voltage Channel ADC, Typical Output RMS Noise (Referred to ADC Voltage Attenuator Input) Table 34. Temperature Channel ADC, Typical Output RMS Noise

MMRs described in detail in the following sections. Table 35. ADCSTA MMR Bit Designations Set automatically in hardware to indicate an ADC calibration cycle has been completed. Cleared after ADCMDE is written to. 14 ADC Temperature Conversion Error. conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. Cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register. 13 ADC Voltage Conversion Error. Cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register. 12 ADC Current Conversion Error. Cleared when a valid (in-range) current conversion result is written to the ADC0DAT register. 11 to 5 Not Used. These bits are reserved for future functionality and should not be monitored by user code. conversions equals the value in the ADC0THV MMR.

Rev. B | Page 49 of 140 Bit Description 2 Temperature Conversion Result Ready Bit. If the temperature channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is written in the temperature data register (ADC2DAT MMR). It is also set at the end of a calibration. Cleared by reading either ADC2DAT or ADC0DAT. 1 Voltage Conversion Result Ready Bit. If the voltage channel ADC is enabled, this bit is set by hardware as soon as a valid voltage conversion result is written in the voltage data register (ADC1DAT MMR). It is also set at the end of a calibration. Cleared by reading either ADC1DAT or ADC0DAT. 0 Current Conversion Result Ready Bit. If the current channel ADC is enabled, this bit is set by hardware as soon as a valid current conversion result is written in the current data register (ADC0DAT MMR). It is also set at the end of a calibration. Cleared by reading ADC0DAT. ADC Interrupt Mask Register Name: ADCMSKI Address: 0xFFFF0504 Default Value: 0x00 Access: Read/write Function: This register allows the ADC interrupt sources to be individually enabled. The bit positions in this register are the same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to a 1, the respective interrupt is enabled. By default, all bits are 0, meaning all ADC interrupt sources are disabled.

Function: The ADC Mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 36. ADCMDE MMR Bit Designations 7 Not Used. This bit is reserved for future functionality and should be written as 0 by user code. Set to 1 to select the 20 kΩ resistor as shown in Figure 20. Set to 0 to select the direct path to ground as shown in Figure 20 (default). 5 Low Power Mode Reference Select. Set to 0 to enable the low power voltage reference in either low power mode or low power plus mode (default). 4 to 3 ADC Power Mode Configuration. low power (131 kHz) oscillator to directly drive the ADC circuits. current consumed also ensures that the ADC noise performance is better than that achieved in ADC low power mode. 2 to 0 ADC Operation Mode Configuration. 000 = ADC power-down mode. All ADC circuits (including internal reference) are powered-down. 001 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts. 011 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. the calibration and conversion ready status bits are set at the end of an offset calibration cycle. is used, an ADC self-calibration should be performed on the temperature channel. fully settled calibration result is ready. against an external full-scale voltage driven at the ADC input pins.

Function: The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC. Note: If the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ADC are also reset. Table 37. ADC0CON MMR Bit Designations 15 Current Channel ADC Enable. Set to 1 by user code to enable the I-ADC. Clearing this bit to 0 powers down the I-ADC and resets the respective ADC ready bit in the ADCSTA MMR to 0. 14, 13 IIN Current Source Enable. 01 = enables 50 μA current source on IIN+. 10 = enables 50 μ A current source on IIN−. 11 = enables 50 μ A current source on both IIN− and IIN+. 12 to 10 Not Used. These bits are reserved for future functionality and should be written as zero. 9 Current Channel ADC Output Coding. Set to 1 by user code to configure I-ADC output coding as unipolar. Cleared to 0 by user code to configure I-ADC output coding as twos complement. 8 Not Used. This bit is reserved for future functionality and should be written as zero. 7, 6 Current Channel ADC Input Select. 01 = IIN−, IIN− = diagnostic, internal short configuration. reference is selected, REG_AVDD is used for VREF in this mode. This leads to ADC0DAT scaled by two. 5, 4 Current Channel ADC Reference Select. 01 = external reference inputs (VREF, GND_SW) are selected. 11 = (REG_AVDD, AGND) divided-by-two selected. 3 to 0 Current Channel ADC Gain Select. Note that the nominal I-ADC full-scale input voltage = (VREF/gain). 1xxx = I-ADC gain is undefined.

Function: The voltage/temperature channel ADC control MMR is a 16-bit register that is used to configure the V/T-ADC. Table 38. ADC1CON MMR Bit Designations 15 Voltage/Temperature Channel ADC Enable. also be enabled/disabled via HVCFG1[7] if measuring battery voltage. Clearing this bit to 0 powers down the V/T-ADC. 14, 13 VTEMP Current Source Enable. 01 = enables 50 μA current source on VTEMP . 10 = enables 50 μA current source on GND_SW. 11 = enables 50 μA current source on both VTEMP and GND_SW. 12 to 10 Not Used. These bits are reserved for future functionality and should not be modified by user code. 9 Voltage/Temperature Channel ADC Output Coding. Set to 1 by user code to configure V/T-ADC output coding as unipolar. Cleared to 0 by user code to configure V/T-ADC output coding as twos complement. 8 Not Used. This bit is reserved for future functionality and should be written as 0 by user code. 7, 6 Voltage/Temperature Channel ADC Input Select. 00 = VBAT/24, AGND. VBAT attenuator selected. 01 = VTEMP , GND_SW. External temperature input selected, conversion result written to ADC2DAT. gradient is 0.33 mV/°C; this is only applicable to the internal temperature sensor. 11 = internal short. Shorted input. 5, 4 Voltage/Temperature Channel ADC Reference Select. 00 = internal, 1.2 V precision reference selected. 01 = external reference inputs (VREF, GND_SW) selected. 3 to 0 Not Used. These bits are reserved for future functionality and should not be written as 0 by user code.

Function: The ADC Filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs. Note: If ADCFLT is modified, the current and voltage/temperature ADCs are reset. Table 39. ADCFLT MMR Bit Designations the settling time is two output periods. inactive) does not reduce the ADC output rate but does increase the settling time by one conversion period. Cleared by the user to disable the running average function. Sinc3 decimation factor in this table. where fNOTCH is the location of the first notch in the response. when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125. For SF = 126, fADC is forced to 60 Hz. For SF = 127, fADC is forced to 50 Hz. For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 40. that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in low power mode.

Table 40. ADC Conversion Rates and Settling Times 1 An additional time of approximately 60 μs per ADC is required before the first ADC is available. Table 41. Allowable Combinations of SF and AF

Function: The 8-bit ADC Configuration MMR controls extended functionality related to the on-chip ADCs. Table 42. ADCCFG MMR Bit Designations is not being used. This bit is used in conjunction with ADCMDE[6] to select a 20 kΩ resistor to ground. 6, 5 Current Channel (32-Bit) Accumulator Enable. twice) before the accumulator can be re-enabled to ensure the accumulator is reset. continues to accumulate negatively, below 0. 4, 3 Current Channel ADC Comparator Enable. 01 = comparator active, interrupt asserted if absolute value of I-ADC conversion result |I| ≥ ADC0TH. should not be used in ADC low power mode. 1 Not Used. This bit is reserved for future functionality and should be written as 0 by user code. when the ADC counter interrupt occurs.

Rev. B | Page 56 of 140 Current Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF0520 Default Value: 0x0000 Access: Read only Function: This ADC Data MMR holds the 16-bit conversion result from the I-ADC. The ADC does not update this MMR if the ADC0 conversion result ready bit (ADCSTA[0]) is set. A read of this MMR by the MCU clears all asserted ready flags (ADCSTA[2:0]). Voltage Channel ADC Data Register Name: ADC1DAT Address: 0xFFFF0524 Default Value: 0x0000 Access: Read only Function: This ADC Data MMR holds the 16-bit voltage conversion result from the V/T-ADC. The ADC does not update this MMR if the voltage conversion result ready bit (ADCSTA[1]) is set. If I-ADC is not active, a read of this MMR by the MCU clears all asserted ready flags (ADCSTA[2:1]). Temperature Channel ADC Data Register Name: ADC2DAT Address: 0xFFFF0528 Default Value: 0x0000 Access: Read only Function: This ADC Data MMR holds the 16-bit temperature conversion result from the V/T-ADC. The ADC does not update this MMR if the temperature conversion result ready bit (ADCSTA[2]) is set. If I-ADC and V-ADC is not active, a read of this MMR by the MCU clears all asserted ready flags (ADCSTA[2]). A ready of this MMR clears ADCSTA[2]. Current Channel ADC Offset Calibration Register Name: ADC0OF Address: 0xFFFF0530 Default Value: Part specific, factory programmed Access: Read/write access Function: This ADC Offset MMR holds a 16-bit offset calibration coefficient for the I-ADC. The register is configured at power-on with a factory default value. However, this register automatically over- writes if an offset calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Voltage Channel ADC Offset Calibration Register Name: ADC1OF Address: 0xFFFF0534 Default Value: Part specific, factory programmed Access: Read/write access Function: This offset MMR holds a 16-bit offset calibration coefficient for the voltage channel. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if an offset calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs.

Rev. B | Page 57 of 140 Temperature Channel ADC Offset Calibration Register Name: ADC2OF Address: 0xFFFF0538 Default Value: Part specific, factory programmed Access: Read/write Function: This ADC Offset MMR holds a 16-bit offset cali- bration coefficient for the temperature channel. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if an offset calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Current Channel ADC Gain Calibration Register Name: ADC0GN Address: 0xFFFF053C Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling the I-ADC conversion result. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if a gain calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Voltage Channel Gain Calibration Register Name: ADC1GN Address: 0xFFFF0540 Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling a voltage channel conversion result. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if a gain calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Temperature Channel Gain Calibration Register Name: ADC2GN Address: 0xFFFF0544 Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling a temperature channel conversion result. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if a gain calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs.

Rev. B | Page 58 of 140 Current Channel ADC Result Counter Limit Register Name: ADC0RCL Address: 0xFFFF0548 Default Value: 0x0001 Access: Read/write Function: This 16-bit MMR sets the number of conversions required before an ADC interrupt is generated. By default this register is set to 0x01. The ADC counter function must be enabled via the ADC result counter enable bit in the ADCCFG MMR. Current Channel ADC Result Count Register Name: ADC0RCV Address: 0xFFFF054C Default Value: 0x0000 Access: Read only Function: This 16-bit, read-only MMR holds the current number of I-ADC conversion results. It is used in conjunction with ADC0RCL to mask I-ADC interrupts, generating a lower interrupt rate. When ADC0RCV = ADC0RCL, the value in ADC0RCV resets to 0 and recommences counting. It can also be used in conjunction with the accumulator (ADC0ACC) to allow an average current calculation to be undertaken. The result counter is enabled via ADCCFG[0]. This MMR is also reset to 0 when the I-ADC is reconfigured, that is, when the ADC0CON or ADCMDE are written. Current Channel ADC Threshold Register Name: ADC0TH Address: 0xFFFF0550 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR sets the threshold against which the absolute value of the I-ADC conversion result is compared. In unipolar mode, ADC0TH[15:0] are compared, and in twos complement mode, ADC0TH[14:0] are compared. Current Channel ADC Threshold Count Limit Register Name: ADC0TCL Address: 0xFFFF0554 Default Value: 0x01 Access: Read/write Function: This 8-bit MMR determines how many cumulative (values below the threshold decrement or reset the count to 0) I-ADC conversion result readings above ADC0TH must occur before the I-ADC comparator threshold bit is set in the ADCSTA MMR, generating an ADC interrupt. The I-ADC comparator threshold bit is asserted as soon as ADC0THV = ADC0TCL. Current Channel ADC Threshold Count Register Name: ADC0THV Address: 0xFFFF0558 Default Value: 0x00 Access: Read only Function: This 8-bit MMR increments every time the absolute value of an I-ADC conversion result |I| ≥ ADC0TH. This register is decremented or reset to 0 every time the absolute value of an I-ADC conversion result |I| < ADC0TH. The configuration of this function is enabled via the current channel ADC comparator bits in the ADCCFG MMR. Current Channel ADC Accumulator Register Name: ADC0ACC Address: 0xFFFF055C Default Value: 0x00000000 Access: Read only Function: This 32-bit MMR holds the current accumulator value. The I-ADC ready bit in the ADCSTA MMR should be used to determine when it is safe to read this MMR. The MMR value is reset to 0 by disabling the accumulator in the ADCCFG MMR or reconfi- guring the current channel ADC.

Rev. B | Page 59 of 140 Low Power Voltage Reference Scaling Factor Name: ADCREF Address: 0xFFFF057C Default Value: Part specific, factory programmed Access: Read/write. This register should not be used if the precision reference is being used in low power mode (if ADCMDE[5] is set). Function: This allows user code to correct for the initial error of the LPM reference. If the LPM voltage reference is 1% below 1.200 V , then the value of ADCREF is approximately 0x7EB9. If the LPM voltage reference is 1% above 1.200 V , then the value of ADCREF is approximately 0x8147. This register corrects the effective value of the LPM reference at the temper- ature the reference is measured at during Analog Devices, Inc. production flow, which is 25°C. There is no change to the temperature coefficient of the LPM reference when using the ADCREF MMR. 0x8000 corresponds to no error when compared to the normal mode reference. The magnitude of the ADC result should be multiplied by the value in ADCREF and divided by 0x8000 to compensate for the actual value of the low power reference. ADC POWER MODES OF OPERATION The ADCs can be configured into various reduced or full power modes of operation by configuring ADCMDE[4:3] as appropriate. The ARM7 MCU can also be configured in low power modes of operation (POWCON[5:3]). The core power modes are indepen- dently controlled and are not related to the ADC power modes described in this section. Descriptions of the ADC power modes of operation follow. ADC Start-Up Procedure Prior to beginning a conversion, implement the following procedure: 1. Configure the current ADC (ADC0) into low power mode (ADC0CON = 0x8007; ADCMDE = 0x09). 2. Delay for 200 μs. 3. Switch the current ADC (ADC0) into idle mode (ADCMDE = 0x03), keeping ADC0CON unchanged. If the voltage or temperature channels are to be used, enable them at this time. 4. Delay for 1 ms. 5. Switch ADCMDE to desired mode, for example, ADCMDE = 0x1. ADC Normal Power Mode In normal mode, the current and voltage/temperature channels are fully enabled. The ADC modulator clock is 512 kHz and enables the ADCs to provide regular conversion results at a rate of between 4 Hz and 8 kHz (see the ADC Filter Register section). Both channels are under full control of the MCU and can be reconfigured at any time. The default ADC update rate for all channels in this mode is 1.0 kHz. It is worth emphasizing that I-ADC and V/T-ADC channels can be configured to initiate periodic, normal power mode, high accuracy, single conversion cycles before returning to ADC full power-down mode. This flexibility is facilitated under full MCU control via the ADCMDE MMR; it ensures that continuous peri- odic monitoring of battery current, voltage, and temperature settings is feasible yet ensuring the average dc current consump- tion is minimized. In ADC normal mode, the PLL must not be powered down. ADC Low Power Mode In ADC low power mode, the I-ADC is enabled in a reduced power and reduced accuracy configuration. The ADC modu- lator clock is driven directly from the on-chip 131 kHz low power oscillator, which allows the ADC to be configured at update rates as low as 1 Hz (ADCFLT). The gain of the ADC in this mode is fixed at 128. All of the ADC peripheral functions (result counter, digital comparator, and accumulator) described previously in the ADC Normal Power Mode section can still be enabled in low power mode. Typically, in low power mode, the I-ADC only is configured to run at a low update rate, continuously monitoring battery current. The MCU is in power-down mode and wakes up when the I-ADC interrupts the MCU. This happens after the I-ADC detects a current conversion beyond a preprogrammed threshold, setpoint, or a set number of conversions. It is also possible to select either the ADC precision voltage reference or the ADC low power mode voltage reference via ADCMDE[5]. ADC Low Power Plus Mode In low power plus mode, the I-ADC channel is enabled in a mode almost identical to low power mode (ADCMDE[4:3]). However, in this mode, the I-ADC gain is fixed at 512 and the ADC consumes an additional 200 μA (approximately) to yield improved noise performance relative to the low power mode setting. Again, all of the ADC peripheral functions (result counter, digital comparator, and accumulator) described in the ADC Normal Power Mode section can still be enabled in low power plus mode. As in low power mode, the I-ADC only is configured to run at a low update rate, continuously monitoring battery current. The MCU is in power-down mode and only wakes up when the I-ADC interrupts the MCU. This happens after the I-ADC detects a current conversion result beyond a preprogrammed threshold or setpoint.

Rev. B | Page 63 of 140 Self-Calibration In self (offset or gain) calibration, the ADC generates its calibration coefficient based on an internally generated 0 V in the case of self-offset calibration, and full-scale voltage in the case of self-gain calibration. It should be emphasized that ADC self-calibrations correct for offset and gain errors within the ADC. Self-calibrations cannot compensate for other external errors in the system, for example, shunt resistor tolerance/drift, external offset voltages, and so on. Note that in self-calibration mode, ADC0GN must first contain the values for PGA = 1, before a calibration scheme is started. System Calibration In system (offset or gain) calibration, the ADC generates its calibration coefficient based on an externally generated zero-scale voltage (in the case of system offset calibration) and full-scale voltage (in the case of system gain calibration), which are applied to the external ADC input for the duration of the calibration cycle. The duration of an offset calibration is a single conversion cycle (3/fADC with chop off, 2/fADC with chop on) before returning the ADC to idle mode. A gain calibration is a two-stage process and, therefore, takes twice as long as an offset calibration cycle. When a calibration cycle is initiated, any ongoing ADC conver- sion is immediately halted, the calibration is automatically carried out at an ADC update rate programmed into ADCFLT, and the ADC is always returned to idle after any calibration cycle. It is strongly recommended that ADC calibration is initiated at as low an ADC update rate as possible (high SF value in ADCFLT) to minimize the impact of ADC noise during calibration. Using the Offset and Gain Calibration If the Chop Enable Bit ADCFLT[15] is enabled, then internal ADC offset errors are minimized and an offset calibration may not be required. If chopping is disabled however, an initial offset calibration is required and may need to be repeated, particularly after a large change in temperature. A gain calibration, particularly in the context of the I-ADC (with internal PGA), may need to be carried out at all relevant system gain ranges depending on system accuracy requirements. If it is not possible to apply an external full-scale current on all gain ranges, then it is possible to apply a lower current and scale the result produced by the calibration. For example, apply a 50% current and then divide the ADC0GN value produced-by-two and write this value back into ADC0GN. Note that there is a lower limit to the input signal that can be applied for a system calibration because ADC0GN is only a 16-bit register. The input span (difference between the system zero-scale value and system full-scale value) should be greater than 40% of the nominal full- scale-input range, that is, >40% of VREF/gain. The on-chip Flash/EE memory can be used to store multiple calibration coefficients. These can be copied by user code directly into the relevant calibration registers, as appropriate, based on the system configuration. In general, the simplest way to use the calibration registers is to let the ADC calculate the values required as part of the ADC automatic calibration modes. A factory, or end-of-line calibration, for the I-ADC is a two- step procedure. 1. Apply 0 A current. Configure the ADC in the required PGA setting, and so on, and write to ADCMDE[2:0] to perform a system zero-scale calibration. This writes a new offset calibration value into ADC0OF. 2. Apply a full-scale current for the selected PGA setting. Write to ADCMDE to perform a system full-scale calibration. This writes a new gain calibration value into ADC0GN. Understanding the Offset and Gain Calibration Registers The output of the average block in the ADC signal flow (described previously from the ADC Sinc3 Digital Filter Response section to the Using the Offset and Gain Calibration section) can be considered a fractional number with a span for a ±full-scale input of approximately ±0.75. The span is less than ±1.0 because there is attenuation in the modulator to accommodate some overrange capacity on the input signal. The exact value of the attenuation varies slightly from part to part, because of manufacturing tolerances. The offset coefficient is read from the ADC0OF calibration register. This value is a 16-bit, twos complement number. The range of this number, in terms of the signal chain, is effectively ±1.0. Therefore, 1 LSB of the ADC0OF register is not the same as 1 LSB of ADC0DAT. A positive value of ADC0OF indicates that when offset is subtracted from the output of the filter, a negative value is added. The nominal value of this register is 0x0000, indicating zero offset is to be removed. The actual offset of the ADC can vary slightly from part to part and at different PGA gains. The offset within the ADC is minimized if the chopping mode is active (ADCFLT[15] = 1). The gain coefficient is a unitless scaling factor. The 16-bit value in this register is divided by 16,384 and then multiplied by the offset corrected value. The nominal value of this register equals 0x5555, corresponding to a multiplication factor of 1.3333. This scales the nominal ±0.75 signal to produce a full-scale output signal of ±1.0, which is checked for overflow/underflow and converted to twos complement or unipolar mode as appropriate before being output to the data register. The actual gain, and the required scaling coefficient for zero gain error, varies slightly from part to part, at different PGA settings, and in normal/low power mode. The value down- loaded into ADC0GN at power-on-reset represents the scaling factor for a PGA gain = 1. There is some level of gain error if this value is used at different PGA settings. User code can overwrite the calibration coefficients or run ADC calibrations to correct the gain error at the current PGA setting.

Rev. B | Page 64 of 140 Low Power Plus Mode In summary, the simplified ADC transfer function can be described as The PGA gain is set to 512 and the K factor is 8. NOMREF IN OUT ADCGN ADCGNADCOFV PGA VADC ×−×= ⎥ ⎡ In low power and low power plus modes, the K factor doubles if (REG_AVDD)/2 is used as the reference. ADC DIAGNOSTICS This equation is valid for the voltage/temperature channel ADC. The ADuC7033 features diagnostic capability on both ADCs. For the current channel ADC, Current ADC Diagnostics NOMREF IN OUT ADCGN ADCGNADCOF KV ⎡ The ADuC7033 features the capability to detect open-circuit conditions on the application board. This is accomplished using the two current sources on IIN+ and IIN−; these are controlled via ADC0CON[14:13]. where K is dependent on the PGA gain setting and ADC mode. Normal Mode Note that these current sources have a tolerance of ±30%. A PGA gain ≥ 2 (ADC0CON[3:0] ≥ 0001) must be used when current sources are enabled. For PGA gains of 1, 4, 8, 16, 32, and 64, the K factor is 1. For PGA gains of 2 and 128, the K factor is 2. For a PGA gain of 256, the K factor is 4. For a PGA gain of 512, the K factor is 8. Temperature ADC Diagnostics Low Power Mode The ADuC7033 features the capability to detect open-circuit conditions on the temperature channel inputs. This is accomplished using the two current sources on VTEMP and GND_SW , controlled via ADC1CON[14:13]. The PGA gain is set to 128 and the K factor is 32.

including the precision analog circuits on-chip. is recommended to ensure the stability of the regulators. RSTSTA MMR to indicate a POR reset event has occurred. enabled, the status of this bit can be monitored via HVMON[3]. cleared, then the SRAM contents can be corrupted. Figure 28. Typical Power-On Cycle

XTAL1 pin, the PLL lock status, and the PLL interrupt. core begins executing code as soon as the PLL begins oscillating. output divided by eight clock source while the PLL is locking. output divided by eight to the locked PLL output. resuming normal code execution. (prewrite key) and PLLKEY1 (postwrite key). POWKEY0 (prewrite key) and POWKEY1 (postwrite key). An example of writing to both MMRs follows. PLLCON = 0x0; //Switch to Low Power Osc. Function: This 8-bit register allows user code to monitor the lock state of the PLL and the status of the external crystal. Table 44. PLLSTA MMR Bit Designations if an external clock source is present. If present, this bit alternates high and low at a frequency of 32.768 kHz. 1 PLL Lock Status Bit, Read Only. Set when the PLL is locked and outputting 20.48 MHz. Clear when the PLL is not locked and outputting an fCORE divided by 8 clock source. Set if the PLL lock status bit signal goes low. Cleared by writing 1 to this bit.

PLLCON. PLLKEY0 is the prewrite key. PLLCON. PLLKEY1 is the postwrite key. three different oscillator sources. Table 45. PLLCON MMR Bit Designations 00 = lower power, 131 kHz oscillator. 01 = precision 131 kHz oscillator. 10 = external 32.768 kHz crystal.

1 If the user code switches MCU clock sources, a dummy MCU cycle should be

included after the clock switch is written to PLLCON. POWCON. POWKEY0 is the prewrite key. POWCON. POWKEY1 is the postwrite key.

Table 46. POWCON MMR Bit Designations 7 Precision 131 kHz Input Enable. Cleared by the user to power-down the precision 131 kHz input enable. Cleared by the user to power down the external crystal circuitry. Set by the user to enable the external crystal circuitry. source remain in normal power mode. 3, Bit 4, and Bit 5 must be cleared simultaneously. Set by default, and set by hardware on a wake-up event. GPIO interfaces, and SPI and UART serial ports. (Timer2) can remain active if driven from a low power oscillator even if this bit is cleared. Set by default, and/or by hardware, on a wake-up event. Cleared to power down the ARM core. Set by default, and set by hardware on a wake-up event. 2 to 0 CD Core Clock Divider Bits. oscillator trim register are used to implement this feature. 131 kHz, the typical trim range is between 127 kHz to 135 kHz. OSC0CON—control bits for calibration. OSC0STA—calibration status register. OSC0V AL0—9-bit counter, Counter 0. OSC0V AL1—10-bit counter, Counter 1. OSC0TRM—oscillator trim register. (OSC0V AL0) reaches 0x1FF, both counters are disabled.

• OSC0V AL0 = OSC0V AL1. No further action is required.
• OSC0V AL0 > OSC0V AL1. The low power oscillator is running slow. OSC0TRM must be decreased.
• OSC0V AL0 < OSC0V AL1. The low power oscillator is running fast. OSC0TRM must be increased. When the OSC0TRM is changed, the routine should be run again and the new frequency checked. Using the internal, precision 131 kHz oscillator, it takes approximately 4 ms to execute the calibration routine. If the external 32.768 kHz crystal is used, the time increases to 16 ms. Prior to the clock calibration routine being started, it is required that the user switch to either the precision 131 kHz oscillator or the external 32.768 kHz watch crystal to serve as the PLL clock source. If this is not done, the PLL can lose lock each time OSC0TRM is modified. This increases the length of time it takes to calibrate the low power oscillator. BEGIN CALIBRATION ROUTINE WHILE OSC0STA[0] = 1 INCREASE OSC0TRM DECREASE OSC0TRM OSC0VAL0 < OSC0VAL1 OSC0VAL0 > OSC0VAL1 END CALIBRATION ROUTINE IS ERROR WITHIN DESIRED LEVEL? OSC0VAL0 = OSC0VAL1 NO YES 06847-028

Figure 30. OSC0TRM Calibration Routine Table 47. OSC0TRM MMR Bit Designations 7 to 4 Reserved. Should be written as zeros. oscillator calibration routine. Table 48. OSC0CON MMR Bit Designations 7 to 5 Reserved. Should be written as 0. Set to select external 32.768 kHz crystal. counters and disable the calibration logic. Cleared to abort calibration.

power oscillator calibration routine. Table 49. OSC0STA MMR Bit Designations Cleared by a read of OSC0VAL1.

source as described in Table 50. interrupt sources are serviced. is set and can be cleared only by writing to T0CLRI. FIQSTA/IRQSTA[2] is not set and an interrupt does not occur. ARM core can only be powered up by a reset event if this occurs. Table 50. IRQ/FIQ MMRs Bit Designations

0 All interrupts OR’ed (FIQ only)

1 SWI: not used in IRQEN/CLR and FIQEN/CLR

2 Timer0 See the Timer0—Lifetime Timer section. 3 Timer1 See the Timer1 section. 4 Timer2 or wake-up timer See the Timer2 or Wake-Up Timer section. 5 Timer3 or watchdog timer See the Timer3 or Watchdog Timer section. 6 Timer4 or STI timer See the Timer4 or STI Timer section. 7 LIN hardware See the LIN (Local Interconnect Network) Interface section. 8 Flash/EE interrupt See the Flash/EE Control Interface section. 9 PLL lock See the System Clocks section. 10 ADC See the 16-Bit, Σ-Δ Analog-to-Digital Converters section. 11 UART See the UART Serial Interface section. 12 SPI master See the Serial Peripheral Interface section. 13 XIRQ0 (GPIO IRQ0 ) See the General-Purpose I/O section. 14 XIRQ1 (GPIO IRQ1) See the General-Purpose I/O section.

15 Reserved—should be written as 0

17 SPI slave See the Serial Peripheral Interface section. 18 XIRQ4 (GPIO IRQ4) See the General-Purpose I/O section. 19 XIRQ5 (GPIO IRQ5) See the General-Purpose I/O section.

handling of internal and external events. cleared when the interrupt in the particular peripheral is cleared. requiring an atomic read-modify-write. software in a common interrupt handler routine. are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. programmed source interrupt. Table 51. SWICFG MMR Bit Designations setting/clearing Bit 1 of FIQSTA and FIQSIG. setting/clearing Bit 1 of IRQSTA and IRQSIG. Figure 31. Interrupt Structure

The ADuC7033 features five general-purpose timer/counters.

• Timer0, or lifetime timer
• Timer1
• Timer2 or wake-up timer
• Timer3 or watchdog timer
• Timer4 or STI timer The five timers in their normal mode of operation can be in either free running mode or periodic mode. Timers are started by writing data to the control register of the corresponding timer (TxCON). The counting mode and speed depend on the configuration chosen in TxCON. In normal mode, an IRQ is generated each time the value of the counter reaches 0 when counting down, or each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing any value to clear the register of that particular timer (TxCLRI). The three timers in their normal mode of operation can be either free-running or periodic. In free-running mode, starting with the value in the TxLD register, the counter decrements/increments from the maximum/ minimum value until zero/full scale and starts again at the maximum/minimum value. This means that in free-running mode, TxV AL is not reloaded when the relevant interrupt bit is set but the count simply rolls over as the counter underflows or overflows. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero/full scale starts again from this value. This means when the relevant interrupt bit is set, TxV AL is reloaded with TxLD and counting starts again from this value. Loading the TxLD register with zero is not recommended. The value of a counter can be read at any time by accessing its value register (TxV AL). In addition, Timer0, Timer1, and Timer4 each have a capture register (T0CAP , T1CAP , and T4CAP , respectively) that can hold the value captured by an enabled IRQ event. The IRQ events are described in Table 52.

Table 52. Timer Event Capture

0 Timer0 or lifetime timer

1 Timer1

2 Timer2 or wake-up timer

3 Timer3 or watchdog timer

4 Timer4 or STI timer

5 LIN hardware

6 Flash/EE interrupt

7 PLL lock

8 ADC

9 UART

10 SPI master

11 XIRQ0 (GPIO_0)

12 XIRQ1 (GPIO_5)

13 Reserved

14 IRQ3 (high voltage interrupt)

15 SPI slave

16 XIRQ4 (GPIO_7), see the General-Purpose I/O section

17 XIRQ5 (GPIO_8), see the General-Purpose I/O section

Rev. B | Page 76 of 140 Starting Timer2 When starting Timer2, it is recommended to first load Timer2 with the required TxLD value. Next, start the timer by setting the T2CON bits as required. This enables the timer but only once the T2CON bits have been latched internally in the Timer2 clock domain. Therefore, it is advised that a delay of more than three clock periods (that is, 100 μs for a 32 kHz timer clock source) is inserted to allow both the T2LD value and the T2CON value to be latched through the synchronization logic and reach the Timer2 domain. After the delay, it is recommended that any (inadvertent) Timer2 interrupts are now cleared using T2CLRI = 0x00. Finally, the Timer2 system interrupt can be unmasked by setting the appropriate bit in the IRQEN MMR. An example of this code follows (where it is assumed that Timer2 is halted). Example Code T2LD = 0x1; //Reload timer T2CON = 0x02CF; //Enable T2, low power oscillator, 32768 prescaler Delay(100us); //Include delay to ensure T2CON bits take effect T2CLRI = 0 ; //*ClearTimerIrq IRQEN = WAKEUP_TIMER_BIT; //Unmask Timer2

20.48 MHz with a prescaler of 1. counter value can be read from T0V AL0 and T0V AL1. than by servicing an interrupt alone. Timer0 reloads the value from T0LD when Timer0 overflows. The Timer0 interface consists of six MMRS.

• T0LD is a 16-bit register holding the 16-bit value that is loaded into the counter. T0LD is only available in 16-bit mode.
• T0CAP is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event. T0CAP is only available in 16-bit mode.
• T0V AL0/T0V AL1 are 16-bit and 32-bit registers that hold the 16 least significant bits (LSBs) and 32 most significant bits (MSBs), respectively. T0V AL0 and T0V AL1 are read only. In 16-bit mode, 16-bit T0V AL0 is used. In 48-bit mode, both 16-bit T0V AL0 and 32-bit T0V AL1 are used.
• T0CLRI is an 8-bit register. Writing any value to this register clears the interrupt. T0CLRI is only available in 16-bit mode.
• T0CON is the configuration MMR described in Table 53. Timer0 Value Registers (T0VAL0/T0VAL1) Name: T0V AL0/T0V AL1 Address: 0xFFFF0304, 0xFFFF0308 Default Value: 0x0000, 0x00000000 Access: Read access only Function: T0V AL0 and T0V AL1 are 16-bit and 32-bit registers that hold the 16 LSBs and 32 MSBs, respectively. T0V AL0 and T0V AL1 are read only. In 16-bit mode, 16-bit T0V AL0 is used. In 48-bit mode, both 16-bit T0V AL0 and 32-bit T0V AL1 are used. Timer0 Capture Register Name: T0CAP Address: 0xFFFF0314 Default Value: 0x0000 Access: Read/write Function: This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Available only in 16-bit mode. TIMER0 VALUE LOW POWER 32.768kHz OSCILLATOR PRECISION 32.768kHz OSCILLATOR EXTERNAL 32.768kHz WATCH CRYSTAL CORE CLOCK FREQUENCY PRESCALER 1, 16, 256, OR 32768 TIMER0 IRQ48-BIT UP COUNTER 16-BIT UP/DOWN COUNTER 16-BIT LOAD CAPTUREIRQ[31:0] 06847-030

Figure 34. Timer0 Block Diagram

Function: The 32-bit MMR configures the mode of operation for Timer0. Table 53. T0CON MMR Bit Designations Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event Select Range (0 to 31). The events are as described in Table 52. 01 = low power (32.768 kHz) oscillator. 10 = external (32.768 kHz) watch crystal. 11 = precision (32.768 kHz) oscillator. 8 Count Up. Available in 16-bit mode only. Set by user for Timer0 to count up. Cleared by user for Timer0 to count down (default). Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 0 = 16-bit operation (default). 0000 = source clock/1 (default).

Rev. B | Page 79 of 140 Timer0 Load Registers Name: T0LD Address: 0xFFFF0300 Default Value: 0x0000 Access: Read/write Function: T0LD0 is the 16-bit register holding the 16-bit value that is loaded into the counter. Available in 16-bit mode only. Timer0 Clear Register Name: T0CLRI Address: 0xFFFF0310 Access: Write only Function: This 16-bit, write only MMR is written (with any value) by user code to clear the interrupt.

and with a prescaler of 1 (ignoring the external GPIOs). hours:minutes:seconds:hundredths. event with increased accuracy. The Timer1 interface consists of five MMRS.

• T1LD, T1V AL, and T1CAP are 32-bit registers and hold 32-bit unsigned integers. T1V AL and T1CAP are read only.
• T1CLRI is an 8-bit register. Writing any value to this register clears the Timer1 interrupt.
• T1CON is the configuration MMR described in Table 54. Timer1 features a postscaler allowing the user to count between 1 and 256 the number of Timer1 timeouts. To activate the post- scaler, the user sets Bit 18 and writes the desired number to count into Bits[31:24] of T1CON. When that number of timeouts is reached, Timer1 can generate an interrupt if T1CON[18] is set. Note that if the part is in a low power mode, and Timer1 is clocked from the GPIO or low power oscillator source, Timer1 continues to operate. Timer1 reloads the value from T1LD when Timer1 overflows. Timer1 Load Registers Name: T1LD Address: 0xFFFF0320 Default Value: 0x00000000 Access: Read/write Function: T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Timer1 Clear Register Name: T1CLRI Address: 0xFFFF032C Access: Write only Function: This 32-bit, write only MMR is written (with any value) by user code to clear the interrupt. Timer1 Value Register Name: T1VAL Address: 0xFFFF0324 Default Value: 0xFFFFFFFF Access: Read only Function: T1V AL is a 32-bit register that holds the current value of Timer1. TIMER1 VALUE LOW POWER 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY GPIO GPIO PRESCALER 1, 16, 256, OR 32768 TIMER1 IRQ 32-BIT UP/DOWN COUNTER 8-BIT POSTSCALER 32-BIT LOAD CAPTUREIRQ[31:0] 06847-031

Figure 35. Timer1 Block Diagram

Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Function: This 32-bit MMR configures the mode of operation of Timer1. Table 54. T1CON MMR Bit Designations By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1. By reading these eight bits, the current value of the counter is read. 23 Timer1 Enable Postscaler. Cleared to disable the Timer1 postscaler. 22 to 20 Reserved. These bits are reserved and should be written as 0 by user code. Set to select interrupt generation from the postscaler counter. Cleared to select interrupt generation directly from Timer1. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event select range, 0 to 31. The events are described in Table 52. 001 = low power 32.768 kHz oscillator. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down (default). Set by user to enable Timer1. Cleared by user to disable Timer1 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default).

10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). 0000 = source clock/1 (default). 20.48 MHz with a prescaler of 1. hours:minutes:seconds:hundredths. Timer2 reloads the value from T2LD when Timer2 overflows. The Timer2 interface consists of four MMRS. unsigned integers. T2V AL is read only. register clears the Timer2 interrupt.  T2CON is the configuration MMR described in Table 55. value that is loaded into the counter. any value) by user code to clear the interrupt. Figure 36. Timer2 Block Diagram

Function: This 16-bit MMR configures the mode of operation of Timer2. Table 55. T2CON MMR Bit Designations 10 to 9 Clock Source Select. 01 = low power (32.768 kHz) oscillator. 10 = external (32.768 kHz) watch crystal. 11 = precision (32.768 kHz) oscillator. Set by user for Timer2 to count up. Cleared by user for Timer2 to count down (default). Set by user to enable Timer2. Cleared by user to disable Timer2 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). 10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). This is only valid with a 32 kHz clock. 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). This is only valid with a 32 kHz clock. 0000 = source clock/1 (default). hours:minutes:seconds:hundredths. See Format 10 and Format 11 listed with Bits[5:4] in this table.

Figure 37. Timer3 Block Diagram Timer3 reloads the value from T3LD when Timer3 overflows. prescaler/256 and full scale in T3LD. erase cycle and kernel execution. reloads the counter with T3LD and begins a new timeout period. should only configure a minimum timeout period of 30 ms. that the watchdog timer continues to count during power-down. The Timer3 interface consists of four MMRs. T3CON is the configuration MMR described in Table 56. 16-bit unsigned integers. T3V AL is read only. timeout period in watchdog mode.

Function: The 16-bit MMR configures the mode of operation of Timer3 as described in detail in Table 56. Table 56. T3CON MMR Bit Designations 15 to 9 Reserved. These bits are reserved and should be written as 0 by user code. 8 Count Up/Count Down Enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. Set by user code to enable Timer3. Cleared by user code to disable Timer3. Set by user code to configure Timer3 to operate in periodic mode. Cleared by user to configure Timer3 to operate in free running mode. 5 Watchdog Timer Mode Enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. 4 Reserved. This bit is reserved and should be written as 0 by user code. 3 to 2 Timer3 Clock (32.768 kHz) Prescaler. 00 = source clock/1 (default). 1 Watchdog Timer IRQ Enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. Set by the user code to stop Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR. Cleared by the user code to enable Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR.

timer value is copied to T4CAP , and the timer continues running. Timer4 interface consists of five MMRs.

• T4LD, T4V AL, and T4CAP are 16-bit registers and hold 16-bit unsigned integers. T4V AL and T4CAP are read only.
• T4CLRI is an 8-bit register. Writing any value to this register clears the interrupt.
• T4CON is the configuration MMR described in Table 57. Timer4 Load Register Name: T4LD Address: 0xFFFF0380 Default Value: 0x00000 Access: Read/write Function: T4LD 16-bit register holds the 16-bit value that is loaded into the counter. Timer4 Clear Register Name: T4CLRI Address: 0xFFFF038C Access: Write only Function: This 8-bit, write only MMR is written (with any value) by user code to clear the interrupt. Timer4 Value Register Name: T4VAL Address: 0xFFFF0384 Default Value: 0xFFFF Access: Read only Function: T4V AL is a 16-bit register that holds the current value of Timer4. Timer4 Capture Register Name: T4CAP Address: 0xFFFF0390 Default Value: 0x0000 Access: Read only Function: This is a 16-bit register that holds the 32-bit value captured by an enabled IRQ event. Timer4 Control Register Name: T4CON Address: 0xFFFF0388 Default Value: 0x00000000 Access: Read/write Function: This 32-bit MMR configures the mode of operation of Timer4. PRESCALER 1, 16, 256, OR 32768 STI TIMER4 IRQ16-BIT UP/DOWN COUNTER LOW POWER 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY 16-BIT LOAD TIMER4 VALUE CAPTUREIRQ[31:0] 06847-034

Figure 38. Timer4 Block Diagram

Table 57. T4CON MMR Bit Designations Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16 to 12 Event Select Range, 0 to 31. The events are described in Table 52. 1 = low power (32.768 kHz) oscillator. Set by user for Timer4 to count up. Cleared by user for Timer4 to count down (default). Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Set by user to operate in periodic mode. Cleared by user to operate in free running mode. Default mode. 0000 = source clock/1 (default).

0.8 mA and a source capability of 0.1 mA. Table 58. A typical GPIO structure is shown Figure 39. one CD divided core clock to guarantee recognition.

• GPxCON: Portx control register
• GPxDAT: Portx configuration and data register
• GPxSET: Data Set Portx
• GPxCLR: Data Clear Portx where x corresponds to the port number (0, 1, or 2). During normal operation, user code can control the function and state of the external GPIO pins by these general-purpose registers. All GPIO pins retain their external level (high or low) during power-down (POWCON) mode. 1ONLY AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8. GPIO REG_DVDD OUTPUT DRIVE ENABLE GPxDAT[31:24] OUTPUT DATA GPxDAT[23:16] INPUT DATA GPxDAT[7:0] GPIO IRQ1 06847-035

Figure 39. ADuC7033 GPIO

Table 58. External GPIO Pin to Internal Port Signal Assignments Port0 GPIO_0 P0.0 General-Purpose I/O. IRQ0 External Interrupt Request 0. SS Slave Select I/O for SPI. GPIO_1 P0.1 General-Purpose I/O. SCLK Serial Clock I/O for SPI. GPIO_2 P0.2 General-Purpose I/O. MISO Master Input, Slave Output for SPI. GPIO_3 P0.3 General-Purpose I/O. MOSI Master Output, Slave Input for SPI. GPIO_4 P0.4 General-Purpose I/O. P0.5 1 High Voltage Serial Interface. P0.6 1 High Voltage Serial Interface. Port1 GPIO_5 P1.0 General-Purpose I/O. IRQ1 External Interrupt Request 1. GPIO_6 P1.1 General-Purpose I/O. Port2 GPIO_7 Port2.0 General-Purpose I/O. IRQ4 External Interrupt Request 4. LIN output pin Used to read directly from LIN pin for conformance testing. GPIO_8 P2.1 General-Purpose I/O. IRQ5 External Interrupt Request 5. LIN input pin Used to directly drive LIN pin for conformance testing. GPIO_11 2 P2.42 General-Purpose I/O; LIN/BSD Input Pin. GPIO_12 2 P2.52 General-Purpose I/O; LIN/BSD Output Pin. GPIO_13 1 P2.6 1 General-Purpose I/O; STI Data Output. readback (GPIO_11) capability.

Function: The 32-bit MMR selects the pin function for each Port0 pin. Table 59. GP0CON MMR Bit Designations 31 to 29 Reserved. These bits are reserved and should be written as 0 by user code. 28 Reserved. This bit is reserved and should be written as 1 by user code. 27 to 25 Reserved. These bits are reserved and should be written as 0 by user code. using the HVCON and HVDAT registered high voltage interface. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. using the HVCON and HVDAT registered high voltage interface. 19 to 17 Reserved. These bits are reserved and should be written as 0 by user code. 16 GPIO_4 Function Select Bit. Cleared by user code to 0 to configure the GPIO_4 pin as a general-purpose I/O (GPIO) pin. Set to 1 by user code to configure the GPIO_4 pin as ECLK enabling a 2.56 MHz clock output on this pin. 15 to 13 Reserved. These bits are reserved and should be written as 0 by user code. 12 GPIO_3 Function Select Bit. Cleared by user code to 0 to configure the GPIO_3 pin as a general-purpose I/O (GPIO) pin. Set to 1 by user code to configure the GPIO_3 pin as MOSI, master output, and slave input data for the SPI port. 11 to 9 Reserved. These bits are reserved and should be written as 0 by user code. 8 GPIO_2 Function Select Bit. Cleared to 0 by user code to configure the GPIO_2 pin as a general-purpose I/O (GPIO) pin. Set to 1 by user code to configure the GPIO_2 pin as MISO, master input, and slave output data for the SPI port. 7 to 5 Reserved. These bits are reserved and should be written as 0 by user code. 4 GPIO_1 Function Select Bit. Cleared to 0 by user code to configure the GPIO_1 pin as a general-purpose I/O (GPIO) pin. Set to 1 by user code to configure the GPIO_1 pin as SCLK, serial clock I/O for the SPI port. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_0 Function Select Bit. Cleared to 0 by user code to configure the GPIO_0 pin as a general-purpose I/O (GPIO) pin. Set to 1 by user code to configure the GPIO_0 pin as SS, slave select I/O for the SPI port.

Function: The 32-bit MMR selects the pin function for each Port1 pin. Table 60. GP1CON MMR Bit Designations 31 to 5 Reserved. These bits are reserved and should be written as 0 by user code. 4 GPIO_6 Function Select Bit. Cleared by user code to 0 to configure the GPIO_6 pin as a general-purpose I/O (GPIO) pin. Set to 1 by user code to configure the GPIO_6 pin as TxD, transmit data for UART serial port. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_5 Function Select Bit. Cleared by user code to 0 to configure the GPIO_5 pin as a general-purpose I/O (GPIO) pin. Set by user code to 1 to configure the GPIO_5 RxD, receive data for UART serial port. Function: The 32-bit MMR selects the pin function for each Port2 pin. Table 61. GP2CON MMR Bit Designations 31 to 25 Reserved. These bits are reserved and should be written as 0 by user code. 24 GPIO_13 Function Select Bit. Set to 1 by user code to route the STI data output to the STI pin. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. 20 GPIO_12 Function Select Bit. Set to 1 by user code to route the UART TxD (transmit data) to the LIN/BSD data pin. This configuration is used in LIN mode. 19 to 17 Reserved. These bits are reserved and should be written as 0 by user code. 16 GPIO_11 Function Select Bit. support diagnostic readback on all external high voltage I/O pins (see HVCFG1[2:0]). logic and to the UART RxD (receive data). This mode must be configured by user code when using LIN or BSD modes. 15 to 5 Reserved. These bits are reserved and should be written as 0 by user code.

Rev. B | Page 92 of 140 Bit Description 4 GPIO_8 Function Select Bit. Cleared by user code to 0 to configure the GPIO_8 pin as a general-purpose I/O (GPIO) pin. Set by user code to 1 to route the LIN/BSD input data to the GPIO_8 pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU or UART. 3 to 1 Reserved. These bits are reserved and should be written as 0 by user code. 0 GPIO_7 Function Select Bit. Cleared by user code to 0 to configure the GPIO_7 pin as a general-purpose I/O (GPIO) pin. Set by user code to 1 to route data driven into the GPIO_7 pin through the on-chip LIN transceiver to be output at the LIN/BSD pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU or UART.

output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 62. GP0DAT MMR Bit Designations 31 to 29 Reserved. These bits are reserved and should be written as 0 by user code. 28 Port0.4 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.4 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port0.4 as an output. 27 Port0.3 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.3 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port0.3 as an output. 26 Port0.2 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.2 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port0.2 as an output. 25 Port0.1 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.1 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port0.1 as an output. 24 Port0.0 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port0.0 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port0.0 as an output. 23 to 21 Reserved. These bits are reserved and should be written as 0 by user code. 20 Port0.4 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.4. 19 Port0.3 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.3. 18 Port0.2 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.2. 17 Port0.1 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.1. 16 Port0.0 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.0. 15 to 5 Reserved. These bits are reserved and should be written as 0 by user code.

output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 63. GP1DAT MMR Bit Designations 31 to 26 Reserved. These bits are reserved and should be written as 0 by user code. 25 Port1.1 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port1.1 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port1.1 as an output. 24 Port1.0 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port1.0 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port1.0 as an output. 23 to 18 Reserved. These bits are reserved and should be written as 0 by user code. 17 Port1.1 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port1.1. 16 Port1.0 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port1.0. 15 to 2 Reserved. These bits are reserved and should be written as 0 by user code.

output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 64. GP2DAT MMR Bit Designations 31 Reserved. This bit is reserved and should be written as 0 by user code. 30 Port2.6 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port2.6 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port2.6 as an output. 29 Port2.5 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port2.5 as an input. diagnostic write capability to the high voltage I/O pins. 28 Port2.4 Direction Select Bit. diagnostic readback capability from the high voltage I/O pins (see HVCFG1[2:0]). Set to 1 by user code to configure the GPIO pin assigned to Port2.4 as an output. 27 to 26 Reserved. These bits are reserved and should be written as 0 by user code. 25 Port2.1 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port2.1 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port2.1 as an output. 24 Port2.0 Direction Select Bit. Cleared to 0 by user code to configure the GPIO pin assigned to Port2.0 as an input. Set to 1 by user code to configure the GPIO pin assigned to Port2.0 as an output. 23 Reserved. This bit is reserved and should be written as 0 by user code. 22 Port2.6 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port2.6. 21 Port2.5 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port2.5. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. 17 Port2.1 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port2.1. 16 Port2.0 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port2.0. 15 to 7 Reserved. These bits are reserved and should be written as 0 by user code. 3 to 2 Reserved. These bits are reserved and should be written as 0 by user code.

user code requires when using GP0DAT). Table 65. GP0SET MMR Bit Designations 31 to 21 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_4 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_4 pin. Set to 1 by user code to set the external GPIO_3 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_3 pin. Set to 1 by user code to set the external GPIO_2 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_2 pin. Set to 1 by user code to set the external GPIO_1 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_1 pin. Set to 1 by user code to set the external GPIO_0 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_0 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. user code requires when using GP1DAT). Table 66. GP1SET MMR Bit Designations 31 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_6 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_6 pin. Set to 1 by user code to set the external GPIO_5 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_5 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

Table 67. GP2SET MMR Bit Designations 31 to 23 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_13 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_13 pin. Set to 1 by user code to set the external GPIO_12 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_12 pin. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to set the external GPIO_8 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_8 pin. Set to 1 by user code to set the external GPIO_7 pin high. If user software clears this bit to 0, it has no effect on the external GPIO_7 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. Table 68. GP0CLR MMR Bit Designations 31 to 21 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_4 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_4 pin. Set to 1 by user code to clear the external GPIO_3 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_3 pin. Set to 1 by user code to clear the external GPIO_2 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_2 pin. Set to 1 by user code to clear the external GPIO_1 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_1 pin. Set to 1 by user code to clear the external GPIO_0 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_0 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

(as user code requires when using GP1DAT). Table 69. GP1CLR MMR Bit Designations 31 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_6 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_6 pin. Set to 1 by user code to clear the external GPIO_5 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_5 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code. (as user code requires when using GP2DAT). Table 70. GP2CLR MMR Bit Designations 31 to 23 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_13 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_8 pin. Set to 1 by user code to clear the external GPIO_12 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_7 pin. 20 to 18 Reserved. These bits are reserved and should be written as 0 by user code. Set to 1 by user code to clear the external GPIO_8 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_8 pin. Set to 1 by user code to clear the external GPIO_7 pin low. If user software clears this bit to 0, it has no effect on the external GPIO_7 pin. 15 to 0 Reserved. These bits are reserved and should be written as 0 by user code.

suggests) indirectly via the HVCON and HVDAT MMRs.

• Precision oscillator
• Wa ke-up ( WU) pin f u nc t iona lity
• Power supply monitor (PSM)
• Low voltage flag (LVF)
• LIN operating modes
• STI diagnostics
• High voltage diagnostics
• High voltage attenuator/buffer circuit
• High voltage (HV) temperature monitor ARM7 MCU AND PERIPHERALS HIGH VOLTAGE INTERFACE MMRs HVCON HVDAT PRECISION OSCILLATORHVCFG0[6] LVFHVCFG0[2] LIN MODES PSMHVCFG0[3] ATTENUATOR AND BUFFERHVCFG1[5] HVCFG1[7] HV TEMP MONITOR HVCFG1[6] HVCFG1[3] HVCFG0 (INDIRECT) HIGH VOLTAGE REGISTERS HVCFG1 HVSTA HVMON SERIAL INTERFACE CONTROLLER SERIAL DATA SERIAL CLOCK HIGH VOLTAGE INTERRUPT CONTROLLER PSM—HVSTA[5] WU—HVSTA[4] OVER TEMP—HVSTA[3] LIN S-SCT—HVSTA[2] STI S-SCT—HVSTA[1] WU S-SCT—HVSTA[0] IRQ3 (IRQEN[16]) HIGH VOLTAGE DIAGNOSTIC CONTROLLER WU DIAGNOSTIC INPUT HVCFG0[4] STI DIAGNOSTIC INPUT P2.6 LIN DIAGNOSTIC INPUT P2.5 WU DIAGNOSTIC OUTPUT HVMON[7] STI DIAGNOSTIC OUTPUT HVMON[5] LIN DIAGNOSTIC OUTPUT P2.4 HVCFG0[5] HVCFG0[1:0] WU I/O CONTROL HVCFG0[4] HVCFG1[4] HVCFG1[4] STI I/O CONTROL HVCFG1[3] 06847-036

Figure 40. High Voltage Interface, Top Level Block Diagram

register are interpreted as read or write commands to a set of four indirect registers related to the high voltage circuits. The HVDAT register is used to store data to be written to, or read back from, the indirect registers. Table 71. HVCON MMR Write Bit Designations 0x00 = read back High Voltage Register HVCFG0 into HVDAT. 0x01 = read back High Voltage Register HVCFG1 into HVDAT. 0x02 = read back High Voltage Status Register HVSTA into HVDAT. 0x03 = read back High Voltage Status Register HVMON into HVDAT. 0x08 = write the value in HVDAT to the High Voltage Register HVCFG0. 0x09 = write the value in HVDAT to the High Voltage Register HVCFG1. All other command bytes are reserved and should not be written by user code. Table 72. HVCON MMR Read Bit Designations 2 Transmit Command to High Voltage Die Status. 1 = command completed successfully. 1 Read Command from High Voltage Die Status. 1 = command completed successfully. 0 = high voltage interface is not busy and has completed the command written to HVCON. Bit 1 and Bit 2 are valid.

high voltage interface registers. Table 73. HVDAT MMR Bit Designations 0x00 = read back High Voltage Register HVCFG0 into HVDAT. 0x01 = read back High Voltage Register HVCFG1 into HVDAT. 0x02 = read back High Voltage Status Register HVSTA into HVDAT. 0x03 = read back High Voltage Status Register HVMON into HVDAT. 0x08 = write the value in HVDAT to the High Voltage Register HVCFG0. 0x09 = write the value in HVDAT to the High Voltage Register HVCFG1. 7 to 0 High Voltage Data to Read/Write.

this register is loaded via the HVDAT MMR, and data is read back from this register via the HVDAT MMR. Table 74. HVCFG0 Bit Designations 7 Wake/STI Thermal Shutdown Disable. Set to 1 to disable the automatic shutdown of the wake/STI driver when a thermal event occurs. Cleared to 0 to enable the automatic shutdown of the wake/STI driver when a thermal event occurs. 6 Precision Oscillator Enable Bit. interface latency of 10 μs). Cleared to 0 to power down the precision, 131 kHz oscillator. 5 Bit Serial Device (BSD) Mode Enable Bit. Cleared to 0 to enable an internal (LIN) pull-up resistor on the LIN/BSD pin. Set to 1 to disable the internal (LIN) pull-up and configure the LIN/BSD pin for BSD operation. Set to 1 to assert the external WU pin high. Cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor. 3 Power Supply Monitor (PSM) Enable Bit. Cleared to 0 to disable the power supply (voltage at the VDD pin) monitor. while IRQ3 (IRQEN[16]) is enabled, the PSM generates an interrupt. 2 Low Voltage Flag (LVF) Enable Bit. Cleared to 0 to disable the LVF function. determine if the REG_DVDD voltage previously dropped below 2.1 V. 1 to 0 LIN Operating Mode. These bits enable/disable the LIN driver. 01 = reserved (not LIN 2.0 compliant).

this register is loaded through HVDAT and data is read back from this register using HVDAT. Table 75. HVCFG1 Bit Designations Cleared to 0 to disable the internal voltage attenuator and attenuator buffer. Set to 1 to enable the internal voltage attenuator and attenuator buffer. negative temperature coefficient of typically −2.1 mV/°C. monitor is routed directly to the voltage channel ADC. Cleared to 0 to disable the on-chip, high voltage temperature monitor. 5 Voltage Channel Short Enable Bit. allows noise be measured as a self-diagnostic test. Cleared to 0 to disable an internal short on the voltage channel. 4 WU and STI Readback Enable Bit. Cleared to 0 to disable input capability on the external WU/STI pins. the HVMON register (HVMON[7] and HVMON[5]). 3 High Voltage I/O Driver Enable Bit. enabling the high voltage I/O pins. 2 Enable/Disable Short-Circuit Protection (LIN/BSD and STI). does not disable the short-circuiting pin. circuiting pin. When disabled, the I/O pin can only be re-enabled by writing to HVCFG1[3]. 1 WU Pin Timeout (Monoflop) Counter Enable/Disable. Set to disable the WU I/O timeout counter. 0 WU Open-Circuit Diagnostic Enable. Cleared to disable an internal WU I/O diagnostic pull-up resistor.

HVCON registered interface, and data is read back from this register via HVDAT. Table 76. HVMON Bit Designations 7 WU Pin Diagnostic Readback. When enabled via HVCFG1[4], this read-only bit reflects the state of the external WU pin. This bit is 0 if a thermal shutdown event has not occurred. This bit is 1 if a thermal shutdown event has occurred. 5 STI Pin Diagnostic Readback. When enabled via HVCFG1[4], this read-only bit reflects the state of the external STI pin. This bit is 0 if the voltage channel ADC input buffer is disabled. This bit is 1 if the voltage channel ADC input buffer is enabled. 3 Low Voltage Flag Status Bit. Valid only if enabled via HVCFG0[2]. This bit is 0 on power-on if REG_DVDD has dropped below 2.1 V. In this state, RAM contents can be deemed corrupt. is only cleared by re-enabling the low voltage flag in HVCFG0[2]. 2 LIN/BSD Short-Circuit Status Flag. This bit is 0 if the LIN/BSD driver is operating normally. 1 STI Short-Circuit Status Flag. This bit is 0 if the STI driver is operating normally. 0 Wake Short-Circuit Status Flag. This bit is 0 if the wake driver is operating normally. This bit is 1 if the wake driver has experienced a short-circuit condition.

(HVSTA) into the HVDAT register. Table 77. HVSTA Bit Designations 7 to 6 Reserved. These bits should not be used and are reserved for future use. 5 PSM Status Bit. Valid only if enabled via HVCFG0[3]. This bit is not latched and the IRQ needs to be enabled to detect it. This bit is 0 if the voltage at the VDD pin stays above 6.0 V. This bit is 1 if the voltage at the VDD pin drops below 6.0 V. that a rising or falling edge transition on the WU pin generated a high voltage interrupt. 3 Overtemperature. This bit is always enabled. This bit is 0 if a thermal shutdown event has not occurred. automatically disabled once a thermal shutdown has occurred. 2 LIN/BSD Short-Circuit Status Flag. This bit is 0 during normal LIN/BSD operation and is cleared automatically by reading the HVSTA register. This bit is 1 if a LIN/BSD short circuit is detected. In this condition, the LIN driver is automatically disabled. 1 STI Short-Circuit Status Flag. This bit is 0 if the STI driver is operating normally and is cleared automatically by reading the HVSTA register. This bit is 1 if the STI driver has experienced a short-circuit condition. 0 WU Short-Circuit Status Flag. This bit is 0 during normal wake operation. This bit is 1 if a wake-up short circuit is detected.

internal 10 kΩ pull-down resistor and high-side FET driver. output by writing directly to HVCFG0[4]. monoflop (a 1.3-second timeout timer) is included. the wake-up driver should be disabled after 1.3 seconds. The WU pin also features a short-circuit detection feature. 400 μs, a high voltage interrupt is generated with HVMON[0] set. during a thermal event via HVCFG0[7]. Figure 41. WU Circuit, Block Diagram

high voltage interrupt and the appropriate action can be taken. functionality using HVCFG0[2]. STI bus as listed in Table 78. Table 78. High Voltage Diagnostics more than 100 mA is continuously drawn. Drive LIN high LIN/STI readback reads back low. Drive WU low Readback high in HVMON[7]. than 100 mA typically is sourced.

GPIO_6/TxD pins of the ADuC7033. tion options selectable in the configuration register.

450 UART Baud Rate Generation section and the Fractional

Table 79 lists common baud rate values. Table 79. Baud Rate Using the Standard Baud Rate Generator erator allows the generation of accurate, high speed baud rates. Figure 42. Fractional Divider Baud Rate Generation

2048 CD × × × ×= + DLrate Baud

Table 80 lists common baud rate values. Table 80. Baud Rate Using the Fractional Baud Rate Generator

• COMTX: 8-bit transmit register
• COMRX: 8-bit receive register
• COMDIV0: divisor latch (low byte)
• COMDIV1: divisor latch (high byte)
• COMCON0: line control register
• COMSTA0: line status register
• COMIEN0: interrupt enable register
• COMIID0: interrupt identification register
• COMDIV2: 16-bit fractional baud divide register COMTX, COMRX, and COMDIV0 share the same address location. COMTX and COMRX can be accessed when Bit 7 in the COMCON0 register is cleared. COMDIV0 can be accessed when Bit 7 of COMCON0 is set.

Rev. B | Page 109 of 140 UART Tx Register Name: COMTX Address: 0xFFFF0700 Access: Write only Function: Write to this 8-bit register to transmit data using the UART . UART Rx Register Name: COMRX Address: 0xFFFF0700 Default Value: 0x00 Access: Read only Function: This 8-bit register is read from to receive data transmitted using the UART. UART Divisor Latch Register 0 Name: COMDIV0 Address: 0xFFFF0700 Default Value: 0x00 Access: Read/write Function: This 8-bit register contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates. UART Divisor Latch Register 1 Name: COMDIV1 Address: 0xFFFF0704 Default Value: 0x00 Access: Read/write Function: This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates.

Function: This 8-bit register controls the operation of the UART in conjunction with COMCON1. Table 81. COMCON0 MMR Bit Designations 7 DLAB Divisor Latch Access. Set by user to enable access to COMDIV0 and COMDIV1 registers. Set by user to force TxD to 0. Cleared to operate in normal mode. 5 SP Stick Parity. Set by user to force parity to defined values. 4 EPS Even Parity Select Bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. Cleared by the user to generate one stop bit in the transmitted data. 1 to 0 WLS Word Length Select.

Function: This 8-bit register controls the operation of the UART in conjunction with COMCON0. Table 82. COMCON1 MMR Bit Designations 00 = RxD driven by LIN input; required for LIN communications using the LIN pin. 10 = RxD driven by GP5; required for serial communications using GPIO_5 pin (RxD). 4 LOOPBACK Loopback. Set by user to enable loopback mode. In loopback mode, the TxD is forced high. Function: This 8-bit, read-only register reflects the current status on the UART. Table 83. COMSTA0 MMR Bit Designations 6 TEMT COMTX and Shift Register Empty Status Bit. transmitted, that is, it is no longer present in the shift register. Cleared automatically when writing to COMTX. 5 THRE COMTX Empty Status Bit. may not have been transmitted yet and can still be present in the shift register. Cleared automatically when writing to COMTX. Set when SIN is held low for more than the maximum word length. Set when the stop bit is invalid. Set when a parity error occurs. Set automatically if data are overwritten before being read. Set automatically when COMRX is full.

Function: The 8-bit register enables and disables the individual UART interrupt sources. Table 84. COMIEN0 MMR Bit Designations 3 EDSSI Reserved. This bit should be written as 0. 2 ELSI RxD Status Interrupt Enable Bit. 1 ETBEI Enable Transmit Buffer Empty Interrupt. 0 ERBFI Enable Receive Buffer Full Interrupt. Set by the user to enable an interrupt when the buffer is full during a reception. Function: This 8-bit register reflects the source of the UART interrupt. Table 85. COMIID0 MMR Bit Designations

Function: This 16-bit register controls the operation of the fractional divider for the ADuC7033. Table 86. COMDIV2 MMR Bit Designations 15 FBEN Fractional Baud Rate Generator Enable Bit. Set by the user to enable the fractional baud rate generator. Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator. and Table 80 for common baud rate values.

transmitted and received simultaneously, that is, full duplex. and consists of four pins that are multiplexed with four GPIOs. Table 88. SPI Speed vs. Clock Divider Bits in Master Mode accepts data from an external master up to 5.12 Mb at CD = 0. as byte-wide (8-bit) serial data, MSB first. for the master and slave devices. . In slave mode, SS is always an input. wide (8-bit) serial data, MSB first. master mode and as an input in slave mode.

Function: The 16-bit MMR configures the serial peripheral interface. Table 89. SPICON MMR Bit Designations 12 Continuous Transfer Enable. the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty. exists in the SPITX register, a new transfer is initiated after a stall period. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. Set by user to enable the slave output. Cleared by user to disable slave output. 9 Slave Select Input Enable. Set by user in master mode to enable the output. 8 SPIRX Overflow Overwrite Enable. Set by the user, the valid data in the SPIRX register is overwritten by the new serial byte received. Cleared by the user, the new serial byte received is discarded. Set by the user to transmit the previous data. Cleared by the user to transmit 0. 6 Transfer and Interrupt Mode (Master Mode). Set by the user to initiate a transfer with a write to the SPITX register. Interrupt occurs when SPITX is empty. Cleared by the user to initiate a transfer with a read of the SPIRX register. Interrupt occurs when SPIRX is full. 5 LSB First Transfer Enable Bit. Set by the user; the LSB is transmitted first. Cleared by the user; the MSB is transmitted first. 4 Reserved. Should be written as 0. 3 Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user the serial clock idles low. 2 Serial Clock Phase Mode Bit. Set by the user. The serial clock pulses at the beginning of each serial bit transfer. Cleared by the user. The serial clock pulses at the end of each serial bit transfer. Set by the user to enable master mode. Cleared by the user to enable slave mode. Set by the user to enable the SPI.

serial peripheral interface. Table 90. SPISTA MMR Bit Designations 5 SPIRX Data Register Overflow Status Bit. Set if SPIRX is overflowing. Cleared by reading the SPIRX register. Set automatically if Bit 3 or Bit 5 is set. Cleared by reading the SPIRX register. 3 SPIRX Data Register Full Status Bit. Cleared by reading the SPIRX register. 2 SPITX Data Register Underflow Status Bit. Set automatically if SPITX is underflowing. Cleared by writing in the SPITX register. Set automatically if Bit 0 is clear or Bit 2 is set. finished transmission, by disabling the SPI. 0 SPITX Data Register Empty Status Bit. during transmission of data. Cleared when SPITX is empty. the serial peripheral interface. serial peripheral interface.

Figure 43. Serial ADC Test Interface Example, Three-Byte Transmission diagnostics on finished production units. The STI port is configured and controlled via six MMRs. the STIKEY1 MMR to protect the STICON MMR. before any attempt is made to write to STICON. the STIKEY0 MMR to protect the STICON MMR. after any attempt is made to write to STICON. Bits[7:0] and the second byte occupies Bits[15:8]. Bits[7:0] and the fourth byte occupies Bits[15:8].

Rev. B | Page 118 of 140 Serial Test Interface Data 2 Register Name: STIDAT1 Address: 0xFFFF0894 Default Value: 0x0000 Access: Read/write Function: The STIDAT2 MMR is a 16-bit register that holds the fifth and sixth data bytes that are to be trans- mitted on the STI pin when the STI port is enabled. The fifth byte to be transmitted occupies Bits[7:0] and the sixth byte occupies Bits[15:8]. Serial Test Interface Control Register Name: STICON Address: 0xFFFF0884 Default Value: 0x0000 Access: Read/write access, write protected by two key registers (STIKEY0 and STIKEY1). A write access to STICON is completed correctly only when the following triple write sequence is followed: 1. STIKEY0 MMR is written with 0x0007. 2. STICON is written. 3. The sequence is completed by writing 0x00B9 to STIKEY1. Function: The STI control MMR is a 16-bit register that configures the mode of operation of the serial test interface. Note: GPIO_13 must be configured for STI operation in GP2CON for STI communications.

Table 91. STICON MMR Bit Designations 16 to 9 Reserved. These bits are reserved for future use and should be written as 0 by user code. 8 to 5 State Bits, Read Only. If the interface is in the middle of a transmission, these bits are not 0. write the bytes to be transmitted into the STIDAT0, STIDAT1, and STIDAT2 MMRs. 1 Reset Serial Test Interface. Set to 1 to reset the serial test interface; a subsequent read of STICON returns all 0s. This bit is 0 by default to operate in normal mode. 0 Serial Test Interface Enable. Set to 1 by user code to enable the serial test interface. Set to 0 by user code to disable the serial test interface. configuration is shown in Figure 4. Figure 44. STI Output Structure

1. Configure Timer4 for baud rate generation.
2. Correctly enable STICON using STIKEY0 and STIKEY1
3. Required bytes to be transmitted are written into

STIDAT0, STIDAT1, and STIDAT2. ADC conversion result being available. the serial interface, user code must write a 0 to STICON[0].

Rev. B | Page 120 of 140 An example code segment configuring the STI port to transmit five bytes and then to transmit two bytes follows: T4LD = 267; // Timer4 Reload Value T4CON = 0xC0; // Enable T4, selecting core clock in periodic mode STIKEY0 = 07; // STICON start write sequence STICON = 0x11; // Enable and transmit 5 bytes STIKEY1 = 0xb9; // STICON complete write STIDAT0 = 0xAABB; // 5 bytes for STIDAT1 = 0xCCDD; // Transmission STIDAT2 = 0xFF; while(STICON != 0x09) // Wait for transmission to complete STIKEY0 = 07; // STICON start write sequence STICON = 0x05; // Enable and transmit 2 bytes STIKEY1 = 0xb9; // STICON complete write STIDAT0 = 0xEEFF; // 2 bytes for transmission while(STICON != 0x09) // Wait for transmission to complete

the PLL is used for the synchronous byte timing. Table 92. LIN MMR Descriptions configuration of the LHS timer. LHSVAL1 LHS Break Timer Register. Figure 45. LIN I/O, Block Diagram

Table 93. LHSSTA MMR Bit Designations 31 to 7 Reserved. These read-only bits are reserved for future use. 6 Rising Edge Detected (BSD Mode Only). Set to 1 by hardware to indicate a rising edge has been detected on the BSD bus. Cleared to 0, after user code reads the LHSSTA MMR. Set to 1 by hardware to indicate a LHS reset command has completed successfully. Cleared to 0, after user code reads the LHSSTA MMR. overflows to indicate the LIN bus has stayed low too long, thus indicating a possible LIN bus error. Cleared to 0, after user code reads the LHSSTA MMR. Set to 1 by hardware when the value in LHSVAL0 (LIN synchronization bit timer) = the value in the LHSCMP register. Cleared to 0, after user code reads the LHSSTA MMR. Set to 1 by hardware when a stop condition is detected. Cleared to 0, after user code reads LHSSTA MMR. 1 Start Condition Interrupt. Set to 1 by hardware when a start condition is detected. Cleared to 0, after user code reads LHSSTA MMR. 0 Break Timer Compare Interrupt. section for more information). Cleared to 0 after user code reads the LHSSTA MMR.

Table 94. LHSCON0 MMR Bit Designations 31 to 13 Reserved. These bits are reserved for future use and should be written as 0 by user software. 12 Rising Edge Detected Interrupt Disable. Set to 1 to disable the rising edge detected interrupt. Cleared to 0 to enable the break rising edge detected interrupt. Set to 1 to enable the rising edge detected interrupt. Cleared to 0 to disable the break rising edge detected interrupt. 11 Break Timer Compare Interrupt Disable. Set to 1 to disable the break timer compare interrupt. Cleared to 0 to enable the break timer compare interrupt. 10 Break Timer Error Interrupt Disable. Set to 1 to disable the break timer error interrupt. Cleared to 0 to enable the break timer error interrupt. 9 LIN Transceiver, Standalone Test Mode. Cleared to 0 by user code to operate the LIN in normal mode, it is driven directly from the on-chip UART. via the GPIO function select Bit 0 and Bit 4 in the GP2CON register. break or sync field periods that have to be flushed out of the UART before valid data fields can be received. have been detected so that the UART can receive the subsequent LIN data fields. BSD read mode. A stop condition interrupt can be used to ensure that this scenario is avoided. timer overflows. This configuration can be used in BSD read mode to detect fault conditions on the BSD bus. pulse width in transmitted data bits.

Rev. B | Page 124 of 140 Bit Description 7 Sync Timer Stop Edge Type Bit. Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4] register. Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register. 6 Mode of Operation Bit. Cleared to 0 by user code to select LIN mode of operation. Set to 1 by user code to select BSD mode of operation. 5 Enable Compare Interrupt Bit. Cleared to 0 by user code to disable compare interrupts. Set to 1 by user code to generate an LHS interrupt (IRQEN[7]) when the value in LHSVAL0 (LIN synchronization bit timer) = the value in the LHSCMP register. The LHS Compare Interrupt Bit LHSSTA[3] is set when this interrupt occurs. This configuration is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be transmitted. 4 Enable Stop Interrupt. Cleared to 0 by user code to disable interrupts when a stop condition occurs. Set to 1 by user code to generate an interrupt when a stop condition occurs. 3 Enable Start Interrupt. Cleared to 0 by user code to disable interrupts when a start condition occurs. Set to 1 by user code to generate an interrupt when a start condition occurs. 2 LIN Sync Enable Bit. Cleared to 0 by user code to disable LHS functionality. Set to 1 by user code to enable LHS functionality. 1 Edge Counter Clear Bit. Set to 1 by user code to clear the internal edge counters in the LHS peripheral. This bit is automatically cleared to 0 after a 15 μs delay. 0 LHS Reset Bit. Set to 1 by user code to reset all LHS logic to default conditions. This bit is automatically cleared to 0 after a 15 μs delay.

Table 95. LHSCON1 MMR Bit Designations 31 to 8 Reserved. These bits are reserved for future use and should be written as 0 by user software. start of the LIN break pulse. that the first falling edge is taken as the falling edge at the start of the LIN break pulse. from the ADuC7033 slave to the LIN master node. timing through the LHSV AL0 register does not occur.

break symbol, sync byte, protected identifier, and data bytes. and manage LIN-based transmissions and receptions. bus fault condition (bus held low) occurs, it must be flagged. Hardware Synchronization Status Register section. Figure 4. The protected identifier consists of two subfields: the the number of data bytes to be either received or transmitted. The data byte frame carries between one and eight bytes of data. COMDIV0: divisor latch (low byte). COMDIV1: divisor latch (high byte). from the LHSVAL0 to generate the required baud rate. transmitting data is identical to the UART specification.

• COMTX: 8-bit transmit register.
• COMRX: 8-bit receive register.
• COMCON0: line control register.
• COMSTA0: line status register. Transmitting data on the LIN bus requires that the relevant data be placed into COMTX. Reading data received on the LIN bus requires the monitoring of COMRX. To ensure that data is received or transmitted correctly, COMSTA0 is monitored. For more information refer to the UART Serial Interface and UART Register Definition sections of this data sheet. Under software control, it is possible to multiplex the UART data lines (TxD and RxD) to the external GPIO pins (GPIO_7 and GPIO_8). For more information, refer to the description of the GPIO Port1 Control Register (GP1CON) section.

Rev. B | Page 128 of 140 Example LIN Hardware Synchronization Routine Consider the following C-Source Code LIN initialization routine. void LIN_INIT(void ) char HVstatus; GPCON = 0x110000; // Enable LHS on GPIO pins LHSCON0 = 0x1; // Reset LHS interface do{ HVDAT = 0x02; // Enable normal LIN TX mode HVCON = 0x08; // Write to Config0 do{ HVstatus = HVCON; while(HVstatus & 0x1);// Wait until command is finished while (!(HVstatus & 0x4)); // Transmit command is correct while((LHSSTA & 0x20) == 0 ) { // Wait until the LHS hardware is reset LHSCON1 = 0x062; // Sets Stop Edge as the fifth falling edge // and the Start Edge as the first falling // edge in the sync byte LHSCON0 = 0x0114; // Gates UART RX line, ensure no interference // from the LIN into the UART // Selects the stop condition as a falling edge // Enables generation of an Interrupt on the // stop condition // Enables the interface LHSVAL1 = 0x03F; // Set number of 131 kHz periods to generate // a break interrupt 0x3F / 131 kHz ~ 480 μs // which is just over 9.5 tbits Using this configuration, LHSV AL1 begins to count on the first falling edge received on the LIN bus. If LHSV AL1 exceeds the value written to LHSV AL1, in this case 0x3F, a break compare interrupt is generated. On the next falling edge, LHSV AL0 begins counting. LHSV AL0 monitors the number of falling edges and compares this to the value written to LHSCON1[7:4]. In this example, the number of edges to monitor is the sixth falling edge of the LIN frame, or the fifth falling edge of the sync byte. When this number of falling edges is received, a stop condition interrupt is generated. It is at this point that the UART is configured to receive the protected identifier. The UART must not be ungated (through LHSCON0[8]) before the LIN bus returns high. If this occurs, UART communication errors can occur. This process is shown in detail in Figure . Example code to ensure this is as follows:

Figure 51. Example LIN Configuration user software, allowing the user to detect open-circuit conditions. communications continue uninterrupted.

Figure 52. BSD I/O Hardware Interface 19 bits and communication occurs at 1200 bps ± 3%. Table 96. BSD Bit Level Description all of which are under software control.

• An internal GPIO signal (GPIO_12) that is routed to the external LIN/BSD pin and is controlled directly by software to generate 0s and 1s.
• When reading bits, the LIN synchronization hardware uses LHSV AL1 to count the width of the incoming pulses so that user code can interpret the bits as sync, 0, or 1.
• When writing bits, user code toggles a GPIO pin and uses the LHSCAP and LHSCMP registers to time pulse widths and generate an interrupt when the BSD output pulse width has reached its required width. The ADuC7033 MMRs required for BSD communication are as follows: LHSSTA: LIN hardware sync status register. LHSCON0: LIN hardware sync control register. LHSVAL0: LIN hardware sync Timer0 (16-bit timer). LHSCON1: LIN hardware sy nc edge setup register. LHSVAL1: LIN sync break timer. LHSCAP: LIN sync capture register. LHSCMP: LIN sync compare register. IRQEN/CLR: Enable interrupt register. FIQEN/CLR: Enable fast interrupt register. GP2DAT: GPIO data register. GP2SET: GPIO set register. GP2CLR: GPIO clear register.

Figure 55. BSD Slave Transmitting Zero constructs the relevant address. Figure 56. BSD Slave Node State Machine section) generates an interrupt on the rising edge of the BSD bus. to determine if the received data bit is a BSD sync pulse, 0, or 1.

1 LHSVAL1 STOPPED

Figure 57. Master Transmit, Slave Read long the BSD bus should be held low for 0 or 1 bit transmissions. should be driven high for a 0 or 1 pulse width can be made. compare interrupt (LHSSTA[3]). can be transmitted from the ADuC7033, as shown in Figure 5. mode to BSD read mode, as described in LHSCON0[8].

1 SOFTWARE ASSERTS

code should enable the start condition interrupt (LHSCON0[3]). Figure 58. Master Read, Slave Transmit

SYSSER1 MMRs. See Table 99 and Table 100 for details. part of the branding on the package as shown Table 98. Table 98. Branding Example the MMRs, SYSSER1, and FEE0ADR. full manufacturing history of this part to be traced (bottom die only). Table 99. SYSSER0 MMR Bit Designations wafer lot. When it is used in conjunction with SYSSER0[21:0], it provides wafer lot traceability. conjunction with SYSSER0[26:22] and SYSSER0[15:0], provides wafer lot traceability. 15 to 0 Wafer Lot Fabrication ID. These 16 LSBs hold a 16-bit number to be interpreted as the wafer fabrication lot ID number.

revision number (bottom die only) as detailed in Table 100. Table 100. SYSSER1 MMR Bit Designations The allowable range for this value is 1 to 15, which is interpreted as 41 to 4F or ASCII Character A to ASCII Character O. be interpreted as A, indicating a Revision A kernel is on-chip. 19 to 16 Reserved. For prerelease samples, these bits refer to the kernel minor revision number of the device. value in SYSSER0, that is, the manufacturing lot ID, this number is a unique identifier for the part. Function: At power-on, this 32-bit register holds the kernel checksum.

Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEE0CON acts. Note: This MMR is also used to identify the ADuC703x family member and prerelease silicon revision. Table 101. FEE0ADR System Identification MMR Bit Designations

system meets any EMC and other overvoltage/overcurrent compliance requirements. Figure 59. Schematic

Figure 60. 48-Lead Low Profile Quad Flat Package [LQFP]

Rev. B | Page 139 of 140 NOTES

Rev. B | Page 140 of 140 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06847-0-10/10(B)