ADUC7023BCPZ62I-RL

ADUC7023 AD | Alldatasheet

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Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler Data Sheet ADuC7023 Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2010–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Multichannel, 12-bit, 1 MSPS ADC Up to 12 ADC channels Fully differential and single-ended modes

0 V to VREF analog input range

12-bit voltage output DACs

4 DAC outputs available

On-chip temperature sensor Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 44 MHz

41.78 MHz PLL with programmable divider

62 kB Flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug Software-triggered in-circuit reprogrammability Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs On-chip peripherals 2× fully I 2C-compatible channels SPI (20 Mbps in master mode, 10 Mbps in slave mode) With 4-byte FIFO on input and output stages Up to 20 GPIO pins—Digital only GPIOs are 5 V tolerant 3× general-purpose timers Watchdog timer (WDT) Programmable logic array (PLA)

16 PLA elements

16-bit, 5-channel PWM Power Specified for 3 V operation Active mode: 11 mA at 5 MHz, 28 mA at 41.78 MHz Packages and temperature range 32-lead 5 mm × 5 mm LFCSP 40-lead LFCSP 36-Lead WLCSP Fully specified for −40°C to +125°C operation Tools Low cost QuickStart development system Full third-party support

APPLICATIONS

Industrial control and automation systems Smart sensors, precision instrumentation Base station systems GENERAL DESCRIPTION The ADuC7023 is a fully integrated, 1 MSPS, 12-bit data acquisition system, incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional four inputs are available but are multiplexed with the four DAC output pins. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 V to VREF. A low drift band gap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. The DAC output range is programmable to one of two voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. The devices operate from an on-chip oscillator and a PLL, generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI®, 16-bit/32-bit RISC machine that offers up to 41 MIPS peak performance. Eight kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE memory are provided on chip. The ARM7TDMI core views all memory and registers as a single linear array. The ADuC7023 contains an advanced interrupt controller. The vectored interrupt controller (VIC) allows every interrupt to be assigned a priority level. It also supports nested interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 nested interrupt levels are supported. On-chip factory firmware supports in-circuit download via the I serial interface port, and nonintrusive emulation is supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting this MicroConverter® family. The part contains a 16-bit PWM with five output signals. For communication purposes, the part contains 2 × I2C channels that can be individually configured for master or slave mode. An SPI interface supporting both master and slave modes is also provided. The parts operate from 2.7 V to 3.6 V and are specified over an industrial temperature range of −40°C to +125°C. The ADuC7023 is available in either a 32-lead or 40-lead LFCSP package. A 36-ball wafer level CSP package (WLCSP) is also available.

Rev. H | Page 2 of 98 TABLE OF CONTENTS

Rev. H | Page 3 of 98

REVISION HISTORY

11/2020—Rev. G to Rev. H 1/2015—Rev. F to Rev. G Changes to I 5/2014—Rev. E to Rev. F Changes to I 7/2013—Rev. D to Rev. E 7/2013—Rev. C to Rev. D Added Shared Analog/Digital Inputs to AGND Rating of −0.3 V to AV DD + 0.3 V, Endnote 1, and Endnote 2; Table 8 ... 13 Added Figure 9; Renumbered Sequentially; Added WLCSP Pin Changes to Pin P1.7/PWM3/SDA1/PLAI[6] and Pin Changes to ADC Circuit Overview Section, Transfer Function Changes to Typical Operation Section, ADCCON Register Changes to Converter Operation Section and Deleted Pseudo 5/2012—Rev. B to Rev. C Changed SDATA to SDA and SCLK to SCL, Table 2; SDATA to SDA and SCLK to SCL, Table 3; and SDATA to SDA and Changes to Bit 6, Table 24 and 4 to 0, Description Column, Changed Reference in REFCON Register Section from Table 22 Changed SPICLK (Serial Clock I/O) Pin Section to SCLK Changed SPICLK to SCLK in Serial Peripheral Interface Added Hours, Minutes, Seconds, and 1/128 Format Section and 7/2010—Rev. A to Rev. B Changes to ADCGN Register and ADCOF Register Sections . 32 Change to REMAP Register and RSTCLR Register Sections ... 41 Change to RSTKEY1 Register and RSTKEY2 Register Changes to Table 83 and Pulse-Width Modulator General

Rev. H | Page 4 of 98 6/2010—Rev. 0 to Rev. A 1/2010—Revision 0: Initial Version

Rev. H | Page 5 of 98 FUNCTIONAL BLOCK DIAGRAM 08675-001 ADuC7023 40-LEAD LFCSP DAC0 DAC1 DAC2 DAC3 ADC0 XCLKI XCLKO RST VREF ADC12 ADC2/CMP0 ADC3/CMP1 CMPOUT 12-BIT DAC 12-BIT DAC 12-BIT DAC 12-BIT DAC VECTORED INTERRUPT CONTROLLER 1MSPS 12-BIT ADC TEMP SENSOR BAND GAP REF MUX OSC AND PLL PSM POR ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS PLA

3 GENERAL-

2k × 32 SRAM 31k × 16 FLASH/EEPROM SPI, 2 × I2C GPIO PWM JTAG Figure 1.

Rev. H | Page 6 of 98 SPECIFICATIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and f ADC/2 ADC Power-Up Time 5 μs DC Accuracy1, 2 Resolution 12 Bits Integral Nonlinearity ±0.6 ±1 .5 LSB 2.5 V internal reference ±1.0 LSB 1.0 V external reference Differential Nonlinearity3, 4 ±0.5 +1/−0.9 LSB 2.5 V internal reference +0.7/−0.6 LSB 1.0 V external reference DC Code Distribution 1 LSB ADC input is a dc voltage ENDPOINT ERRORS5 Offset Error ±1 ±2 LSB Offset Error Match ±1 LSB Gain Error ±2 LSB Gain Error Match ±1 LSB DYNAMIC PERFORMANCE f IN = 10 kHz sine wave, fSAMPLE = 1 MSPS Signal-to-Noise Ratio (SNR) 69 dB In cludes distortion and noise components Total Harmonic Distortion (THD) −78 dB Peak Harmonic or Spurious Noise −75 dB Channel-to-Channel Crosstalk −80 dB Measured on adjacent channels ANALOG INPUT Input Voltage Ranges Differential Mode VCM ± VREF/26 V Single-Ended Mode 0 to VREF V Leakage Current ±1 ±6 μA Input Capacitance 20 pF During ADC acquisition ON-CHIP VOLTAGE REFERENCE 0.47 μF from V REF to AGND Output Voltage 2.5 V Accuracy ±4 mV TA = 25°C Reference Temperature Coefficient ±15 ppm/°C Power Supply Rejection Ratio 75 dB Output Impedance 51 Ω T A = 25°C Internal VREF Power-On Time 1 ms EXTERNAL REFERENCE INPUT Input Voltage Range 0.625 AVDD V DAC CHANNEL SPECIFICATIONS DC Accuracy7 R L = 5 kΩ, CL = 100 pF Resolution 12 Bits Relative Accuracy ±2 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Offset Error ±15 mV 2.5 V internal reference Gain Error8 ±1 % Gain Error Mismatch 0.1 % % of full scale on DAC0 DC Accuracy9 R L = 1 kΩ, CL = 100 pF Resolution 12 Bits Relative Accuracy ±2.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Offset Error ±15 mV 2.5 V internal reference Gain Error10 ±1 % Gain Error Mismatch 0.1 % % of full scale on DAC0 ANALOG OUTPUTS Output Voltage Range 1 0 to 2.5 V V REF range: AGND to AVDD Output Voltage Range 2 0 to AV DD V Output Impedance 2 Ω

Rev. H | Page 7 of 98 Parameter Min Typ Max Unit Test Conditions/Comments DAC IN OP AMP MODE DAC Output Buffer in Op Amp Mode Input Offset Voltage ±0.25 mV Input Offset Voltage Drift 8 μV/°C Input Offset Current 0.3 nA Input Bias Current 0.4 nA Gain 80 dB 5 kΩ load Unity-Gain Frequency 5 MHz R L = 5 kΩ, CL = 100 pF CMRR 80 dB Settling Time 10 μs R L = 5 kΩ, CL = 100 pF Output Slew Rate 1.5 V/μs R L = 5 kΩ, CL = 100 pF PSRR 75 dB DAC AC CHARACTERISTICS Voltage Output Settling Time 10 μs Digital-to-Analog Glitch Energy ±20 nV-sec 1 LSB change at major carry (where maximum number of bits simultaneously change in the DACxDAT register) COMPARATOR Input Offset Voltage ±10 mV Input Bias Current 1 μA Input Voltage Range AGND AVDD – 1.2 V Input Capacitance 7 pF Hysteresis4, 6 2 15 mV Hysteresis can be tu rned on or off via the CMPHYST bit in the CMPCON register Response Time 3 μs 100 mV overdrive and configured with CMPRES = 11 TEMPERATURE SENSOR Indicates die temperature Voltage Output at 25°C 1.369 V Voltage TC 4.42 mV/°C Accuracy with No Calibration ±3 °C Accuracy with One Point Calibration Using Contents of TEMPREF Register ±1.5 °C θJA Thermal Impedance 40-Lead LFCSP 26 °C/W 32-Lead LFCSP 32.5 °C/W POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection 2.79 V One trip point Power Supply Trip Point Accuracy ±2 % Of the selected nominal trip point voltage POWER-ON RESET 2.41 V WATCHDOG TIMER (WDT) Timeout Period 0 512 sec FLASH/EE MEMORY Endurance11 10,000 Cycles Data Retention12 20 Years T J = 85°C DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO Logic 1 Input Current ±0.2 ±1 μA V IH = VDD or VIH = 5 V Logic 0 Input Current −40 −60 μA V IL = 0 V; except TDI −80 −120 μA VIL = 0 V; TDI Input Capacitance 10 pF LOGIC INPUTS4 All logic inputs excluding XCLKI VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 2.0 V LOGIC OUTPUTS All digital outputs excluding XCLKO VOH, Output High Voltage 2.4 V I SOURCE = 1.6 mA VOL, Output Low Voltage13 0.4 V I SINK = 1.6 mA CRYSTAL INPUTS XCLKI AND XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage 1.1 V VINH, Input High Voltage 1.7 V XCLKI Input Capacitance 20 pF XCLKO Output Capacitance 20 pF

Rev. H | Page 8 of 98 Parameter Min Typ Max Unit Test Conditions/Comments INTERNAL OSCILLATOR 32.768 kHz ±3 % MCU CLOCK RATE From 32 kHz Internal Oscillator 326 kHz CD = 7 From 32 kHz External Crystal 41.78 MHz CD = 0 Using an External Clock 0.05 44 MHz T A = 85°C 0.05 41.78 MHz TA = 125°C START-UP TIME Core clock = 41.78 MHz At Power-On 66 ms From Pause/Nap Mode 24 ns CD = 0 3.07 μs CD = 7 From Sleep Mode 1.58 ms From Stop Mode 1.7 ms PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay 12 ns From input pin to output pin Element Propagation Delay 2.5 ns POWER REQUIREMENTS14, 15 Power Supply Voltage Range AVDD to AGND and IOVDD to DGND 2.7 3.6 V Analog Power Supply Currents AVDD Current 200 μA ADC in idle mode Digital Power Supply Current IOVDD Current in Normal Mode Code executing from Flash/EE 8.5 10 mA CD = 7 11 15 mA CD = 3 28 35 mA CD = 0 (41.78 MHz clock) IOVDD Current in Pause Mode 14 20 mA CD = 0 (41.78 MHz clock) IOVDD Current in Sleep Mode 230 650 μA T A = 125°C Additional Power Supply Currents ADC 1.4 mA At 1 MSPS 0.7 mA At 62.5 kSPS DAC 400 μA Per DAC ESD TESTS 2.5 V reference, T A = 25°C HBM Passed 3 kV FICDM Passed 1.0 kV 1 All ADC channel specifications are guaranteed during normal microcontroller core operation. 2 Apply to all ADC input channels. 3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN). 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 28. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 DAC linearity is calculated using a reduced code range of 100 to 3995. 8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 9 DAC linearity is calculated using a reduced code range of 100 to 3995. 10 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 11 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 12 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 13 Test carried out with a maximum of eight I/Os set to a low output level. 14 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with 3.6 V supply, and sleep mode with 3.6 V supply. 15 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.

Table 2. I2C Timing in Fast Mode (400 kHz) Table 3. I2C Timing in Standard Mode (100 kHz) Figure 2. I2C-Compatible Interface Timing

Table 4. SPI Master Mode Timing (Phase Mode = 1) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Figure 3. SPI Master Mode Timing (Phase Mode = 1)

Table 5. SPI Master Mode Timing (Phase Mode = 0) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Figure 4. SPI Master Mode Timing (Phase Mode = 0)

Table 6. SPI Slave Mode Timing (Phase Mode = 1) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Figure 5. SPI Slave Mode Timing (Phase Mode = 1)

Table 7. SPI Slave Mode Timing (Phase Mode = 0) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Figure 6. SPI Slave Mode Timing (Phase Mode = 0)

Rev. H | Page 14 of 98 ABSOLUTE MAXIMUM RATINGS AGND = GNDREF, TA = 25°C, unless otherwise noted. Table 8. P1.1, P1.6, and P1.7 pins. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION Parameter Rating AVDD to IOVDD −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V IOVDD to DGND, AVDD to AGND −0.3 V to +6 V Digital Input Voltage to DGND1 −0.3 V to +5.3 V Digital Output Voltage to DGND1 −0.3 V to IOV DD + 0.3 V Shared Analog/Digital Inputs to AGND2 −0.3 V to AV DD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.3 V Analog Inputs to AGND −0.3 V to AVDD + 0.3 V Analog Outputs to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range, Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 40-Lead LFCSP 26°C/W 32-Lead LFCSP 32.5°C/W 36-Lead WLCSP 50°C/W Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) 240°C RoHS Compliant Assemblies (20 sec to 40 sec) 260°C

1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND

EITHER CONNECTED TO AGND OR LEFT FLOATING.

23 RTCK

24 TMS

22 XCLKO

21 XCLKI

Figure 7. 40-Lead LFCSP Pin Configuration

1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND

EITHER CONNECTED TO AGND OR LEFT FLOATING. Figure 8. 32-Lead LFCSP Pin Configuration Figure 9. 36-Lead WLCSP Pin Configuration Table 9. Pin Function Descriptions 36 28 A4 ADC0 Single-Ended or Differential Analog Input 0. 37 29 B4 ADC1 Single-Ended or Differential Analog Input 1. 38 30 A5 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input. 39 31 B5 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input. ferential Analog Input/Programmable Logic Array Input Element 10.

Rev. H | Page 16 of 98 Pin No. 40- LFCSP 32- LFCSP 36- WLCSP Mnemonic Description 31 N/A A1 P2.3/ADC8/PLAO[7] General-Purpose Input and Output Port 2.3/ADC Single-Ended or Differential Analog Input 8/Programmable Logic Array Output Element 7. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. When used as ADC input, pull-up resistor should be disabled manually. 30 N/A B1 P2.2/ADC7/SYNC/PLAO[6] General-Purpose Input and Output Port 2.2/ADC Single-Ended or Differential Analog Input 7/PWM Sync/Programmable Logic Array Output Element 6. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. When used as ADC input, pull-up resistor should be disabled manually. 8 N/A E6 P2.0/ADC12/PWM4/PLAI[7] General-Purpose Input and Output Port 2.0/ADC Single-Ended or Differential Analog Input 12/PWM Output 4/Programmable Logic Array Input Element 7. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. When used as an ADC input, it is not possible to disable the internal pull-up resister. This means that this pin has a higher leakage current value than other analog input pins. 2 2 C4 GND REF Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from DGND. 3 3 C5 DAC0 DAC0 Voltage Output or ADC Input. 4 4 C6 DAC1 DAC1 Voltage Output or ADC Input. 5 5 D5 DAC2 DAC2 Voltage Output 6 6 D6 DAC3 DAC3 Voltage Output 24 20 D2 TMS Test Mode Select, JTAG Test Port Input. Debug and download access. This pin has an internal pull-up resistor to IOV DD. In some cases an external pull-up resistor is also required to ensure the part does not enter an erroneous state. 25 21 D1 P0.0/nTRST/ADC BUSY/PLAI[8]/BM This is a multifunction pin as follows: General-Purpose Input and Output Port 0.0. By default, this pin is configured as GPIO. JTAG Reset Input. Debug and download access. If this pin is held low, JTAG access is not possible because the JTAG interface is held in reset and P0.1/P0.2/P0.3 are configured as GPIO pins. ADC Busy Signal. Programmable Logic Array Input Element 8. Boot Mode Entry Pin. The ADuC7023 enters I 2C download mode if BM is low at reset with a flash address 0x80014 = 0xFFFFFFFFF. The ADuC7023 executes code if BM is pulled high at reset or if BM is low at reset with a flash address 0x80014 not equal to 0xFFFFFFFFF. 26 22 C1 P0.1/PLAI[9]/TDO The default value of this pin depends on the level of P0.0/BM. If P0.0/ BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin defaults to a JTAG test data output pin and does not work as a GPIO. This is a multifunction pin as follows: General-Purpose Input and Output Port 0.1. Programmable Logic Array Input Element 9. Test Data Out, JTAG Test Port Output. Debug and download access. When debugging the part via JTAG, this pin must not be toggled by user code, and the GP0CON/GP0DAT register bits affecting this pin must not be changed as doing so disables JTAG access. 27 23 C2 P0.2/PLAO[8]/TDI The default value of this pin depends on the level of P0.0/BM. If P0.0/ BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin defaults to a JTAG test data input pin and does not work as a GPIO. This is a multifunction pin as follows: General-Purpose Input and Output Port 0.2. Programmable Logic Array Output Element 8. Test Data In, JTAG Test Port Input. Debug and download access. When debugging the part via JTAG, this pin must not be toggled by user code, and the GP0CON/GP0DAT register bits affecting this pin must not be changed as doing so disables JTAG access.

Rev. H | Page 17 of 98 Pin No. 40- LFCSP 32- LFCSP 36- WLCSP Mnemonic Description 28 24 C3 P0.3/PLAO[9]/TCK The default value of this pin depends on the level of P0.0/BM. If P0.0/BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin defaults to a JTAG test data clock pin. This is a multifunction pin as follows: General-Purpose Input and Output Port 0.3. Programmable Logic Array Output Element 9. Test Clock, JTAG Test Port Clock Input. Debug and download access. When debugging the part via JTAG, this pin must not be toggled by user code and the GP0CON/GP0DAT register bits affecting this pin must not be changed as doing so disables JTAG access. 17 13 E3 DGND Digital Ground. 18 14 F3 IOV DD 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 19 15 D3 LV DD 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF capacitor to DGND only. 20 16 F2 RST Reset Input, Active Low. 23 19 E1 RTCK Return JTAG Clock Signal. This is not the standard JTAG clock signal. It is an output signal from the JTAG controller. If using a 20-lead JTAG header, connect to Pin 11. 9 7 F6 P0.4/IRQ0/SCL0/PLAI[0]/CONV General-Purpose Input and Output Port 0.4/External Interrupt Request 0/ I2C0 Clock Signal/Programmable Logic Array Input Element 0/ADC External Convert Start. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 10 8 E5 P0.5/SDA0/PLAI[1]/COMP OUT General-Purpose Input and Output Port 0.5/I2C0 Data Signal/ Programmable Logic Array Input Element 1/Voltage Comparator Output. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 9 F5 P0.6/MISO/SCL1/PLAI[2] General-Purpose Input and Output Port 0.6/SPI MISO Signal/I2C1 Clock On 32-Lead and 36-Ball Packages/Programmable Logic Array Input Element 2. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 10 D4 P0.7/MOSI/SDA1/PLAO[0] General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I2C1 Data Signal On 32-Lead and 36-Ball Packages/Programmable Logic Array Output Element 0. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 11 P0.6/MISO/PLAI[2] General-Purpose Input and Output Port 0.6/SPI MISO Signal/Programmable Logic Array Input Element 2. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 12 P0.7/MOSI/PLAO[0] General-Purpose Input and Output Port 0.7/SPI MOSI Signal/Programmable Logic Array Output Element 0. By default this pin is configured as a digital input with a weak pull-up reisistor enabled. 21 17 F1 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. Connect to DGND if unused. 22 18 E2 XCLKO Output from the Crystal Oscillator Inverter. Leave unconnected if unused. 16 N/A N/A P1.7/PWM3/SDA1/PLAI[6] General-Purpose Input and Output Port 1.7/PWM Output 3/I2C1 Data Signal/Programmable Logic Array Input Element 6. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 15 N/A N/A P1.6/PWM2/SCL1/PLAI[5] General-Purpose Input and Output Port 1.6/PWM Output 2/I2C1 Clock Signal/Programmable Logic Array Input Element 5. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 29 N/A N/A P1.5/ADC6/PWM TRIPINPUT/PLAO[4] General-Purpose Input and Output Port 1.5/ADC Single-Ended or Differential Analog Input 6/PWMTRIPINPUT/Programmable Logic Array Output Element 4. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. When used as ADC input, the pull-up resistor should be disabled manually. 7 N/A N/A P1.4/ADC10/PLAO[3] General-Purpose Input and Output Port 1.4/ADC Single-Ended or Dif- ferential Analog Input 10/Programmable Logic Array Output Element 3. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. When used as ADC input, the pull-up resistor should be disabled manually.

Rev. H | Page 18 of 98 Pin No. 40- LFCSP 32- LFCSP 36- WLCSP Mnemonic Description 34 26 A3 P1.3/ADC5/IRQ3/PLAI[4] General-Purpose Input and Output Port 1.3/ADC Single-Ended or Differential Analog Input 5/External Interrupt Request 3/ Programmable Logic Array Input Element 4. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. When used as ADC input, the pull-up resistor should be disabled manually. 33 25 A2 P1.2/ADC4/IRQ2/PLAI[3]/ECLK/ General-Purpose Input and Output Port 1.2/ADC Single-Ended or Differential Analog Input 4/External Interrupt Request 2/ Programmable Logic Array Input Element 3/Input-Output for External Clock. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. When used as ADC input, the pull-up resistor should be disabled manually. 14 12 F4 P1.1/SS/IRQ1/PWM1/PLAO[2]/T1 General-Purpose Input and Output Port 1.1/SPI Interface Slave Select (Active Low)/External Interrupt Request 1/PWM Output 1/ Programmable Logic Array Output Element 2/Timer 1 Input Clock. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 13 11 E4 P1.0/SCLK/PWM0/PLAO[1] General-Purpose Input and Output Port 1.0/SPI Interface Clock Signal/ PWM Output 0/Programmable Logic Array Output Element 1. By default, this pin is configured as a digital input with a weak pull-up resistor enabled. 35 27 B3 V REF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. 40 32 A6 AGND Analog Ground. Ground reference point for the analog circuitry. 1 1 B6 AV DD 3.3 V Analog Power.

Rev. H | Page 20 of 98 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale − 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes the output to settle to within a 1 LSB level for a full-scale input change.

Rev. H | Page 22 of 98 More information relative to the model of the programmer and the ARM7TDMI core architecture can be found in ARM7TDMI technical and ARM architecture manuals available directly from ARM Ltd. INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following: the longest time the request can take to pass through the synchronizer, the time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC, and the time for the data abort and FIQ entry. At the end of this time, the ARM7TDMI executes the instruc- tion at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 μs in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in thumb mode where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode. The ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.

page. These two blocks are mapped as shown in Figure 16. Figure 16. Physical Memory Map Address 0x00000000 by clearing Bit 0 of the Remap MMR. is in the highest byte address.

32 BITS

Figure 17. Little Endian Format on-chip kernel. The page size of this Flash/EE memory is 512 bytes. Execution Time from SRAM and Flash/EE section. addressing through the ARM7 banked registers. are on the APB except the Flash/EE memory and the GPIOs.

Figure 18. Memory Mapped Registers

Table 10. IRQ Address Base = 0xFFFF0000 0x0000 IRQSTA 4 R 0x00000000 Active IRQ source. 0x0004 IRQSIG 4 R Current state of all IRQ sources (enabled and disabled). 0x0008 IRQEN 4 R/W 0x00000000 Enabled IRQ sources. 0x000C IRQCLR 4 W MMR to disable IRQ sources. 0x0010 SWICFG 4 W Software interrupt configuration MMR. which can contain up to 32 pointers to separate subroutine handlers. to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7. 0x002C RESERVED 4 R/W 0x00000000 Reserved. 0x0030 IRQCONN 4 R/W 0x00000000 Used to enab le IRQ and FIQ interrupt nesting. falling edge, or level triggered. 0x0038 IRQCLRE 4 R/W 0x00000000 Used to clear an edge level triggered interrupt source. caused an interrupt exception. 0x0100 FIQSTA 4 R 0x00000000 Active FIQ source. 0x0104 FIQSIG 4 R Current state of all FIQ sources (enabled and disabled). 0x0108 FIQEN 4 R/W 0x00000000 Enabled FIQ sources. 0x010C FIQCLR 4 W MMR to disable FIQ sources. 0x011C FIQVEC 4 R 0x00000000 FIQ interrupt vector. Table 11. System Control Address Base = 0xFFFF0200 0x0220 Remap 2 1 R/W 0x00 Remap control register. 0x0230 RSTSTA 1 R/W 0x01 RSTSTA status MMR. 0x0234 RSTCLR 1 W 0x00 RS TCLR MMR for clearing RSTSTA register. 0x0248 RSTKEY1 1 W 0xXX 0x76 should be written to this register before writing to RSTCFG. 0x0250 RSTKEY2 1 W 0xXX 0xB1 should be written to this register after writing to RSTCFG.

Table 12. Timer Address Base = 0xFFFF0300 0x0300 T0LD 2 R/W 0x0000 Timer0 load register. 0x0304 T0VAL 2 R 0xFFFF Timer0 value register. 0x0308 T0CON 2 R/W 0x0000 Timer0 control MMR. 0x030C T0CLRI 1 W 0xXX Timer0 interrupt clear register. 0x0320 T1LD 4 R/W 0x00000000 Timer1 load register. 0x0328 T1CON 4 R/W 0x00000000 Timer1 control MMR. 0x032C T1CLRI 1 W 0xXX Timer1 interrupt clear register. 0x0330 T1CAP 4 R 0x00000000 Timer1 capture register. 0x0360 T2LD 2 R/W 0x0000 Timer2 load register. 0x0364 T2VAL 2 R 0xFFFF Timer2 value register. 0x0368 T2CON 2 R/W 0x0000 Timer2 control MMR. 0x036C T2CLRI 1 W 0xXX Timer2 interrupt clear register. Table 13. PLL/PSM Base Address = 0xFFFF0400 0x0404 POWKEY1 2 W 0xXXXX POWCON0 prewrite key. 0x0408 POWCON0 1 R/W 0x00 Power control and core speed control register. 0x040C POWKEY2 2 W 0xXXXX POWCON0 postwrite key. 0x0410 PLLKEY1 2 W 0xXXXX PLLCON prewrite key. 0x0414 PLLCON 1 R/W 0x21 PLL clock source selection MMR. 0x0418 PLLKEY2 2 W 0xXXXX PLLCON postwrite key. 0x0434 POWKEY3 2 W 0xXXXX POWCON1 prewrite key. 0x0438 POWCON1 2 R/W 0x0004 Power control and core speed control register. 0x043C POWKEY4 2 W 0xXXXX POWCON1 postwrite key. 0x0440 PSMCON 2 R/W 0x0008 Power supp ly monitor control register. 0x0444 CMPCON 2 R/W 0x0000 Comparator control register. Table 14. Reference Base Address = 0xFFFF0480 Description: Reference control register. Table 15. ADC Address Base = 0xFFFF0500 0x0500 ADCCON 2 R/W 0x0600 ADC control MMR. 0x0504 ADCCP 1 R/W 0x00 ADC positi ve channel selection register. 0x0508 ADCCN 1 R/W 0x01 ADC negative channel selection register. 0x050C ADCSTA 1 R 0x00 ADC status MMR. 0x0510 ADCDAT 4 R 0x00000000 ADC data output MMR.

0x0514 ADCRST 1 R/W 0x00 ADC reset MMR. 0x0530 ADCGN 2 R/W Factory configured ADC gain calibration MMR. 0x0534 ADCOF 2 R/W Factory configured ADC offset calibration MMR. 0x0544 TSCON 1 R/W 0x00 Temperature sensor chopping enable register. 0x0548 TEMPREF 2 R/W Factory configured Temperature sensor reference value. Table 16. DAC Address Base = 0xFFFF0600 0x0600 DAC0CON 1 R/W 0x00 DAC0 control MMR. 0x0608 DAC1CON 1 R/W 0x00 DAC1 control MMR. 0x060C DAC1DAT 4 R/W 0x00000000 DAC1 data MMR. 0x0610 DAC2CON 1 R/W 0x00 DAC2 control MMR. 0x0618 DAC3CON 1 R/W 0x00 DAC3 control MMR. 0x061C DAC3DAT 4 R/W 0x00000000 DAC3 data MMR. Table 17. I2C0 Base Address = 0XFFFF0800 0x0800 I2C0MCON 2 R/W 0x0000 I 2C0 master control register. 0x0804 I2C0MSTA 2 R 0x0000 I 2C0 master status register. 0x0808 I2C0MRX 1 R 0x00 I 2C0 master receive register. 0x080C I2C0MTX 1 W 0x00 I 2C0 master transmit register. bytes into this register prior to reading from a slave device. number of bytes already received during a read from slave sequence. here prior to communications. here prior to communications. Used in 10-bit mode only. 0x0824 I2C0DIV 2 R/W 0x1F1F I 2C0 clock control register. Used to configure the SCL frequency. 0x0828 I2C0SCON 2 R/W 0x0000 I 2C0 slave control register. 0x082C I2C0SSTA 2 R/W 0x0000 I 2C0 slave status register. 0x0830 I2C0SRX 1 R 0x00 I 2C0 slave receive register. 0x0834 I2C0STX 1 W 0x00 I 2C0 slave transmit register. 0x0838 I2C0ALT 1 R/W 0x00 I 2C0 hardware general call recognition register. 0x083C I2C0ID0 1 R/W 0x00 I 2C0 slave ID0 register. Slave bus ID register. 0x0840 I2C0ID1 1 R/W 0x00 I 2C0 slave ID1 register. Slave bus ID register. 0x0844 I2C0ID2 1 R/W 0x00 I 2C0 slave ID2 register. Slave bus ID register. 0x0848 I2C0ID3 1 R/W 0x00 I 2C0 slave ID3 register. Slave bus ID register. 0x084C I2C0FSTA 2 R/W 0x0000 I 2C0 FIFO status register. Used in both master and slave modes. Table 18. I2C1 Base Address = 0XFFFF0900 0x0900 I2C1MCON 2 R/W 0x0000 I 2C1 master control register. 0x0904 I2C1MSTA 2 R 0x0000 I 2C1 master status register.

Rev. H | Page 28 of 98 Address Name Byte Access Type Default Value Description 0x0908 I2C1MRX 1 R 0x00 I 2C1 master receive register. 0x090C I2C1MTX 1 W 0x00 I2C1 master transmit register. 0x0910 I2C1MCNT0 2 R/W 0x0000 I2C1 master read count register. Write the number of required bytes into this register prior to reading from a slave device.

number of bytes already received during a read from slave sequence. here prior to communications. here prior to communications. Used in 10-bit mode only. 0x0924 I2C1DIV 2 R/W 0x1F1F I 2C1 clock control register. Used to configure the SCL frequency. 0x0928 I2C1SCON 2 R/W 0x0000 I 2C1 slave control register. 0x092C I2C1SSTA 2 R/W 0x0000 I 2C1 slave status register. 0x0930 I2C1SRX 1 R 0x00 I 2C1 slave receive register. 0x0934 I2C1STX 1 W 0x00 I 2C1 slave transmit register. 0x0938 I2C1ALT 1 R/W 0x00 I 2C1 hardware general call recognition register. 0x093C I2C1ID0 1 R/W 0x00 I2C1 slave ID0 register. Slave bus ID register. 0x0940 I2C1ID1 1 R/W 0x00 I 2C1 slave ID1 register. Slave bus ID register. 0x0944 I2C1ID2 1 R/W 0x00 I 2C1 slave ID2 register. Slave bus ID register. 0x0948 I2C1ID3 1 R/W 0x00 I 2C1 slave ID3 register. Slave bus ID register. 0x094C I2C1FSTA 2 R/W 0x0000 I 2C1 FIFO status register. Used in both master and slave modes. Table 19. SPI Base Address = 0xFFFF0A00 0x0A00 SPISTA 2 R 0x0000 SPI status MMR. 0x0A04 SPIRX 1 R 0x00 SPI receive MMR. 0x0A08 SPITX 1 W 0xXX SPI transmit MMR. 0x0A0C SPIDIV 1 R/W 0x00 SPI baud rate select MMR. 0x0A10 SPICON 2 R/W 0x0000 SPI control MMR. Table 20. PLA Base Address = 0XFFFF0B00 0x0B00 PLAELM0 2 R/W 0x0000 PLA El ement 0 control register. 0x0B04 PLAELM1 2 R/W 0x0000 PLA El ement 1 control register. 0x0B08 PLAELM2 2 R/W 0x0000 PLA El ement 2 control register. 0x0B0C PLAELM3 2 R/W 0x0000 PLA El ement 3 control register. 0x0B10 PLAELM4 2 R/W 0x0000 PLA El ement 4 control register. 0x0B14 PLAELM5 2 R/W 0x0000 PLA El ement 5 control register. 0x0B18 PLAELM6 2 R/W 0x0000 PLA El ement 6 control register. 0x0B1C PLAELM7 2 R/W 0x0000 PLA El ement 7 control register. 0x0B20 PLAELM8 2 R/W 0x0000 PLA El ement 8 control register. 0x0B24 PLAELM9 2 R/W 0x0000 PLA El ement 9 control register. 0x0B28 PLAELM10 2 R/W 0x0000 PLA El ement 10 control register. 0x0B2C PLAELM11 2 R/W 0x0000 PLA El ement 11 control register. 0x0B30 PLAELM12 2 R/W 0x0000 PLA El ement 12 control register. 0x0B34 PLAELM13 2 R/W 0x0000 PLA El ement 13 control register. 0x0B38 PLAELM14 2 R/W 0x0000 PLA El ement 14 control register. 0x0B3C PLAELM15 2 R/W 0x0000 PLA El ement 15 control register. 0x0B40 PLACLK 1 R/W 0x00 PLA clock select register. 0x0B44 PLAIRQ 4 R/W 0x00000000 PLA interrupt control register. 0x0B48 PLAADC 4 R/W 0x00000000 PLA ADC trigger control register. 0x0B4C PLADIN 4 R/W 0x00000000 PLA data in register. 0x0B50 PLADOUT 4 R 0x00000000 PLA data out register. 0x0B54 PLALCK 1 W 0x00 PLA lock register.

Table 21. PWM Base Address = 0xFFFF0F80 0x0F84 PWM0COM0 2 R/W 0x0000 Compare Regist er 0 for PWM Output 0 and PWM Output 1. 0x0F88 PWM0COM1 2 R/W 0x0000 Compare Regist er 1 for PWM Output 0 and PWM Output 1. 0x0F8C PWM0COM2 2 R/W 0x0000 Compare Regist er 2 for PWM Output 0 and PWM Output 1. 0x0F90 PWM0LEN 2 R/W 0x0000 Frequency cont rol for PWM Output 0 and PWM Output 1. 0x0F94 PWM1COM0 2 R/W 0x0000 Compare Regist er 0 for PWM Output 2 and PWM Output 3. 0x0F98 PWM1COM1 2 R/W 0x0000 Compare Regist er 1 for PWM Output 2 and PWM Output 3. 0x0F9C PWM1COM2 2 R/W 0x0000 Compare Regist er 2 for PWM Output 2 and PWM Output 3. 0x0FA0 PWM1LEN 2 R/W 0x0000 Frequency cont rol for PWM Output 2 and PWM Output 3. 0x0FA4 PWM2COM0 2 R/W 0x0000 Compar e Register 0 for PWM Output 4. 0x0FA8 PWM2COM1 2 R/W 0x0000 Compar e Register 1 for PWM Output 4. 0x0FB0 PWM2LEN 2 R/W 0x0000 Frequen cy control for PWM Output 4. clears a PWM interrupt source. Table 22. GPIO Base Address = 0xFFFFF400 0xF400 GP0CON 4 R/W 0x00001111 GPIO Port0 control MMR. 0xF404 GP1CON 4 R/W 0x00000000 GPIO Port1 control MMR. 0xF408 GP2CON 4 R/W 0x00000000 GPIO Port2 control MMR. 0xF420 GP0DAT 4 R/W 0x000000XX GPIO Port0 data control MMR. 0xF424 GP0SET 4 W 0x000000XX GPIO Port0 data set MMR. 0xF428 GP0CLR 4 W 0x000000XX GPIO Port0 data clear MMR. 0xF42C GP0PAR 4 R/W 0x22220000 GPIO Port0 pull-up disable MMR. 0xF430 GP1DAT 4 R/W 0x000000XX GPIO Port1 data control MMR. 0xF434 GP1SET 4 W 0x000000XX GPIO Port1 data set MMR. 0xF438 GP1CLR 4 W 0x000000XX GPIO Port1 data clear MMR. 0xF43C GP1PAR 4 R/W 0x22000022 GPIO Port1 pull-up disable MMR. 0xF440 GP2DAT 4 R/W 0x000000XX GPIO Port2 data control MMR. 0xF444 GP2SET 4 W 0x000000XX GPIO Port2 data set MMR. 0xF448 GP2CLR 4 W 0x000000XX GPIO Port2 data clear MMR. 0xF44C GP2PAR 4 R/W 0x00000000 GPIO Port2 pull-up disable MMR. Table 23. Flash/EE Base Address = 0xFFFFF800 0xF800 FEESTA 1 R 0x20 Flash/EE status MMR. 0xF804 FEEMOD 2 R/W 0x 0000 Flash/EE control MMR. 0xF808 FEECON 1 R/W 0x 07 Flash/EE control MMR. 0xF80C FEEDAT 2 R/W 0xXXXX Flash/EE data MMR. 0xF810 FEEADR 2 R/W 0x0000 Flash/EE address MMR. 0xF818 FEESIGN 3 R 0xFFFFFF Flash/EE LFSR MMR. 0xF81C FEEPRO 4 R/W 0x00000000 Fl ash/EE protection MMR. 0xF820 FEEHIDE 4 R/W 0xFFFFFFFF Flash/EE protection MMR.

track-and-hold, an on-chip reference, and an ADC. signals) or single-ended mode (for any single-ended signals). Figure 19. Examples of Balanced Signals in Fully Differential Mode described later in the Band Gap Reference section. temperature sensor channel that measures die temperature.

1 LSB = FS/4096, or

Figure 20. ADC Transfer Function in Single-Ended Mode the signals applied to the VIN+ and VIN– pins (that is, VIN+ − VIN−). Figure 21. ADC Transfer Function in Differential Mode

This bit is set by the user to start any type of conversion command. when continuously converting).

6 Reserved

5 μs before it converts correctly). This bit is cleared by the user to place the ADC in power-down mode. 000 Enable CONVSTART pin as a conversion input. 001 Enable Timer1 as a conversion input. 010 Enable Timer0 as a conversion input. 100 Continuous software conversion. Table 25. ADCCP MMR Bit Designation 4 to 0 Positive channel selection bits.

01101 Reserved

01110 DAC0

01111 DAC1

10001 AGND (self-diagnostic feature). 10010 Internal reference (self-diagnostic feature).

1 When a selected ADC channel is shared with one GPIO, by default, this pin is

pull-up resistor on P2.0/AIN12 for 40-lead package cannot be disabled.

Table 26. ADCCN MMR Bit Designation 4 to 0 Negative channel selection bits.

01011 Reserved

01110 Reserved

10001 AGND (self-diagnostic feature). 10010 Internal reference (s elf-diagnostic feature).

10011 Reserved

Function: ADCDAT is an ADC data result register.

The ADCCON register must be configured to 0x37A3. T is the temperature result. corresponds to 1/V TC specification as shown in Table 1. controlled temperature value. register, see the TEMPREF Register section. TTREF can be calculated using the TEMPREF register. Table 28. TSCON MMR Bit Designations 0 Temperature sensor chop enable bit. This bit is cleared to disable chopping. This bit is clea red by default. Table 29. TEMPREF MMR Bit Designations 8 Temperature reference voltage sign. 7 to 0 Temperature sensor offset calibration voltage. CTREF is calculated as above. VREF is 2.5 V, internal reference voltage. TREF is 27°C, when using TEMREF register. TREF is calculated as above. must only be used with the TEMPREF register.

external reference input on the VREF pin. Table 30. REFCON MMR Bit Designations 0 Internal reference output enable. for an external component but needs to be buffered. reference from the VREF pin. configured to use the same or different reference resource.

correctly referred to as Flash/EE memory. programmable (OTP) devices at remote operating nodes. (such as ADC, temperature sensor, and band gap references). This 2 kB embedded firmware is hidden from user code. cycling endurance and Flash/EE memory data retention.

1. Initial page erase sequence.
2. Read/verify sequence (single Flash/EE).
3. Byte program sequence memory.
4. Second read/verify sequence (endurance cycle).

A117 over the industrial temperature range of −40° to +125°C. figure over a supply temperature of 10,000 cycles. Figure 30. Flash/EE Memory Data Retention using the serial download mode or the provided JTAG mode. The ADuC7023 facilitates code download via the the I2C port. downloading via the I2C in more detail. facilitate code download and debug.

the 62 kB from being read through JTAG programming mode. protection is activated for all types of access. FEEHIDE MMR. This protection does not remain after reset. takes effect after a save protection command (0x0C) and a reset. The FEEPRO MMR is protected by a key to avoid direct access. the key again to modify the FEEPRO register is not allowed.

1. Write the bit in FEEPRO corresponding to the page to be
2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5
3. Write a 32-bit key in FEEADR, FEEDAT.
4. Run the write key command 0x0C in FEECON; wait for

the read to be successful by monitoring FEESTA. mass erase unprotects the part, but it also erases all user code. FEEADR = 0xDEAD and FEEDAT = 0xDEAD. Table 31. FEESTA MMR Bit Designations 3 Flash interrupt status bit. in the FEEMOD register is set. This bit is cleared when reading FEESTA register. This bit is set automatically when the controller is busy. This bit is cleared automatically when the controller is not busy. This bit is set automatically when a command is not completed. This bit is cleared automatically when reading FEESTA register. This bit is set by the MicroConve rter when a command is completed. This bit is cleared a utomatically when reading the FEESTA register.

Function: FEEMOD sets the operating mode of the flash control interface. Table 32 shows FEEMOD MMR bit designations. Table 32. FEEMOD MMR Bit Designations 8 Reserved. Always set this bit to 0. 7 to 5 Reserved. Always set this bit to 0 except when writing keys. See the Sequence to Write the Key section. 4 Flash/EE interrupt enable. This bit is set by the user to en able the Flash/EE interrupt. The interrupt occurs when a command is complete. This bit is cleared by the user to disable the Flash/EE interrupt. 3 Erase/write command protection. This bit is set by the user to enable the erase and write commands. This bit is cleared to protect th e Flash/EE against erase/write command. 2 to 0 Reserved. Always set this bit to 0. Function: FEECON is an 8-bit command register. The commands are described in Table 33. Table 33. Command Codes in FEECON 0x011 Single read Load FEEDAT with the 16-bit data. Indexed by FEEADR. 0x021 Single write Write FEEDAT at the address poi nted by FEEADR. This operation takes 50 μs. 0x051 Single erase Erase the page indexed by FEEADR. Executing a Mass Erase section. 0x0B Signature Give a signature of the 64 kB of Flash/EE in the 24-bit FEESIGN MMR. This operation takes 32,778 clock cycles.

0x0F Ping No operation; interrupt generated. 1 The FEECON register always reads 0x07 immediately after execution of any of these commands. Function: FEEDAT is a 16-bit data register. Function: FEEADR is anothe r 16-bit address register. Function: FEESIGN is a 24-bit code signature. software key (see Table 34). cleared by a reset (see Table 34). Table 34. FEEPRO and FEEHIDE MMR Bit Designations This bit is set by the user to allow reading the code. to Page 116, and Page 0 to Page 3. This bit is set by the user to allow writing the pages.

two cycles to fill the pipeline with the new instructions. data for any value of CD bits. and two cycles are needed to get the 32-bit data from Flash/EE. Table 35. Execution Cycles in ARM/Thumb Mode

1 The SWAP instruction combines an LD and STR instruction with only one

fetch, giving a total of eight cycles + 40 ns.

2 N is the number of data to load or store in the multiple load/store instruction

Figure 31. Remap for Exception Execution of the array because this is replaced by the SRAM. Address 0x00000000 by clearing Bit 0 of the Remap MMR. Flash/EE memory at the bottom of the array.

Table 36. REMAP MMR Bit Designations only 32 kB of Flash/EE memory is available. only 4 kB of SRAM is available. as GPIO, but this disables JTAG access. access is disabled if they are used as GPIO. 0x80014 during the last reset sequence. RSTSTA is null, the reset is external. state after a watchdog or software reset. Table 37. RSTSTA MMR Bit Designations This bit is set by the user to force a software reset.

Table 38. RSTCFG MMR Bit Designations 7 to 3 Reserved. Always set to 0.

2 This bit is set to 1 to configure the DAC outputs to retain

their state after a watchdog or software reset. return to their default state. 1 Reserved. Always set to 0.

0 This bit is set to 1 to configure the GPIO pins to retain

their state after a watchdog or software reset. return to their default state. Table 39. RSTCFG Write Sequence

capable of driving 5 kΩ/100 pF. gap 2.5 V reference) and 0 V to AVDD. The signal range is 0 V to AVDD. state during a watchdog or software reset. DAC0DAT (see Table 41) are described in detail in this section. Table 40. DAC0CON MMR Bit Designations

6 DACBY This bit is set to bypass the DAC

reset data register of the DAC to 0. 3 Reserved. This bit remains at 0. 2 Reserved. This bit remains at 0. Table 41. DAC0DAT MMR Bit Designations 27 to 16 12-bit data for DAC0. Figure 32. DAC Structure DD mode only, Code 3995 to Code 4095.

AVDD), showing no signs of endpoint linearity errors. Figure 33. Endpoint Nonlinearities Due to Amplifier Saturation can significantly limit output voltage swing. Table 42. Reference Source Selection for ADC and DAC 1 11 ADC works with internal VREF. DACs work with internal AVDD. amp with the DAC itself disabled. Table 43. DACBCFG MMR Bit Designations 7 to 4 Reserved. Always set to 0.

3 This bit is set to 1 to configure DAC3 output

2 This bit is set to 1 to configure DAC2 output

1 This bit is set to 1 to configure DAC1 output

0 This bit is set to 1 to configure DAC0 output

The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 46. Table 46. CMPCON MMR Bit Descriptions 10 CMPEN Comparator enable bit. This bit is set by the user to enable the comparator. This bit is cleared by the user to disable the comparator. 9 to 8 CMPIN Comparator negative input select bits. 7 to 6 CMPOC Comparator output configuration bits. input is below the negative input. 4 to 3 CMPRES Response time. 00 5 μs response time typical for large signals (2.5 V differential). 17 μs response time typical for small signals (0.65 mV differential). 2 CMPHYST Comparator hysteresis bit. This bit is set by the user to have a hysteresis of about 7.5 mV. This bit is cleared by the user to have no hysteresis. 1 CMPORI Comparator output rising edge interrupt. This bit is set automatically when a rising edge occurs on the monitored voltage (CMP0). This bit is cleared by the user by writing a 1 to this bit. 0 CMPOFI Comparator output rallying edge interrupt. This bit is set automatically when a falling edge occurs on the monitored voltage (CMP0). This bit is cleared by user.

Figure 36. Clocking System default, the part uses the internal oscillator feeding the PLL. came from the watchdog timer. A choice of operating modes is available on the ADuC7023. modes and indicates the power-up time. modes, depending on the clock divider bits. The ADC is turned off. Table 47. Operating Modes Table 48. Typical Current Consumption at 25°C in mA

be followed to write to the PLLCON and POWCONx registers. Table 49. PLLCON MMR Bit Designations to select the external 32 kHz crystal. 1 to 0 MDCLK Clocking modes. 01 PLL default configuration.

11 External clock on Pin 33 (40-lead

LFCSP)/Pin 25 (32-lead LFCSP). Table 50. PLLCON Write Sequence Table 51. POWCON0 MMR Bit Designations 2 to 0 CD CPU clock divider bits.

Table 52. POWCON0 Write Sequence Table 53. POWCON1 MMR Bit Designations

11 PWMPO Clearing this bit powers

8 SPIPO Clearing this bit powers

5 I2C1PO Clearing this bit powers

2 I2C0PO Clearing this bit powers

1 Divided clock for SPI/I2C0/I2C1 must be greater than or equal to the CPU

Table 54. POWCON1 Write Sequence

pins are configured in GPIO mode. registers, it is possible to enable/disable the pull-up resistors. The 20 GPIOs are grouped in three ports, Port 0 to Port 2 (Port x). Each port is controlled by four or five MMRs. other than GPIO. The PLA input is always active. Table 55. GPIO Pin Function Descriptions

1 These pins should not be used by user code when debugging the part via

P0.0/BM pin during the last reset sequence.

2 If the pins are configured for JTAG mode (see Table 36), then these pins

3 I2C1 function is only available on the 32-lead and 36-ball packages. configure it as a clock input, the MDCLK bits in PLLCON must be set to 11. 5 I2C1 function is only available on the 40-lead package. function of each pin of Port x as described in Table 56. Table 56. GPxCON MMR Bit Descriptions 29 to 28 Select function of Px.7 pin. 25 to 24 Select function of Px.6 pin. 21 to 20 Select function of Px.5 pin. 17 to 16 Select function of Px.4 pin. 13 to 12 Select function of Px.3 pin. 9 to 8 Select function of Px.2 pin. 5 to 4 Select function of Px.1 pin. 1 to 0 Select function of Px.0 pin.

Table 57. GPxPAR MMR Bit Descriptions 30 to 29 Drive strength Px.7. 26 to 26 Drive strength Px.6. 22 to 21 Drive strength Px.5. 18 to 17 Drive strength Px.4. 14 to 13 Drive strength Px.3. 10 to 9 Drive strength Px.2. Table 58. GPIO Drive Strength Control Bits Descriptions Figure 37. Programmable Strength for High Level Figure 38. Programmable Strength for Low Level The drive strength bits can be written one time only after reset. Table 59. GPxPAR Control Bits Access Descriptions1

31 Reserved Reserved Reserved

28 R/W R/W Reserved

27 Reserved Reserved Reserved

24 R/W R/W Reserved

23 Reserved Reserved Reserved

20 R/W R/W Reserved

19 Reserved Reserved Reserved

16 R/W R/W R/W

15 Reserved Reserved Reserved

12 R/W R/W R/W

11 Reserved Reserved Reserved

8 Reserved R/W R/W

7 Reserved Reserved Reserved

4 Reserved R/W Reserved

3 Reserved Reserved Reserved

0 R/W R/W R (b0)

input value of the pins configured as input. Table 60. GPxDAT MMR Bit Descriptions 31 to 24 Direction of the data. 23 to 16 Port x data output. 15 to 8 Reflect the state of Port x pins at reset (read only). 7 to 0 Port x data input (read only). Function: GP0SET is a data set Port x register. Table 61. GPxSET MMR Bit Descriptions Function: GP0CLR is a data clear Port x register. Function: GP1CLR is a data clear Port x register. Function: GP2CLR is a data clear Port x register.

Table 62. GPxCLR MMR Bit Descriptions 23 to 16 Data port x clear bit. full duplex up to a maximum bit rate of 20 Mbps. transmitted and received through the MOSI SCLK period. mode and as an input in slave mode. fUCLK is the clock selected by POWCON1 Bit 7 to Bit 6. accepts data from an external master up to 10 Mbps. same for the master and slave devices. . In slave mode, SS is always an input. deasserts itself upon completion. and high at the end of a transfer. P0.6 is the master in, slave out (MISO) pin. P0.7 is the master out, slave in (MOSI) pin. SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. interface in both master and slave modes.

Table 63. SPISTA MMR Bit Designations 11 SPIREX SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON. This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE. 10 to 8 SPIRXFSTA[2:0] SP I Rx FIFO status bits. [001] = 1 valid byte in the FIFO. [010] = 2 valid byte in the FIFO. [011] = 3 valid byte in the FIFO. [100] = 4 valid byte in the FIFO. 7 SPIFOF SPI Rx FIFO overflow status bit. except when SPIRFLH is set in SPICON. This bit is cleared when the SPISTA register is read. 6 SPIRXIRQ SPI Rx IRQ status bit. required number of bytes have been received. This bit is cleared when the SPISTA register is read. 5 SPITXIRQ SPI Tx IRQ status bit. number of bytes have been transmitted. This bit is cleared when the SPISTA register is read. 4 SPITXUF SPI Tx FIFO underflow. except when SPITFLH is set in SPICON. This bit is cleared when the SPISTA register is read. 3 to 1 SPITXFSTA[2:0] SP I Tx FIFO status bits. [001] = 1 valid byte in the FIFO. [010] = 2 valid byte in the FIFO. [011] = 3 valid byte in the FIFO. [100] = 4 valid byte in the FIFO. 0 SPIISTA SPI interrupt status bit. This bit is set to 1 when an SPI based interrupt occurs. This bit is cleared after reading SPISTA. Function: This 8-bit MMR is the SPI receive register. Function: This 8-bit MMR is the SPI transmit register.

Rev. H | Page 58 of 98 SPIDIV Register Name: SPIDIV Address: 0xFFFF0A0C Default value: 0x00 Access: Read/write Function: This 6-bit MMR is the SPI baud rate selection register. (Note that the maximum value of this MMR is 0x3F.) SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the SPI peripheral in both master and slave modes.

Table 64. SPICON MMR Bit Designations SPIMDE SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. been received into the FIFO. 13 SPITFLH SPI Tx FIFO flush enable bit. This bit is set to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then eith er the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. Any writes to the Tx FIFO ar e ignored while this bit is set. This bit is cleared to disable Tx FIFO flushing. 12 SPIRFLH SPI Rx FIFO flush enable bit. This bit is set to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer. This bit is cleared to disable Rx FIFO flushing. 11 SPICONT Continuous transfer enable. the Tx register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. This bit is cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle. 10 SPILP Loop back enable bit. This bit is set by the user to conn ect MISO to MOSI and test software. This bit is cleared by the user to be in normal mode. 9 SPIOEN Slave MISO output enable bit. This bit is set for MISO to operate as normal. This bit is cleared to disable the o utput driver on the MISO pin. The MISO pin is open-drain when this bit is clear. 8 SPIROW SPIRX overflow overwrite enable. This bit is set by the user; the va lid data in the Rx register is overwritten by the new serial byte received. This bit is cleared by the user; the new serial byte received is discarded. 7 SPIZEN SPI transmit zeros when Tx FIFO is empty. This bit is set to transmit 0x00 when there is no valid data in the Tx FIFO. This bit is cleared to transmit the last transmitted value when there is no valid data in the Tx FIFO. 6 SPITMDE SPI transfer and interrupt mode. This bit is set by the user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty. This bit is cleared by the us er to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full. 5 SPILF LSB first transfer enable bit. This bit is set by the user; the LSB is transmitted first. This bit is cleared by the us er; the MSB is transmitted first. 4 SPIWOM SPI wired or mode enable bit. This bit is set to 1 enable open-drain data output. External pull- ups are required on data out pins. This bit is cleared for normal output levels. 3 SPICPO Serial clock polarity mode bit. This bit is set by the user; the serial clock idles high. This bit is cleared by the user; the serial clock idles low. 2 SPICPH Serial clock phase mode bit. This bit is set by the user; the serial clock pu lses at the beginning of each serial bit transfer. This bit is cleared by the use r; the serial clock pulses at the end of each serial bit transfer.

Rev. H | Page 60 of 98 Bit Name Description 1 SPIMEN Master mode enable bit. This bit is set by the us er to enable master mode. This bit is cleared by the user to enable slave mode. 0 SPIEN SPI enable bit. This bit is set by the user to enable the SPI. This bit is cleared by th e user to disable the SPI.

Rev. H | Page 61 of 98 I2C The ADuC7023 incorporates two I2C peripherals that may be configured as a fully I2C-compatible I2C bus master device or as a fully I2C bus-compatible slave device. The two pins used for data transfer, SDA and SCL, are configured in a wire-AND format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up values are between 4.7 kΩ and 10 kΩ. The I 2C bus peripheral address in the I2C bus system is pro- grammed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (read or/write) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges the data, transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. The I2C peripheral can only be configured as a master or slave at any given time. The same I2C channel cannot simultaneously support master and slave modes. The I 2C interface on the ADuC7023 includes support for repeated start conditions. In master mode, the ADuC7023 can be programmed to generate a repeated start. In slave mode, the ADuC7023 recognizes repeated start conditions. In master and slave mode, the part recognizes both 7-bit and 10-bit bus addresses. In I 2C master mode, the ADuC7023 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence. Clock stretching can be enabled by other devices on the bus without causing any issues with the ADuC7023. However, the ADuC7023 cannot enable clock stretching. In slave mode, the ADuC7023 can be programmed to return a NACK. This allows the validation of checksum bytes at the end of I2C transfers. Bus arbitration in master mode is supported. Internal and external loopback modes are supported for I 2C hardware testing. In loopback mode. The transmit and receive circuits in both master and slave mode contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs. CONFIGURING EXTERNAL PINS FOR I2C FUNCTIONALITY The I2C pins of the ADuC7023 device are P0.4 and P0.5 for I2C0 and P0.6 and P0.7 for I2C1. P0.4 and P0.6 are the I2C clock signals and P0.5 and P0.7 are the I2C data signals. For instance, to configure I2C0 pins (SCL0, SDA0), Bit 16 and Bit 20 of the GP0CON register must be set to 1 to enable I 2C mode. On the other hand, to configure I2C1 pins (SCL1, SDA1), Bit 25 and Bit 29 of the GP0CON register must be set to 1 to enable I 2C mode, as shown in the GPIO section. I2C1 function is available at P0.6 and P0.7 on 32-lead and 36-ball packages and available at P1.6 and P1.7 on 40-lead package. SERIAL CLOCK GENERATION The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CDIV MMR as follows: ) (2 ) 2 (DIVLDIVH     UCLK CLOCKSERIAL ff where: fUCLK is the clock before the clock divider and the clock selected by POWCON1 Bit 4 to Bit 0. DIVH is the high period of the clock. DIVL is the low period of the clock. Thus, for 100 kHz operation, DIVH = DIVL = 0xCF and for 400 kHz, DIVH = 0x28, DIVL = 0x3C The I2CDIV register corresponds to DIVH:DIVL. I2C BUS ADDRESSES Slave Mode In slave mode, the registers I2CxID0, I2CxID1, I2CxID2, and I2CxID3 contain the device IDs. The device compares the four I2CxIDx registers to the address byte received from the bus master. To be correctly addressed, the 7MSBs of either ID register must be identical to that of the 7MSBs of the first received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The ADuC7023 also supports 10-bit addressing mode. When Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in registers I2CxID0 and I2CxID1. The 10-bit address is derived as follows: I2CxID0[7:3] must be set to 11110b. I2CxID0[2:1] = Address Bits[9:8]. I2CxID0[0] is the read/write bit and is not part of the I address. This must be written as 0. I2CxID0[7:0] = Address Bits[7:0]. Master Mode In master mode, the I2CxADR0 register is programmed with the I2C address of the device. In 7-bit address mode, I2CxADR0[7:1] are set to the device address. I2CxADR0[0] is the read/write bit. In 10-bit address mode, the 10-bit address is created as follows: I2CxADR0[7:3] must be set to 11110b. I2CxADR0[2:1] = Address Bits[9:8]. I2CxADR1[7:0] = Address Bits[7:0].

I2CxADR0[0] is the read/write bit. I2CxADR0 while the master is still busy. The I2C peripheral interfaces consist of a number of MMRs. These are described in the following section. Function: These 16-bit MMRs configure the I 2C peripheral in master mode. Table 65. I2CxMCON MMR Bit Designations 15 to 9 Reserved. These bits are reserved and should not be written to. 8 I2CMCENI I 2C transmission complete interrupt enable bit. This bit is set to enable an interrupt on detecting a stop condition on the I2C bus. This bit clears this interrupt source. 7 I2CNACKENI I 2C no acknowledge received interrupt enable bit. This bit is set to enable interrupts when the I 2C master receives a no acknowledge. This bit clears this interrupt source. 6 I2CALENI I 2C arbitration lost interrupt enable bit. This bit is set to enable interrupts when the I 2C master has lost in trying to gain control of the I2C bus. This bit clears this interrupt source. 5 I2CMTENI I 2C transmit interrupt enable bit. This bit is set to enable interrupts when the I 2C master has transmitted a byte. This bit clears this interrupt source. 4 I2CMRENI I 2C receive interrupt enable bit. This bit is set to enable interrupts when the I 2C master receives data. This bit is cleared by the user to disable interrupts when the I2C master is receiving data. 3 Reserved. Write a value of 0 to this bit. 2 I2CILEN I 2C internal loopback enable bit. their respective input signals. This bit is cleared by the user to disable loopback mode. 1 I2CBD I 2C master backoff disable bit. This bit is cleared to back off until the I2C bus becomes free. 0 I2CMEN I 2C master enable bit. This bit is set by the user to enable I 2C master mode. This bit is cleared to disable I 2C master mode.

Function: These 16-bit MMRs are the I 2C status registers in master mode. Table 66. I2CxMSTA MMR Bit Designations 15 to 11 Reserved. These bits are reserved. 10 I2CBBUSY I 2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. 9 I2CMRxFO Master Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. 8 I2CMTC I 2C transmission complete status bit. communicating. If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit clears this interrupt source. 7 I2CMNA I 2C master no acknowledge data bit. transfer. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 6 I2CMBUSY I2C master busy status bit. This bit is set to 1 when the mast er is busy processing a transaction. This bit is cleared if the master is ready or if another master device has control of the bus. 5 I2CAL I 2C arbitration lost status bit. I2C1MCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 4 I2CMNA I 2C master no acknowledge address bit. This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the I2CNACKENI bit in I2C1MCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 3 I2CMRXQ I 2C master receive request bit. This bit is cleared in all other conditions. 2 I2CMTXQ I 2C master transmit request bit. address and write. If the I2CMTENI bit in I2C1MCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. 1 to 0 I2CMTFSTA I 2C master Tx FIFO status bits. 00 = I 2C master Tx FIFO empty. 10 = 1 byte in master Tx FIFO. 11 = I 2C master Tx FIFO full.

sequence from a slave device. Table 67. I2CxMCNT0 MMR Bit Descriptions: Address =

8 I2CRECNT This bit is set if greater than 256 bytes are

these bits should be set to 0. Table 68. I2CxADR0 MMR in 7-Bit Address Mode: Address = 0 R/W Bit 0 is the read/write bit. Table 69. I2CxADR0 MMR in 10-Bit Address Mode

the least significant byte of the address. Table 70. I2CxADR1 MMR in 10-Bit Address Mode pin. For further details, see the I2C initial section. Table 71. I2CxDIV MMR Table 72. I2CxSCON MMR Bit Designations 10 I2CSTXENI Slave transmit interrupt enable bit. This bit is set to enable an interrupt after a slave transmits a byte. This bit clears this interrupt source. 9 I2CSRXENI Slave receive interrupt enable bit. This bit is set to enable an interrupt after the slave receives data. This bit clears this interrupt source. 8 I2CSSENI I 2C stop condition detected interrupt enable bit. This bit is set to enable an interrupt on detecting a stop condition on the I2C bus. This bit clears this interrupt source. 7 I2CNACKEN I 2C no acknowledge enable bit. This bit is set to no acknowledge the next byte in the transmission sequence. This bit is cleared to let the hardware control the acknowledge/no acknowledge sequence. 6 Reserved. Write a value of 0 to this bit. 5 I2CSETEN I 2C early transmit interrupt enable bit.

Rev. H | Page 66 of 98 Bit Name Description 4 I2CGCCLR I 2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register. This bit is cleared at all other times. 3 I2CHGCEN I2C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CxALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a broadcast message to all master devices on the bus. The ADuC7023 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be written to 1, as per the I2C January 2000 bus specification. This bit and I2CGCEN are set to enable hardware general call recognition in slave mode. This bit is cleared to disable recognition of hardware general call commands. 2 I2CGCEN I2C general call enable. This bit is set to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. This bit is set to allow the slave acknowledge I2C general call commands. This bit is cleared to disable recognition of general call commands. 1 ADR10EN I 2C 10-bit address mode. This bit is set to 1 to enable 10-bit address mode. This bit is cleared to 0 to enable normal address mode. 0 I2CSEN I 2C slave enable bit. This bit is set by user to enable I2C slave mode. This bit is cleared by the user to disable I2C slave mode. I2C Slave Status Registers, I2CxSSTA Name: I2C0SSTA, I2C1SSTA Address: 0xFFFF082C, 0xFFFF092C Default value: 0x0000, 0x0000 Access: Read/write Function: These 16-bit MMRs are the I 2C status registers in slave mode.

Table 73. I2CxSSTA MMR Bit Designations byte (0x01) is received. If general calls are enabled and a general call code of (0x00) is received. This bit is cleared on receiving a stop condition. 13 I2CREPS This bit is set to 1 if a re peated start condition is detected. This bit is cleared on receiving a stop condition. A read of the I2CxSSTA register also clears this bit. 12 to 11 I2CID[1:0] I2C address matching register. These bits indicate which I2CxIDx register matches the received address. [00] = received address matches I2CxID0. [01] = received address matches I2CxID1. [10] = received address matches I2CxID2. [11] = received address matches I2CxID3. 10 I2CSS I 2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated. This bit is cleared by reading this register. 9 to 8 I2CGCID[1:0] I 2C general call ID bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative ID. These bits are not cleared by a general call reset command. These bits are cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON. 7 I2CGC I 2C general call status bit. This bit is cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON. 6 I2CSBUSY I 2C slave busy status bit. This bit is set to 1 when the slave receives a start condition. 5 I2CSNA I 2C slave no acknowledge data bit. the I2CNACKEN bit is set in the I2CxSCON register. This bit is cleared in all other conditions. 4 I2CSRxFO Slave Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. 3 I2CSRXQ I 2C slave receive request bit. I2CSRXENI bit in I2CxSCON is set. The Rx FIFO must be read or flushed to clear this bit. 2 I2CSTXQ I 2C slave transmit request bit. bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCON is set. This bit is cleared in all other conditions.

Rev. H | Page 68 of 98 Bit Name Description 1 I2CSTFE I 2C slave FIFO underflow status bit. This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. 0 I2CETSTA I 2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CxSCON is = 0, this bit goes high if the slave Tx FIFO is empty. If the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read. I2C Slave Receive Registers, I2CxSRX Name: I2C0SRX, I2C1SRX Address: 0xFFFF0830, 0xFFFF0930 Default value: 0x00 Access: Read Function: These 8-bit MMRs are the I 2C slave receive register. I2C Slave Transmit Registers, I2CxSTX Name: I2C0STX, I2C1STX Address: 0xFFFF0834, 0xFFFF0934 Default value: 0x00 Access: Write Function: These 8-bit MMRs are the I 2C slave transmit registers. I2C Hardware General Call Recognition Registers, I2CxALT Name: I2C0ALT, I2C1ALT Address: 0xFFFF0838, 0xFFFF0938 Default value: 0x00 Access: Read/write Function: These 8-bit MMRs are used with hardware general calls when the I2CxSCON Bit 3 is set to 1. These registers are used in cases where a master is unable to generate an address for a slave, and instead, the slave must generate the address for the master. I2C Slave Device ID Registers, I2CxIDx Name: I2C0IDx, I2C1IDx Addresses: 0xFFFF093C = I2C1ID0 0xFFFF083C = I2C0ID0 0xFFFF0940 = I2C1ID1 0xFFFF0840 = I2C0ID1 0xFFFF0944 = I2C1ID2 0xFFFF0844 = I2C0ID2 0xFFFF0948 = I2C1ID3 0xFFFF0848 = I2C0ID3 Default value: 0x00 Access: Read/write Function: These 8-bit MMRs are programmed with I2C bus IDs of the slave. See the I2C Bus Addresses section for further details. I2C Common Registers I2C FIFO Status Registers, I2CxFSTA Name: I2C0FSTA, I2C1FSTA Address: 0xFFFF084C, 0xFFFF094C Default value: 0x0000 Access: Read/write Function: These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes.

Table 74. I2CxFSTA MMR Bit Designations

9 I2CFMTX This bit is set to 1 to flush the master

8 I2CFSTX This bit is set to 1 to flush the slave Tx

7 to 6 I2CMRXSTA I 2C master receive FIFO status bits. [01] = byte written to FIFO. 5 to 4 I2CMTXSTA I 2C master transmit FIFO status bits. [01] = byte written to FIFO. 3 to 2 I2CSRXSTA I 2C slave receive FIFO status bits. 1 to 0 I2CSTXSTA I 2C slave transmit FIFO status bits. [01] = byte written to FIFO. (PLA) consisting of sixteen PLA elements. two inputs and a flip-flop. This is represented in Figure 39. Figure 39. PLA Element Table 75. Element Input/Output 1 Internal pins only. Read via GPxDAT register. described in the following sections. Table 76. PLAELMx Registers

Table 77. PLAELMx MMR Bit Descriptions 10 to 9 Mux 0 control (see Table 81). 8 to 7 Mux 1 control (see Table 81). bit value from the PLADIN register. input pin of the particular element. 4 to 1 Look-up table control. flip-flop (cleared by default). Table 78. PLACLK MMR Bit Descriptions 6 to 4 Clock source selection. 100 External 32.768 kHz crystal. 111 Internal 32,768 oscillator. 2 to 0 Clock source selection. 100 External 32.768 kHz crystal. 111 Internal 32,768 oscillator.

selects the source of the IRQ. Table 79. PLAIRQ MMR Bit Descriptions

Table 80. Feedback Configuration

01 Element 2 Element 2 Element 10 Element 10

10 Element 4 Element 4 Element 12 Element 12

11 Element 6 Element 6 Element 14 Element 14

01 Element 3 Element 3 Element 11 Element 11

10 Element 5 Element 5 Element 13 Element 13

11 Element 7 Element 7 Element 15 Element 15

Table 81. PLAADC MMR Bit Descriptions 4 ADC start conversion enable bit. 3 to 0 ADC start conversion source. Function: PLADIN is a data input MMR for PLA. Table 82. PLADIN MMR Bit Descriptions 15 to 0 Input bit to El ement 15 to Element 0. Function: PLADOUT is a data output MMR for PLA. This register is always updated. Table 83. PLADOUT MMR Bit Descriptions 15 to 0 Output bit from El ement 15 to Element 0. development system to easily configure PLA.

and over the duty cycle of each individual output. Table 84. PWM MMRs PWMCON1 PWM Control Register 1. PWM2LEN Frequency control for PWM Output 4. PWMCLRI PWM interrupt clear. pair of PWM outputs (PWM0 and PWM1) is shown in Figure 40. Figure 40. PWM Timing

1. The length of a PWM period is defined by PWMxLEN.

PWM0 and PWM1 waveforms in Figure 40. high-side waveform (PWM0) goes low. when the timer count reaches the value held in PWM0COM1.

Table 85. PWMCON1 MMR Bit Designations 14 SYNC Enables PWM synchronization. transition on the P2.2/SYNC pin. Cleared by the user to ignore transitions on the P2.2/SYNC pin. 13 Reserved Set to 0 by the user. 12 PWM3INV Set to 1 by the user to invert PWM3. Cleared by the user to use PWM3 in normal mode. 11 PWM1INV Set to 1 by the user to invert PWM1. Cleared by the user to use PWM1 in normal mode. PWMEN bit is cleared and an interrupt is generated. Cleared by the user to disable the PWMTRIP interrupt. 9 ENA If HOFF = 0 and HMODE = 1. Note that, if not in H-bridge mode, this bit has no effect. Set to 1 by the user to enable PWM outputs. Cleared by the user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 86. 8 to 6 PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider. 5 POINV Set to 1 by the user to invert all PWM outputs. Cleared by the user to use PWM outputs as normal. Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low. Cleared by the user to use the PWM outputs as normal. 3 LCOMP Load compare registers. the PWM timer from 0x00 to 0x01. Cleared by the user to use the values previously stored in the internal compare registers. Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. Cleared by the user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. Set to 1 by the user to enable H-bridge mode. Cleared by the user to operate the PWMs in standard mode. 0 PWMEN Set to 1 by the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs. 1 In H-bridge mode, HMODE = 1. See Table 86 to determine the PWM outputs.

generation of multiple interrupts. Table 86. PWM Output Selection 2 HS = high side, LS = low side. Table 87. Compare Registers

Rev. H | Page 76 of 98 PWM0COM0 Compare Register Name: PWM0COM0 Address: 0xFFFF0F84 Default value: 0x0000 Access: Read and write Function: PWM0 output pin goes high when the PWM timer reaches the count value stored in this register. PWM0COM1 Compare Register Name: PWM0COM1 Address: 0xFFFF0F88 Default value: 0x0000 Access: Read and write Function: PWM0 output pin goes low when the PWM timer reaches the count value stored in this register. PWM0COM2 Compare Register Name: PWM0COM2 Address: 0xFFFF0F8C Default value: 0x0000 Access: Read and write Function: PWM1 output pin goes low when the PWM timer reaches the count value stored in this register. PWM0LEN Register Name: PWM0LEN Address: 0xFFFF0F90 Default value: 0x0000 Access: Read and write Function: PWM1 output pin goes high when the PWM timer reaches the value stored in this register. PWM1COM0 Compare Register Name: PWM1COM0 Address: 0xFFFF0F94 Default value: 0x0000 Access: Read and write Function: PWM2 output pin goes high when the PWM timer reaches the count value stored in this register. PWM1COM1 Compare Register Name: PWM1COM1 Address: 0xFFFF0F98 Default value: 0x0000 Access: Read and write Function: PWM2 output pin goes low when the PWM timer reaches the count value stored in this register. PWM1COM2 Compare Register Name: PWM1COM2 Address: 0xFFFF0F9C Default value: 0x0000 Access: Read and write Function: PWM3 output pin goes low when the PWM timer reaches the count value stored in this register. PWM1LEN Register Name: PWM1LEN Address: 0xFFFF0FA0 Default value: 0x0000 Access: Read and write Function: PWM3 output pin goes high when the PWM timer reaches the value stored in this register.

Rev. H | Page 77 of 98 PWM2COM0 Compare Register Name: PWM2COM0 Address: 0xFFFF0FA4 Default value: 0x0000 Access: Read/write Function: PWM4 output pin goes high when the PWM timer reaches the count value stored in this register. PWM2COM1 Compare Register Name: PWM2COM1 Address: 0xFFFF0FA8 Default value: 0x0000 Access: Read/write Function: PWM4 output pin goes low when the PWM timer reaches the count value stored in this register. PWM2LEN Register Name: PWM2LEN Address: 0xFFFF0FB0 Default value: 0x0000 Access: Read/write Function: PWM2LEN defines the period of PWM4. PWMCLRI Register Name: PWMCLRI Address: 0xFFFF0FB8 Default value: 0x0000 Access: Write Function: Write any value to this register to clear a PWM interrupt source. This register must be written to before exiting a PWM interrupt service routine; otherwise, multiple interrupts occur.

normal interrupt request IRQ or a fast interrupt request FIQ. All the interrupts can be masked separately. when the full-vectored interrupt controller is enabled. interrupt sources are serviced. Table 88. IRQ/FIQ MMRs Bit Description 0 All interrupts OR’ed (FIQ only). interrupt handling of internal and external events. sources can be masked in the IRQEN MMR.

Rev. H | Page 79 of 98 IRQEN Register Name: IRQEN Address: 0xFFFF0008 Default value: 0x00000000 Access: Read/write Function: IRQEN provides the value of the current enable mask. When each bit is set to 1, the source request is enabled to create an IRQ exception. When each bit is set to 0, the source request is disabled or masked, which does not create an IRQ exception. To clear an already enabled interrupt source, users must set the appropriate bit in the IRQCLR register. Clearing an interrupt IRQEN bit does not disable this interrupt. IRQCLR Register Name: IRQCLR Address: 0xFFFF000C Default value: 0x00000000 Access: Write Function: IRQCLR (write-only register) clears the IRQEN register to mask an interrupt source. Each bit set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, independently manipulate the enable mask without requiring an atomic read-modify-write. FAST INTERRUPT REQUEST (FIQ) The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks. FIQSIG FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal the corresponding bit in the FIQSIG is set, otherwise it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only. FIQSIG Register Name: FIQSIG Address: 0xFFFF0104 Default value: 0x00000000 Access: Read only FIQEN FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or masked which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt. FIQEN Register Name: FIQEN Address: 0xFFFF0108 Default value: 0x00000000 Access: Read/write FIQCLR FIQCLR is a write-only register that allows the FIQEN register to clear in order to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. This register should only be used to disable an interrupt source when in the interrupt sources interrupt service routine or if the peripheral is temporarily disabled by its own control register. This register should not be used to disable an IRQ source if that IRQ source has an interrupt pending or could have an interrupt pending. FIQCLR Register Name: FIQCLR Address: 0xFFFF010C Default value: 0x00000000 Access: Write only

programmed source interrupt. Table 89. SWICFG MMR Bit Designations Figure 41. Interrupt Structure achieved by using the IRQBASE and IRQVEC registers. possible to have 16 separate interrupt levels. Table 90. IRQBASE MMR Bit Designations 31:16 Read only Reserved Always read as 0. 15:0 R/W 0 Vector base address.

enabled by setting Bit 0 of the IRQCONN register. Table 91. IRQVEC MMR Bit Designations 31 to 23 Read only 0 Always read as 0. 22 to 7 R/W 0 IRQBASE register value. 1 to 0 Reserved 0 Reserved bits. enabled by setting Bit 0 of the IRQCONN register.

Table 92. IRQP0 MMR Bit Designations

31 Reserved Reserved bit

27 Reserved Reserved bit

23 Reserved Reserved bit

the Flash controller interrupt source.

7 Reserved Reserved bit

the software interrupt source. 3 to 0 Reserved Interrupt 0 cannot be prioritized. Table 93. IRQP1 MMR Bit Designations Table 94. IRQP2 MMR Bit Designations 31 to 23 Reserved Reserved bit.

The IRQCONN register is the IRQ and FIQ control register. nesting and prioritization of FIQ interrupts. FIQ does have a higher priority than an IRQ. Table 95. IRQCONN MMR Bit Designations

1 ENFIQN This bit is set to 1 to enable nesting of FIQ

prioritization of FIQs is allowed.

0 ENIRQN This bit is set to 1 to enable nesting of IRQ

Table 96. IRQSTAN MMR Bit Designations setting Bit 1 of the IRQCONN register. Table 97. FIQVEC MMR Bit Designations 31 to 23 Read only 0 Always read as 0. 22 to 7 R/W 0 IRQBASE register value. 1 to 0 Reserved 0 Reserved bits.

is of Priority 1, then Bit 1 asserts, and so forth. Table 98. FIQSTAN MMR Bit Designations individually configured as level or rising/falling edge triggered. IRQCONE register must be appropriately configured. Table 99. IRQCONE MMR Bit Designations

10 PLA IRQ1 triggers on rising

01 PLA IRQ1 triggers on low

00 PLA IRQ1 triggers on high

10 External IRQ3 triggers on

01 External IRQ3 triggers on

00 External IRQ3 triggers on

10 External IRQ2 triggers on

01 External IRQ2 triggers on

00 External IRQ2 triggers on

10 PLA IRQ0 triggers on rising

01 PLA IRQ0 triggers on low

00 PLA IRQ0 triggers on high

10 External IRQ1 triggers on

01 External IRQ1 triggers on

00 External IRQ1 triggers on

10 External IRQ0 triggers on

01 External IRQ0 triggers on

00 External IRQ0 triggers on

Table 100. IRQCLRE MMR Bit Designations

20 PLA1CLRI A 1 must be written to this bit in the PLA IRQ1

triggered PLA IRQ1 interrupt.

19 IRQ3CLRI A 1 must be written to this bit in the external

18 IRQ2CLRI A 1 must be written to this bit in the external

17 PLA0CLRI A 1 must be written to this bit in the PLA IRQ0

triggered PLA IRQ0 interrupt.

16 IRQ1CLRI A 1 must be written to this bit in the external

13 IRQ0CLRI A 1 must be written to this bit in the external

Timer0, Timer1, and Timer2 or Watchdog Timer. either free-running or periodic. starts again at the value stored in the load register. The timer interval is calculated as follows. different, it should be read a third time to get the correct value. corresponding timer (TxCON). each time the counter value reaches full scale when counting up. that particular timer (TxCLRI). routine. This can be done by checking the IRQSTA MMR. Table 101. Hours, Minutes, Seconds, and Hundreds Format Figure 42. Timer0 Block Diagram

T0CON is the configuration MMR described in Table 102. Table 102. T0CON MMR Bit Descriptions free-running mode. Default mode. 10 Internal 32768 Hz oscillator. 3 to 2 00 Source clock/1. Default value. 11 Undefined. Equivalent to 00. hours, minutes, seconds, hundredths. precision allowed by the RTOS timer when the IRQ is serviced. Figure 43. Timer1 Block Diagram

T1CON is the configuration MMR described in Table 103. Table 103. T1CON MMR Bit Descriptions

010 UCLK

011 P1.1 raising edge triggered. by the user to disable Timer1 by default.

10 Hours, minutes, seconds, hundredths

11 Hours, minutes, seconds, hundredths

clears the Timer1 interrupt.

prevent it from forcing a processor reset. Figure 44. Timer2 Block Diagram Watchdog mode is entered by setting Bit 5 in the T2CON MMR. can be 512 sec using the prescaler/256, and full-scale in T2LD. reloads the counter with T2LD and begins a new timeout period. value that is loaded into the counter. T2CON is the configuration MMR described in Table 104. Table 104. T2CON MMR Bit Descriptions This bit is set by the user for Timer2 to count up. secure clear option by default. 00 Source clock/1 by default. 11 Undefined. Equivalent to 00. instead of a reset when the watchdog reaches 0.

mode or resets a new timeout period in watchdog mode. resetting the timeout period. The secure clear bit is provided for a higher level of protection. polynomial = X8 + X6 + X5 + X + 1 shown in Figure 45. if the count has not yet expired. it must be tracked/generated in software.

1. Enter initial seed, 0xAA, in T2CLRI before starting Timer2
2. Enter 0xAA in T2CLRI; Timer2 is reloaded.
3. Enter 0x37 in T2CLRI; Timer2 is reloaded.
4. Enter 0x6E in T2CLRI; Timer2 is reloaded.
5. Enter 0x66. 0xDC was expected; the watchdog resets the chip.

Figure 45. 8-Bit LFSR

Figure 54. Typical System Configuration

Rev. H | Page 94 of 98 DEVELOPMENT TOOLS PC-BASED TOOLS Four types of development systems are available for the ADuC7023 family. The ADuC7023 QuickStart Plus is intended for new users who want to have a comprehensive hardware development environment. These systems consist of the following PC-based (Windows® compatible) hardware and software development tools. Hardware The hardware system uses the ADuC7023 evaluation board, a serial port programming cable, and a RDI-compliant JTAG emulator (included in the ADuC7023 QuickStart Plus only). Software The software system has an integrated development environment, incorporating an assembler, compiler, and nonintrusive JTAG- based debugger. The software sytem uses a serial downloader software and example code. Miscellaneous The miscellaneous systems use CD-ROM documentation. IN-CIRCUIT I2C DOWNLOADER An I2C-based serial downloader is available at www.analog.com. This software requires an USB-to-I2C adaptor board available from Analog Devices. The part number for this USB-to-I2C adapter is USB-I2C/LIN-CONV-Z.

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

Figure 55. 40-Lead Frame Chip Scale Package [LFCSP] COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

3.50 REF

0.25 MIN

Figure 56. 32-Lead Lead Frame Chip Scale Package [LFCSP]

Figure 57. 36-Ball Wafer Level Chip Scale Package [WLCSP]

Rev. H | Page 97 of 98 ORDERING GUIDE Model1 ADC Channels DAC Channels FLASH/ RAM GPIO Downloader Temperature Range Package Description Package Option Ordering Quantity ADuC7023BCP6Z62I 12 4 62 kB/8 kB 20 I 2C −40°C to +125°C 40-Lead LFCSP CP-40-10 490 ADuC7023BCP6Z62IRL 12 4 62 kB/8 kB 20 I 2C −40°C to +125°C 40-Lead LFCSP CP-40-10 2,500 ADuC7023BCP6Z62IR7 12 4 62 kB/8 kB 20 I 2C −40°C to +125°C 40-Lead LFCSP CP-40-10 750 ADuC7023BCPZ62I 6 4 62 kB/8 kB 12 I 2C −40°C to +125°C 32-Lead LFCSP_ CP-32-11 490 ADuC7023BCPZ62I-RL 6 4 62 kB/8 kB 12 I 2C −40°C to +125°C 32-Lead LFCSP CP-32-11 5,000 ADuC7023BCPZ62I-R7 6 4 62 kB/8 kB 12 I 2C −40°C to +125°C 32-Lead LFCSP CP-32-11 1,500 ADuC7023BCBZ62I-R7 10 4 62 kB/8 kB 16 I 2C −40°C to +125°C 36-Ball WLCSP CB-36-03 1,500 EVAL-ADuC7023QSPZ ADuC7023 QuickStart Plus Development System Using 32-Pin ADuC7023 EVAL-ADuC7023QSPZ1 ADuC7023 QuickStart Plus Development System Using 40-Pin ADuC7023 EVAL-ADuC7023QSPZ2 ADuC7023 QuickStart Plus Development System Using 36-Ball ADuC7023 1 Z = RoHS Compliant Part.

Rev. H | Page 98 of 98 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08675-11/20(H)