ADuC7022BCPZ32

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Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005-2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Multichannel, 12-bit, 1 MSPS ADC Up to 16 ADC channels1 Fully differential and single-ended modes

0 V to VREF analog input range

12-bit voltage output DACs Up to 4 DAC outputs available1 On-chip voltage reference On-chip temperature sensor (±3°C) Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 44 MHz

41.78 MHz PLL with programmable divider

62 kB Flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug Software-triggered in-circuit reprogrammability On-chip peripherals UART, 2× I2C® and SPI serial I/O Up to 40-pin GPIO port1 4× general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor 3-phase, 16-bit PWM generator1 Programmable logic array (PLA) External memory interface, up to 512 kB1 Power Specified for 3 V operation Active mode: 11 mA @ 5 MHz, 40 mA @ 41.78 MHz Packages and temperature range From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP1 Fully specified for –40°C to +125°C operation Tools Low cost QuickStart™ development system Full third-party support

APPLICATIONS

Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking FUNCTIONAL BLOCK DIAGRAM 1MSPS 12-BIT ADC DAC012-BIT DAC DAC1 DAC2 3-PHASE PWM (SEE NOTE 1) ADuC7019 ADC0 TO ADC4, ADC12 TO ADC14 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA

4 GENERAL-

2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 12-BIT DAC 12-BIT DAC NOTES 1. SEE APPLICATION NOTE AN-798. ADC15 04955-100 Figure 1. 1 Depending on part model. See Ordering Guide for more information.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 2 of 104 TABLE OF CONTENTS

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 3 of 104

REVISION HISTORY

5/13—Rev. E to Rev. F Added Table 83, Figure 73, Figure 74, Following Text, and 7/12—Rev. D to Rev. E Changed SCLOCK to SCLK When Refering to SPI Clock, SPIMISO to MISO when Refering to SPI MISO, SPIMOSI to MOSI when Refering to SPI MOSI, and SPICSL to CS when Changes to Example Source Code (External Crystal Selection) Section and Example Source Code (External Clock Selection) Changes to SPICON[10] and SPICON[9] Descriptions in Changes to Timer Interval Down Equation and Added Timer 5/11—Rev. C to Rev. D 12/09—Rev. B to Rev. C 3/07—Rev. A to Rev. B 1/06—Rev. 0 to Rev. A 10/05—Revision 0: Initial Version

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 4 of 104 GENERAL DESCRIPTION The ADuC7019/20/21/22/24/25/26/27/28/29 are fully integrated,

1 MSPS, 12-bit data acquisition systems incorporating high

performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash®/EE memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional four inputs are available but are multiplexed with the four DAC output pins. The four DAC outputs are available only on certain models (ADuC7020, ADuC7026, ADuC7028, and ADuC7029). However, in many cases where the DAC outputs are not present, these pins can still be used as additional ADC inputs, giving a maximum of 16 ADC input channels. The ADC can operate in single-ended or differential input mode. The ADC input voltage is 0 V to VREF. A low drift band gap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. Depending on the part model, up to four buffered voltage output DACs are available on-chip. The DAC output range is programmable to one of three voltage ranges. The devices operate from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz (UCLK). This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI®, 16-bit/32-bit RISC machine, which offers up to 41 MIPS peak performance. Eight kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE memory are provided on-chip. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the UART or I 2C serial interface port; nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting this MicroConverter® family. The parts operate from 2.7 V to 3.6 V and are specified over an industrial temperature range of −40°C to +125°C. When operating at 41.78 MHz, the power dissipation is typically 120 mW . The ADuC7019/20/21/22/24/25/26/27/28/29 are available in a variety of memory models and packages (see Ordering Guide). 1MSPS 12-BIT ADC DAC012-BIT DAC DAC1 DAC2 DAC3 3-PHASE PWM (SEE NOTE 1) ADuC7020 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 12-BIT DAC 12-BIT DAC 12-BIT DAC NOTES 1. SEE APPLICATION NOTE AN-798. 04955-101 ADC0 TO ADC4, ADC12 TO ADC15 Figure 2.

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 5 of 104 1MSPS 12-BIT ADC DAC012-BIT DAC DAC1 3-PHASE PWM (SEE NOTE 1) ADuC7021 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 12-BIT DAC NOTES 1. SEE APPLICATION NOTE AN-798. 04955-102 ADC0 TO ADC7, ADC12 TO ADC13 Figure 3. 1MSPS 12-BIT ADC 3-PHASE PWM (SEE NOTE 1) ADuC7022 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS NOTES 1. SEE APPLICATION NOTE AN-798. 04955-103 ADC0 TO ADC9 Figure 4.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 6 of 104 1MSPS 12-BIT ADC DAC012-BIT DAC DAC1 PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L 3-PHASE PWM (SEE NOTE 1) ADuC7024 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 12-BIT DAC NOTES 1. SEE APPLICATION NOTE AN-798. 04955-104 ADC0 TO ADC9, ADC12, ADC13 Figure 5. 1MSPS 12-BIT ADC PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L 3-PHASE PWM (SEE NOTE 1) ADuC7025 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS NOTES 1. SEE APPLICATION NOTE AN-798. 04955-105 ADC0 TO ADC9, ADC12, ADC13 Figure 6.

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 7 of 104 1MSPS 12-BIT ADC DAC012-BIT DAC DAC1 DAC2 DAC3 PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L 3-PHASE PWM EXT. MEMORY INTERFACE ADuC7026 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 12-BIT DAC 12-BIT DAC 12-BIT DAC 04955-106 ADC0 TO ADC15 Figure 7. 1MSPS 12-BIT ADC PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L 3-PHASE PWM EXT. MEMORY INTERFACE ADuC7027 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 04955-107 ADC0 TO ADC15 Figure 8.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 8 of 104 1MSPS 12-BIT ADC DAC012-BIT DAC DAC1 DAC2 DAC3 PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L 3-PHASE PWM ADuC7028 XCLKI XCLKO RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 12-BIT DAC 12-BIT DAC 12-BIT DAC 04955-108 ADC0 TO ADC7, ADC12 TO ADC15 Figure 9. 1MSPS 12-BIT ADC DAC012-BIT DAC DAC1 DAC2 DAC3 PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L 3-PHASE PWM ADuC7029 RST VREF MUX TEMP SENSOR BAND GAP REF OSC AND PLL PSM POR CMP0 CMP1 CMPOUT PLA 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO JTAG ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 12-BIT DAC 12-BIT DAC 12-BIT DAC 04955-109 ADC0 TO ADC6, ADC12 TO ADC15 Figure 10.

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 9 of 104 DETAILED BLOCK DIAGRAM 04955-002 77ADC0 78ADC1 79ADC2/CMP0 80ADC3/CMP1 1ADC4 2ADC5 3ADC6 4ADC7 5ADC8 6ADC9 7ADC10 76ADC11 9ADCNEG 20BM/P0.0/CMPOUT/PLAI[7]/MS0 18P4.6/AD14/PLAO[14] 19P4.7/AD15/PLAO[15] * SEE ORDERING GUIDE FOR FEATURE AVAILABILITY ON DIFFERENT MODELS. P4.0/AD8/PLAO[8] P4.1/AD9/PLAO[9] P4.2/AD10/PLAO[10] P4.3/AD11/PLAO[11] P4.4/AD12/PLAO[12] P4.5/AD13/PLAO[13] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] TMS TDI TDO TCK P0.6/T1/MRST/PLAO[3] P2.1/WS/PWM0H/PLAO[6] P2.2/RS/PWM0L/PLAO[7] P2.3/AE P2.4/PWM0H/MS0 P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 P2.7/PWM1L/MS3 P0.2/PWM2L/BHE P0.1/PWM2H/BLE P0.3/TRST/A16/ADCBUSY P2.0/SPM9/PLAO[5]/CONVSTART P1.7/SPM7/PLAO[0] MUX 12-BIT VOLTAGE OUTPUT DAC BUF 10 DAC0*/ADC12 12-BIT VOLTAGE OUTPUT DAC BUF 11 DAC1*/ADC13 12-BIT VOLTAGE OUTPUT DAC BUF 12 DAC2*/ADC14 12-BIT VOLTAGE OUTPUT DAC BUF 13 DAC3*/ADC15 29 P3.0/AD0/PWM0H/PLAI[8] 30 P3.1/AD1/PWM0L/PLAI[9] 31 P3.2/AD2/PWM1H/PLAI[10] 32 P3.3/AD3/PWM1L/PLAI[11] 38 P3.4/AD4/PWM2H/PLAI[12] 39 P3.5/AD5/PWM2L/PLAI[13] 46 P3.6/AD6/PWMTRIP/PLAI[14] 47 P3.7/AD7/PWMSYNC/PLAI[15]

44 XCLKO

45 XCLKI

40 IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 41 IRQ1/P0.5/ADCBUSY/PLAO[2]/MS2 43 P0.7/ECLK/XCLK/SPM8/PLAO[4] ADuC7026* DACREF DACGND DACVDD RST LVDD DGND IOVDD IOGND IOVDD IOGND AVDD AVDD REFGND AGND AGND

8 GNDREF

(31k × 16 BITS)

8192 BYTES USER RAM

(2k × 32 BITS) WAKE-UP/ RTC TIMER POWER SUPPLY MONITOR PROG. CLOCK DIVIDER JTAG EMULATOR DOWNLOADER PROG. LOGIC ARRAY SPI/I2C SERIAL INTERFACE SERIAL PORT MULTIPLEXER UART SERIAL PORT POR INTERRUPT CONTROLLER 12-BIT SAR ADC 1MSPS ADC CONTROL PLL OSC

68 VREFVREF

Figure 11.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 10 of 104 SPECIFICATIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and fADC/2 ADC Power-Up Time 5 μs DC Accuracy1, 2 Resolution 12 Bits Integral Nonlinearity ±0.6 ±1.5 LSB 2.5 V internal reference ±1.0 LSB 1.0 V external reference Differential Nonlinearity3, 4 ±0.5 +1/−0.9 LSB 2.5 V internal reference +0.7/−0.6 LSB 1.0 V external reference DC Code Distribution 1 LSB ADC input is a dc voltage ENDPOINT ERRORS5 Offset Error ±1 ±2 LSB Offset Error Match ±1 LSB Gain Error ±2 ±5 LSB Gain Error Match ±1 LSB DYNAMIC PERFORMANCE fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS Signal-to-Noise Ratio (SNR) 69 dB Includes distortion and noise components Total Harmonic Distortion (THD) −78 dB Peak Harmonic or Spurious Noise (PHSN) −75 dB Channel-to-Channel Crosstalk −80 dB Measured on adjacent channels ANALOG INPUT Input Voltage Ranges Differential Mode VCM6 ± VREF/2 V Single-Ended Mode 0 to VREF V Leakage Current ±1 ±6 µA Input Capacitance 20 pF During ADC acquisition ON-CHIP VOLTAGE REFERENCE 0.47 µF from VREF to AGND Output Voltage 2.5 V Accuracy ±5 mV TA = 25°C Reference Temperature Coefficient ±40 ppm/°C Power Supply Rejection Ratio 75 dB Output Impedance 70 Ω TA = 25°C Internal VREF Power-On Time 1 ms EXTERNAL REFERENCE INPUT Input Voltage Range 0.625 AVDD V DAC CHANNEL SPECIFICATIONS RL = 5 kΩ, CL = 100 pF DC Accuracy7 Resolution 12 Bits Relative Accuracy ±2 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Offset Error ±15 mV 2.5 V internal reference Gain Error8 ±1 % Gain Error Mismatch 0.1 % % of full scale on DAC0 ANALOG OUTPUTS Output Voltage Range_0 0 to DACREF V DACREF range: DACGND to DACVDD Output Voltage Range_1 0 to 2.5 V Output Voltage Range_2 0 to DACVDD V Output Impedance 2 Ω

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 11 of 104 Parameter Min Typ Max Unit Test Conditions/Comments DAC AC CHARACTERISTICS Voltage Output Settling Time 10 µs Digital-to-Analog Glitch Energy ±20 nV-sec 1 LSB change at major carry (where maximum number of bits simultaneously changes in the DACxDAT register) COMPARATOR Input Offset Voltage ±15 mV Input Bias Current 1 µA Input Voltage Range AGND AVDD − 1.2 V Input Capacitance 7 pF Hysteresis4, 6 2 15 mV Hysteresis turned on or off via the CMPHYST bit in the CMPCON register Response Time 3 µs 100 mV overdrive and configured with CMPRES = 11 TEMPERATURE SENSOR Voltage Output at 25°C 780 mV Voltage TC −1.3 mV/°C Accuracy ±3 °C POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection 2.79 V Two selectable trip points 3.07 V Power Supply Trip Point Accuracy ±2.5 % Of the selected nominal trip point voltage POWER-ON-RESET 2.36 V GLITCH IMMUNITY ON RESET PIN4 50 µs WATCHDOG TIMER (WDT) Timeout Period 0 512 sec FLASH/EE MEMORY Endurance9 10,000 Cycles Data Retention10 20 Years TJ = 85°C DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO Logic 1 Input Current ±0.2 ±1 µA VIH = IOVDD or VIH = 5 V Logic 0 Input Current −40 −60 µA VIL = 0 V; except TDI on ADuC7019/20/21/22/24/25/29 −80 −120 µA VIL = 0 V; TDI on ADuC7019/20/21/22/24/25/29 Input Capacitance 10 pF LOGIC INPUTS3 All logic inputs excluding XCLKI VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 2.0 V LOGIC OUTPUTS All digital outputs excluding XCLKO VOH, Output High Voltage 2.4 V ISOURCE = 1.6 mA VOL, Output Low Voltage11 0.4 V ISINK = 1.6 mA CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage 1.1 V VINH, Input High Voltage 1.7 V XCLKI Input Capacitance 20 pF XCLKO Output Capacitance 20 pF INTERNAL OSCILLATOR 32.768 kHz ±3 % ±24 % TA = 0°C to 85°C range

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 12 of 104 Parameter Min Typ Max Unit Test Conditions/Comments MCU CLOCK RATE From 32 kHz Internal Oscillator 326 kHz CD12 = 7 From 32 kHz External Crystal 41.78 MHz CD12 = 0 Using an External Clock 0.05 44 MHz TA = 85°C 0.05 41.78 MHz TA = 125°C START-UP TIME Core clock = 41.78 MHz At Power-On 130 ms From Pause/Nap Mode 24 ns CD12 = 0 3.06 µs CD12 = 7 From Sleep Mode 1.58 ms From Stop Mode 1.7 ms PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay 12 ns From input pin to output pin Element Propagation Delay 2.5 ns POWER REQUIREMENTS13, 14 Power Supply Voltage Range AVDD to AGND and IOVDD to IOGND 2.7 3.6 V Analog Power Supply Currents AVDD Current 200 µA ADC in idle mode; all parts except ADuC7019 400 µA ADC in idle mode; ADuC7019 only DACVDD Current15 3 25 µA Digital Power Supply Current IOVDD Current in Normal Mode Code executing from Flash/EE 7 10 mA CD12 = 7 11 15 mA CD12 = 3 40 45 mA CD12 = 0 (41.78 MHz clock) IOVDD Current in Pause Mode 25 30 mA CD12 = 0 (41.78 MHz clock) IOVDD Current in Sleep Mode 250 400 µA TA = 85°C 600 1000 µA TA = 125°C Additional Power Supply Currents ADC 2 mA @ 1 MSPS 0.7 mA @ 62.5 kSPS DAC 700 µA per DAC ESD TESTS 2.5 V reference, TA = 25°C HBM Passed Up To 4 kV FCIDM Passed Up To 0.5 kV 1 All ADC channel specifications are guaranteed during normal MicroConverter core operation. 2 Apply to all ADC input channels. 3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN). 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 59. Based on external ADC system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 DAC linearity is calculated using a reduced code range of 100 to 3995. 8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 9 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 10 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature. 11 Test carried out with a maximum of eight I/Os set to a low output level. 12 See the POWCON register. 13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with 3.6 V supply, and sleep mode with 3.6 V supply. 14 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle. 15 On the ADuC7019/20/21/22, this current must be added to the AVDD current.

Table 2. External Memory Write Cycle Figure 12. External Memory Write Cycle (See Table 78)

Table 3. External Memory Read Cycle Figure 13. External Memory Read Cycle (See Table 78)

Table 4. I2C Timing in Fast Mode (400 kHz) 1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 67. Table 5. I2C Timing in Standard Mode (100 kHz) 1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 67. Figure 14. I2C Compatible Interface Timing

Table 6. SPI Master Mode Timing (Phase Mode = 1) 1 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67. 2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67. Figure 15. SPI Master Mode Timing (Phase Mode = 1)

Table 7. SPI Master Mode Timing (Phase Mode = 0) 1 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67. 2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67. Figure 16. SPI Master Mode Timing (Phase Mode = 0)

Table 8. SPI Slave Mode Timing (Phsae Mode = 1) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67. 2 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67. Figure 17. SPI Slave Mode Timing (Phase Mode = 1)

Table 9. SPI Slave Mode Timing (Phase Mode = 0) 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67. 2 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 67. Figure 18. SPI Slave Mode Timing (Phase Mode = 0)

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 20 of 104 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GNDREF, TA = 25°C, unless otherwise noted. Table 10. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION Parameter Rating AVDD to IOVDD −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V IOVDD to IOGND, AVDD to AGND −0.3 V to +6 V Digital Input Voltage to IOGND −0.3 V to +5.3 V Digital Output Voltage to IOGND −0.3 V to IOVDD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.3 V Analog Inputs to AGND −0.3 V to AVDD + 0.3 V Analog Outputs to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range, Industrial –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 40-Lead LFCSP 26°C/W 49-Ball CSP_BGA 80°C/W 64-Lead LFCSP 24°C/W 64-Ball CSP_BGA 75°C/W 64-Lead LQFP 47°C/W 80-Lead LQFP 38°C/W Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) 240°C RoHS Compliant Assemblies (20 sec to 40 sec) 260°C

Table 11. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022) 38 37 36 ADC0 Single-Ended or Differential Analog Input 0. 39 38 37 ADC1 Single-Ended or Differential Analog Input 1. 40 39 38 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input. 2 1 40 ADC4 Single-Ended or Differential Analog Input 4. ‒ 2 1 ADC5 Single-Ended or Differential Analog Input 5. ‒ 3 2 ADC6 Single-Ended or Differential Analog Input 6. ‒ 4 3 ADC7 Single-Ended or Differential Analog Input 7. ‒ ‒ 4 ADC8 Single-Ended or Differential Analog Input 8. ‒ ‒ 5 ADC9 Single-Ended or Differential Analog Input 9. analog power supply should be separated from IOGND and DGND. 4 6 ‒ DAC0/ADC12 DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. 5 7 ‒ DAC1/ADC13 DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. 6 ‒ ‒ DAC2/ADC14 DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. Differential Analog Input 15 (see Figure 53). 8 8 7 TMS Test Mode Select, JTAG Test Port Input. Debug and download access. 9 9 8 TDI Test Data In, JTAG Test Port Input. Debug and download access. 13 13 12 TDO Test Data Out, JTAG Test Port Output. Debug and download access. 14 14 13 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. connected to a 0.47 µF capacitor to DGND only. 17 17 16 DGND Ground for Core Logic. 19 19 18 RST Reset Input, Active Low. Logic Array Output Element 1. Logic Array Output Element 2.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 24 of 104 Pin No. 7019/7020 7021 7022 Mnemonic Description 22 22 21 P2.0/SPM9/PLAO[5]/CONVSTART Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/ Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. 23 23 22 P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/ Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/ Programmable Logic Array Output Element 4. 24 24 23 XCLKO Output from the Crystal Oscillator Inverter. 25 25 24 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. 26 26 25 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. 27 27 26 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. 28 28 27 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. 29 29 28 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. 30 30 29 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. 31 31 30 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. 32 32 31 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. 33 33 32 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/ Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. 34 ‒ ‒ P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. 35 34 33 VREF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the internal reference. 36 35 34 AGND Analog Ground. Ground reference point for the analog circuitry. 37 36 35 AVDD 3.3 V Analog Power. 0 0 0 EP Exposed Pad. The pin configuration for the ADuC7019/ADuC7020/ ADuC7021/ADuC7022 has an exposed pad that must be soldered for mechanical purposes and left unconnected.

42 IOVDD

41 IOGND

36 XCLKI

35 XCLKO

64 ADC3/CMP1

63 ADC2/CMP0

62 ADC1

61 ADC0

60 DACVDD

59 AVDD

58 AGND

57 DACGND

56 DACREF

55 VREF

1. THE EXPOSED PAD MUST BE SOLDERED FOR MECHANICAL PURPOSES AND LEFT UNCONNECTED.

Figure 23. 64-Lead LFCSP_VQ Pin Configuration (ADuC7024/ADuC7025) Figure 24. 64-Lead LQFP Pin Configuration (ADuC7024/ADuC7025)

Table 12. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead LFCSP_VQ and 64-Lead LQFP) 1 ADC4 Single-Ended or Differential Analog Input 4. 2 ADC5 Single-Ended or Differential Analog Input 5. 3 ADC6 Single-Ended or Differential Analog Input 6. 4 ADC7 Single-Ended or Differential Analog Input 7. 5 ADC8 Single-Ended or Differential Analog Input 8. 6 ADC9 Single-Ended or Differential Analog Input 9. should be separated from IOGND and DGND. to the ground of the signal to convert. This bias point must be between 0 V and 1 V. 11 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. 13 P4.6/PLAO[14] General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14. 14 P4.7/PLAO[15] General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15. and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. On Reset Output/Programmable Logic Array Output Element 3. 17 TCK JTAG Test Port Input, Test Clock. Debug and download access. 18 TDO JTAG Test Port Output, Test Data Out. Debug and download access. 19 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. 20 IOVDD 3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator. 22 DGND Ground for Core Logic. 27 P0.3/TRST/ADCBUSY General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. 28 RST Reset Input, Active Low. Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2. Array Output Element 5/Start Conversion Input Signal for ADC. 35 XCLKO Output from the Crystal Oscillator Inverter. 36 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 27 of 104 Pin No. Mnemonic Description 37 P3.6/PWMTRIP/PLAI[14] General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array Input Element 14. 38 P3.7/PWMSYNC/PLAI[15] General-Purpose Input and Output Port 3.7/PWM Synchronization Input and Output/ Programmable Logic Array Input Element 15. 39 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. 40 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. 41 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. 42 IOVDD 3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator. 43 P4.0/PLAO[8] General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8. 44 P4.1/PLAO[9] General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9. 45 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. 46 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. 47 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. 48 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. 49 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. 50 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/ Programmable Logic Array Input Element 0. 51 P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. 52 P4.3/PLAO[11] General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11. 53 P4.4/PLAO[12] General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12. 54 P4.5/PLAO[13] General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13. 55 VREF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the internal reference. 56 DACREF External Voltage Reference for the DACs. Range: DACGND to DACVDD. 57 DACGND Ground for the DAC. Typically connected to AGND. 58 AGND Analog Ground. Ground reference point for the analog circuitry. 59 AVDD 3.3 V Analog Power. 60 DACVDD 3.3 V Power Supply for the DACs. Must be connected to AVDD. 61 ADC0 Single-Ended or Differential Analog Input 0. 62 ADC1 Single-Ended or Differential Analog Input 1. 63 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input. 64 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input. 0 EP Exposed Pad. The pin configuration for the ADuC7024/ADuC7025 LFCSP_VQ has an exposed pad that must be soldered for mechanical purposes and left unconnected.

54 IOVDD

53 IOGND

80 ADC3/CMP1

79 ADC2/CMP0

78 ADC1

77 ADC0

76 ADC11

75 DACVDD

74 AVDD

73 AVDD

72 AGND

71 AGND

70 DACGND

69 DACREF

68 VREF

67 REFGND

Figure 25. 80-Lead LQFP Pin Configuration (ADuC7026/ADuC7027) Table 13. Pin Function Descriptions (ADuC7026/ADuC7027) 1 ADC4 Single-Ended or Differential Analog Input 4. 2 ADC5 Single-Ended or Differential Analog Input 5. 3 ADC6 Single-Ended or Differential Analog Input 6. 4 ADC7 Single-Ended or Differential Analog Input 7. 5 ADC8 Single-Ended or Differential Analog Input 8. 6 ADC9 Single-Ended or Differential Analog Input 9. 7 ADC10 Single-Ended or Differential Analog Input 10. should be separated from IOGND and DGND. to the ground of the signal to convert. This bias point must be between 0 V and 1 V. 14 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. 15 TDI JTAG Test Port Input, Test Data In. Debug and download access. 17 P2.3/AE General-Purpose Input and Output Port 2.3/External Memory Access Enable.

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 29 of 104 Pin No. Mnemonic Description 18 P4.6/AD14/PLAO[14] General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic Array Output Element 14. 19 P4.7/AD15/PLAO[15] General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic Array Output Element 15. 20 BM/P0.0/CMPOUT/PLAI[7]/MS0 Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if BM is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/General- Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7/External Memory Select 0. 21 P0.6/T1/MRST/PLAO[3] Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/ Power-On Reset Output/Programmable Logic Array Output Element 3. 22 TCK JTAG Test Port Input, Test Clock. Debug and download access. 23 TDO JTAG Test Port Output, Test Data Out. Debug and download access. 24 P0.2/PWM2L/BHE General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory Byte High Enable. 25 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. 26 IOVDD 3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator. 27 LVDD 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF capacitor to DGND only. 28 DGND Ground for Core Logic. 29 P3.0/AD0/PWM0H/PLAI[8] General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 High-Side Output/Programmable Logic Array Input Element 8. 30 P3.1/AD1/PWM0L/PLAI[9] General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 Low-Side Output/Programmable Logic Array Input Element 9. 31 P3.2/AD2/PWM1H/PLAI[10] General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 High-Side Output/Programmable Logic Array Input Element 10. 32 P3.3/AD3/PWM1L/PLAI[11] General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 Low-Side Output/Programmable Logic Array Input Element 11. 33 P2.4/PWM0H/MS0 General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory Select 0. 34 P0.3/TRST/A16/ADCBUSY General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. 35 P2.5/PWM0L/MS1 General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory Select 1. 36 P2.6/PWM1H/MS2 General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory Select 2. 37 RST Reset Input, Active Low. 38 P3.4/AD4/PWM2H/PLAI[12] General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 High-Side Output/Programmable Logic Array Input 12. 39 P3.5/AD5/PWM2L/PLAI[13] General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 Low-Side Output/Programmable Logic Array Input Element 13. 40 IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1/ External Memory Select 1. 41 IRQ1/P0.5/ADCBUSY/PLAO[2]/MS2 Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2/External Memory Select 2. 42 P2.0/SPM9/PLAO[5]/CONVSTART Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. 43 P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output Element 4. 44 XCLKO Output from the Crystal Oscillator Inverter. 45 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 30 of 104 Pin No. Mnemonic Description 46 P3.6/AD6/PWM TRIP/PLAI[14] General-Purpose Input and Output Port 3.6/External Memory Interface/PWM Safety Cutoff/ Programmable Logic Array Input Element 14. 47 P3.7/AD7/PWM SYNC/PLAI[15] General-Purpose Input and Output Port 3.7/External Memory Interface/PWM Synchronization/ Programmable Logic Array Input Element 15. 48 P2.7/PWM1 L/MS3 General-Purpose Input and Output Port 2.7/PWM Phase 1 Low-Side Output/External Memory Select 3. 49 P2.1/WS/PWM0H/PLAO[6] General-Purpose Input and Output Port 2.1/ External Memory Write Strobe/PWM Phase 0 High- Side Output/Programmable Logic Array Output Element 6. 50 P2.2/RS/PWM0L/PLAO[7] General-Purpose Input and Output Port 2. 2/External Memory Read Strobe/PWM Phase 0 Low- Side Output/Programmable Logic Array Output Element 7. 51 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. 52 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. 53 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. 54 IOV DD 3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator. 55 P4.0/AD8/PLAO[8] General-Purpose Input and Output Port 4.0/External Memory Interface/Programmable Logic Array Output Element 8. 56 P4.1/AD9/PLAO[9] General-Purpose Input and Output Port 4.1/External Memory Interface/Programmable Logic Array Output Element 9. 57 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. 58 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. 59 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. 60 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. 61 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. 62 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/ Programmable Logic Array Input Element 0. 63 P4.2/AD10/PLAO[10] General-Purpose Input and Output Port 4.2/External Memory Interface/Programmable Logic Array Output Element 10. 64 P4.3/AD11/PLAO[11] General-Purpose Input and Output Port 4.3/External Memory Interface/Programmable Logic Array Output Element 11. 65 P4.4/AD12/PLAO[12] General-Purpose Input and Output Port 4.4/External Memory Interface/Programmable Logic Array Output Element 12. 66 P4.5/AD13/PLAO[13] General-Purpose Input and Output Port 4.5/External Memory Interface/Programmable Logic Array Output Element 13. 67 REFGND Ground for the Reference. Typically connected to AGND. 68 V REF 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. 69 DAC REF External Voltage Reference for the DACs. Range: DACGND to DACVDD. 70 DACGND Ground for the DAC. Typically connected to AGND. 71, 72 AGND Analog Ground. Ground reference point for the analog circuitry. 73, 74 AV DD 3.3 V Analog Power. 75 DACV DD 3.3 V Power Supply for the DACs. Must be connected to AVDD. 76 ADC11 Single-Ended or Differential Analog Input 11. 77 ADC0 Single-Ended or Differential Analog Input 0. 78 ADC1 Single-Ended or Differential Analog Input 1. 79 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input. 80 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.

Figure 26. 64-Ball CSP_BGA Pin Configuration (ADuC7028) Table 14. Pin Function Descriptions (ADuC7028) A1 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input. A2 DACVDD 3.3 V Power Supply for the DACs. Must be connected to AVDD. A4 AGND Analog Ground. Ground reference point for the analog circuitry. A5 DACGND Ground for the DAC. Typically connected to AGND. A6 P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. Logic Array Input Element 1. Logic Array Input Element 2. B1 ADC4 Single-Ended or Differential Analog Input 4. B2 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input. B3 ADC1 Single-Ended or Differential Analog Input 1. B4 DACREF External Voltage Reference for the DACs. Range: DACGND to DACVDD. Programmable Logic Array Input Element 0. Logic Array Input Element 4/External Interrupt Request 2, Active High. Logic Array Input Element 3. C1 ADC6 Single-Ended or Differential Analog Input 6. C2 ADC5 Single-Ended or Differential Analog Input 5. C3 ADC0 Single-Ended or Differential Analog Input 0. C4 P4.5/PLAO[13] General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13. C5 P4.3/PLAO[11] General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11. C6 P4.0/PLAO[8] General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8. C7 P4.1/PLAO[9] General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9. C8 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. should be separated from IOGND and DGND. D3 ADC7 Single-Ended or Differential Analog Input 7. D4 P4.4/PLAO[12] General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12. Logic Array Output Element 0.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 32 of 104 Ball No. Mnemonic Description D7 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. D8 IOVDD 3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator. E1 DAC3/ADC15 DAC3 Voltage Output/ADC Input 15. E2 DAC2/ADC14 DAC2 Voltage Output/ADC Input 14. E3 DAC1/ADC13 DAC1 Voltage Output/ADC Input 13. E4 P3.0/PWM0H/PLAI[8] General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable Logic Array Input Element 8. E5 P3.2/PWM1H/PLAI[10] General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable Logic Array Input Element 10. E6 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. E7 P3.7/PWMSYNC/PLAI[15] General-Purpose Input and Output Port 3.7/PWM Synchronization/Programmable Logic Array Input Element 15. E8 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. F1 P4.6/PLAO[14] General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14. F2 TDI JTAG Test Port Input, Test Data In. Debug and download access. F3 DAC0/ADC12 DAC0 Voltage Output/ADC Input 12. F4 P3.1/PWM0L/PLAI[9] General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable Logic Array Input Element 9. F5 P3.3/PWM1L/PLAI[11] General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable Logic Array Input Element 11. F6 RST Reset Input, Active Low. F7 P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output Element 4. F8 XCLKO Output from the Crystal Oscillator Inverter. G1 BM/P0.0/CMPOUT/PLAI[7] Multifunction I/O Pin. Boot mode. The ADuC7028 enters UART download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/General- Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. G2 P4.7/PLAO[15] General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15. G3 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. G4 TDO JTAG Test Port Output, Test Data Out. Debug and download access. G5 P0.3/TRST/ADCBUSY General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. G6 P3.4/PWM2H/PLAI[12] General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable Logic Array Input 12. G7 P3.5/PWM2L/PLAI[13] General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable Logic Array Input Element 13. G8 P2.0/SPM9/PLAO[5]/CONVSTART Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. H1 P0.6/T1/MRST/PLAO[3] Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/ Power-On Reset Output/Programmable Logic Array Output Element 3. H2 TCK JTAG Test Port Input, Test Clock. Debug and download access. H3 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. H4 IOVDD 3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator. H5 LVDD 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF capacitor to DGND only. H6 DGND Ground for Core Logic. H7 IRQ0/P0.4/PWMTRIP/PLAO[1] Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. H8 IRQ1/P0.5/ADCBUSY/PLAO[2] Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.

Figure 27. 49-Ball CSP_BGA Pin Configuration (ADuC7029) Table 15. Pin Function Descriptions (ADuC7029) A1 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input. A2 ADC1 Single-Ended or Differential Analog Input 1. A3 ADC0 Single-Ended or Differential Analog Input 0. Programmable Logic Array Input Element 0. Logic Array Input Element 1. B1 ADC6 Single-Ended or Differential Analog Input 6. B2 ADC5 Single-Ended or Differential Analog Input 5. B3 ADC4 Single-Ended or Differential Analog Input 4. B4 AGND Analog Ground. Ground reference point for the analog circuitry. B5 DACREF External Voltage Reference for the DACs. Range: DACGND to DACVDD. Logic Array Input Element 4/External Interrupt Request 2, Active High. Logic Array Input Element 3. should be separated from IOGND and DGND. C2 AGND Analog Ground. Ground reference point for the analog circuitry. C3 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input. C4 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. Logic Array Input Element 2. Logic Array Input Element 6. Logic Array Input Element 5/External Interrupt Request 3, Active High. D1 DAC0/ADC12 DAC0 Voltage Output/ADC Input 12. D2 DAC3/ADC15 DAC3 Voltage Output/ADC Input 15. D3 DAC1/ADC13 DAC1 Voltage Output/ADC Input 13. Logic Array Input Element 11. Logic Array Output Element 0.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 34 of 104 Ball No. Mnemonic Description E1 TMS JTAG Test Port Input, Test Mode Select. Debug and download access. E2 BM/P0.0/CMPOUT/PLAI[7] Multifunction I/O Pin. Boot mode. The ADuC7029 enters UART download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/General- Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. E3 DAC2/ADC14 DAC2 Voltage Output/ADC Input 14. E4 IOVDD 3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator. E5 P3.2/PWM1H/PLAI[10] General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable Logic Array Input Element 10. E6 P3.5/PWM2L/PLAI[13] General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable Logic Array Input Element 13. E7 P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output Element 4. F1 TDI JTAG Test Port Input, Test Data In. Debug and download access. F2 P0.6/T1/MRST/PLAO[3] Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/ Power-On Reset Output/Programmable Logic Array Output Element 3. F3 IOGND Ground for GPIO (see Table 78). Typically connected to DGND. F4 P3.1/PWM0L/PLAI[9] General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable Logic Array Input Element 9. F5 P3.0/PWM0H/PLAI[8] General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable Logic Array Input Element 8. F6 RST Reset Input, Active Low. F7 P2.0/SPM9/PLAO[5]/CONVSTART Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. G1 TCK JTAG Test Port Input, Test Clock. Debug and download access. G2 TDO JTAG Test Port Output, Test Data Out. Debug and download access. G3 LVDD 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF capacitor to DGND only. G4 DGND Ground for Core Logic. G5 P0.3/TRST/ADCBUSY General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. G6 IRQ0/P0.4/PWMTRIP/PLAO[1] Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. G7 IRQ1/P0.5/ADCBUSY/PLAO[2] Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 38 of 104 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale − 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio (SINAD) The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes the output to settle to within a 1 LSB level for a full-scale input change.

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 40 of 104 More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following materials from ARM:

• DDI0029G, ARM7TDMI Technical Reference Manual
• DDI-0100, ARM Architecture Reference Manual INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following:
• The longest time the request can take to pass through the synchronizer
• The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC
• The time for the data abort entry
• The time for FIQ entry At the end of this time, the ARM7TDMI executes the instruc- tion at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 µs in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar but must allow for the fact that FIQ has higher priority and may delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in thumb mode where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.

Figure 45. Physical Memory Map and the most significant byte is in the highest byte address.

32 BITS

Figure 46. Little Endian Format on-chip kernel. The page size of this Flash/EE memory is 512 bytes. executing from Flash/EE memory for optimum access speed. 41.78 MHz in thumb mode and 20.89 MHz in full ARM mode. Execution Time from SRAM and Flash/EE section. addressing through the ARM7 banked registers. user software. Table 16 shows the full MMR memory map.

Figure 47. Memory Mapped Registers Table 16. Complete MMR List

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 43 of 104 Address Name Byte Access Type Default Value Page Reference Address Base = 0xFFFF0480 0x048C REFCON 1 R/W 0x00 50 ADC Address Base = 0xFFFF0500 0x0500 ADCCON 2 R/W 0x0600 46 0x0504 ADCCP 1 R/W 0x00 47 0x0508 ADCCN 1 R/W 0x01 47 0x050C ADCSTA 1 R 0x00 48 0x0510 ADCDAT 4 R 0x00000000 48 0x0514 ADCRST 1 R/W 0x00 48 0x0530 ADCGN 2 R/W 0x0200 48 0x0534 ADCOF 2 R/W 0x0200 48 DAC Address Base = 0xFFFF0600 0x0600 DAC0CON 1 R/W 0x00 56 0x0604 DAC0DAT 4 R/W 0x00000000 56 0x0608 DAC1CON 1 R/W 0x00 56 0x060C DAC1DAT 4 R/W 0x00000000 56 0x0610 DAC2CON 1 R/W 0x00 56 0x0614 DAC2DAT 4 R/W 0x00000000 56 0x0618 DAC3CON 1 R/W 0x00 56 0x061C DAC3DAT 4 R/W 0x00000000 56 UART Base Address = 0xFFFF0700 0x0700 COMTX 1 R/W 0x00 71 COMRX 1 R 0x00 71 COMDIV0 1 R/W 0x00 71 0x0704 COMIEN0 1 R/W 0x00 71 COMDIV1 1 R/W 0x00 72 0x0708 COMIID0 1 R 0x01 72 0x070C COMCON0 1 R/W 0x00 72 0x0710 COMCON1 1 R/W 0x00 72 0x0714 COMSTA0 1 R 0x60 72 0x0718 COMSTA1 1 R 0x00 73 0x071C COMSCR 1 R/W 0x00 73 0x0720 COMIEN1 1 R/W 0x04 73 0x0724 COMIID1 1 R 0x01 73 0x0728 COMADR 1 R/W 0xAA 74 0x072C COMDIV2 2 R/W 0x0000 73 Address Name Byte Access Type Default Value Page I2C0 Base Address = 0xFFFF0800 0x0800 I2C0MSTA 1 R/W 0x00 76 0x0804 I2C0SSTA 1 R 0x01 76 0x0808 I2C0SRX 1 R 0x00 77 0x080C I2C0STX 1 W 0x00 77 0x0810 I2C0MRX 1 R 0x00 77 0x0814 I2C0MTX 1 W 0x00 77 0x0818 I2C0CNT 1 R/W 0x00 77 0x081C I2C0ADR 1 R/W 0x00 77 0x0824 I2C0BYTE 1 R/W 0x00 77 0x0828 I2C0ALT 1 R/W 0x00 78 0x082C I2C0CFG 1 R/W 0x00 78 0x0830 I2C0DIV 2 R/W 0x1F1F 79 0x0838 I2C0ID0 1 R/W 0x00 79 0x083C I2C0ID1 1 R/W 0x00 79 0x0840 I2C0ID2 1 R/W 0x00 79 0x0844 I2C0ID3 1 R/W 0x00 79 0x0848 I2C0CCNT 1 R/W 0x01 79 0x084C I2C0FSTA 2 R/W 0x0000 79 I2C1 Base Address = 0xFFFF0900 0x0900 I2C1MSTA 1 R/W 0x00 76 0x0904 I2C1SSTA 1 R 0x01 76 0x0908 I2C1SRX 1 R 0x00 77 0x090C I2C1STX 1 W 0x00 77 0x0910 I2C1MRX 1 R 0x00 77 0x0914 I2C1MTX 1 W 0x00 77 0x0918 I2C1CNT 1 R/W 0x00 77 0x091C I2C1ADR 1 R/W 0x00 77 0x0924 I2C1BYTE 1 R/W 0x00 77 0x0928 I2C1ALT 1 R/W 0x00 78 0x092C I2C1CFG 1 R/W 0x00 78 0x0930 I2C1DIV 2 R/W 0x1F1F 79 0x0938 I2C1ID0 1 R/W 0x00 79 0x093C I2C1ID1 1 R/W 0x00 79 0x0940 I2C1ID2 1 R/W 0x00 79 0x0944 I2C1ID3 1 R/W 0x00 79 0x0948 I2C1CCNT 1 R/W 0x01 79 0x094C I2C1FSTA 2 R/W 0x0000 79 SPI Base Address = 0xFFFF0A00 0x0A00 SPISTA 1 R 0x00 75 0x0A04 SPIRX 1 R 0x00 75 0x0A08 SPITX 1 W 0x00 75 0x0A0C SPIDIV 1 R/W 0x1B 75 0x0A10 SPICON 2 R/W 0x0000 75

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 44 of 104 Address Name Byte Access Type Default Value Page PLA Base Address = 0xFFFF0B00 0x0B00 PLAELM0 2 R/W 0x0000 80 0x0B04 PLAELM1 2 R/W 0x0000 80 0x0B08 PLAELM2 2 R/W 0x0000 80 0x0B0C PLAELM3 2 R/W 0x0000 80 0x0B10 PLAELM4 2 R/W 0x0000 80 0x0B14 PLAELM5 2 R/W 0x0000 80 0x0B18 PLAELM6 2 R/W 0x0000 80 0x0B1C PLAELM7 2 R/W 0x0000 80 0x0B20 PLAELM8 2 R/W 0x0000 80 0x0B24 PLAELM9 2 R/W 0x0000 80 0x0B28 PLAELM10 2 R/W 0x0000 80 0x0B2C PLAELM11 2 R/W 0x0000 80 0x0B30 PLAELM12 2 R/W 0x0000 80 0x0B34 PLAELM13 2 R/W 0x0000 80 0x0B38 PLAELM14 2 R/W 0x0000 80 0x0B3C PLAELM15 2 R/W 0x0000 80 0x0B40 PLACLK 1 R/W 0x00 81 0x0B44 PLAIRQ 4 R/W 0x00000000 81 0x0B48 PLAADC 4 R/W 0x00000000 82 0x0B4C PLADIN 4 R/W 0x00000000 82 0x0B50 PLADOUT 4 R 0x00000000 82 0x0B54 PLALCK 1 W 0x00 82 External Memory Base Address = 0xFFFFF000 0xF000 XMCFG 1 R/W 0x00 90 0xF010 XM0CON 1 R/W 0x00 90 0xF014 XM1CON 1 R/W 0x00 90 0xF018 XM2CON 1 R/W 0x00 90 0xF01C XM3CON 1 R/W 0x00 90 0xF020 XM0PAR 2 R/W 0x70FF 90 0xF024 XM1PAR 2 R/W 0x70FF 90 0xF028 XM2PAR 2 R/W 0x70FF 90 0xF02C XM3PAR 2 R/W 0x70FF 90 Address Name Byte Access Type Default Value Page GPIO Base Address = 0xFFFFF400 0xF400 GP0CON 4 R/W 0x00000000 68 0xF404 GP1CON 4 R/W 0x00000000 68 0xF408 GP2CON 4 R/W 0x00000000 68 0xF40C GP3CON 4 R/W 0x00000000 68 0xF410 GP4CON 4 R/W 0x00000000 68 0xF420 GP0DAT 4 R/W 0x000000XX1 70 0xF424 GP0SET 4 W 0x000000XX1 70 0xF428 GP0CLR 4 W 0x000000XX1 70 0xF42C GP0PAR 4 R/W 0x20000000 68 0xF430 GP1DAT 4 R/W 0x000000XX1 69 0xF434 GP1SET 4 W 0x000000XX1 70 0xF438 GP1CLR 4 W 0x000000XX1 70 0xF43C GP1PAR 4 R/W 0x00000000 68 0xF440 GP2DAT 4 R/W 0x000000XX1 69 0xF444 GP2SET 4 W 0x000000XX1 70 0xF448 GP2CLR 4 W 0x000000XX1 70 0xF450 GP3DAT 4 R/W 0x000000XX1 69 0xF454 GP3SET 4 W 0x000000XX1 70 0xF458 GP3CLR 4 W 0x000000XX1 70 0xF460 GP4DAT 4 R/W 0x000000XX1 69 0xF464 GP4SET 4 W 0x000000XX1 70 0xF468 GP4CLR 4 W 0x000000XX1 70 1 X = 0, 1, 2, or 3. Flash/EE Base Address = 0xFFFFF800 0xF800 FEESTA 1 R 0x20 52 0xF804 FEEMOD 2 R/W 0x0000 52 0xF808 FEECON 1 R/W 0x07 53 0xF80C FEEDAT 2 R/W 0xXXXX1 53 0xF810 FEEADR 2 R/W 0x0000 53 0xF818 FEESIGN 3 R 0xFFFFFF 53 0xF81C FEEPRO 4 R/W 0x00000000 53 0xF820 FEEHIDE 4 R/W 0xFFFFFFFF 53 1 X = 0, 1, 2, or 3. PWM Base Address = 0xFFFFFC00 0xFC00 PWMCON 2 R/W 0x0000 66 0xFC04 PWMSTA 2 R/W 0x0000 66 0xFC08 PWMDAT0 2 R/W 0x0000 67 0xFC0C PWMDAT1 2 R/W 0x0000 67 0xFC10 PWMCFG 2 R/W 0x0000 67 0xFC14 PWMCH0 2 R/W 0x0000 67 0xFC18 PWMCH1 2 R/W 0x0000 67 0xFC1C PWMCH2 2 R/W 0x0000 67 0xFC20 PWMEN 2 R/W 0x0000 67 0xFC24 PWMDAT2 2 R/W 0x0000 67

track-and-hold, an on-chip reference, and an ADC. signal configuration, the ADC can operate in one of three modes. maximum amplitude of 2 VREF (see Figure 48). Figure 48. Examples of Balanced Signals in Fully Differential Mode described in the Band Gap Reference section. used to generate a repetitive trigger for ADC conversions. that measures die temperature to an accuracy of 3°C.

1 LSB = FS/4096, or

Figure 49. ADC Transfer Function in Pseudo Differential or Single-Ended Mode is, therefore, the voltage that the two inputs are centered on. (see the Driving the Analog Inputs section). input/output transfer characteristic is shown in Figure 50. Figure 50. ADC Transfer Function in Differential Mode

Table 18. ADCCON MMR Bit Designations 1 MSPS ADC with an external clock <41.78 MHz. 10 Eight clocks (default value). stop the ADC when continuously converting). user to place the ADC in power-down mode. 10 Pseudo differential mode. 000 Enable CONVSTART pin as a conversion input. 001 Enable Timer1 as a conversion input. 010 Enable Timer0 as a conversion input. 100 Continuous software conversion. Table 19. ADCCP Register MMR is described in Table 20. Table 20. ADCCP1 MMR Bit Designation 4:0 Positive channel selection bits. 10001 AGND (self-diagnostic feature). 10010 Internal reference (self-diagnostic feature). Table 21. ADCCN Register MMR is described in Table 22.

Table 28. VCM Ranges until the ADC result (ADCDAT) reads Code 4094 to Code 4095. channel, measuring die temperature to an accuracy of ±3°C. and DAC. This internal reference also appears on the VREF pin. pin. Note that it is not possible to disable the internal reference. overdriving the internal reference source. Table 29. REFCON Register REFCON, described in Table 30. Table 30. REFCON MMR Bit Designations connect the internal 2.5 V reference to the VREF pin. the reference from the VREF pin.

nonvolatile, in-circuit reprogrammable memory space. and more correctly referred to as Flash/EE memory. (OTP) devices at remote operating nodes. (such as ADC, temperature sensor, and band gap references). This 2 kB embedded firmware is hidden from user code. cycling endurance and Flash/EE memory data retention.

1. Initial page erase sequence
2. Read/verify sequence (single Flash/EE)
3. Byte program sequence memory
4. Second read/verify sequence (endurance cycle)

supply temperature of 10,000 cycles. Figure 61. Flash/EE Memory Data Retention using the serial download mode or the provided JTAG mode. download via the standard UART serial port or via the I2C port. development system for serial downloading via the UART.

the 62 kB from being read through JTAG programming mode. protection is activated for all types of access.

• Protection can be set and removed by writing directly into FEEHIDE MMR. This protection does not remain after reset.
• Protection can be set by writing into the FEEPRO MMR. It takes effect only after a save protection command (0x0C) and a reset. The FEEPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEEPRO. A mass erase sets the key back to 0xFFFF but also erases all the user code.
• Flash can be permanently protected by using the FEEPRO MMR and a particular value of key: 0xDEADDEAD. Entering the key again to modify the FEEPRO register is not allowed. Sequence to Write the Key 1. Write the bit in FEEPRO corresponding to the page to be protected. 2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5 must equal 0). 3. Write a 32-bit key in FEEADR and FEEDAT. 4. Run the write key command 0x0C in FEECON; wait for the read to be successful by monitoring FEESTA. 5. Reset the part. To remove or modify the protection, the same sequence is used with a modified value of FEEPRO. If the key chosen is the value 0xDEAD, the memory protection cannot be removed. Only a mass erase unprotects the part, but it also erases all user code. The sequence to write the key is illustrated in the following example (this protects writing Page 4 to Page 7 of the Flash): FEEPRO=0xFFFFFFFD; //Protect pages 4 to 7 FEEMOD=0x48; //Write key enable FEEADR=0x1234; //16 bit key value FEEDAT=0x5678; //16 bit key value FEECON= 0x0C; // Write key command The same sequence should be followed to protect the part permanently with FEEADR = 0xDEAD and FEEDAT = 0xDEAD. FLASH/EE CONTROL INTERFACE Serial and JTAG programming use the Flash/EE control interface, which includes the eight MMRs outlined in this section.

Table 31. FEESTA Register flash control interface as described in Table 32. Table 32. FEESTA MMR Bit Designations register is set. Cleared when reading the FEESTA register. reading the FEESTA register. ally when reading the FEESTA register. Table 33. FEEMOD Register FEEMOD sets the operating mode of the flash control interface. Table 34 shows FEEMOD MMR bit designations. Table 34. FEEMOD MMR Bit Designations 8 Reserved. This bit should always be set to 0. protect the Flash against the erase/write command. 2:0 Reserved. These bits should always be set to 0.

Table 35. FEECON Register Table 36. Command Codes in FEECON 0x011 Single read Load FEEDAT with the 16-bit data. by FEEADR. This operation takes 50 µs. 0x051 Single erase Erase the page indexed by FEEADR. required to execute this instruction. Executing a Mass Erase section. operation takes 32,778 clock cycles. only with a mass erase (0x06) of the key. 0x0F Ping No operation; interrupt generated.

1 The FEECON register always reads 0x07 immediately after execution of any

Table 37. FEEDAT Register FEEDAT is a 16-bit data register. Table 38. FEEADR Register FEEADR is another 16-bit address register. Table 39. FEESIGN Register FEESIGN is a 24-bit code signature. Table 40. FEEPRO Register reset of the MMR. It requires a software key (see Table 42). Table 41. FEEHIDE Register FEEHIDE are cleared by a reset (see Table 42). Table 42. FEEPRO and FEEHIDE MMR Bit Designations 31 Read protection. Cleared by user to protect all code. Set by user to allow reading the code.

two cycles to fill the pipeline with the new instructions. one cycle (as can be done from SRAM when the CD Bit = 0). and two cycles are needed to get the 32-bit data from Flash/EE. Table 43. Execution Cycles in ARM/Thumb Mode

1 The SWAP instruction combines an LD and STR instruction with only one

fetch, giving a total of eight cycles + 40 ns.

2 N is the amount of data to load or store in the multiple load/store instruction

Figure 62. Remap for Exception Execution 32-bit wide SRAM instead of 16-bit wide Flash/EE memory. 0x00000000, to execute the user’s reset exception routine. of the array because this is replaced by the SRAM. Address 0x00000000 by clearing Bit 0 of the REMAP MMR. Flash/EE memory at the bottom of the array.

exception service routine to identify the source of the reset. If RSTSTA is null, the reset is external. Table 44. REMAP Register Table 45. REMAP MMR Bit Designations Flash/EE memory is available. Table 46. RSTSTA Register Table 47. RSTSTA MMR Bit Designations 2 Software reset. Set by user to force a software reset. Cleared by setting the corresponding bit in RSTCLR. Table 48. RSTCLR Register

capable of driving 5 kΩ/100 pF. band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD. DACREF is equivalent to an external reference for the DAC. The signal range is 0 V to AVDD. (see Table 52) are described in detail in this section. Table 49. DACxCON Registers Table 50. DAC0CON MMR Bit Designations update the DAC using Timer1. 3 Reserved. This bit should be left at 0. 2 Reserved. This bit should be left at 0. Table 51. DACxDAT Registers Table 52. DAC0DAT MMR Bit Designations Figure 63. DAC Structure spans from 0 V to the internal 2.5 V reference, VREF. DD mode only, Code 3995 to Code 4095.

width of the hysteresis range. which is described in Table 56. Table 55. CMPCON Register Table 56. CMPCON MMR Bit Descriptions by user to disable the comparator. 5 CMPOL Comparator output logic state bit. is above the negative input (CMP1). large signals (2.5 V differential). small signals (0.65 mV differential).

1 CMPORI Comparator output rising edge

user by writing a 1 to this bit.

0 CMPOFI Comparator output falling edge

voltage (CMP0). Cleared by user. core clock is the PLL clock divided by 8 (CD = 3) or 5.22 MHz. clock source to an external device without an external buffer. Figure 67. Clocking System default, the part uses the internal oscillator feeding the PLL.

1. Enable the Timer2 interrupt and configure it for a timeout
2. Follow the write sequence to the PLLCON register, setting

the MDCLK bits to 01 and clearing the OSEL bit.

1. Force the part into NAP mode by following the correct

write sequence to the POWCON register.

halted, and this interrupt is only serviced when the lock is restored. reset came from the watchdog timer. on in the different modes and indicates the power-up time. Table 57. Operating Modes1 1 X indicates that the part is powered on. Table 58. Typical Current Consumption at 25°C in Milliamperes

clock frequency and the power-down mode. Table 59. PLLKEYx Registers Table 60. PLLCON Register Table 61. PLLCON MMR Bit Designations user to select the external 32 kHz crystal. 01 PLL. Default configuration. 11 External clock on the P0.7 pin. Table 62. POWKEYx Registers Table 63. POWCON Register Table 64. POWCON MMR Bit Designations 2:0 CD CPU clock divider bits. Table 65. PLLCON and POWCON Write Sequence

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 61 of 104 DIGITAL PERIPHERALS 3-PHASE PWM Each ADuC7019/20/21/22/24/25/26/27/28/29 provides a flexible and programmable, 3-phase pulse-width modulation (PWM) waveform generator. It can be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction motor control (ACIM). Note that only active high patterns can be produced. The PWM generator produces three pairs of PWM signals on the six PWM output pins (PWM0H, PWM0L, PWM1H, PWM1L, PWM2H, and PWM2L). The six PWM output signals consist of three high-side drive signals and three low-side drive signals. The switching frequency and dead time of the generated PWM patterns are programmable using the PWMDAT0 and PWMDAT1 MMRs. In addition, three duty-cycle control registers (PWMCH0, PWMCH1, and PWMCH2) directly control the duty cycles of the three pairs of PWM signals. Each of the six PWM output signals can be enabled or disabled by separate output enable bits of the PWMEN register. In addition, three control bits of the PWMEN register permit crossover of the two signals of a PWM pair. In crossover mode, the PWM signal destined for the high-side switch is diverted to the comple- mentary low-side output. The signal destined for the low-side switch is diverted to the corresponding high-side output signal. In many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the inverter power devices. In general, there are two common isolation techniques: optical isolation using optocouplers and transformer isolation using pulse transformers. The PWM controller permits mixing of the output PWM signals with a high frequency chopping signal to permit easy interface to such pulse transformers. The features of this gate-drive chopping mode can be controlled by the PWMCFG register. An 8-bit value within the PWMCFG register directly controls the chopping frequency. High frequency chopping can be independently enabled for the high- side and low-side outputs using separate control bits in the PWMCFG register. The PWM generator can operate in one of two distinct modes: single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period so that the resulting PWM patterns are symmetrical about the midpoint of the PWM period. In the double update mode, a second updating of the PWM duty cycle values is implemented at the midpoint of the PWM period. In double update mode, it is also possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 3-phase PWM inverters. This technique permits closed-loop controllers to change the average voltage applied to the machine windings at a faster rate. As a result, faster closed-loop bandwidths are achieved. The operating mode of the PWM block is selected by a control bit in the PWMCON register. In single update mode, an internal synchronization pulse, PWMSYNC, is produced at the start of each PWM period. In double update mode, an additional PWMSYNC pulse is produced at the midpoint of each PWM period. The PWM block can also provide an internal synchronization pulse on the PWM SYNC pin that is synchronized to the PWM switching frequency. In single update mode, a pulse is produced at the start of each PWM period. In double update mode, an additional pulse is produced at the mid-point of each PWM period. The width of the pulse is programmable through the PWMDAT2 register. The PWM block can also accept an external synchro- nization pulse on the PWM SYNC pin. The selection of external synchronization or internal synchronization is in the PWMCON register. The SYNC input timing can be synchronized to the internal peripheral clock, which is selected in the PWMCON register. If the external synchronization pulse from the chip pin is asynchronous to the internal peripheral clock (typical case), the external PWMSYNC is considered asynchronous and should be synchronized. The synchronization logic adds latency and jitter from the external pulse to the actual PWM outputs. The size of the pulse on the PWM SYNC pin must be greater than two core clock periods. The PWM signals produced by the ADuC7019/20/21/22/24/25/ 26/27/28/29 can be shut off via a dedicated asynchronous PWM shutdown pin, PWM TRIP. When brought low, PWMTRIP instanta- neously places all six PWM outputs in the off state (high). This hardware shutdown mechanism is asynchronous so that the associated PWM disable circuitry does not go through any clocked logic. This ensures correct PWM shutdown even in the event of a core clock loss. Status information about the PWM system is available to the user in the PWMSTA register. In particular, the state of the PWM TRIP pin is available, as well as a status bit that indicates whether oper- ation is in the first half or the second half of the PWM period. 40-Pin Package Devices On the 40-pin package devices, the PWM outputs are not directly accessible, as described in the General-Purpose Input/Output section. One channel can be brought out on a GPIO (see Table 78) via the PLA as shown in the following example: PWMCON = 0x1; // enables PWM o/p PWMDAT0 = 0x055F; // PWM switching freq // Configure Port Pins GP4CON = 0x300; // P4.2 as PLA output GP3CON = 0x1; // P3.0 configured as // output of PWM0 //(internally) // PWM0 onto P4.2 PLAELM8 = 0x0035; // P3.0 (PWM output) // input of element 8 PLAELM10 = 0x0059; // PWM from element 8

are cleared so that high frequency chopping is disabled, by default. Figure 72. Typical PWM Signals with High Frequency Gate Chopping Bit 3 of the PWMSTA register. interrupts share the same bit in the interrupt controller. Therefore, only one of the interrupts can be used at a time. See the Interrupt System section for further details. Table 66. PWMCON Register Table 67. PWMCON MMR Bit Descriptions sync. Cleared to use internal sync. external synchronous sync signal. Cleared for asynchronous sync signal. to enable double update mode. by user to disable synchronization. Table 68. PWMSTA Register PWMSTA reflects the status of the PWM. Table 69. PWMSTA MMR Bit Descriptions this bit clears this interrupt. this bit clears this interrupt. 3 PWMTRIP Raw signal from the PWM TRIP pin.

Table 70. PWMCFG Register PWMCFG is a gate chopping register. Table 71. PWMCFG MMR Bit Descriptions 9 CHOPLO Low-side gate chopping enable bit. 8 CHOPHI High-side gate chopping enable bit. 7:0 GDCLK PWM gate chopping period (unsigned). Table 72. PWMEN Register its bit definitions in Table 73. Table 73. PWMEN MMR Bit Descriptions 8 0H0L_XOVR Channel 0 output crossover enable bit. 7 1H1L_XOVR Channel 1 output crossover enable bit. 6 2H2L_XOVR Channel 2 output crossover enable bit. by user to enable the 0L output of the PWM. 0 by user to enable the 0H output of the PWM. by user to enable the 1L output of the PWM. 0 by user to enable the 1H output of the PWM. by user to enable the 2L output of the PWM. 0 by user to enable the 2H output of the PWM. Table 74. PWMDAT0 Register PWMDAT0 is an unsigned 16-bit register for switching period. Table 75. PWMDAT1 Register PWMDAT1 is an unsigned 10-bit register for dead time. Table 76. PWMCHx Registers Table 77. PWMDAT2 Register tolerant, meaning the GPIOs support an input voltage of 5 V . pins are configured in GPIO mode. maximum of 20 GPIOs can drive 1.6 mA at the same time. P0.6, P0.7, and the eight GPIOs of P1. The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x). Each port is controlled by four or five MMRs. other than GPIO. The PLA input is always active. power-saving mode, the GPIO pins retain their state.

Table 78. GPIO Pin Function Descriptions configure it as a clock input, the MDCLK bits in PLLCON must be set to 11. 2 The CONVSTART signal is active in all modes of P2.0. Table 79. GPxCON Registers function of each pin of Port x as described in Table 80. Table 80. GPxCON MMR Bit Descriptions 29:28 Select function of the Px.7 pin. 25:24 Select function of the Px.6 pin. 21:20 Select function of the Px.5 pin. 17:16 Select function of the Px.4 pin. 13:12 Select function of the Px.3 pin. 9:8 Select function of the Px.2 pin. 5:4 Select function of the Px.1 pin. 1:0 Select function of the Px.0 pin. Table 81. GPxPAR Registers Table 82. GPxPAR MMR Bit Descriptions

Table 83. GPIO Drive Strength Control Bits Descriptions Figure 73. Programmable Strength for High Level Figure 74. Programmable Strength for Low Level cannot be changed (see Table 84). Table 84. GPxPAR Control Bits Access Descriptions

31 Reserved Reserved

28 R/W R/W

27 Reserved Reserved

24 R/W R/W

23 Reserved Reserved

20 R/W R/W

19 Reserved Reserved

16 R/W R/W

15 Reserved Reserved

12 R/W R/W

11 Reserved Reserved

8 R/W R/W

7 Reserved Reserved

4 R/W R/W

3 Reserved Reserved

0 R/W R/W

Table 85. GPxDAT Registers input value of the pins configured as input. Table 86. GPxDAT MMR Bit Descriptions configure the GPIO pin as an input. 15:8 Reflect the state of Port x pins at reset (read only). 7:0 Port x data input (read only). Table 87. GPxSET Registers GPxSET are data set Port x registers. Table 88. GPxSET MMR Bit Descriptions also sets the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data out. Table 89. GPxCLR Registers GPxCLR are data clear Port x registers. Table 90. GPxCLR MMR Bit Descriptions MMR. Cleared to 0 by user; does not affect the data out. one of its specific I/O functions as described in Table 91. Table 91. SPM Configuration Table 91 also details the mode for each of the SPMMUX pins. Table 92. UART Signal Description SPM0 (Mode 1) SIN Serial receive data. SPM1 (Mode 1) SOUT Serial transmit data. SPM2 (Mode 1) RTS Request to send. SPM3 (Mode 1) CTS Clear to send. SPM4 (Mode 1) RI Ring indicator. SPM5 (Mode 1) DCD Data carrier detect. SPM6 (Mode 1) DSR Data set ready. SPM7 (Mode 1) DTR Data terminal ready. SPM8 (Mode 2) SIN Serial receive data. SPM9 (Mode 2) SOUT Serial transmit data.

generation options selectable in the configuration register. 450 UART baud rate generation and the fractional divider. in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL). Table 93 gives some common baud rate values. Table 93. Baud Rate Using the Normal Baud Rate Generator generator, produces a wider range of more accurate baud rates. Figure 75. Baud Rate Generation Options Table 94. COMTX Register COMTX is an 8-bit transmit register. Table 95. COMRX Register COMRX is an 8-bit receive register. Table 96. COMDIV0 Register Table 97. COMIEN0 Register COMIEN0 is the interrupt enable register. Table 98. COMIEN0 MMR Bit Descriptions any of COMSTA1[3:1] is set. Cleared by user. COMSTA0[4:1] is set. Cleared by user. empty during a transmission. Cleared by user. during a reception. Cleared by user.

Table 99. COMDIV1 Register COMDIV1 is a divisor latch (high byte) register. Table 100. COMIID0 Register COMIID0 is the interrupt identification register. Table 101. COMIID0 MMR Bit Descriptions Table 102. COMCON0 Register COMCON0 is the line control register. Table 103. COMCON0 MMR Bit Descriptions to generate 1 stop bit in the transmitted data. Table 104. COMCON1 Register COMCON1 is the modem control register. Table 105. COMCON1 MMR Bit Descriptions parity transmission or checking. bit in the transmitted data. Table 106. COMSTA0 Register COMSTA0 is the line status register. Table 107. COMSTA0 MMR Bit Descriptions the maximum word length. Cleared automatically. 3 FE Framing error. Set when an invalid stop bit occurs. 2 PE Parity error. Set when a parity error occurs. written before being read. Cleared automatically. 0 DR Data ready. Set automatically when COMRX is full.

Table 108. COMSTA1 Register COMSTA1 is a modem status register. Table 109. COMSTA1 MMR Bit Descriptions automatically by reading COMSTA1. automatically by reading COMSTA1. automatically by reading COMSTA1. Table 110. COMSCR Register storage. It is also used in network addressable UART mode. Table 111. COMDIV2 Register COMDIV2 is a 16-bit fractional baud divide register. Table 112. COMDIV2 MMR Bit Descriptions 15 FBEN Fractional baud rate generator enable bit. 10:0 FBN[10:0] N (see the Fractional Divider section). Table 114). Note that there is no parity check in this mode. COMADR are used in network addressable UART mode only. Table 113. COMIEN1 Register COMIEN1 is an 8-bit network enable register. Table 114. COMIEN1 MMR Bit Descriptions disable network address mode. 4 ENI Network interrupt enable bit. cleared. Cleared for 8-bit data. 1 NABP Network address bit. Interrupt polarity bit. Table 115. COMIID1 Register are reserved (see Table 116).

Table 116. COMIID1 MMR Bit Descriptions Table 117. COMADR Register processor and/or sets the appropriate status bit in COMIID1. The SPI port can be configured for master or slave operation. discarded, SPISTA, Bit 5 (the overflow bit) is set. mode and as an input in slave mode. divider bits and is summarized in Table 118. Table 118. SPI Speed vs. Clock Divider Bits in Master Mode accepts data from an external master up to 10.4 Mb at CD = 0. for the master and slave devices. deassertion of CS. In slave mode, CS is always an input.

interface: SPISTA, SPIRX, SPITX, SPIDIV , and SPICON. Table 119. SPISTA Register register determines which bit generates the interrupt. Table 120. SPISTA MMR Bit Descriptions overflowing. Cleared by reading the SPIRX register. is set. Cleared by reading the SPIRX register. finished transmission disabling the SPI. data. Cleared when SPITX is empty. Table 121. SPIRX Register SPIRX is an 8-bit, read-only receive register. Table 122. SPITX Register SPITX is an 8-bit, write-only transmit register. Table 123. SPIDIV Register SPIDIV is an 8-bit, serial clock divider register. Table 124. SPICON Register SPICON is a 16-bit control register. Table 125. SPICON MMR Bit Descriptions serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period. 11 Loop back enable Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. set. Clear this bit for MISO to operate as normal. the new serial byte received is discarded. 7 SPITX underflow mode Set by user to transmit 0. Cleared by user to transmit the previous data. 6 Transfer and interrupt mode Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs only when TX is empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs only when RX is full. 5 LSB first transfer enable bit Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.

4 Reserved

3 Serial clock polarity mode bit Set by user, the serial clock idles high. Cleared by user, the serial clock idles low. clock pulses at the end of each serial bit transfer. 1 Master mode enable bit Set by user to enable master mode. Cleared by user to enable slave mode. 0 SPI enable bit Set by user to enable the SPI. Cleared by user to disable the SPI.

faces are identical, this data sheet describes only I2C0 in detail. interrupts (see the Interrupt System section). multimaster system. These pins require external pull-up resistors. Typical pull-up values are 10 kΩ. to respond to four slave addresses. the master issues a stop condition and the bus becomes idle. support master and slave modes. fast mode (400 kHz) or standard mode (100 kHz). fUCLK = clock before the clock divider. DIVH = the high period of the clock. DIVL = the low period of the clock. The I2CxDIV registers correspond to DIVH:DIVL. Table 126. I2CxMSTA Registers I2CxMSTA are status registers for the master channel. Table 127. I2C0MSTA MMR Bit Descriptions flushes the slave receive FIFO. busy. Cleared automatically. 3 R Master receive IRQ. Set after receiving data. writing to the I2C0MTX register. cally by writing twice to the I2C0STX register. Table 128. I2CxSSTA Registers I2CxSSTA are status registers for the slave channel.

Table 129. I2C0SSTA MMR Bit Descriptions 31:15 Reserved. These bits should be written as 0. receives a valid start plus matching address. 00 Received Address Matched ID Register 0. 01 Received Address Matched ID Register 1. 10 Received Address Matched ID Register 2. 11 Received Address Matched ID Register 3. 10 Stop after start and matching address interrupt. read of the I2C0SSTA register. 01 General call reset and program address. 10 General call program address. 11 General call matching alternative ID. bus specification, Version 2.1, January 2000. 6 Slave busy. Set automatically if the slave is busy. reading the I2C0SSTA register. automatically by reading the I2C0SSTA register. 3 Slave receive IRQ. Set after receiving data. register or flushing the FIFO. automatically by writing to the I2C0SSTA register. matically by writing twice to the I2C0STX register. Table 130. I2CxSRX Registers I2CxSRX are receive registers for the slave channel. Table 131. I2CxSTX Registers I2CxSTX are transmit registers for the slave channel. Table 132. I2CxMRX Registers I2CxMRX are receive registers for the master channel. Table 133. I2CxMTX Registers I2CxMTX are transmit registers for the master channel. Table 134. I2CxCNT Registers Table 135. I2CxADR Registers register when the master enable bit is set. Table 136. I2CxBYTE Registers

Table 137. I2CxALT Registers I2CxALT are hardware general call ID registers used in slave mode. Table 138. I2CxCFG Registers I2CxCFG are configuration registers. Table 139. I2C0CFG MMR Bit Descriptions 31:5 Reserved. These bits should be written by the user as 0. condition and matching address. Cleared by the user to disable the generation of an interrupt upon receiving a stop condition. 11 Enable stretch SCL (holds SCL low). Set by the user to stretch the SCL line. Cleared by the user to disable stretching of the SCL line. interrupt latency into account. call status bits are cleared. user to enable start backoff. After losing arbitration, the master waits before trying to retransmit. the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. 1 Master enable bit. Set by user to enable the master I2C channel. Cleared by user to disable the master I2C channel.

Table 140. I2CxDIV Registers I2CxDIV are the clock divider registers. Table 141. I2CxIDx Registers device ID registers of I2Cx. Table 142. I2CxCCNT Registers off SDA low for start and stop conditions. Table 143. I2CxFSTA Registers I2CxFSTA are FIFO status registers. Table 144. I2C0FSTA MMR Bit Descriptions user to flush the master Tx FIFO. also flushes the slave receive FIFO. 7:6 R Master Rx FIFO status bits. 5:4 R Master Tx FIFO status bits. 3:2 R Slave Rx FIFO status bits. 1:0 R Slave Tx FIFO status bits.

two inputs and a flip-flop. This is represented in Figure 76. Figure 76. PLA Element comparator output is also included as one of the 16 input pins. of Mux 0 of Element 0 (Block 0). of Mux 0 of Element 8 (Block 1). Table 145. Element Input/Output Table 146. PLAELMx Registers Table 147. PLAELMx MMR Bit Descriptions 10:9 Mux 0 control (see Table 152). 8:7 Mux 1 control (see Table 152).

Table 148. PLACLK Register GPIO pins as the clock input for the PLA blocks is 44 MHz. Table 149. PLACLK MMR Bit Descriptions 6:4 Block 1 clock source selection. 100 OCLK (32.768 kHz) external crystal only. 2:0 Block 0 clock source selection. 100 OCLK (32.768 kHz) external crystal only. Table 150. PLAIRQ Register Table 151. PLAIRQ MMR Bit Descriptions disable IRQ1 output from PLA. disable IRQ0 output from PLA. Table 152. Feedback Configuration

01 Element 2 Element 2 Element 10 Element 10

10 Element 4 Element 4 Element 12 Element 12

11 Element 6 Element 6 Element 14 Element 14

01 Element 3 Element 3 Element 11 Element 11

10 Element 5 Element 5 Element 13 Element 13

11 Element 7 Element 7 Element 15 Element 15

Table 153. PLAADC Register PLAADC is the PLA source for the ADC start conversion signal. Table 154. PLAADC MMR Bit Descriptions to enable ADC start conversion from PLA. 3:0 ADC start conversion source. Table 155. PLADIN Register PLADIN is a data input MMR for PLA. Table 156. PLADIN MMR Bit Descriptions 15:0 Input bit to Element 15 to Element 0. Table 157. PLADOUT Register Table 158. PLADOUT MMR Bit Descriptions 15:0 Output bit from Element 15 to Element 0. Table 159. PLALCK Register

the same interrupt source as described in Table 160. Table 160. IRQ/FIQ MMRs Bit Description

0 All interrupts OR’ed (FIQ only)

1 SWI

2 Timer0

3 Timer1

4 Wake-up timer (Timer2)

5 Watchdog timer (Timer3)

6 Flash control

7 ADC channel

8 PLL lock

9 I2C0 slave

10 I2C0 master

11 I2C1 master

12 SPI slave

13 SPI master

14 UART

15 External IRQ0

16 Comparator

17 PSM

18 External IRQ1

19 PLA IRQ0

20 PLA IRQ1

21 External IRQ2

22 External IRQ3

23 PWM trip (IRQ only)/PWM sync (FIQ only)

interrupt handling of internal and external events. Table 161. IRQSTA Register Table 162. IRQSIG Register 1 X indicates an undefined value. sources can be masked in the IRQEN MMR. IRQSIG is read only. Table 163. IRQEN Register interrupt’s IRQEN bit does not disable the interrupt. Table 164. IRQCLR Register an atomic read-modify-write.

are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Table 165. FIQSTA Register Table 166. FIQSIG Register 1 X indicates an undefined value. Table 167. FIQEN Register Table 168. FIQCLR Register in FIQEN does, as a side effect, clear the same bit in IRQEN. interrupt’s FIQEN bit does not disable the interrupt. allows the control of a programmed source interrupt. Table 169. SWICFG Register Table 170. SWICFG MMR Bit Descriptions

• Timer0
• Timer1
• Timer2 or wake-up timer
• Timer3 or watchdog timer These four timers in their normal mode of operation can be either free running or periodic. In free-running mode, the counter decreases from the maximum value until zero scale and starts again at the minimum value. (It also increases from the minimum value until full scale and starts again at the maximum value.) In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero/full scale and starts again at the value stored in the load register. The timer interval is calculated as follows: If the timer is set to count down then ( ) ClockSource PrescalerTxLDInterval ×= If the timer is set to count up, then ( ) ClockSource PrescalerTxLDFsInterval ×−= The value of a counter can be read at any time by accessing its value register (TxV AL). Note that when a timer is being clocked from a clock other than core clock, an incorrect value may be read (due to an asynchronous clock system). In this configur- ation, TxV AL should always be read twice. If the two readings are different, it should be read a third time to get the correct value. Timers are started by writing in the control register of the corresponding timer (TxCON).

register of that particular timer (TxCLRI). minute, and second are not consecutive in the register. TxCON[5:4]. See Table 171 for additional details. Table 171. Hour:Minnute:Second:Hundredths Format Figure 77. Timer0 Block Diagram Table 172. T0LD Register T0LD is a 16-bit load register. Table 173. T0VAL Register Table 174. T0CON Register T0CON is the configuration MMR described in Table 175. Table 175. T0CON MMR Bit Descriptions 7 Timer0 enable bit. Set by user to enable Timer0. Cleared by user to disable Timer0 by default. in free-running mode. Default mode. 00 Core Clock/1. Default value. 11 Undefined. Equivalent to 00. Table 176. T0CLRI Register

hours: minutes: seconds: hundredths. precision allowed by the RTOS timer when the IRQ is serviced. Figure 78. Timer1 Block Diagram Table 177. T1LD Register T1LD is a 32-bit load register. Table 178. T1VAL Register Table 179. T1CON Register T1CON is the configuration MMR described in Table 180.

Table 180. T1CON MMR Bit Descriptions disable time capture of an event. 001 External 32.768 kHz crystal. 010 P1.0 rising edge triggered. 011 P0.6 rising edge triggered. free-running mode. Default mode. 10 Hr: min: sec: hundredths (23 hours to 0 hour).

11 Hr: min: sec: hundredths (255 hours to 0

Table 181. T1CLRI Register clears the Timer1 interrupt. Table 182. T1CAP Register hours: minutes: seconds: hundredths. Figure 79. Timer2 Block Diagram Table 183. T2LD Register T2LD is a 32-bit register load register. Table 184. T2VAL Register Table 185. T2CON Register T2CON is the configuration MMR described in Table 186.

Table 186. T2CON MMR Bit Descriptions 8 Count up. Set by user for Timer2 to count up. 7 Timer2 enable bit. Set by user to enable Timer2. Cleared by user to disable Timer2 by default. free-running mode. Default mode. 10 Hr: min: sec: Hundredths (23 hours to 0 hour). 11 Hr: min: sec: Hundredths (255 hours to 0 hour). 0000 Source Clock/1 by default.

1000 Source Clock/256 expected for Format 2 and

Table 187. T2CLRI Register clears the Timer2 interrupt. servicing to prevent it from forcing a processor reset. Figure 80. Timer3 Block Diagram Watchdog mode is entered by setting Bit 5 in the T3CON MMR. Timer3 decreases from the value present in the T3LD register to 0. value must be written to T3CLRI before the expiration period. Table 188. T3LD Register T3LD is a 16-bit register load register. Table 189. T3VAL Register Table 190. T3CON Register T3CON is the configuration MMR described in Table 191.

Table 191. T3CON MMR Bit Descriptions 8 Count up. Set by user for Timer3 to count up. 7 Timer3 enable bit. Set by user to enable Timer3. Cleared by user to disable Timer3 by default. in free-running mode. Default mode. disable watchdog mode by default. secure clear option by default. 00 Source Clock/1 by default. 11 Undefined. Equivalent to 00. Table 192. T3CLRI Register mode or resets a new timeout period in watchdog mode. register to ensure resetting the timeout period. The secure clear bit is provided for a higher level of protection. Figure 81. 8-Bit LFSR generated, even if the count has not yet expired. cannot be read; it must be tracked/generated in software.

1. Enter initial seed, 0xAA, in T3CLRI before starting Timer3
2. Enter 0xAA in T3CLRI; Timer3 is reloaded.
3. Enter 0x37 in T3CLRI; Timer3 is reloaded.
4. Enter 0x6E in T3CLRI; Timer3 is reloaded.
5. Enter 0x66. 0xDC was expected; the watchdog resets the chip.

MMR must be set to 1 to use the external port. lower 16 bits of the address are on external pins. asynchronous memory (SRAM or/and EEPROM). Table 193. External Memory Interfacing Pins in Table 194. Associated with each region are the MS[3:0] pins. in Figure 82). The four regions are configured independently. Table 194. Memory Regions MMRs: XMCFG, XMxCON, and XMxPAR.

Figure 85. External Memory Write Cycle with Address and Write Hold Cycles

1 WRITE STROBE WAIT STATE

1 ADDRESS WAIT STATE

Figure 86. External Memory Write Cycle with Wait States

split supply configuration is shown in Figure 87. Figure 87. External Dual Supply Connections the AVDD supply line as well. Figure 88. External Single Supply Connections each of these capacitors directly to the underlying ground plane. the same system ground reference point at all times. is the supply source for the internal oscillator and PLL circuits. on top of the supply causes the core to stop working. Figure 89. Recommended IOVDD Supply Filter core logic. The LVDD pin is the 2.6 V supply for the core logic. these pins) to act as a tank of charge as shown in Figure 90.

27 LVDD

28 DGND

Figure 90. Voltage Regulator Connections

the part in reset until LVDD drops below 2.35 V . Figure 94 illustrates the operation of the internal POR in detail. Figure 94. Internal Power-On Reset Operation

3 GNDREF

4 DAC0

8 TMS

9 TDI

1 C1+

3 C1–

4 C2+

5 C2–

7 T2OUT

8 R2IN

PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006. Figure 95. Typical System Configuration

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 96 of 104 DEVELOPMENT TOOLS PC-BASED TOOLS Four types of development systems are available for the ADuC7019/20/21/22/24/25/26/27/28/29 family.

• The ADuC7026 QuickStart Plus is intended for new users who want to have a comprehensive hardware development environment. Because the ADuC7026 contains the superset of functions available on the ADuC7019/20/21/22/24/25/ 26/27/28/29, it is suitable for users who wish to develop on any of the parts in this family. All parts are fully code compatible.
• The ADuC7020, ADuC7024, and ADuC7026 QuickStart systems are intended for users who already have an emulator. These systems consist of the following PC-based (Windows® compatible) hardware and software development tools. Hardware
• ADuC7019/20/21/22/24/25/26/27/28/29 evaluation board
• Serial port programming cable
• RDI-compliant JTAG emulator (included in the ADuC7026 QuickStart Plus only) Software
• Integrated development environment, incorporating assembler, compiler, and nonintrusive JTAG-based debugger
• Serial downloader software
• Example code Miscellaneous CD-ROM documentation IN-CIRCUIT SERIAL DOWNLOADER The serial downloader is a Windows application that allows the user to serially download an assembled program to the on-chip program Flash/EE memory via the serial port on a standard PC. The UART-based serial downloader is included in all the development systems and is usable with the ADuC7019/20/21/ 22/24/25/26/27/28/29 parts that do not contain the I suffix in the Ordering Guide. An I2C based serial downloader and a USB-to-I2C adaptor board, USB-EA-CONVZ, are also available at www.analog.com. The I2C-based serial downloader is only usable with the part models containing the I suffix (see Ordering Guide).

4.50 REF

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.60 MAX

Figure 96. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. Figure 97. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

7.50 REF

Figure 98. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Figure 99. 64-Lead Low Profile Quad Flat Package [LQFP]

Figure 100. 80-Lead Low Profile Quad Flat Package [LQFP] WITH THE EXCEPTION TO PACKAGE HEIGHT.

0.15 MIN

Figure 101. 64-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Figure 102. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 101 of 104 ORDERING GUIDE Model1, 2 ADC Channels3 DAC Channels FLASH/ RAM GPIO Down- loader Temperature Range Package

Description

ADuC7019BCPZ62I 5 3 62 kB/8 kB 14 I2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 ADuC7019BCPZ62I-RL 5 3 62 kB/8 kB 14 I2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 2,500 ADuC7019BCPZ62IRL7 5 3 62 kB/8 kB 14 I2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 750 ADuC7020BCPZ62 5 4 62 kB/8 kB 14 UART −40°C to +125°C 40-Lead LFCSP_WQ CP-40-9 ADuC7020BCPZ62-RL7 5 4 62 kB/8 kB 14 UART −40°C to +125°C 40-Lead LFCSP_WQ CP-40-9 750 ADuC7020BCPZ62I 5 4 62 kB/8 kB 14 I2C −40°C to +125°C 40-Lead LFCSP_WQ CP-40-9 ADuC7020BCPZ62I-RL 5 4 62 kB/8 kB 14 I2C −40°C to +125°C 40-Lead LFCSP_WQ CP-40-9 2,500 ADuC7020BCPZ62IRL7 5 4 62 kB/8 kB 14 I2C −40°C to +125°C 40-Lead LFCSP_WQ CP-40-9 750 ADuC7021BCPZ62 8 2 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 ADuC7021BCPZ62-RL 8 2 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 2,500 ADuC7021BCPZ62-RL7 8 2 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 750 ADuC7021BCPZ62I 8 2 62 kB/8 kB 13 I2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 ADuC7021BCPZ62I-RL 8 2 62 kB/8 kB 13 I2C −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 2,500 ADuC7021BCPZ32 8 2 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 ADuC7021BCPZ32-RL7 8 2 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 750 ADuC7022BCPZ62 10 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 ADuC7022BCPZ62-RL7 10 62 kB/8 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 750 ADuC7022BCPZ32 10 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 ADuC7022BCPZ32-RL 10 32 kB/4 kB 13 UART −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 2,500 ADuC7024BCPZ62 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 ADuC7024BCPZ62-RL7 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 750 ADuC7024BCPZ62I 10 2 62 kB/8 kB 30 I2C −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 ADuC7024BCPZ62I-RL 10 2 62 kB/8 kB 30 I2C −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 2,500 ADuC7024BSTZ62 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LQFP ST-64-2 ADuC7024BSTZ62-RL 10 2 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LQFP ST-64-2 1,500 ADuC7025BCPZ62 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 ADuC7025BCPZ62-RL 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 2,500 ADuC7025BCPZ32 12 32 kB/4 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 ADuC7025BCPZ32-RL 12 32 kB/4 kB 30 UART −40°C to +125°C 64-Lead LFCSP_VQ CP-64-1 2,500 ADuC7025BSTZ62 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LQFP ST-64-2 ADuC7025BSTZ62-RL 12 62 kB/8 kB 30 UART −40°C to +125°C 64-Lead LQFP ST-64-2 1,000 ADuC7026BSTZ62 12 4 62 kB/8 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 ADuC7026BSTZ62-RL 12 4 62 kB/8 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 1,000 ADuC7026BSTZ62I 12 4 62 kB/8 kB 40 I2C −40°C to +125°C 80-Lead LQFP ST-80-1 ADuC7026BSTZ62I-RL 12 4 62 kB/8 kB 40 I2C −40°C to +125°C 80-Lead LQFP ST-80-1 1,000 ADuC7027BSTZ62 16 62 kB/8 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 ADuC7027BSTZ62-RL 16 62 kB/8 kB 40 UART −40°C to +125°C 80-Lead LQFP ST-80-1 1,000 ADuC7027BSTZ62I 16 62 kB/8 kB 40 I2C −40°C to +125°C 80-Lead LQFP ST-80-1 ADuC7027BSTZ62I-RL 16 62 kB/8 kB 40 I2C −40°C to +125°C 80-Lead LQFP ST-80-1 1,000 ADuC7028BBCZ62 8 4 62 kB/8 kB 30 UART −40°C to +125°C 64-Ball CSP_BGA BC-64-4 ADuC7028BBCZ62-RL 8 4 62 kB/8 kB 30 UART −40°C to +125°C 64-Ball CSP_BGA BC-64-4 2,500 ADuC7029BBCZ62 7 4 62 kB/8 kB 22 UART −40°C to +125°C 49-Ball CSP_BGA BC-49-1 ADuC7029BBCZ62-RL 7 4 62 kB/8 kB 22 UART −40°C to +125°C 49-Ball CSP_BGA BC-49-1 4,000 ADuC7029BBCZ62I 7 4 62 kB/8 kB 22 I2C −40°C to +125°C 49-Ball CSP_BGA BC-49-1 ADuC7029BBCZ62I-RL 7 4 62 kB/8 kB 22 I2C −40°C to +125°C 49-Ball CSP_BGA BC-49-1 4,000

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet Rev. F | Page 102 of 104 Model1, 2 ADC Channels3 DAC Channels FLASH/ RAM GPIO Down- loader Temperature Range Package EVAL-ADuC7020MKZ ADuC7020 MiniKit EVAL-ADuC7020QSZ ADuC7020 QuickStart Development System EVAL-ADuC7020QSPZ ADuC7020 QuickStart Development System EVAL-ADuC7024QSZ ADuC7024 QuickStart Development System EVAL-ADuC7026QSZ ADuC7026 QuickStar Development System EVAL-ADuC7026QSPZ ADuC7026 QuickStart Plus Development System EVAL-ADuC7028QSZ ADuC7028 QuickStart Development System EVAL-ADUC7029QSZ ADuC7029 QuickStart Development System 1 Z = RoHS Compliant Part. 2 Models ADuC7026 and ADuC7027 include an external memory interface. 3 One of the ADC channels is internally buffered for ADuC7019 models.

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29 Rev. F | Page 103 of 104 NOTES

Rev. F | Page 104 of 104 NOTES I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors). ©2005-2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04955-0-5/13(F)