ADT7460ARQ-REEL

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Document overview

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Technical content

Features

• Controls and Monitors Up to 4 Fans
• 1 On-chip and 2 Remote Temperature Sensors
• Dynamic TMIN Control Mode Optimizes System Acoustics Intelligently
• Automatic Fan Speed Control Mode Controls System Cooling Based on Measured Temperature
• Enhanced Acoustic Mode Dramatically Reduces User Perception of Changing Fan Speeds
• Thermal Protection Feature via THERM Output
• Monitors Performance Impact of Intel® Pentium® 4 Processor
• Processor Thermal Control Circuit via THERM Input
• 2-wire and 3-wire Fan Speed Measurement
• Limit Comparison of All Monitored Values
• This is a Pb-Free Device

Applications

• Low Acoustic Noise PCs
• Networking and Telecommunications Equipment http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 46 of this data sheet.

ORDERING INFORMATION

QSOP−16 CASE 492 T7460ARQZ= Specific Device Code # = Pb-Free Package YY = Date Code WW = Work Week T7460A RQZ #YYWW VCCP SDA PWM1/XTO D1+ D1− D2− TACH4/ADDR SELECT/ THERM D2+ SCL GND VCC TACH3 PWM2/ SMBALERT TACH1 TACH2 PWM3/ ADDR ENABLE ADT7460 (Top View)

Figure 1. Functional Block Diagram Table 1. ABSOLUTE MAXIMUM RATINGS NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

Table 2. THERMAL CHARACTERISTICS

1. /C0113JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 3. PIN ASSIGNMENT 1 SCL Digital Input (Open-Drain). SMBus serial clock input. Requires SMBus pullup. 2 GND Ground Pin for the ADT7460. 3 VCC Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. to correctly measure a 5.0 V supply. reconfigured as an analog input (AIN3) to measure the speed of 2-wire fans. to signal out-of-limit conditions. reconfigured as an analog input (AIN1) to measure the speed of 2-wire fans. reconfigured as an analog input (AIN2) to measure the speed of 2-wire fans. Pin 9 determines the ADT7460’s slave address. reconfigured as an analog input (AIN4) to measure the speed of 2-wire fans. ADDRESS SELECT If in address select mode, this pin determines the SMBus device address. sensor. Can be used as an output to signal overtemperature conditions. 10 D2− Cathode Connection to Second Thermal Diode. 11 D2+ Anode Connection to Second Thermal Diode. 12 D1− Cathode Connection to First Thermal Diode. 13 D1+ Anode Connection to First Thermal Diode. 14 +2.5 VIN Analog Input. Monitors 2.5 V supply, typically a chipset voltage. to signal out-of-limit conditions. 16 SDA Digital I/O (Open-Drain). SMBus bidirectional serial data. Requires SMBus pullup.

Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)

1. All voltages are measured with respect to GND, unless otherwise specified. Logic inputs accept input high voltages up to VMAX even when
2. Typicals are at T A =2 5°C and represent the most likely parametric norm.
3. The delay is the time between the round robin finishing one set of measurements and starting the next.
4. Guaranteed by design; not production tested

Figure 2. Serial Bus Timing Diagram

controller for any system requiring monitoring and cooling. indicate out-of-limit conditions. is configured to monitor 2.5 V . thermal diode, may be connected. read over the serial bus to flag out-of-limit conditions.

• Two PWM Outputs for Fan Control of Up to Three Fans (the Front and Rear Chassis Fans are Connected in Parallel)
• Three TACH Fan Speed Measurement Inputs
• VCC Measured Internally Through Pin 3
• CPU Temperature Measured Using Remote 1 Temperature Channel
• Ambient Temperature Measured Through Remote 2 Temperature Channel
• Bidirectional THERM Pin. Allows Intel® Pentium® 4 PROCHOT Monitoring and Can Function as an Overtemperature THERM Output
• SMBALERT System Interrupt Output

Figure 12. Recommended Implementation

Table 5. SUMMARY INTERNAL REGISTERS Configuration These registers provide control and configuration of the ADT7460, including alternate pinout functionality. ADT7460, the first byte of data is always a register address, which is written to the address pointer register. asserts low whenever an unmasked status bit is set. along with their limit values. TMIN These registers program the starting temperature for each fan under automatic fan speed control. measured temperature and system performance. Enhance Acoustics These registers allow each PWM output controlling fan to be tweaked to enhance the system’s acoustics. state of Pin 9 then determines the device’s SMBus address. The logic state of these pins is sampled on powerup. changes in the address has no effect after this. Table 6. ADDRESS SELECT MODE

0 Low (10 k/C0087 to GND) 0101100 (0x2C)

0 High (10 k/C0087 Pullup) 0101101 (0x2D)

1 Don’t Care 0101110 (0x2E) (Default)

Figure 13. Default SMBus Address 0x2E

Figure 14. SMBus Address 0x2C (Pin 9 = 0) Figure 15. SMBus Address 0x2D (Pin 9 = 1) Figure 16. Unpredictable SMBus Address if Pin 8 CORRECT CIRCUIT IS MUXED IN AT THE CORRECT TIME.

8 FLOATING COULD CAUSE THE ADT7460 TO POWERUP WITH

than one ADT7460 is used in a system.

1. The master initiates data transfer by establishing a

master reads from the slave device.

1. Data is sent over the serial bus in sequences of

Acknowledge bit from the slave device. and slave devices can handle.

1. When all data bytes have been read or written,

during the low period before the ninth clock pulse. 10th clock pulse to assert a stop condition. changed without starting a new operation. be written to the internal data register.

Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

1. If the ADT7460’s address pointer register value is

written to the register. This is shown in Figure 18.

1. If the address pointer register is known to be

address pointer register is already at the correct value. set by the address select mode function previously defined. Rev. 2.0 for more information). instead of a stop condition to begin a new operation.

1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and

Figure 18. Writing to the Address Pointer Register Only Figure 19. Reading Data from a Previously Selected Register

1 A1 A0

read from the same address. This is illustrated in Figure 20. Figure 20. Setting a Register Address for

1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end

This is illustrated in Figure 21. Figure 21. Single-Byte Write to a Register The ADT7460 uses the following SMBus read protocols. This is useful when repeatedly reading a single register.

1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and

previously been set by a send byte or by write byte operation. Figure 22. Single-Byte Read from a Register to the host when multiple devices exist on the same bus.

1. Master initiates a read operation and sends the
2. The device whose SMBALERT
3. If more than one device’s SMBALERT
4. Once the ADT7460 has responded to the alert

the error condition has gone away. device from locking or holding the SMBus expecting data. feature, so it can be disabled. Table 7. CONFIGURATION REGISTER 1 (REG. 0X40) channel. It can also measure its own supply voltage, VCC. monitor a chipset supply voltage in computer systems.

2.25 V , but the input has built-in attenuators to allow

Table 8. VOLTAGE MEASUREMENT REGISTERS or low limit causes the appropriate status bit to be set. Table 9. 2.5 V LIMITS REGISTERS Figure 23. Structure of Analog Inputs

2.5 VIN

output codes of the 10-bit ADC. reduce noise; a measurement takes nominally 11.38 ms.

Table 10. 10-BIT A/D OUTPUT CODE VS. VIN

1. The V CC output codes listed assume that V CC is 3.3 V. If VCC input is reconfigured for 5.0 V operation (by setting Bit 7 of Configuration

Register 1), the VCC output codes are the same as for the 5.0 VIN column. ADT7460 to offer the systems designer increased flexibility. results averaged before being placed into the value register. Configuration Register 2 (Reg. 0x73) turns averaging off.

attenuators is 0 V to 2.25 V . TACH1 Minimum High Byte register (Reg. 0x55). Table 11. CONFIGURATION REGISTER 2 (REG. 0X73) Table 12. TACH1 MINIMUM HIGH BYTE (REG. 0X55)

010 VCC

sensor whose output is digitized by the on-chip 10-bit ADC. Table 13. Theoretically, the temperature sensor and ADC measurements outside this range are not possible. Pins 12 and 13, or Pins 10 and 11. q is the charge on the carrier. T is the absolute temperature in Kelvins. N is the ratio of the two currents. transistor, such as a 2N3904. Figure 24. Signal Conditioning for Diode Temperature Sensors by an internal diode at the D− input.

Table 16. TEMPERATURE OFFSET REGISTERS high or low limit causes the appropriate status bit to be set. Table 17. TEMPERATURE MEASUREMENT LIMIT (hysteresis registers). The default hysteresis value is 4°C. Figure 27. THERM Limit Operation ADT7460 to offer the systems designer increased flexibility. temperature measurement takes 1.4 ms. minimum high byte register (Reg. 0x55). Table 18. CONFIGURATION REGISTER 2 (REG. 0X73) Table 19. TACH1 MINIMUM HIGH BYTE (REG. 0X55)

101 Remote 1 Temp

110 Local Temp

111 Remote 2 Temp

out-of-limit condition and detected by polling the device. The following is a list of 8-bit limits on the ADT7460. Table 20. VOLTAGE LIMIT REGISTERS

Figure 31. Temperature > High Limit: INT Occurs the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). monitoring cycle time is important, it can easily be calculated. 25.5 ms for each remote temperature reading. channels are measured approximately every 120 ms. synchronized with the analog measurements in any way. Table 24. STATUS REGISTER 1 (REG. 0X41)

7 OOL 1 denotes a bit in Status Register 2 is set

and Status Register 2 should be read.

6 R2T 1 indicates that the Remote 2

5 LT 1 indicates that the Local temperature

high or low limit has been exceeded.

4 R1T 1 indicates that the Remote 1

2 VCC 1 indicates that the VCC high or low

Figure 33. Status Register 2 Table 25. STATUS REGISTER 2 (REG. 0X42)

7 D2 1 indicates an open or short on

6 D1 1 indicates an open or short on

5 F4P 1 indicates that Fan 4 has dropped

4 FAN3 1 indicates that Fan 3 has dropped

3 FAN2 1 indicates that Fan 2 has dropped

2 FAN1 1 indicates that Fan 1 has dropped

1 OVT 1 indicates that a THERM

bits behave when writing interrupt handler software. Figure 34. SMBALERT and Status Bit Behavior has implications on how software handles the interrupt.

1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
4. Mask the interrupt source by setting the
5. Take the appropriate action for a given interrupt
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the

Figure 35. How Masking the Interrupt Source Affects

Table 26. INTERRUPT MASK REGISTER 1

7 OOL 1 masks SMBALERT for any alert

condition flagged in Status Register 2.

6 R2T 1 masks SMBALERT for Remote 2

5 LT 1 masks SMBALERT for local

4 R1T 1 masks SMBALERT for Remote 1

2 VCC 1 masks SMBALERT for the VCC

Table 27. INTERRUPT MASK REGISTER 2 7 D2 1 masks SMBALERT for Diode 2 errors. 6 D1 1 masks SMBALERT for Diode 1 errors. 4 FAN3 1 masks SMBALERT for Fan 3. 3 FAN2 1 masks SMBALERT for Fan 2. 2 FAN1 1 masks SMBALERT for Fan 1.

1 OVT 1 masks SMBALERT for

output to signal out-of-limit conditions. Table 28. CONFIGURATION REGISTER 4 (REG. 0X7D) Table 29. CONFIGURATION REGISTER 3 (REG. 0X78) THERM, see the Generating Interrupts from Events sections. THERM pin is driven low externally, the fans run at 100%. The fans run at 100% while the THERM pin is pulled low. effect. See Figure 36 for more information. Figure 36. Asserting THERM Low as an Input in at that reading until cleared.

Figure 38. Functional Diagram of the ADT7460 THERM Monitoring Circuitry

1. Configure the THERM input.
2. Select the desired fan behavior for THERM events.
3. Select whether THERM events should generate
4. Select a suitable THERM limit value.

to be generated on the first THERM assertion.

1. Select a THERM monitoring time.

determine the cumulative THERM assertion time. being exceeded, another time-stamp can be taken. remain low for at least one monitoring cycle.

event of a critical overtemperature. Figure 39. Asserting THERM as an Output, Based on MOSFET needs to handle the higher current requirements. maximum operating speed of the fan. Figure 40. Driving a 3-wire Fan Using an N-channel

12 V12 V

to ensure that it meets the fan’s current requirements. transistor is saturated when the fan is powered on. Figure 41. Driving a 3-wire Fan Using connecting another fan directly in parallel with the first. 8 mA maximum current specified on the data sheet. synchronized to PWM3, so PWM3 can drive two fans.

Figure 46. Planning for 2-wire or 3-wire Fans slow rise and fall times typical of fan tachometer outputs. must be included to keep inputs within an acceptable range. be connected directly to the fan input, as shown in Figure 47. Figure 47. Fan with TACH Pullup to VCC

12 V VCC

Zener. A value of between 3 V and 5.0 V is suitable. Figure 48. Fan with TACH Pullup to Voltage . 5.0 V, calculating resistor values. 47 k/C0087. This gives a high input voltage of 3.83 V . Figure 49. Fan with Strong TACH. Pullup to > VCC or

5.0 V or12 V

Figure 50. Fan with Strong TACH. Pullup to > VCC or

inversely proportional to the fan speed. Figure 51. Fan Speed Measurement of a 2-byte read from the ADT7460. Table 31. FAN SPEED MEASUREMENT REGISTERS (assuming two pulses per revolution are being counted). running very slowly (<100 RPM). limit registers are 16-bit values consisting of two bytes. Table 32. FAN TACH LIMIT REGISTERS associated dc bit in Configuration Register 3 should be set. basis for fans connected directly to a dc source.

lowest ripple determines the correct pulses/revolution value. Table 33. FAN PULSES/REVOLUTION REGISTER Table 34. FAN PULSES/REVOLUTION REGISTER reprogrammed as analog inputs, AIN. Table 35. CONFIGURATION REGISTER 2 (REG. 0X73)

3 AIN4 1 indicates that Pin 9 is reconfigured to

2 AIN3 1 indicates that Pin 4 is reconfigured to

1 AIN2 1 indicates that Pin 7 is reconfigured to

0 AIN1 1 indicates that Pin 6 is reconfigured to

threshold for the AIN signal. Table 36. CONFIGURATION REGISTER 4 (REG. 0X7D) than fans programmed to spinup for a given spin-up time. Table 37. PWM1 TO PWM3 CONFIGURATION Table 38. PWM1 TO PWM3 CONFIGURATION frequency for PWM1 to PWM3, respectively.

Table 39. PWM1 TO PWM3 FREQUENCY REGISTERS Fan Speed Control Loop Application Note. control, which is described next. Table 40. PWM1 TO PWM3 CONFIGURATION (PWMx current duty cycle registers). Figure 52. Control PWM Duty Cycle Manually with a Table 41. PWM DUTY CYCLE REGISTERS speed control mode or in acoustic enhancement mode.

the XNOR tree test enable register (Reg. 0x6F). Figure 53. XNOR Tree Test to 100 (fans run full speed) by default. Table 42. ADT7460 REGISTERS

Table 43. VOLTAGE READING REGISTERS (POWER-ON DEFAULT = 0X00) (Note 1)

1. These voltage readings are in twos complement format. If the extended resolution bits of these readings are also being read, the extended

registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. Table 44. TEMPERATURE READING REGISTERS (POWER-ON DEFAULT = 0X80) (Note 1) 0x26 Read-only Local temperature reading (8 MSBs of reading). 0x27 Read-only Remote 2 temperature reading (8 MSBs of reading).

1. These voltage readings are in twos complement format.
2. Note that a reading of 0x80 in a temperature reading register indicates a diode fault (open or short) on that channel. If the extended resolution

Table 45. FAN TACHOMETER READING REGISTERS (POWER-ON DEFAULT = 0X00) (Note 1)

1. The Fan Tachometer Reading registers count the number of 11.11 /C0109s periods (based on an internal 90 kHz clock) that occur between a

occurring while the fans are spinning up.

• Stalled or blocked (object jamming the fan).
• Failed (internal circuitry destroyed).
• Not populated. (The ADT7460 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low byte should be set to 0xFFFF.)
• Alternate function, for example, TACH4 reconfigured as a THERM pin.
• 2-wire Instead of 3-wire Fan

Table 46. CURRENT PWM DUTY CYCLE REGISTERS (POWER-ON DEFAULT = 0XFF) (Note 1) 0x30 R/W PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF). 0x31 R/W PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF). 0x32 R/W PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF).

1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7460

cycle value by writing to these registers. Table 47. OPERATING POINT REGISTERS (POWER-ON DEFAULT = 0X64) (Note 1)

1. These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers

fans being controlled are adjusted to maintain temperature about an operating point.

Table 48. REGISTER 0X36 − DYNAMIC TMIN CONTROL REGISTER 1 (POWER-ON DEFAULT = 0X00) (Note 1) of fans and the control loop. <1> Reserved Read-only Reserved for future use. register reflects its programmed value. point register reflects its programmed value. register reflects its programmed value. channel behaves as described in the Automatic Fan Control section. behaves as described in the Automatic Fan Control section. channel behaves as described in the Automatic Fan Control section.

1. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 49. REGISTER 0X37 − DYNAMIC TMIN CONTROL REGISTER 2 (POWER-ON DEFAULT = 0X00) (Note 1) response of fans and the control loop.

8 Cycles (1 s)

16 Cycles (2 s)

32 Cycles (4 s)

64 Cycles (8 s)

128 Cycles (16 s)

256 Cycles (32 s)

512 Cycles (64 s)

1024 Cycles (128 s)

be found to optimize the response of fans and the control loop. to optimize the response of fans and the control loop.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 50. REGISTER 0X40 − CONFIGURATION REGISTER 1 (POWER-ON DEFAULT = 0X00) <0> STRT R/W Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed. <4> RES Read-only Reserved for future use. entire fan spin-up timeout selected. <7> VCC R/W When set to 1, the ADT7460 rescales its VCC pin to measure a 5.0 V supply. Table 51. REGISTER 0X41 − INTERRUPT STATUS REGISTER 1 (POWER-ON DEFAULT = 0X00) the status register only if the error condition has subsided. <1> RES Read-only Reserved for future use. the status register only if the error condition has subsided. <3> RES Read-only Reserved for future use. cleared on a read of the status register only if the error condition has subsided. read of the Status Register only if the error condition has subsided. cleared on a read of the status register only if the error condition has subsided.

Table 52. REGISTER 0X42 − INTERRUPT STATUS REGISTER 2 (POWER-ON DEFAULT = 0X00) <0> RES Read-only Reserved for future use. cleared on a read of the status register when the temperature drops below THERM − THYST. when the PWM1 output is off. when the PWM2 output is off. when the PWM3 output is off. when the PWM3 output is off. THERM assertion time exceeds the limit programmed in the THERM Limit Register (Reg. 0x7A). <6> D1 Read-only A 1 indicates either an open or short circuit on the Thermal Diode 1 inputs. <7> D2 Read-only A 1 indicates either an open or short circuit on the Thermal Diode 2 inputs. Table 53. VOLTAGE LIMIT REGISTERS (Note 1)

1. Setting the Configuration Register 1 lock bit has no effect on these registers.
2. High limits: an interrupt is generated when a value exceeds its high limit (> comparison); low limits: an interrupt is generated when a value

is equal to or below its low limit (≤ comparison). Table 54. TEMPERATURE LIMIT REGISTERS (Note 1)

1. Exceeding any of these temperature limits by 1 °C causes the appropriate status bit to be set in the interrupt status register. Setting the

Configuration Register 1 lock bit has no effect on these registers.

1. High limits: an interrupt is generated when a value exceeds its high limit (> comparison); low limits: an interrupt is generated when a value

is equal to or below its low limit (≤ comparison). Table 55. FAN TACHOMETER LIMIT REGISTERS (POWER-ON DEFAULT = 0XFF) (Note 1)

1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate s tatus bit is set

in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.

Table 56. PWM CONFIGURATION REGISTERS (POWER-ON DEFAULT = 0X62) (Note 1)

1. These registers become read-only when the Configuration Register1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.

Table 57. PWM CONFIGURATION REGISTER BITS contains 0xFFFF or 0x0000, the Status Register 2 bit is not set, even if the fan has not started. <3> SLOW R/W SLOW = 1 makes the ramp rates for acoustic enhancement four times longer. <7:5> BHVR R/W These bits assign each fan to a particular temperature sensor for localized cooling. 000 = Remote 1 temperature controls PWMx (automatic fan control mode). 001 = Local temperature controls PWMx (automatic fan control mode). 010 = Remote 2 temperature controls PWMx (automatic fan control mode). 011 = PWMx runs full speed (default). 101 = Fastest speed calculated by Local and Remote 2 Temperature Control PWMx. 110 = Fastest speed calculated by all three Temperature Channels Control PWMx. 111 = Manual mode. PWM duty cycle registers (Reg. 0x30–0x32) become writable. Table 58. TEMP TRANGE/PWM FREQUENCY REGISTERS (POWER-ON DEFAULT = 0XC4) (Note 1)

1. These registers become read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to the is register have no effect.

Table 59. TEMP TRANGE/PWM FREQUENCY REGISTER BITS <2:0> FREQ R/W These bits control the PWMx frequency. one monitoring cycle. This allows clock modulation of devices that incorporate this feature. monitoring, when Pin 9 is configured as THERM. <7:4> RANGE R/W These bits determine the PWM duty cycle vs. temperature slope for automatic fan control.

Table 60. REGISTER 0X62 − ENHANCED ACOUSTICS REGISTER 1 (POWER-ON DEFAULT = 0X00) (Note 1) by these bits. This feature enhances the acoustics of the fan being driven by the PWM1 output. <3> EN1 R/W When this bit is 1, acoustic enhancement is enabled on PWM1 output. <4> SYNC R/W SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to be measured. SYNC = 0, only TACH3 and TACH4 are synchronized to PWM3 output. its TMIN − Hysteresis value.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 61. REGISTER 0X63 − ENHANCED ACOUSTICS REGISTER 2 (POWER-ON DEFAULT = 0X00) (Note 1) by these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output. <3> EN3 R/W When this bit is 1, acoustic enhancement is enabled on PWM3 output. by these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output. <7> EN2 R/W When this bit is 1, acoustic enhancement is enabled on PWM2 output.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 62. PWM MIN DUTY CYCLE REGISTERS (Note 1)

1. These registers become read-only when the ADT7460 is in automatic fan control mode.

Table 63. PWM MIN DUTY CYCLE REGISTER BITS R/W These bits define the PWMMIN duty cycle for PWMx. Table 64. TMIN REGISTERS (Note 1)

1. These registers become read-only when the Configuration Register1 lock bit is set. Further attempts to write to these registers have no effect.
2. These are the T MIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at

minimum speed and increase with temperature according to TRANGE. Table 65. THERM LIMIT REGISTERS (Note 1)

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.
2. If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism

Table 66. TEMPERATURE HYSTERESIS REGISTERS (Note 1)

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.
2. Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that

drops below THERM – Hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN.

Table 67. XNOR TREE TEST ENABLE REGISTER (POWER-ON DEFAULT = 0X00) (Note 1) <0> XEN If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit removes the device from the XNOR test mode. <7:1> RES Unused. Do not write to these bits.

1. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 68. REMOTE 1 TEMPERATURE OFFSET REGISTER (POWER-ON DEFAULT = 0X00) (Note 1) PCB trace resistance. LSB value = 0.25°C.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 69. LOCAL TEMPERATURE OFFSET REGISTER (POWER-ON DEFAULT = 0X00) (Note 1) temperature reading. LSB value = 0.25°C.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 70. REMOTE 2 TEMPERATURE OFFSET REGISTER (POWER-ON DEFAULT = 0X00) (Note 1) PCB trace resistance. LSB value = 0.25°C.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 71. REGISTER 0X73 − CONFIGURATION REGISTER 2 (POWER-ON DEFAULT = 0X00) (Note 1) coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D). measurements on each channel to be made much faster. for other functions such as connecting up external sensors. selected by writing to Bits <7:5> of TACH1 min high byte register (Reg. 0x55). 0x00 to indicate that the fans are not being driven.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 72. REGISTER 0X74 − INTERRUPT MASK REGISTER 1 (POWER-ON DEFAULT <7:0> = 0X00) 0 2.5V R/W A 1 masks SMBALERT for out-of-limit conditions on the 2.5 V channel. 1 RES R/W Reserved for future use. 2 VCC R/W A 1 masks SMBALERT for out-of-limit conditions on the VCC channel. 3 RES R/W Reserved for future use. 4 R1T R/W A 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel. 5 LT R/W A 1 masks SMBALERT for out-of-limit conditions on the Local temperature channel. 6 R2T R/W A 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel. 7 OOL R/W A 1 masks SMBALERT for any out-of-limit condition in Status Register 2.

Table 73. REGISTER 0X75 − INTERRUPT MASK REGISTER 2 (POWER-ON DEFAULT = 0X00) 0 RES R/W Reserved for future use. 1 OVT Read-only A 1 masks SMBALERT for overtemperature THERM conditions. 2 FAN1 R/W A 1 masks SMBALERT for a Fan 1 fault. 3 FAN2 R/W A 1 masks SMBALERT for a Fan 2 fault. 4 FAN3 R/W A 1 masks SMBALERT for a Fan 3 fault. this bit masks SMBALERT for a THERM timer event. 6 D1 R/W A 1 masks SMBALERT for a diode open or short on Remote 1 channel. 7 D2 R/W A 1 masks SMBALERT for a diode open or short on Remote 2 channel. Table 74. REGISTER 0X76 − EXTENDED RESOLUTION REGISTER 1 <3:2> RES R/W Reserved for future use. <5:4> VCC Read-only VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement. <7:6> RES R/W Reserved for future use.

1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

Table 75. REGISTER 0X77 − EXTENDED RESOLUTION REGISTER 2 (Note 1) <1:0> RES R/W Reserved for future use. <5:4> LTMP Read-only Local Temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.

1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

Table 76. REGISTER 0X78 − CONFIGURATION REGISTER 3 (POWER-ON DEFAULT = 0X00) (Note 1) indicate out-of-limit error conditions. timer can be triggered to time how long THERM has been asserted for. <2> BOOST R/W BOOST = 1, assertion of THERM causes all fans to run at 100% duty cycle for fail-safe cooling. measurement rate from once per second, to once every 250 ms (4×). <4> DC1 R/W DC1 = 1 enables TACH measurements to be continuously made on TACH1. <5> DC2 R/W DC2 = 2 enables TACH measurements to be continuously made on TACH2. <6> DC3 R/W DC3 = 1 enables TACH measurements to be continuously made on TACH3. <7> DC4 R/W DC4 = 1 enables TACH measurements to be continuously made on TACH4.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 77. REGISTER 0X79 − THERM STATUS REGISTER (POWER-ON DEFAULT = 0X00) Table 78. REGISTER 0X7A − THERM LIMIT REGISTER (POWER-ON DEFAULT = 0X00) Table 79. REGISTER 0X7B − FAN PULSES PER REVOLUTION REGISTER (POWER-ON DEFAULT = 0X55) fan’s pulses per revolution for unknown fan type. fan’s pulses per revolution for unknown fan type. fan’s pulses per revolution for unknown fan type. fan’s pulses per revolution for unknown fan type. Table 80. REGISTER 0X7D − CONFIGURATION REGISTER 4 (POWER-ON DEFAULT = 0X00) (Note 1) indicate out-of-limit error conditions. AL2.5V = 0, Pin 14 (2.5 V/SMBALERT) is configured as a 2.5 V measurement input.

1. This regi ster becomes read-only when the Configuration Register1 lock bit is set to 1. Further attempts to write to this register have no effect.

Table 81. REGISTER 0X7E − MANUFACTURER’S TEST REGISTER 1 (POWER-ON DEFAULT = 0X00) should NOT be written to under normal operation. Table 82. REGISTER 0X7F − MANUFACTURER’S TEST REGISTER 2 (POWER-ON DEFAULT = 0X00) should NOT be written to under normal operation. Table 83. ORDERING INFORMATION Specifications Brochure, BRD8011/D. *The “Z’’ suffix indicates Pb−Free part.

http://onsemi.com PACKAGE DIMENSIONS QSOP16 CASE 492−01 ISSUE A E M0.25 C C DETAIL A DETAIL A h x 45/C0095 DIM MAXMIN INCHES A 0.053 0.069 b 0.008 0.012 L 0.016 0.050 e 0.025 BSC h 0.009 0.020 c 0.007 0.010 A1 0.004 0.010 M 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.005 PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.005 PER SIDE. D AND E1 ARE DETERMINED AT DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. /C0095/C0095 b L 6.40 16X 0.42 16X 1.12 0.635 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* D D 16X SEATING PLANE 0.10 C A A-B D 0.20 C e 16 9 16X C M D 0.193 BSC E 0.237 BSC E1 0.154 BSC L2 0.010 BSC D

0.25 C D

B

0.20 C D

0.10 C H

C A2 0.049 ---- 1.35 1.75 0.20 0.30 0.40 1.27

0.635 BSC

0.22 0.50 0.19 0.25 0.10 0.25 0 8 /C0095/C0095

4.89 BSC

6.00 BSC

3.90 BSC

0.25 BSC

1.24 ---- MAXMIN MILLIMETERS A SEATING PLANE *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a numb er of patents, trademarks, reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 ADT7460/D Pentium is a registered trademark of Intel Corporation. LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative