ADT7317ARQ-REEL

ADT7318ARQZ AD | Alldatasheet

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±0.5°C Accurate Digital Temperature Sensor and Quad Voltage Output 12-/10-/8-Bit DACs ADT7316/ADT7317/ADT7318 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.

FEATURES

ADT7316—four 12-bit DACs ADT7317—four 10-bit DACs ADT7318—four 8-bit DACs Buffered voltage output Guaranteed monotonic by design over all codes 10-bit temperature-to-digital converter Temperature range: −40°C to +120°C Temperature sensor accuracy of ±0.5°C Supply range: 2.7 V to 5.5 V DAC output range: 0 V to 2 V REF Power-down current : <10 μA Internal 2.28 V REF option Double-buffered input logic Buffered/unbuffered reference input option Power-on reset to 0 V Simultaneous update of outputs (LDAC function) On-chip rail-to-rail output buffer amplifier I 2C®-, SMBus-, SPI®-, QSPI™-, MICROWIRE™-, and DSP- compatible 4-wire serial interface SMBus packet error checking (PEC) compatible 16-lead QSOP

APPLICATIONS

Portable battery-powered instruments Personal computers Telecommunications systems Electronic test equipment Domestic appliances Process control PIN CONFIGURATION VOUT-A VREF-AB CS VDD GND VOUT-B VOUT-D VREF-CD SCL/SCLK INT/INT D– LDAC DOUT/ADD SDA/DIN VOUT-C TOP VIEW (Not to Scale) ADT7316/ ADT7317/ ADT7318 02661-006 Figure 1. GENERAL DESCRIPTION The ADT7316/ADT7317/ADT73181combine a 10-bit temperature-to-digital converter and a quad 12-/10-/8-bit DAC, respectively, in a 16-lead QSOP . This includes a band gap temperature sensor and a 10-bit ADC to monitor and digitize the temperature reading to a resolution of 0.25°C. The ADT7316/ ADT7317/ADT7318 operate from a single 2.7 V to 5.5 V supply. The output voltage of the DAC ranges from 0 V to 2 V REF, with an output voltage settling time of 7 μs typically. The ADT7316/ ADT7317/ADT7318 provide two serial inter- face options, a 4-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards, and a 2-wire SMBus/I 2C interface. They feature a standby mode that is controlled via the serial interface. The reference for the four DACs is derived either internally or from two reference pins (one per DAC pair). The outputs of all DACs may be updated simultaneously using the software LDAC function or external LDAC pin. The ADT7316/ADT7317/ ADT7318 incorporate a power-on-reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The ADT7316/ADT7317/ADT7318 wide supply voltage range, low supply current, and SPI-/I2C-compatible interface make them ideal for a variety of applications, including personal computers, office equipment, and domestic appliances. 1 Protected by the following U.S. patent numbers: 5,764,174; 5,867,012;

Rev. B | Page 2 of 44 TABLE OF CONTENTS

REVISION HISTORY

1/07—Rev. A to Rev. B Changes to Internal T HIGH Limit Register (Read/Write) Changes to Internal TLOW Limit Register (Read/Write) Changes to External THIGH Limit Register (Read/Write) External T LOW Limit Register (Read/Write) [Address 0x28] 6/04—Rev. 0 to Rev. A U 8/03—Revision 0: Initial Version

Rev. B | Page 3 of 44 SPECIFICATIONS Table 1. Parameter1 Min Typ Max Unit Conditions/Comments DAC DC PERFORMANCE2 , 3 ADT7318 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic over all codes. ADT7317 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic over all codes. ADT7316 Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Differential Nonlinearity ±0.02 ±0.9 LSB Guaranteed monotonic over all codes. Offset Error ±0.4 ±2 % of FSR Gain Error ±0.4 ±2 % of FSR Lower Dead Band 20 65 mV Lower dead band exists only if offset error is negative. See Figure 2. Upper Dead Band 60 100 mV Upper dead band exists if VREF = VDD and offset plus gain error is positive. See Figure 3. Offset Error Drift −12 ppm of FSR/°C Gain Error Drift −5 ppm of FSR/°C DC Power Supply Rejection Ratio −60 dB ∆VDD = ±10%. DC Crosstalk 200 μV See Figure 6. THERMAL CHARACTERISTICS INTERNAL TEMPERATURE SENSOR Internal reference used. Averaging on. Accuracy at VDD = 3.3 V ±10% ±1.5 °C TA = 85°C. Accuracy at VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C. Resolution 10 Bits Equivalent to 0.25°C. Long-Term Drift 0.25 °C Drift over 10 years if part is operated at 55°C. EXTERNAL TEMPERATURE SENSOR External transistor = 2N3906. Accuracy at VDD = 3.3 V ±10% ±1.5 °C TA = +85°C. ±3 °C TA = 0°C to +85°C. ±5 °C TA = −40°C to +120°C. Accuracy at VDD = 5 V ±5% ±2 ±3 °C TA = 0°C to +85°C. Resolution 10 Bits Equivalent to +0. 25°C. Output Source Current 180 μA High level. 11 μA Low lev el. Thermal Voltage Output 8-Bit DAC Output Resolution 1 °C Scale Factor 8.79 mV/°C 0 V to VREF output. TA = −40°C to +120°C. 17.58 mV/°C 0 V to 2 VREF output. TA = −40°C to +120°C. 10-Bit DAC Output Resolution 0.25 °C Scale Factor 2.2 mV/°C 0 V to VREF output. TA = −40°C to +120°C. 4.39 mV/°C 0 V to 2 VREF output. TA= −40°C to +120°C.

Rev. B | Page 4 of 44 Parameter1 Min Typ Max Unit Conditions/Comments CONVERSION TIMES Single channel mode. Slow ADC VDD 11.4 ms Averaging (16 samples) on. 712 μs Averaging off. Internal Temperature 11.4 ms Averaging (16 samples) on. 712 μs Averaging off. External Temperature 24.22 ms Averaging (16 samples) on 1.51 ms Averaging off. Fast ADC VDD 712 μs Averaging (16 samples) on. 44.5 μs Averaging off. Internal Temperature 2.14 ms Averaging (16 samples) on. 134 μs Averaging off. External Temperature 14.25 ms Averaging (16 samples) on. 890 μs Averaging off. ROUND ROBIN UPDATE RATE4 Time to complete one measurement cycle through al l channels. Slow ADC at 25°C 59.95 ms Averaging on. 6.52 ms Averaging off. Fast ADC at 25°C 19.59 ms Averaging on. 2.89 ms Averaging off. DAC EXTERNAL REFERENCE INPUT5 VREF Input Range 1 VDD V Buffered reference mode. VREF Input Range 0.25 VDD V Unbuffered reference mode. VREF Input Impedance 37 45 kΩ Unbuffered reference mode. 0 V to 2 VREF output range. 74 90 kΩ Unbuffered reference mode. 0 V to VREF output range. >10 MΩ Buffered reference mode and power-down mode. Reference Feedthrough −90 dB Frequency = 10 kHz. Channel-to-Channel Isolation −75 dB Frequency = 10 kHz. ON-CHIP REFERENCE Reference Voltage5 2.2662 2.28 2.2938 V Temperature Coefficient5 80 ppm/°C OUTPUT CHARACTERISTICS5 Output Voltage6 0.001 VDD to 0.001 V This is a measure of the minimum and maximum drive capability o f the output amplifier. DC Output Impedance 0.5 Ω Short-Circuit Current 25 mA VDD = 5 V. 16 mA VDD = 3 V. Power-Up Time 2.5 μs Coming out of power-down mode. VDD = 5 V. 5 μs Coming out of power-down mode. VDD = 3.3 V. DIGITAL INPUTS5 Input Current ±1 μA VIN = 0 V to VDD. Input Low Voltage, VIL 0.8 V Input High Voltage, VIH 1.89 V Pin Capacitance 3 10 pF All dig ital inputs. SCL, SDA Glitch Rejection 50 ns Input filtering suppresses noise spikes of less than ns. LDAC Pulse Width 20 ns Edge triggered input.

Rev. B | Page 5 of 44 Parameter1 Min Typ Max Unit Conditions/Comments DIGITAL OUTPUT Output High Voltage, VOH 2.4 V I SOURCE = ISINK = 200 μA. Output Low Voltage, VOL 0.4 V I OL = 3 mA. Output High Current, IOH 1 mA V OH = 5 V. Output Capacitance, COUT 50 pF INT/INT Output Saturation Voltage 0.8 V I OUT = 4 mA. I2C TIMING CHARACTERISTICS7, 8 Serial Clock Period, t1 2.5 μs Fast-mode I2C. See Figure 4. Data In Setup Time to SCL High, t2 50 ns Data Out Stable After SCL Low, t3 0 ns See Figure 4. SDA Low Setup Time to SCL Low (Start Condition), t4 50 ns See Figure 4. SDA High Hold Time After SCL High (Stop Condition), t5 50 ns See Figure 4. SDA and SCL Fall Time, t6 300 ns See Figure 4. SDA and SCL Rise Time, t6 300 9 ns See Figure 4. SPI TIMING CHARACTERISTICS10, 11 CS to SCLK Setup Time, t1 0 ns See Figure 7. SCLK High Pulse Width, t2 50 ns See Figure 7. SCLK Low Pulse Width, t3 50 ns See Figure 7. Data Access Time After SCLK Falling Edge, t412 35 ns See Figure 7. Data Setup Time Prior to SCLK Rising Edge, t5 20 ns See Figure 7. Data Hold Time after SCLK Rising Edge, t6 0 ns See Figure 7. CS to SCLK Hold Time, t7 0 ns See Figure 7. CS to DOUT High Impedance, t8 40 ns See Figure 7. POWER REQUIREMENTS VDD 2.7 5.5 V VDD Settling Time 50 ms VDD settles to within 10% of its final voltage level. IDD (Normal Mode)13 3 mA V DD = 3.3 V, VIH = VDD, and VIL = GND. 2.2 3 mA VDD = 5 V, VIH = VDD , and VIL = GND. IDD (Power-Down Mode) 10 μA VDD = 3.3 V, VIH = VDD, and VIL = GND. 10 μA VDD = 5 V, VIH = VDD, and VIL = GND. Power Dissipation 10 mW VDD = 3.3 V, using normal mode. 33 μW VDD = 3.3 V, using shutdown mode. 1 See the Terminology section. 2 DC specifications tested with the outputs unloaded. 3 Linearity is tested using a reduced code range: ADT7316 (Code 115 to 4095); ADT7317 (Code 28 to 1023); ADT7318 (Code 8 to 255). 4 A round robin is the continuous sequential measurement of the following three channels: VDD, internal temperature, and external temperature. 5 Guaranteed by design and characterization, but not production tested. 6 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD, offset plus gain error must be positive. 7 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate, but has a negative effect on the EMC behavior of the part. 8 Guaranteed by design. Not tested in production. 9 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns. 10 Guaranteed by design and characterization, but not production tested. 11 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 12 Measured with the load circuit of Figure 5. 13 IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Rev. B | Page 8 of 44 FUNCTIONAL BLOCK DIAGRAM VDD VALUE REGISTER EXTERNAL TEMPERATURE VALUE REGISTER A-TO-D CONVERTER INTERNAL TEMPERATURE VALUE REGISTER ON-CHIP TEMPERATURE SENSOR ANALOG MUX DIG IT AL M UX LIMIT COMPARATOR DIG IT AL M UX DAC A REGISTERS DAC B REGISTERS DAC C REGISTERS DAC D REGISTERS GAIN SELECT LOGIC POWER- DOWN LOGIC SMBus/SPI INTERFACE CS SCL/SCLK SDA/DIN DOUT/ADD INT/INTSTATUS REGISTERS VDD SENSOR VDD GND INTERNAL REFERENCE VREF-AB VREF-CDLDAC 6 5 4 13 12 11 9 3 14 VOUT-D15 VOUT-C16 VOUT-B1 VOUT-A2STRING DAC A STRING DAC B STRING DAC C STRING DAC D ADT7316/ ADT7317/ ADT7318 ADDRESS POINTER REGISTER THIGH LIMIT REGISTERS TLOW LIMIT REGISTERS VDD LIMIT REGISTERS CONTROL CONFIG. 1 REGISTER CONTROL CONFIG. 3 REGISTER CONTROL CONFIG. 2 REGISTER DAC CONFIGURATION REGISTER LDAC CONFIGURATION REGISTER INTERRUPT MASK REGISTERS 02661-001 Figure 8.

Rev. B | Page 9 of 44 DAC AC CHARACTERISTICS Guaranteed by design and characterization, but not production tested. VDD = 2.7 V to 5.5 V; RL = 4.7 kΩ to GND; CL = 200 pF to GND; 4.7 kΩ to VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 Min Typ (@ 25°C) Max Unit Conditions and Comments Output Voltage Settling Time VREF = VDD = +5 V. ADT7318 6 8 μs 1/4 scale to 3/4 scale change (0 x40 to 0xC0). ADT7317 7 9 μs 1/4 scale to 3/4 scale change (0 x100 to 0x300). ADT7316 8 10 μs 1/4 scale to 3/4 scale change (0 x400 to 0xC00). Slew Rate 0.7 V/μs Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry. Digital Feedthrough 0.5 Digital Crosstalk 1 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p. Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz. See Terminology section.

1 Values relate to package being used on a 4-layer board.

2 Junction-to-case resistance is applicable to components featuring a

Table 4. I

Figure 9. Pin Configuration QSOP Table 5. Pin Function Descriptions 1 V OUT-B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 2 V OUT-A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. AC B. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. DAC A and DAC B default on power-up to this pin. 5 GND Ground Reference Point for All Circuitry on the Part. Analog and digital ground. 6 V DD Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground. 7 D+ Positive connection to external temperature sensor. 8 D− Negative connection to external temperature sensor. simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin. Default is with the LDAC pin controlling the loading of DAC registers. temperature or VDD limits are exceeded. Default is active low. Open-drain output—needs a pull-up resistor. the falling edge of SCLK. Open-drain output—needs a pull-up resistor. affect on the I2C serial bus address. drain configuration—needs a pull-up resistor. clocked into a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor. configuration; needs a pull-up resistor. AC D. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. DAC C and DAC D default, on power-up, to this pin. 15 VOUT-D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 16 VOUT-C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Rev. B | Page 12 of 44 TERMINOLOGY Relative Accuracy Relative accuracy or integral nonlinearity (INL) is a measure of t he maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 10, Figure 11, and Figure 12. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured cha nge and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±0.9 LSB maximum ensures monotonicity. Typical DAC DNL vs. code plots can be seen in Figure 13, Figure 14, and Figure 15. Offset Error This is a measure of the offset error of the DAC and the output a mplifier (see Figure 2 and Figure 3). It can be negative or p ositive. It is expressed as a percentage of the full-scale range. Gain Error This is a measure of the span error of the DAC. It is the devia- t ion in slope of the actual DAC transfer characteristic from the ideal. It is expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in t emperature. It is expressed in ppm of full-scale range/°C. Gain Error Drift This is a measure of the change in gain error with changes in t emperature. It is expressed in ppm of full-scale range/°C. Long T erm T emperature Drift This is a measure of the change in temperature error with the p assage of time. It is expressed in degrees Celsius. The concept of long term stability has been used for many years to describe by what amount an IC’s parameter would shift during its lifetime. This is a concept that has been typically applied to both voltage references and monolithic temperature sensors. Unfortunately, integrated circuits cannot be evaluated at room temperature (25°C) for 10 years or so to determine this shift. As a result, manufacturers very typically perform accelerated lifetime testing of integrated circuits by operating ICs at elevated tem- peratures (between 125°C and 150°C) over a shorter period of time (typically between 500 and 1000 hours). As a result of this operation, the lifetime of an integrated circuit is significantly accelerated due to the increase in rates of reaction within the semiconductor material. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes i n the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VREF is held at 2 V and VDD is varied ±10%. DC Crosstalk This is the dc change in the output level of one DAC in response t o a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in microvolts. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to t he reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels. Channel-to-Channel Isolation This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in decibels. Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse i njected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011…11 to 100…00 or 100...00 to 011…11). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into t he analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to. It is specified in nV-s and is measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC a t midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC d ue to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC d ue to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s.

Rev. B | Page 13 of 44 Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The m ultiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion This is the difference between an ideal sine wave and its a ttenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. Round Robin This term is used to describe the ADT7316/ADT7317/ ADT7318 cycling through the available measurement channels in sequence, taking a measurement on each channel. DAC Output Settling Time This is the time required, following a prescribed data change, fo r the output of a DAC to reach and remain within ±0.5 LSB of the final value. A typical prescribed change is from 1/4 scale to 3/4 scale.

0.25 INL WCP

Figure 16. ADT7318 INL Error and DNL Error vs. VREF Figure 17. ADT7318 INL Error and DNL Error vs. Temperature Figure 18. Offset Error and Gain Error vs. Temperature Figure 19. Offset Error and Gain Error vs. VDD Figure 20. VOUT Source and Sink Current Capability Figure 21. Supply Current vs. DAC Code

Rev. B | Page 19 of 44 THEORY OF OPERATION Directly after the power-up calibration routine, the ADT7316/ ADT7317/ADT7318 go into idle mode. In this mode, the device is not performing any measurements and is fully powered up. All four DAC outputs are at 0 V . To begin monitoring, write to the Control Configuration 1 r egister (Address 0x18), and set Bit C0 = 1. The ADT7316/ ADT7317/ADT7318 go into their power-up default measure- ment mode, which is round robin. The device proceeds to take measurements on the V DD channel, the internal temperature sensor channel, and the external temperature sensor channel. Once it finishes taking measurements on the external tempera- ture sensor channel, the device immediately loops back to start taking measurements on the V DD channel and repeats the same cycle as before. This loop continues until the monitoring is stopped by resetting Bit C0 of the Control Configuration 1 register to 0. It is also possible to continue monitoring as well as switching to sin gle-channel mode by writing to the Control Configuration 2 register (Address 0x19) and setting Bit C4 = 1. Further explana- tion of the single-channel and round robin measurement modes is given in later sections. All measurement channels have averaging enabled on power-up. Averaging forces the device to take an average of 16 readings before giving a final measured result. To disable averaging and consequently decrease the conversion time by a factor of 16, set C5 = 1 in the Control Configuration 2 register. Controlling the DAC outputs can be done by writing to the DAC MS B and LSB registers (Address 0x10 to Address 0x17). The power-up default setting is to have a low going pulse on the LDAC pin controlling the updating of the DAC outputs from the DAC registers. Alternatively, users can configure the updating of the DAC outputs to be controlled by means other than the LDAC pin by setting C3 = 1 of the Control Configuration 3 register (Address 0x1A). The DAC Configuration register (Address 0x1B), and the LDAC Configuration register (Address 0x1C) can then be used to control the DAC updating. These two registers also control the output range of the DACs, enabling or disabling the external reference buffer, and selecting between the internal or external reference. DAC A and DAC B outputs can be configured to give a voltage output proportional to the temperature of the internal and external temperature sensors, respectively. The dual serial interface defaults to the I 2C protocol on power- up. To select and lock in the SPI protocol, follow the selection process as described in the Serial Interface Selection section. The I 2C protocol cannot be locked in, while the SPI protocol, when selected, is automatically locked in. The interface can only be switched back to be I2C when the device is powered off and on. When using I2C, the CS pin should be tied to either VDD or GND. There are a number of different operating modes on the ADT7316/AD T7317/ADT7318 devices, and all of them can be controlled by the configuration registers. These features consist of enabling and disabling interrupts, polarity of the INT/INT pin, enabling and disabling the averaging on the measurement channels, SMBus timeout, and software reset. POWER-UP CALIBRATION It is recommended that no communication to the part is initiated until approximately 5 ms after VDD has settled to within 10% of its final value. It is generally accepted that most systems take a maximum of 50 ms to power-up. Power-up time is directly related to the amount of decoupling on the voltage supply line. During the 5 ms after V DD has settled, the part performs a cali- bration routine; any communication to the device interrupts this routine and can cause erroneous temperature measurements. If it is not possible to have V DD at its nominal value by the time 50 ms has elapsed, or that communication to the device has started prior to VDD settling, then it is recommended that a measurement be taken on the VDD channel before a tempera ture measurement is taken. The VDD measurement is used to calibrate out any temperature measurement error due to different supply voltage values. CONVERSION SPEED The internal oscillator circuit used by the ADC has the capa- bility to output two different clock frequencies. This means that the ADC is capable of running at two different speeds when performing a conversion on a measurement channel. Thus, the time taken to perform a conversion on a channel can be reduced by setting C0 of Control Configuration 3 register (Address 0x1A). This increases the ADC clock speed from 1.4 kHz to 22 kHz. At the higher clock speed, the analog filters on the D+ and D− input pins (external temperature sensor) are switched off. This is why the power-up default setting is to have the ADC working at the slow speed. The typical times for fast and slow ADC speeds are given in the Specifications section. The ADT7316/ADT7317/ADT7318 power up with averaging o n. This means every channel is measured 16 times and inter- nally averaged to reduce noise. The conversion time can also be sped up by turning the averaging off; to do so, set Bit C5 of the Control Configuration 2 register (Address 0x19) to 1.

unbuffered to give a reference input range from GND to VDD. be turned off completely with a high impedance output. the digital value that corresponds to the DAC output voltage. be read back until after the LDAC command has been initiated. LDAC Configuration register (Address 0x1C). Figure 39. Single DAC Channel Architecture Figure 40. Resistor String are buffered, but can also be individually configured as unbuffered.

0.25 V and as high as V

output mode and 45 kΩ for 0 V to 2 VREF output mode.

128 Temp) V (0 ) ( CodeRegisterOffset +=dec

Table 6. Thermal Voltage Output (0 V to VREF-AB)

1.5 UDB1 +42 UDB 1

2 UDB1 +99 UDB 1

2.25 UDB1 +127 UDB 1

Table 7. Thermal Voltage Output (0 V to 2 VREF-AB)

3 UDB1 +42 UDB 1

3.25 UDB1 +56 UDB 1

3.5 UDB1 +70 UDB 1

3.75 UDB1 +85 UDB 1

4 UDB1 +99 UDB 1

4.25 UDB1 +113 UDB 1

4.5 UDB1 +127 UDB 1

Figure 43. 10-Bit DAC Output vs. Temperature, VREF-AB = 2.25 V

Rev. B | Page 23 of 44 FUNCTIONAL DESCRIPTION—MEASUREMENT TEMPERATURE SENSOR The ADT7316/ADT7317/ADT7318 contain an ADC with spe- cial input signal conditioning to enable operation with external and on-chip diode temperature sensors. When the ADT7316/ ADT7317/ADT7318 are operating in single-channel mode, the ADC continually processes the measurement taken on one channel only. This channel is preselected by Bit C0 and Bit C1 in the Control Configuration 2 register (Address 0x19). When in round robin mode, the analog input multiplexer sequentially selects the V DD input channel, the on-chip temperature sensor to measure its internal temperature, and the external tempera- ture sensor. These signals are digitized by the ADC and the results stored in the various value registers. The measured results are compared with the internal and ext ernal, THIGH and TLOW, limits. These temperature limits are stored in on-chip registers. If the temperature limits are not masked out, any out-of-limit comparisons generate flags that are stored in the Interrupt Status 1 register (Address 0x00). One or more out-of-limit results cause the INT/INT output to pull either high or low depending on the output polarity setting. Theoretically, the temperature measuring circuit can measure t emperatures from −128°C to +127°C with a resolution of 0.25°C. Temperatures outside TA, however, are outside the guaranteed operating temperature range of the device. Temperature meas- urement from −128°C to +127°C is possible using an external sensor. Temperature measurement is initiated by three methods. The first m ethod is applicable when the part is in single-channel meas- urement mode. The temperature is measured 16 times and internally averaged to reduce noise. In single-channel mode, the part continuously monitors the selected channel, that is, as soon as one measurement is taken, then another one is started on the same channel. The total time to measure a temperature channel with the ADC operating at slow speed is typically 11.4 ms (712 μs × 16) for the internal temperature sensor, and 24.22 ms (1.51 ms × 16) for the external temperature sensor. The new temperature value is stored in two 8-bit registers and ready for reading by the I 2C or SPI interface. The user can disable the averaging by setting Bit 5 = 1 in the Control Con- figuration 2 register (Address 0x19). The ADT7316/ADT7317/ ADT7318 default on power-up, with the averaging enabled. The second temperature measurement method is applicable w hen the part is in round robin measurement mode. The part measures both the internal and external temperature sensors as it cycles through all possible measurement channels. The two temperature channels are measured each time the part runs a round robin sequence. In round-robin mode, the part continuously measures all channels. The third temperature measurement method is initiated after e very read or write to the part when the part is in either single- channel measurement mode or round robin measurement mode. Once serial communication has started, any conversion in pro- gress is stopped and the ADC reset. Conversion starts again immediately after the serial communication has finished. The temperature measurement proceeds normally as described earlier. VDD MONITORING The ADT7316/ADT7317/ADT7318 can monitor their own power supplies. The parts measure the voltage on their VDD pin to a resolution of 10 bits. The resulting value is stored in two 8-bit registers: the 2 LSBs are stored in the Internal Temperature Value/V DD Value register (Address 0x03) and the 8 MSBs are stored in the VDD Value Register MSBs register (Address 0x06). This allows the user to perform a 1-byte read if 10-bit resolution is not important. The measured result is compared with V HIGH and VLOW limits. If the VDD interrupt is not masked out, any out- of-limit comparison generates a flag in the Interrupt Status 2 register (Address 0x10), and one or more out-of-limit results cause the INT/INT output to pull either high or low depending on the output polarity setting. Measuring the voltage on the VDD pin is regarded as monitoring a channel. Therefore, along with the internal and external tem- perature sensors, the VDD voltage makes up the third and final monitoring channel. The user can select the VDD channel for single-channel measurement by setting Bit C4 = 1 and setting Bit C0 to Bit C2 to all 0s in the Control Configuration 2 register (Address 0x19). When measuring the V DD value, the reference for the ADC is sourced from the internal reference. Table 8 shows the data fo rmat. As the maximum VDD voltage measurable is 7 V , internal scaling is performed on the VDD voltage to match the 2.28 V internal reference value. An example of how the transfer function works follows. VDD = 5 V ADC Reference = 2.28 V 1 LSB = ADC R eference/210 = 2.28/1024 = 2.226 mV Scale Factor = F ull-Scale VCC/ADC Reference = 7/2.28 = 3.07 Conversion Result = VDD/(Scale Factor × LSB Size) = 0x2DB

Table 8. VDD Data Format, VREF = 2.28 V power-up reference for the DACs. Configuration 1 Register (Address 0x18) to 1 enables conversions. perature sensor) is measured in each conversion cycle. ical times at 25°C are given in the Specifications section. Figure 44. Top Level Structure of Int ernal Temperature Sensors the internal temperature offset register. ture of one external diode sensor or diode-connected transistor.

q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents. connected to the D− input and the base to the D+ input. A 2N3906 is recommended to be used as the external transistor. but is biased above ground by an internal diode at the D− input. by averaging the results of 16 measurement cycles. temperature sensor is guaranteed to a low value limit of −40°C. external high and low registers. Table 9. Temperature Data Format (Internal and External

power-up, unless otherwise noted. limit event has been corrected. It is also reset by a software reset. Table 11. Interrupt Status 1 Register 1 Default settings at power-up. Table 12. Interrupt Status 1 Register causes an out-of-limit event. limit set causes an out-of-limit event. causes an out-of-limit event. limit event has been corrected. It is also reset by a software reset. Table 13. Interrupt Status 2 Register 1 Default settings at power-up. Table 14. Interrupt Status 2 Register Bit Descriptions and the 2 LSBs of the 10-bit supply voltage reading. Table 15. Internal Temperature/V 1 Default settings at power-up. Table 16. Internal Temperature/VDD LSBs Bit Descriptions D0 LSB of internal temperature value. D1 B1 of internal temperature value. temperature reading from the external temperature sensor. Table 17. External Temperature LSBs 1 Default settings at power-up. Table 18. External Temperature LSBs Bit Descriptions D0 LSB of external temperature value. D1 B1 of external temperature value. This 8-bit, read-only register stores the supply voltage value. The 8 MSBs of the 10-bit value are stored in this register. Table 19. VDD Value MSBs 1 Loaded with VDD value after power-up. format. The 8 MSBs of the 10-bit value are stored in this register. Table 20. Internal Temperature Value MSBs 1 Default settings at power-up.

format. The 8 MSBs of the 10-bit value are stored in this register. Table 21. External Temperature Value MSBs 1 Default settings at power-up. On power-up, the voltage output on the VOUT-A pin is 0 V . Table 22. DAC A (ADT7316) LSBs 1 Default settings at power-up. Table 23. DAC A (ADT7317) LSBs 1 Default settings at power-up. Table 24. DAC A MSBs 1 Default settings at power-up. On power-up, the voltage output on the VOUT-B pin is 0 V . Table 25. DAC B (ADT7316) LSBs 1 Default settings at power-up. Table 26. DAC B (ADT7317) LSBs 1 Default settings at power-up. Table 27. DAC B MSBs 1 Default settings at power-up. MSBs and converted to an analog voltage on the VOUT-C pin. On power-up, the voltage output on the VOUT-C pin is 0 V . Table 28. DAC C (ADT7316) LSBs 1 Default settings at power-up. Table 29. DAC C (ADT7317) LSBs 1 Default settings at power-up. Table 30. DAC C MSBs 1 Default settings at power-up.

On power-up, the voltage output on the VOUT-D pin is 0 V . Table 31. DAC D (ADT7316) LSBs 1 Default settings at power-up. Table 32. DAC D (ADT7317) LSBs 1 Default settings at power-up. Table 33. DAC D MSBs 1 Default settings at power-up. Table 34. Control Configuration 1 1 Default settings at power-up. Table 35. Control Configuration 1 Bit Descriptions mode, but monitoring is not initiated until this bit is set. 0 = Stop monitoring (default). C1:4 Reserved. Only write 0s. C5 0 = Enable INT/INT output. 1 = Disable INT/INT output. C6 Configures INT/INT output polarity. 0 = Active low. part again, write 0 to this bit. Table 36. Control Configuration 2 1 Default settings at power-up. Table 37. Control Configuration 2 temperature sensor for conversion. 01 = Internal temperature sensor. 10 = External temperature sensor. onversion cycle. Default is round robin. annels 16 times. This bit disables this averaging. Channels affected are temperature and VDD. on the master SCL does not lock up the SDA line.

Table 38. Control Configuration 3 1 Default settings at power-up. Table 39. Control Configuration 3 or all three monitoring channels. an 8-bit DAC. In the ADT7318 case, write 0 to this bit. C3 0 = LDAC pin controls updating of DAC outputs. register control the updating of the DAC outputs. oportional to the internal temperature measurement. oportional to the external temperature measurement. disabled (Bit C3 = 1, Control Configuration 3 register). Table 40. DAC Configuration 1 Default settings at power-up. Table 41. DAC Configuration D0 Selects the output range of DAC A. D1 Selects the output range of DAC B. D2 Selects the output range of DAC C. D3 Selects the output range of DAC D. ommand, which updates that DAC only. command, which updates all 4 DACs. 11 = LDAC command generated from LDAC register. reference buffer when supplying DAC A and DAC B. reference buffer when supplying DAC C and DAC D. Table 42. LDAC Configuration 1 Default settings at power-up. Table 43. LDAC Configuration D5:D7 Reserved. Only write 0s.

Table 44. Interrupt Mask 1 1 Default settings at power-up. Table 45. Interrupt Mask 1 Bit Descriptions D0 0 = Enable internal THIGH interrupt. 1 = Disable internal THIGH interrupt. D1 0 = Enable internal TLOW interrupt. 1 = Disable internal TLOW interrupt. D2 0 = Enable external THIGH interrupt. 1 = Disable external THIGH interrupt. D3 0 = Enable external TLOW interrupt. 1 = Disable external TLOW interrupt. D4 0 = Enable external temperature fault interrupt. 1 = Disable external temperature fault interrupt. D5: 7 Reserved. Only write 0s. Table 46. Interrupt Mask 2 1 Default settings at power-up. Table 47. Interrupt Mask 2 Bit Descriptions D0:D3 Reserved. Only write 0s. D4 0 = Enable VDD interrupts. D5:7 Reserved. Only write 0s. it is an 8-bit register, the temperature resolution is 1°C. Table 48. Internal Temperature Offset 1 Default settings at power-up. it is an 8-bit register, the temperature resolution is 1°C. Table 49. External Temperature Offset 1 Default settings at power-up. resolution is 1°C. The default value is −40°C. Table 50. Internal Analog Temperature Offset 1 Default settings at power-up.

to +127°C produces an upper dead band on the DAC B output. Table 51. External Analog Temperature 1 Default settings at power-up. Table 52. VDD VHIGH Limit 1 Default settings at power-up. value has to be less than or equal to the value in this register. The default value is 2.7 V . Table 53. VDD VLOW Limit 1 Default settings at power-up. Table 54. Internal THIGH Limit 1 Default settings at power-up. causes an interrupt and activates the INT/INT output (if enabled). to be more negative than or equal to the value in this register. Table 55. Internal TLOW Limit 1 Default settings at power-up. Table 56. External THIGH Limit 1 Default settings at power-up.

Rev. B | Page 36 of 44 SERIAL INTERFACE There are two serial interfaces that can be used on this part, the I2C and the SPI interface. The device powers up with the serial interface in I2C mode, but it is not locked into this mode. To stay in I2C mode, it is recommended that the user ties the CS line to either VCC or GND. It is not possible to lock the I2C mode, but it is possible to select and lock the SPI mode. To select and lock the interface into the SPI mode, a number o f pulses must be sent down the CS (Pin 4) line. The following section describes how this is done. Once the SPI communication protocol has been locked in, it ca nnot be unlocked while the device is still powered up. Bit D0 of the SPI Lock Status register (Address 0x7F) is set to 1 when a successful SPI interface lock has been accomplished. To reset the serial interface, the user must power down the part and power up again. A software reset does not reset the serial interface. SERIAL INTERFACE SELECTION The CS line controls the selection between I2C and SPI. Figure 50 shows the selection process necessary to lock the SP I interface mode. To communicate to the ADT7316/ADT7317/ADT7318 using t he SPI protocol, send three pulses down the CS line, as shown in Figure 50. On the third rising edge (marked as C in Figure 50), t he part selects and locks the SPI interface. The user is limited to communicating to the device using the SPI protocol. As per most SPI standards, the CS line must be low during every SPI communication to the ADT7316/ADT7317/ ADT7318 and high all other times. Typical examples of how to connect the dual interface as I2C or SPI are shown in Figure 48 and Figure 49. The following sections describe in detail how to use the I2C and SPI protocols associated with the ADT7316/ADT7317/ ADT7318. I2C SERIAL INTERFACE Like all I2C-compatible devices, the ADT7316/ADT7317/ ADT7318 have a 7-bit serial address. The 4 MSBs of this address for the ADT7316/ADT7317/ADT7318 are set to 1001. The 3 LSBs are set by Pin 11, ADD. The ADD pin can be configured three ways to give three different address options: low, floating, and high. Setting the ADD pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010, and setting it high gives the address 1001 011. The recommended pull-up resistor value is 10 kΩ. There is a programmable SMBus timeout. When this is enabled th e SMBus times out after 25 ms of no activity. To enable it, set Bit 6 of the Control Configuration 2 register (Address 0x19). The power-up default is with the SMBus timeout disabled. The ADT7316/ADT7317/ADT7318 support SMBus packet er ror checking (PEC) and its use is optional. It is triggered by supplying the extra clocks for the PEC byte. The PEC byte is calculated using CRC-8. The frame clock sequence (FCS) conforms to CRC-8 by the polynomial: Consult SMBus for more information. The serial bus protocol operates as follows: 1. The mast er initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit address (MSB first) plus an R/W bit, which determines the direction of the data transfer, that is, whether data is to be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle, while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device. 2. Da ta is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. 3. W hen all data bytes have been read or written, stop condi- tions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device pulls the data line high during the low period before the ninth clock pulse. This is known as no acknowledge. The master takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. Any number of bytes of data may be transferred over the serial b us in one operation. However, reads and writes cannot be mixed in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. The I 2C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. This is the SCL cycle directly after the device has seen its own I 2C serial bus address. Any subsequent changes on this pin have no effect on the I2C serial bus address.

followed by the data byte written to the selected data register. register is repeatedly loaded until the last data byte is sent. pointer register again to set up the relevant register address. between any two separate serial communications (see Figure 58). pull-up resistors when the serial clock speed is reduced. provide a serial clock that is synchronized to the serial data. There are two types of serial operations, a read and a write. Table 58. SPI Command Words Figure 52. I2C—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register

• P lace the ADT7316/ADT7317/ADT7318 as close as possible to the remote sensing diode. Provided that the worst noise sources, such as clock generators, data/address buses, and CRTs are avoided, this distance can be 4 inches to 8 inches.
• R oute the D+ and D− tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible.
• U se wide tracks to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended. GND GND

10 MIL

Figure 61. Arrangement of Signal Tracks

• Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/ solder joints are used, make sure that they are in both the D+ and D− paths and at the same temperature. Thermocouple effects should not be a major problem as 1°C corresponds to about 240 μV , and thermocouple voltages are about 3 μV/°C of the temperature difference. Unless there are two thermo- couples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV .
• P lace 0.1 μF bypass and 2200 pF input filter capacitors close to the ADT7316/ADT7317/ADT7318.
• I f the distance to the remote sensor is more than 8 inches, the use of the twisted pair cable is recommended. This works for distances from 6 feet to 12 feet.
• F or really long distances (up to 100 feet), use shielded twisted pair, such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D− and the shield to GND close to the ADT7316/ADT7317/ADT7318. Leave the remote end of the shield unconnected to avoid ground loops.
• B ecause the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. Series resistance o f 1 Ω introduces about 0.5°C error.

Figure 62. 16-Lead Shrink Small Outline Package [QSOP]

Rev. B | Page 43 of 44 NOTES

Rev. B | Page 44 of 44 NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02661-0-1/07(B)