ADSXX53

ADS7253 TI | Alldatasheet

Document overview

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Technical content

1.8 nF VIN+ + + OPA836 AINP AINM GND AVDD ADSxx53 4 /c0d/c03 INPUT DRIVER ADS8353 : 16-bit, 600 kSPS ADS7853 : 14-bit, 1 MSPS ADS7253 : 12-bit, 1 MSPS 1k/c0d/c03 1 k/c0d/c03 VDC Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design ADS8353,ADS7853,ADS7253 SBAS584B –OCTOBER 2013–REVISED AUGUST 2014 ADSxx53Dual,High-Speed,16-,14-,and12-Bit, Simultaneous-Sampling,Analog-to-DigitalConverters

1 Features 2 Applications

1• 16-, 14-, and 12-Bit, Pin-Compatible Family • Motor Control: Position Measurement Using Encoders• Simultaneous Sampling of Two Channels

• Optical Networking: EDFA Gain Control Loops• Supports Single-Ended and Pseudo-Differential Inputs • Protection Relays
• High Speed: • Power Quality Measurement
• Three-Phase Power Controls– ADS8353: 16 Bits, 600 kSPS
• Programmable Logic Controllers– ADS7853: 14 Bits, 1 MSPS – ADS7253: 12 Bits, 1 MSPS

3 Description• Excellent DC Performance:

The ADS8353, ADS7853, and ADS7253 belong to a– ADS8353: family of pin-compatible, dual, high-speed, – 16-Bit NMC DNL, ±2.5-LSB Max INL simultaneous-sampling, analog-to-digital converters (ADCs) that support single-ended and pseudo-– ADS7853: differential analog inputs.– 14-Bit NMC DNL, ±2-LSB Max INL Each device includes two individually programmable– ADS7253: reference sources that can be used for system-level– 12-Bit NMC DNL, ±1-LSB Max INL gain calibration. Also, a flexible serial interface that

• Excellent AC Performance: can operate over a wide power-supply range enables easy communication with a large variety of host– ADS8353: controllers. Power consumption for a given– 89-dB SNR, –100-dB THD throughput can be optimized by using the two low- – ADS7853: power modes supported by the device. All devices are fully specified over the extended industrial– 82-dB SNR, –90-dB THD temperature range (–40°C to 125°C) and are– ADS7253: available in pin-compatible, WQFN-16 (3-mm ×– 72-dB SNR, –90-dB THD 3-mm) and TSSOP-16 packages.
• Dual, Programmable, and Buffered Device Information(1)2.5-V Internal Reference PART NUMBER PACKAGE BODY SIZE (NOM)• Fully-Specified Over the Extended Industrial TSSOP (16) 5.00 mm × 4.40 mmTemperature Range: –40°C to 125°C ADSxx53 WQFN (16) 3.00 mm × 3.00 mm• Small Footprint: WQFN-16 (3-mm × 3-mm) and TSSOP-16 (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS8353,ADS7853,ADS7253 SBAS584B –OCTOBER 2013–REVISED AUGUST 2014 www.ti.com Table of Contents

4 Revision History

Changes from Revision A (July 2014) to Revision B Page Changes from Original (October 2013) to Revision A Page

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5 Device Comparison Table

PRODUCT (Bits) INPUT CONFIGURATION NMC (Bits) INL (LSB) SNR (dB) ADS8354 16 Fully-differential 16 ±2.5 93 (typ) ADS7854 14 Fully-differential 14 ±1.5 88 (typ) ADS7254 12 Fully-differential 12 ±1 74 (typ) Single-ended andADS8353 16 16 ±2.5 89 (typ)pseudo-differential Single-ended andADS7853 14 14 ±2 84 (typ)pseudo-differential Single-ended andADS7253 12 12 ±1 73.5 (typ)pseudo-differential Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADS8353 ADS7853 ADS7253

AINP_A AINM_A REFIO_A REFGND_A REFGND_B REFIO_B AINM_B AINP_B AVDD GND SDO_B SDO_A SCLK CS SDI DVDD REFIO_A REFGND_A REFGND_B REFIO_B SDO_B SDO_A SCLK CS AINM_A16AINM_B 5 AINP_AAINP_B AVDDDVDD GNDSDI Thermal Pad ADS8353,ADS7853,ADS7253 SBAS584B –OCTOBER 2013–REVISED AUGUST 2014 www.ti.com

6 Pin Configurations and Functions

NO. NAME TSSOP WQFN I/O DESCRIPTION AINM_A 2 16 Analog input Negative analog input, channel A AINM_B 7 5 Analog input Negative analog input, channel B AINP_A 1 15 Analog input Positive analog input, channel A AINP_B 8 6 Analog input Positive analog input, channel B AVDD 16 14 Supply Supply voltage for ADC operation CS 11 9 Digital input Chip-select signal; active low DVDD 9 7 Digital I/O supply Digital I/O supply GND 15 13 Supply Digital ground REFGND_A 4 2 Supply Reference ground potential A REFGND_B 5 3 Supply Reference ground potential B REFIO_A 3 1 Analog input/output Reference voltage input/output, channel A REFIO_B 6 4 Analog input/output Reference voltage input/output, channel B SCLK 12 10 Digital input Clock for serial communication SDI 10 8 Digital input Data input for serial communication SDO_A 13 11 Digital output Data output for serial communication, channel A and channel B SDO_B 14 12 Digital output Data output for serial communication, channel B Thermal Exposed thermal pad (only for WQFN). TI recommendsThermal pad — Supplypad connecting this pin to the printed circuit board (PCB) ground.

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7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT AVDD to REFGND_x or DVDD to GND –0.3 6 V Analog (AINP_x and AINM_x) and reference input (REFIO_x) voltage with REFGND_x – 0.3 AVDD + 0.3 Vrespect to REFGND_x Digital input voltage with respect to GND GND – 0.3 DVDD + 0.3 V Ground voltage difference |REFGND_x-GND| 0.3 V Input current to any pin except supply pins ±10 mA Maximum virtual junction temperature, TJ 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

Tstg Storage temperature range –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000 2000pins(1) V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification –500 500JESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog supply voltage 5 V DVDD Digital supply voltage 3.3 V

7.4 Thermal Information

ADS8353, ADS7853, ADS7253 THERMAL METRIC(1) RTE (WQFN) PW (TSSOP) UNIT

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 33.3 86.9 RθJC(top) Junction-to-case (top) thermal resistance 29.5 21 RθJB Junction-to-board thermal resistance 7.3 39.1 °C/W ψJT Junction-to-top characterization parameter 0.2 0.8 ψJB Junction-to-board characterization parameter 7.4 38.4 RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADS8353 ADS7853 ADS7253

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7.5 Electrical Characteristics: ADS8353

All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted. Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 16 Bits DC ACCURACY(1) NMC No missing codes 32-clock mode 16 Bits INL Integral nonlinearity 32-clock mode –2.5 ±1 2.5 LSB DNL Differential nonlinearity 32-clock mode –0.99 ±0.6 2 LSB EIO Input offset error –1 ±0.5 1 mV EIO match ADC_A to ADC_B –1 ±0.5 1 mV dEIO/dT Input offset thermal drift 1 μV/°C EG Gain error Referenced to the voltage at REFIO_x –0.1 ±0.05 0.1 %FS EG match ADC_A to ADC_B –0.1 ±0.05 0.1 %FS dEG/dT Gain error thermal drift Referenced to the voltage at REFIO_x 1 ppm/°C AC ACCURACY(2) VREF = 2.5 V, 80.2 83 dBVREF input range, 32-clock mode VREF = 2.5 V,SINAD Signal-to-noise + distortion 83.9 dB2 × VREF input range, 32-clock mode VREF = 5 V (external), 88.7 dBVREF input range, 32-clock mode VREF = 2.5 V, 80.5 83 dBVREF input range, 32-clock mode VREF = 2.5 V,SNR Signal-to-noise ratio 84 dB2 × VREF input range, 32-clock mode VREF = 5 V (external), 89 dBVREF input range, 32-clock mode VREF = 2.5 V, –100 dBVREF input range, 32-clock mode VREF = 2.5 V,THD Total harmonic distortion –100 dB2 × VREF input range, 32-clock mode VREF = 5 V (external), –100 dBVREF input range, 32-clock mode VREF = 2.5 V, 105 dBVREF input range, 32-clock mode VREF = 2.5 V,SFDR Spurious-free dynamic range 105 dB2 × VREF input range, 32-clock mode VREF = 5 V (external), 105 dBVREF input range, 32-clock mode (1) LSB = least significant bit. (2) All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency.

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7.6 Electrical Characteristics: ADS7853

All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 14 Bits DC ACCURACY(1) 32-clock mode 14 Bits NMC No missing codes 16-clock mode 13 Bits 32-clock mode –2 ±0.7 2 LSB INL Integral nonlinearity 16-clock mode –2.5 ±1 2.5 LSB 32-clock mode –0.99 ±0.5 1 LSB DNL Differential nonlinearity 16-clock mode –1 ±0.9 2 LSB EIO Input offset error –1 ±0.5 1 mV EIO match ADC_A to ADC_B –1 ±0.5 1 mV dEIO/dT Input offset thermal drift ±1 μV/°C EG Gain error Referenced to the voltage at REFIO_x –0.1 ±0.05 0.1 %FS EG match ADC_A to ADC_B –0.1 ±0.05 0.1 %FS dEG/dT Gain error thermal drift Referenced to the voltage at REFIO_x ±1 ppm/°C AC ACCURACY(2) 32-clock mode 78.4 80.9 dBVREF = 2.5 V, VREF input range 16-clock mode 80.3 dB 32-clock mode 81.4 dBVREF = 2.5 V,SINAD Signal-to-noise + distortion 2 × VREF input range 16-clock mode 80.8 dB 32-clock mode 83.9 dBVREF = 5 V (external), VREF input range 16-clock mode 82.9 dB 32-clock mode 78.5 81 dBVREF = 2.5 V, VREF input range 16-clock mode 80.5 dB 32-clock mode 81.5 dBVREF = 2.5 V,SNR Signal-to-noise ratio 2 × VREF input range 16-clock mode 81 dB 32-clock mode 84 dBVREF = 5 V (external), VREF input range 16-clock mode 83.5 dB 32-clock mode –100 dBVREF = 2.5 V, VREF input range 16-clock mode –93 dB 32-clock mode –98 dBVREF = 2.5 V,THD Total harmonic distortion 2 × VREF input range 16-clock mode –94 dB 32-clock mode –102 dBVREF = 5 V (external), VREF input range 16-clock mode –92 dB 32-clock mode 100 dBVREF = 2.5 V, VREF input range 16-clock mode 95 dB 32-clock mode 100 dBVREF = 2.5 V,SFDR Spurious-free dynamic range 2 × VREF input range 16-clock mode 95 dB 32-clock mode 102 dBVREF = 5 V (external), VREF input range 16-clock mode 95 dB fIN = 15 kHz at 10 %FS,ISOXT ADC-to-ADC isolation –100 dBfNOISE = 25 kHz at FS (1) LSB = least significant bit. (2) All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS8353 ADS7853 ADS7253

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7.7 Electrical Characteristics: ADS7253

All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 12 Bits DC ACCURACY(1) NMC No missing codes 12 Bits INL Integral nonlinearity –1 ±0.3 1 LSB DNL Differential nonlinearity –0.99 ±0.3 1 LSB EIO Input offset error –2 ±0.5 2 mV EIO match ADC_A to ADC_B –2 ±0.5 2 mV dEIO/dT Input offset thermal drift ±1 μV/°C EG Gain error Referenced to the voltage at REFIO_x –0.2 ±0.05 0.2 %FS EG match ADC_A to ADC_B –0.2 ±0.05 0.2 %FS dEG/dT Gain error thermal drift Referenced to the voltage at REFIO_x ±1 ppm/°C AC ACCURACY(2) VREF = 2.5 V, 71 72.9 dBVREF input range VREF = 2.5 V,SINAD Signal-to-noise + distortion 72.9 dB2 × VREF input range VREF = 5 V (external), 73.4 dBVREF input range VREF = 2.5 V, 71.5 73 dBVREF input range VREF = 2.5 V,SNR Signal-to-noise ratio 73 dB2 × VREF input range VREF = 5 V (external), 73.5 dBVREF input range VREF = 2.5 V, –90 dBVREF input range VREF = 2.5 V,THD Total harmonic distortion –90 dB2 × VREF input range VREF = 5 V (external), –90 dBVREF input range VREF = 2.5 V, 93.5 dBVREF input range VREF = 2.5 V,SFDR Spurious-free dynamic range 93.5 dB2 × VREF input range VREF = 5 V (external), 93.5 dBVREF input range fIN = 15 kHz at 10 %FS,ISOXT ADC-to-ADC isolation –80 dBfNOISE = 25 kHz at FS (1) LSB = least significant bit. (2) All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency.

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7.8 Electrical Characteristics: All Devices

All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V, and fDATA = maximum, unless otherwise noted. Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Single-ended input, 0 VREF VAINM_x = GNDVREF range Pseudo-differential input, –VREF / 2 VREF / 2 VAINM_x = +VREF / 2 Full-scale input range(1) Single-ended input,FSR (AINP_x – AINM_x) AINM_x = GND, 0 2 × VREF V AVDD ≥ 2 × VREF2 × VREF range Pseudo-differential input, AINM_x = +VREF, –VREF VREF V AVDD ≥ 2 × VREF VREF range 0 VREF VAbsolute input voltageVINP (AINP_x to REFGND) 2 × VREF range, AVDD ≥ 2 × VREF 0 2 × VREF V Single-ended input –0.1 0.1 VVREF range Pseudo-differential input VREF / 2 – 0.1 VREF / 2 VREF / 2 + 0.1 V range Pseudo-differential input, VREF – 0.1 VREF VREF + 0.1 VAVDD ≥ 2 × VREF In sample mode 40 pF Ci Input capacitance In hold mode 4 pF Ilkg(i) Input leakage current 0.1 µA INTERNAL VOLTAGE REFERENCE REFDAC_x = 1FFh (default),VREFOUT Reference output voltage 2.495 2.500 2.505 Vat 25°C REFDAC_x = 1FFh (default),VREF-match VREF_A to VREF_B matching ±1 mVat 25°C REFDAC_x resolution(2) 1.1 mV Reference voltagedVREFOUT/dT REFDAC_x = 1FFh (default) ±10 ppm/°Ctemperature drift dVREFOUT/dt Long-term stability 1000 hours 150 ppm Internal reference outputRO 1 Ωimpedance Reference output dcIREFOUT 2 mAcurrent Recommended outputCREFOUT 10 µFcapacitor Reference output settlingtREFON For CREF = 10 μF 8 mstime VOLTAGE REFERENCE INPUT VREF range 2.4 2.5 AVDD V VREF Reference voltage (input) 2 × VREF range 2.4 2.5 AVDD / 2 V Average Reference inputIREF Per ADC 300 μAcurrent External ceramicCREF 10 μFreference capacitance Ilkg(dc) DC leakage current ±0.1 μA (1) Ideal input span, does not include gain or offset error. (2) Refer to the Reference section for more details. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADS8353 ADS7853 ADS7253

ADS8353,ADS7853,ADS7253 SBAS584B –OCTOBER 2013–REVISED AUGUST 2014 www.ti.com Electrical Characteristics: All Devices (continued) All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V, and fDATA = maximum, unless otherwise noted. Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SAMPLING DYNAMICS tA Aperture delay 8 ns tA match ADC_A to ADC_B 40 ps tAJIT Aperture jitter 50 ps DIGITAL INPUTS(3) DVDD > 2.3 V 0.7 DVDD DVDD + 0.3 V VIH High-level input voltage DVDD ≤ 2.3 V 0.8 DVDD DVDD + 0.3 V DVDD > 2.3 V –0.3 0.3 DVDD V VIL Low-level input voltage DVDD ≤ 2.3 V –0.3 0.2 DVDD V Input current ±10 nA DIGITAL OUTPUTS(3) VOH High-level output voltage IOH = 500-µA source 0.8 DVDD DVDD V VOL Low-level output voltage IOH = 500-µA sink 0 0.2 DVDD V POWER SUPPLY Internal reference 4.5 5.0 5.5 V Internal reference 5.0 5.0 5.5 V±2 × VREF range External reference 2 × VREF_EXT 5.0 5.5 V Digital supply voltageDVDD 1.65 5.5 V(DVDD to AGND) AVDD = 5 V, fastest throughput 8.5 10 mAinternal reference AVDD = 5 V, fastest throughput 7.5 mAexternal reference(4) AVDD = 5 V, no conversion 5.5 7 mAinternal reference AIDD Analog supply current AVDD = 5 V, no conversion 4.5 mAexternal reference(4) AVDD = 5 V, STANDBY mode 2.5 mAInternal Reference AVDD = 5 V, STANDBY mode 1 mAexternal reference(4) Power-down mode 10 50 μA DVDD = 3.3 V, CLOAD = 10 pF, 0.5 mAfastest throughput DIDD Digital supply current DVDD = 5 V, CLOAD = 10 pF 1 mAfastest throughput Power dissipation AVDD = 5V, fastest throughput,PD 42.5 50 mW(normal operation) internal reference (3) Specified by design; not production tested. (4) With internal reference powered down, CFR.B6 = 0.

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7.9 Timing Requirements: Interface Mode(1)

PARAMETER ASSOCIATED FIGURES tCLK CLOCK period Figure 1, Figure 91, Figure 92, Figure 93, Figure 94 tACQ Acquisition time Figure 91, Figure 92, Figure 93, Figure 94 tCONV Conversion time Figure 91, Figure 92, Figure 93, Figure 94 (1) These parameters are specific to the interface mode of operation. Refer to the Conversion Data Read section for more details.

7.10 Timing Characteristics: Serial Interface

PARAMETER TEST CONDITIONS ASSOCIATED FIGURES MIN TYP MAX UNIT TIMING REQUIREMENTS tPH_CK CLOCK high time 0.4 0.6 tCLK tPL_CK CLOCK low time Figure 1 0.4 0.6 tCLK fCLK CLOCK frequency 1 / tCLK MHz tPH_CS CS high time Figure 1 40 ns ADS8353 150 ns tPH_CS_SHRT CS high time after frame abort ADS7853 Figure 99 100 ns ADS7253 70 ns Setup time: CS falling edge totSU_CSCK 15 nsSCLK falling edge Delay time: Last SCLK falling edgetD_CKCS 15 nsto CS rising edge Figure 1 Setup time: DIN data valid to SCLKtSU_CKDI 5 nsfalling edge Hold time: SCLK falling edge totHT_CKDI 5 ns(previous) data valid on DIN Power-up time from STANDBYtPU_STDBY Figure 96 1 µsmode With internal reference 3 ms tPU_SPD Power-up time from SPD mode Figure 98 With external reference 1 ms TIMING SPECIFICATIONS ADS8353 32-CLK mode 1.666 µs Figure 91, Figure 92 32-CLK mode 1 µs ADS7853 tTHROUGHPUT Throughput time 16-CLK mode Figure 93, Figure 94 1 µs 32-CLK mode Figure 91, Figure 92 1 µs ADS7253 16-CLK mode Figure 93, Figure 94 1 µs Figure 91, Figure 92,fTHROUGHPUT Throughput 1 / tTHROUGHPUT kSPSFigure 93, Figure 94 Delay time: CS falling edge to datatDV_CSDO 12 nsenable Delay time: CS rising edge to datatDZ_CSDO Figure 1 12 nsgoing to 3-state Delay time: SCLK falling edge totD_CKDO 20 nsnext data valid Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADS8353 ADS7853 ADS7253

Figure 1 shows the details of the serial interface between the device and the digital host controller. Figure 1. Serial Interface Timing Diagram

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7.11 Typical Characteristics: ADS8353

At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted. Figure 2. Typical FFT Figure 3. Typical FFT Figure 4. SNR vs Temperature Figure 5. SINAD vs Temperature Figure 6. SNR vs Reference Voltage Figure 7. SINAD vs Reference Voltage

At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted. Figure 8. SNR vs Input Frequency Figure 9. SINAD vs Input Frequency Figure 10. THD vs Temperature Figure 11. THD vs Reference Voltage Figure 12. THD vs Input Frequency Figure 13. Analog Supply Current vs Temperature

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At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted. Figure 20. DNL vs Temperature Figure 21. INL vs Temperature Figure 22. DNL vs Reference Voltage Figure 23. INL vs Reference Voltage

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32 CLK Mode

16 CLK Mode

7.12 Typical Characteristics: ADS7853

At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Figure 24. Typical FFT Figure 25. Typical FFT Figure 26. Typical FFT Figure 27. Typical FFT Figure 28. SNR vs Temperature Figure 29. SINAD vs Temperature

At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Figure 30. SNR vs Reference Voltage Figure 31. SINAD vs Reference Voltage Figure 32. SNR vs Input Frequency Figure 33. SINAD vs Input Frequency Figure 34. THD vs Temperature Figure 35. THD vs Reference Voltage

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At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Figure 43. Gain Error vs TemperatureFigure 42. Offset Error vs Temperature Figure 44. Typical DNL Figure 45. Typical INL Figure 46. Typical DNL Figure 47. Typical INL

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7.13 Typical Characteristics: ADS7253

At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Figure 52. Typical FFT Figure 53. Typical FFT Figure 54. Typical FFT Figure 55. Typical FFT Figure 56. SNR vs Temperature Figure 57. SINAD vs Temperature

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At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Figure 58. SNR vs Reference Voltage Figure 59. SINAD vs Reference Voltage Figure 60. SNR vs Input Frequency Figure 61. SINAD vs Input Frequency Figure 62. THD vs Temperature Figure 63. THD vs Reference Voltage

At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Figure 64. THD vs Input Frequency Figure 65. Analog Supply Current vs Temperature Figure 67. Analog Supply Current vs SCLK FrequencyFigure 66. Analog Supply Current vs SCLK Frequency Figure 68. DC Histogram Figure 69. DC Histogram

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At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Figure 70. Offset Error vs Temperature Figure 71. Gain Error vs Temperature Figure 72. Typical DNL Figure 73. Typical INL Figure 74. Typical DNL Figure 75. Typical INL

At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted. Figure 76. DNL vs Temperature Figure 77. DNL vs Temperature Figure 78. DNL vs Reference Voltage Figure 79. INL vs Reference Voltage

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16 CLK Mode 32 CLK Mode

7.14 Typical Characteristics: Common to ADS8353, ADS7853, and ADS7253

At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = maximum, unless otherwise noted. Figure 80. STANDBY Current vs Temperature Figure 81. Power-Down Current vs Temperature Figure 82. Internal Reference Output vs Temperature Figure 83. Internal Reference Output Impedance

ADC_A ADC_B S/H REF_A REF_B ADS8353,ADS7853,ADS7253 SBAS584B –OCTOBER 2013–REVISED AUGUST 2014 www.ti.com

8 Detailed Description

8.1 Overview

These devices belong to a family of pin-compatible, dual, high-speed, simultaneous-sampling, analog-to-digital converters (ADCs). The ADS8353, ADS7853, and ADS7253 support single-ended and pseudo-differential input signals. The devices provide a simple, serial interface to the host controller and operate over a wide range of analog and digital power supplies. These devices have two independently programmable internal references to achieve system-level gain error correction. The Functional Block Diagram section provides a functional block diagram of the device.

8.2 Functional Block Diagram

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Product Folder Links: ADS8353 ADS7853 ADS7253

8.3 Feature Description

8.3.1 Reference

Figure 84. Reference Configurations and Connections operate on external reference voltages provided by the user on the REFIO_A and REFIO_B pins, respectively. respectively. Refer to the REFDAC Registers (REFDAC_A and REFDAC_B) section for more details.

8.3.2 Analog Inputs

channels. These inputs are sampled and converted simultaneously by the two ADCs, ADC_A and ADC_B. ADC_A samples and converts (VAINP_A – VAINM_A), and ADC_B samples and converts (VAINP_B – VAINM_B). Figure 85a and Figure 85b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively. device sampling capacitor (typically 40 pF). Figure 85. Equivalent Circuit for the Analog Input Pins

8.3.2.1 Analog Input: Full-Scale Range Selection

• VREF_A and VREF_B are the reference voltages going to ADC_A and ADC_B, respectively (as described in the Reference section). (2) Therefore, with appropriate settings of the REFDAC_A and REFDAC_B registers, CFR.B7, and CFR.B9, the maximum dynamic range of the ADC can be used. Note that while using CFR.B9 set to 1, care must be taken so that the ADC analog supply (AVDD) is as in Equation 3 and Equation 4: 2 × VREF_A ≤ AVDD ≤ AVDD(max) (3) 2 × VREF_B ≤ AVDD ≤ AVDD(max) (4)

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8.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations

The ADS8353, ADS7853, and ADS7253 can support single-ended or pseudo-differential input configurations. AINM_A and AINM_B must be externally connected to GND. Table 1. Input Configurations

Table 1. Input Configurations (continued)

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8.3.3 Transfer Function

1. Single-ended inputs, CFR.B7 = 0 (default), or
2. Pseudo-differential inputs, CFR.B7 = 1.
3. Straight binary output, CFR.B4 = 0 (default), or
4. Twos compliment output, CFR.B4 = 1.

1 LSB = (FSR_ADC_x) / (2N)

• N = 16 (ADS8353), 14 (ADS7853), or 12 (ADS7253) and
• FSR_ADC_x is the full-scale input range of the ADC (refer to the Analog Input section for more details) (5) Table 2 and Table 3 show the different input voltages and the corresponding output codes from the device.

Table 2. Transfer Characteristics for Straight Binary Output (CFR.B4 = 0, Default) Table 3. Transfer Characteristics for Twos Compliment Output (CFR.B4 = 1)

1 LSB

Figure 86 shows the ideal device transfer characteristics for the single-ended analog input. Figure 86. Ideal Transfer Characteristics for a Single-Ended Analog Input Figure 87 shows the ideal device transfer characteristics for the pseudo-differential analog input. Figure 87. Ideal Transfer Characteristics for a Pseudo-Differential Analog Input

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8.4 Device Functional Modes

allow the user to customize ADC behavior for specific application requirements. Reconversion, or Short-Cycling section).

8.5 Register Maps and Serial Interface

8.5.1 Serial Interface

The device uses the serial clock (SCLK) for synchronizing data transfers in and out of the device. frame is validated and the internal user-programmable registers are updated on the subsequent CS rising edge. This CS rising edge also ends the frame. Table 4. SCLK Falling Edges for a Valid Write Operation valid. Refer to the Frame Abort, Reconversion, or Short-Cycling section for more details.

8.5.2 Write to User Programmable Registers

remain low during the respective frames. bits (B[11:0]). Table 5 lists the various combinations supported for B[15:12]. Table 5. Data Write Operation

8.5.2.1 Configuration Register (CFR)

Figure 88. On power-up, all bits in the CFR default to 0. Figure 88. CFR Bit Functions Table 6. Configuration Register (CFR) Field Descriptions

15 WRITE/READ W 0h

13 ADDR1 R/W 0h to enable bits 11:0

12 ADDR0 R/W 0h

This bit provides clock mode selection for the serial interface.

11 RD_CLK_MODE R/W 0h 1 = Selects 16-CLK mode

This bit provides data line selection for the serial interface.

10 RD_DATA_LINES R/W 0h ADC_B data (default)

9 INPUT_RANGE R/W 0h Analog Inputs section for more details. This bit is used by the device to enter or exit STANDBY mode.5 STANDBY W 0h Refer to the STANDBY Mode section for more details. This bit selects the output data format.

4 RD_DATA_FORMAT R/W 0h 0 = Output is in straight binary format (default)

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8.5.2.2 REFDAC Registers (REFDAC_A and REFDAC_B)

The REFDAC registers, bit functions, and resolution information are described in this section. Figure 89. REFDAC_X Bit Functions Table 7. REFDAC Registers Field Descriptions 15 WRITE/READ W 0h These bits select the configurable register address.

13 ADDR1 R/W 0h 1010 = Select this combination to write to the REFDAC_B

Data to program the individual DAC output voltage. programmed value and the DAC_x output voltage. Table 8. REFDAC Settings with the specified register setting and then experimenting with five codes on either side of the specified register setting.

Valid data as per device configuration. Valid data as per device configuration.

8.5.3 Data Read Operation

8.5.3.1 Reading User-Programmable Registers

The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B. Figure 90 shows a detailed timing diagram for this operation. Note that N is a function of the device configuration, as described in Table 4. Figure 90. Register Readback Timing device during frame (F+1), as shown in Table 9. Frame (F+1) must have at least 48 SCLK falling edges. Table 9. Control Word to Readback User-Programmable Registers 0s for any subsequent SCLK falling edges. The SDO_B pin outputs 0s for all the SCLK falling edges. Table 10. Register Data Read Back Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).

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8.5.3.2 Conversion Data Read

Table 11. Interface Mode Selection The following sections detail the various interface modes supported by the device. writing CFR.B11 = 0 and CFR.B10 = 0. conversion result. Figure 91 shows a detailed timing diagram for this mode. Figure 91. 32-CLK, Dual-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode. result, as shown in Table 12. Table 12. Data Launch Edge ends the frame and puts the serial bus into 3-state. Refer to Table 13 for timing specifications specific to this serial interface mode. Table 13. 32-CLK, Dual-SDO Interface Specific Timing

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Figure 92. 32-CLK, Single-SDO Mode Timing Diagram Table 14. Data Launch Edge ends the frame and puts the serial bus into 3-state.

Refer to Table 15 for timing specifications specific to this serial interface mode. Table 15. 32-CLK, Single-SDO Interface Specific Timing interface mode is not supported by the ADS8353. For the ADS7853 and ADS7253, this interface mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 0. conversion result. Figure 93 shows a detailed timing diagram for this mode. Figure 93. 16-CLK, Dual-SDO Mode Timing Diagram

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A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over. Table 16. Data Launch Edge ends the frame and puts the serial bus into 3-state. Refer to Table 17 for timing specifications specific to this serial interface mode. Table 17. 16-CLK, Dual-SDO Interface Specific Timing

to read the conversion results of both ADCs. This interface mode is not supported by the ADS8353. state and can be treated as a no connect (NC) pin. Figure 94 shows a detailed timing diagram for this mode. Figure 94. 16-CLK, Single-SDO Mode Timing Diagram The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over. Table 18. Data Launch Edge

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ends the frame and puts the serial bus into 3-state. Refer to Table 19 for timing specifications specific to this serial interface mode. Table 19. 16-CLK, Single-SDO Interface Specific Timing

8.5.4 Low-Power Modes

mode and software power-down (SPD) mode.

8.5.4.1 STANDBY Mode

power-up to a normal mode of operation. STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high. To remain in STANDBY mode, SDI must remain low in the subsequent frames. Note that N is a function of the device configuration, as described in Table 4. Figure 95. Enter STANDBY Mode

at least 48 SCLK falling edges. CFR.B[11:6] bits programmed during frame (F+3). Note that N is a function of the device configuration, as described in Table 4. Figure 96. Exit STANDBY Mode Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

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8.5.4.2 Software Power-Down (SPD) Mode

In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down. However, the contents of the REFDAC_A and REFDAC_B registers are retained. To remain in SPD mode, SDI must remain high in subsequent frames. Figure 97. Enter SPD Mode least 48 SCLK falling edges. The output data in frame (F+4) should be discarded. Note that N is a function of the device configuration, as described in Table 4. Figure 98. Exit SPD Mode Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

8.5.5 Frame Abort, Reconversion, or Short-Cycling

edges are provided, the current frame is aborted and the device starts sampling the new analog input signal. The output data bits latched before the CS rising edge are still valid data that correspond to sample N. Figure 99. Frame Abort, Reconversion, or Short-Cycling Feature Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

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/c0b /c0c /cb8 /cb9 /cb7/ca8 /ca9 /ca7/c10 /c10 /c75/c75/c64/c75/c53/c75/c0e /cb8/cb8 /cb8 /cb9 /cb7 /ca8/ca8 /ca8 /ca9 /ca7 /c75/c75 20 dBSNR REF dB 3 RMS_ n PP _AMP_f1 G 10 V 1f2e6 . 6 V /cb8/cb8 /cb9 /cb7 /ca8/ca8 /ca9 /ca7 /c75/c0e/c75/c75/c74/c10 FLTFLTFLT CRRBandwidthGainUnity )(2 /c53 ADS8353,ADS7853,ADS7253 www.ti.com SBAS584B –OCTOBER 2013–REVISED AUGUST 2014

9 Application and Implementation

9.1 Application Information

The two primary circuits required to maximize the performance of a high-precision, successive approximation register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing these circuits, and some application circuits designed using these devices. The device supports operation either with an internal or external reference source. Refer to the Reference section for details about the decoupling requirements. The reference source to the ADC must provide low-drift and very accurate dc voltage and support the dynamic charge requirements without affecting the noise and linearity performance of the device. The output broadband noise (typically in the order of a few 100 μVRMS) of the reference source must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred hertz. After band-limiting the noise from the reference source, the next important step is to design a reference buffer that can drive the dynamic load posed by the reference input of the ADC. At the start of each conversion, the reference buffer must regulate the voltage of the reference pin within 1 LSB of the intended value. This condition necessitates the use of a large filter capacitor at the reference pin of the ADC. The amplifier selected to drive the reference input pin must be stable while driving this large capacitor and should have low output impedance, low offset, and temperature drift specifications. To reduce the dynamic current requirements and crosstalk between the channels, a separate reference buffer is recommended for driving the reference input of each ADC channel. The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision ADC.

9.1.1 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate amplifier to drive the inputs of the ADC are:

• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to maintain the overall stability of the input driver circuit, the amplifier bandwidth should be selected as described in Equation 6: (6)
• Noise. Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band- limited by designing a low cutoff frequency RC filter and is calculated by Equation 7: where:
• V1 / f_AMP_PP is the peak-to-peak flicker noise in µV,
• en_RMS is the amplifier broadband noise density in nV/√Hz,
• f–3dB is the 3-dB bandwidth of the RC filter, and
• NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration. (7) Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: ADS8353 ADS7853 ADS7253

• Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as shown in Equation 8. (8)
• Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired accuracy. Therefore, the settling behavior of the input driver should always be verified by TINA™ - SPICE simulations before selecting the amplifier.

9.1.2 Antialiasing Filter

noise ratio (SNR) of the system. coefficient, and stable electrical characteristics under varying voltages, frequency, and time. Figure 100. Antialiasing Filter

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9.2 Typical Applications

9.2.1 DAQ Circuit to Achieve Maximum SINAD for a 10-kHz Input Signal at Full Throughput

NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels. Figure 101. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at Full Throughput, 32-CLK Interface NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels. Figure 102. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at Full Throughput, 16-CLK Interface

(1) When using the REF5050, AVDD must be set to 5.5 V. Figure 103. Reference Drive Circuit

9.2.1.1 Design Requirements

To design an application circuit optimized to achieve target specifications listed in Table 20. Table 20. Target Specifications

9.2.1.2 Detailed Design Procedure

provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications. without adding distortion to the input signal. in an inverting gain configuration and a low-pass RC filter before being fed into the device.

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before being fed into the device. time makes the OPA2350 a good choice for driving this high capacitive load.

9.2.1.3 Application Curves

operate with internal reference (CFR.B6 = 1) and 2 x VREF_x input full scale range (CFR.B9 = 1). configuration of Figure 101. Figure 104. ADS8353 in 32-CLK Interface Mode Figure 105. ADS7853 in 32-CLK Interface Mode Figure 106. ADS7253 in 32-CLK Interface Mode

respectively, operating at full throughput with 16-CLK interface and the circuit configuration of Figure 102. Figure 107. ADS7853 in 16-CLK Interface Mode Figure 108. ADS7253 in 16-CLK Interface Mode

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9.2.2 DAQ Circuit to Achieve Maximum SINAD for a 100-kHz Input Signal at Full Throughput

NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels. Figure 109. DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at Full Throughput (1) When using the REF5050, AVDD must be set to 5.5 V. Figure 110. Reference Drive Circuit

9.2.2.1 Design Requirements

To design an application circuit optimized to achieve target specifications listed in Table 21. Table 21. Target Specifications

9.2.2.2 Detailed Design Procedure

provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications. required to ensure that the inputs to the device do not exceed AVDD. time makes the OPA2350 a good choice for driving this high capacitive load.

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9.2.2.3 Application Curves

operate with internal reference (CFR.B6 = 1) and 2 x VREF_x input full scale range (CFR.B9 = 1). configuration of Figure 109. Figure 111. ADS8353 in 32-CLK Interface Mode Figure 112. ADS7853 in 32-CLK Interface Mode Figure 113. ADS7253 in 32-CLK Interface Mode

respectively, operating with a 16-CLK interface and the circuit configuration of Figure 109. Figure 114. ADS7853 in 16-CLK Interface Mode Figure 115. ADS7253 in 16-CLK Interface Mode

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10 Power-Supply Recommendations

Figure 116. Power-Supply Decoupling

11 Layout

11.1 Layout Guidelines

Figure 117 shows a board layout example for the ADS8353, ADS7853, and ADS7253 with the WQFN package. the board and the digital connections are routed on the right side of the device. with the reference bypass capacitors to improve stability. changes. Figure 117 shows CIN-A and CIN-B filter capacitors placed across the analog input pins of the device.

11.2 Layout Example

Figure 117. Recommended Layout

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12 Device and Documentation Support

12.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 22. Related Links

12.2 Related Documentation

• TIPD117 Verified Design Reference Guide: 12 Bit 1 MSPS Single Supply Dual Channel Data Acquisition System for Optical Encoders in Motor Control Application Reference Design, SLAU517.
• REF5050 Data Sheet, SBOS410.
• OPA2350 Data Sheet, SBOS099.
• OPA836, OPA2836 Data Sheet, SLOS712.
• THS4032 Data Sheet, SLOS224.

12.3 Trademarks

TINA is a trademark of Texas Instruments Inc.. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS7253IPW Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IPW.A Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IPW.B Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IPWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IPWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IPWR.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IPWRG4 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IPWRG4.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IPWRG4.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7253 ADS7253IRTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7253IRTER.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7253IRTER.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7253IRTET Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7253IRTET.A Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7253IRTET.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7253IRTETG4 Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7253IRTETG4.A Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7253IRTETG4.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7253 ADS7853IPW Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7853 ADS7853IPW.A Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7853 ADS7853IPW.B Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7853 ADS7853IPWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7853 ADS7853IPWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7853 ADS7853IPWR.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7853 ADS7853IRTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7853 ADS7853IRTER.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7853 ADS7853IRTERG4 Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7853 ADS7853IRTERG4.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7853 ADS7853IRTET Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7853 Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS7853IRTET.A Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7853 ADS7853IRTET.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 7853 ADS8353IPW Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IPW.A Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IPW.B Active Production TSSOP (PW) | 16 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IPWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IPWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IPWR.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IPWRG4 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IPWRG4.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IPWRG4.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8353 ADS8353IRTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 ADS8353IRTER.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 ADS8353IRTER.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 ADS8353IRTERG4 Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 ADS8353IRTERG4.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 ADS8353IRTERG4.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 ADS8353IRTET Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 ADS8353IRTET.A Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 ADS8353IRTET.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 8353 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2

www.ti.com 7-Oct-2025 (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS8353 :

• Automotive : ADS8353-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7253IPWR TSSOP PW 16 2000 353.0 353.0 32.0 ADS7253IPWRG4 TSSOP PW 16 2000 353.0 353.0 32.0 ADS7253IRTER WQFN RTE 16 3000 353.0 353.0 32.0 ADS7253IRTET WQFN RTE 16 250 213.0 191.0 35.0 ADS7253IRTETG4 WQFN RTE 16 250 213.0 191.0 35.0 ADS7853IPWR TSSOP PW 16 2000 353.0 353.0 32.0 ADS7853IRTER WQFN RTE 16 3000 353.0 353.0 32.0 ADS7853IRTERG4 WQFN RTE 16 3000 353.0 353.0 32.0 ADS7853IRTET WQFN RTE 16 250 213.0 191.0 35.0 ADS8353IPWR TSSOP PW 16 2000 353.0 353.0 32.0 ADS8353IPWRG4 TSSOP PW 16 2000 353.0 353.0 32.0 ADS8353IRTER WQFN RTE 16 3000 353.0 353.0 32.0 ADS8353IRTERG4 WQFN RTE 16 3000 353.0 353.0 32.0 ADS8353IRTET WQFN RTE 16 250 213.0 191.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADS7253IPW PW TSSOP 16 90 530 10.2 3600 3.5 ADS7253IPW.A PW TSSOP 16 90 530 10.2 3600 3.5 ADS7253IPW.B PW TSSOP 16 90 530 10.2 3600 3.5 ADS7853IPW PW TSSOP 16 90 530 10.2 3600 3.5 ADS7853IPW.A PW TSSOP 16 90 530 10.2 3600 3.5 ADS7853IPW.B PW TSSOP 16 90 530 10.2 3600 3.5 ADS8353IPW PW TSSOP 16 90 530 10.2 3600 3.5 ADS8353IPW.A PW TSSOP 16 90 530 10.2 3600 3.5 ADS8353IPW.B PW TSSOP 16 90 530 10.2 3600 3.5 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRTE 16 PLASTIC QUAD FLATPACK - NO LEAD3 x 3, 0.5 mm pitch 4225944/A

www.ti.com PACKAGE OUTLINE C 3.15 2.85 3.15 2.85 0.8 0.7 0.05 0.00 2X 1.5 12X 0.5 2X 1.5 16X 0.5 0.3 16X 0.30 0.18 0.8 0.1 (0.2) TYP WQFN - 0.8 mm max heightRTE0016D PLASTIC QUAD FLATPACK - NO LEAD 4219118/A 11/2018 0.08 C 0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM EXPOSED THERMAL PAD SYMM 5 8 1316 SCALE 4.000 AB

www.ti.com EXAMPLE BOARD LAYOUT 12X (0.5) (R0.05) TYP

0.07 MAX

0.07 MIN

16X (0.6) 16X (0.24) (2.8) (2.8) ( 0.8) ( 0.2) TYP VIA WQFN - 0.8 mm max heightRTE0016D PLASTIC QUAD FLATPACK - NO LEAD 4219118/A 11/2018 SEE SOLDER MASK DETAIL NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 5 8 1316 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 0.76) (R0.05) TYP WQFN - 0.8 mm max heightRTE0016D PLASTIC QUAD FLATPACK - NO LEAD 4219118/A 11/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X EXPOSED PAD 17 90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 5 8 1316

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