ADSC570WCSWZ42XX

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SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc. Information furnished by Analog Devices is believed to be accurate and reliable. infringements of patents or other rights of third parties that may result from its use. registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved.

500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle

Figure 1. Processor Block Diagram

3 Mb (384 kB)

8 Mb (1 MB)

Rev. B | Page 2 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 TABLE OF CONTENTS ADSP-SC57x/ADSP-2157x Detailed Signal ADSP-SC57x/ADSP-2157x Designer Quick Reference .... 45 ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Configuration of the 176-Lead LQFP Lead

REVISION HISTORY

6/2018—Rev. A to Rev. B Changes to Table 27 and Table 28, Clock Related Operating Changes to Table 29, Table 32, and Table 33, Total Internal Changes to Program Trace Macrocell (PTM) Timing .... 120

require high floating-point performance. across the standard processors. across the automotive processors. Table 1. Common Product Features

Table 2. Comparison of ADSP-SC57x/ADSP-2157x Processor Features1 Table 3. Comparison of ADSP-SC57x/ADSP-2157x Processor Features for Automotive 1

• Instruction cache unit (32 Kb) and data Level 1 (L1) cache unit (32 Kb)
• In order pipeline with dynamic branch prediction
• ARM, Thumb, and ThumbEE instruction set support
• A R M T r u s t Z o n e® security extensions
• Harvard L1 memory system with a memory management unit (MMU)
• ARM v7 debug architecture
• Trace support through an embedded trace macrocell (ETM) interface
• Extension—vector floating-poin t unit (IEEE754) with trap- less execution
• Extension—media processing engine (MPE) with NEON TM technology
• Extension—Jazelle ® hardware acceleration

Figure 2. ARM Cortex-A5 Processor Block Diagram

32 Kb 32 Kb

Figure 5 shows the ADSP-SC57x/ADSP-2157x memory map. also access this memory space with multicycle accesses.

1024 Kb/512 Kb can be configured for data memory (DM),

(DMA) engine in a single cycle. and data using the PM bus for transfers. Figure 4. SHARC+ SIMD Core Block Diagram

accessed either directly or via cache. tions. The second master port drives data to the system world. address, refer to the L1 memory address map in Table 4. (D-cache) (PM/DM caches) with parity support for all caches. controllers automatically manage the configured L1 memory. ing, range bound invalidation, and flushing. control, debug, and monitor functions. shown in Figure 4 and detailed in the following sections. Figure 5. ADSP-SC57x/ADSP-2157x Memory Map

Rev. B | Page 9 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Single-Instruction, Multiple Data (SIMD) Computational Engine The SHARC+ core contains two computational processing ele- ments that operate as a single-instruction, multiple data (SIMD) engine. The processing elements are referred to as PEx and PEy data registers and each contain an arithmetic logic unit (ALU), mul- tiplier, shifter, and register file. PEx is always active and PEy is enabled by setting the PEYEN mode bit in the mode control register (MODE1). SIMD mode allows the processors to execute the same instruc- tion in both processing elements, but each processing element operates on different data. This architecture efficiently executes math intensive DSP algorithms. In addition to all the features of previous generation SHARC cores, the SHARC+ core also pro- vides a new and simpler way to execute an instruction only on the PEy data register. SIMD mode also affects the way data transfers between memory and the processing elements because to sustain computational operation in the processing elements requires twice the data bandwidth. Therefore, entering SIMD mode doubles the band- width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values transfer with each memory or register file access. Independent Parallel Computation Units Within each processing element is a set of pipelined computa- tional units. The computational units consist of a multiplier, arithmetic/logic unit (ALU), and shifter. These units are arranged in parallel, maximizing computational throughput. These computational units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, IEEE 64-bit double-precision floating-point, and 32-bit fixed-point data formats. A multifunction instruction set supports parallel execution of the ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing ele- ments per core. All processing operations take one cycle to complete. For all floating-point operations, the processor takes two cycles to complete in case of data dependency. Double-precision float- ing-point data take two to six cycles to complete. The processor stalls for the appropriate number of cycles for an interlocked pipeline plus data dependency check. Core Timer Each SHARC+ processor core also has a timer. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generating periodic operating system interrupts. Data Register File Each processing element contains a general-purpose data regis- ter file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register register files (16 primary, 16 secondary), combined with the enhanced Harvard architecture of the pro- cessor, allow unconstrained data flow between computation units and internal memory. The registers in the PEx data regis- ter file are referred to as R0–R15 and in the PEy data register file as S0–S15. Context Switch Many of the registers of the processor have secondary registers that can activate during interrupt servicing for a fast context switch. The data, DAG, and multiplier result registers have sec- ondary registers. The primary registers are active at reset, while control bits in MODE1 activate the secondary registers. Universal Registers General-purpose tasks use the universal registers. The four USTAT registers allow easy bit manipulations (set, clear, toggle, test, XOR) for all control and status peripheral registers. The data bus exchange register (PX) permits data to pass between the 64-bit PM data bus and the 64-bit DM data bus or between the 40-bit register file and the PM or DM data bus. These registers contain hardware to handle the data width difference. Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support For indirect addressing and implementing circular data buffers in hardware, the ADSP-SC57x/ADSP-2157x processor uses the two data address generators (DAGs). Circular buffers allow effi- cient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fast Fourier transforms (FFT). The two DAGs of the processors contain sufficient registers to allow the cre- ation of up to 32 circular buffers (16 primary register sets and 16 secondary sets). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set Architecture (ISA) The flexible instruction set architecture (ISA), a 48-bit instruc- tion word, accommodates various parallel operations for concise programming. For example, the processors can condi- tionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Addi- tionally, the double-precision floating-point instruction set is an addition to the SHARC+ core.

Rev. B | Page 10 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Variable Instruction Set Architecture (VISA) In addition to supporting the standard 48-bit instructions from previous SHARC processors, the SHARC+ core processors sup- port 16-bit and 32-bit opcodes for many instructions, formerly 48-bit in the ISA. This feature, called variable instruction set architecture (VISA), drops redundant or unused bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32- bit instructions from both internal and external memories. VISA is not an operating mode; it is only address dependent (refer to memory map ISA/VISA address spaces in Table 7). Furthermore, it allows jumps between ISA and VISA instruc- tion fetches. Single-Cycle Fetch of Instructional Four Operands The ADSP-SC57x/ADSP-2157x processors feature an enhanced Harvard architecture in which the DM bus transfers data and PM bus transfers both instructions and data. With the separate program memory bus, data memory buses, and on-chip instruction conflict cache, the processor can simul- taneously fetch four operands (two over each data bus) and one instruction from the conflict cache, in a single cycle. Core Event Controller (CEC) The SHARC+ core generates various core interrupts (including arithmetic and circular buffer instruction flow exceptions) and SEC events (debug or monitor and software). The core event controller (CEC) is used to unmask interrupts for core process- ing (enabled in the IMASK register). Instruction Conflict Cache The processors include a 32-entry instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions that require fetches conflict with the PM bus data accesses cache. This cache allows full speed execution of core, looped operations, such as digital filter multiply accumulates, and FFT butterfly process- ing. The conflict cache serves for on-chip bus conflicts only. Branch Target Buffer (BTB)/Branch Predictor (BP) Implementation of a hardware-based branch predictor (BP) and branch target buffer (BTB) reduce branch delay. The program sequencer supports efficient branching using the BTB for condi- tional and unconditional instructions. Addressing Spaces In addition to traditionally supported long word, normal word, extended precision word, and short word addressing aliases, the processors support byte addressing for the data and instruction accesses. The enhanced ISA/VISA provides new instructions for accessing all sizes of data from byte space as well as converting word addresses to byte and byte to word addresses. Additional Features The enhanced ISA/VISA of the ADSP-SC57x/ADSP-2157x pro- cessors provides a memory barrier instruction for data synchronization, exclusive data access support for multicore data sharing, and exclusive data access to enable multiprocessor programming. To enhance the reliability of the application, L1 data RAMs support parity error detection logic for every byte. Additionally, the processors detect illegal opcodes. Core inter- rupts flag both errors. Master ports of the core also detect for failed external accesses. SYSTEM INFRASTRUCTURE The following sections describe the system infrastructure of the ADSP-SC57x/ADSP-2157x processors. System L2 Memory A system L2 SRAM memory of 8 Mb (1 MB) is available to both SHARC+ cores, the ARM Cortex-A5 core, and the system DMA channels (see Table 5). The L2 SRAM block is subdivided into eight banks to support concurrent access to the L2 memory ports. Memory accesses to the L2 memory space are multicycle accesses by both the ARM Cortex-A5 and SHARC+ cores. The memory space is used for various situations including

• ARM Cortex-A5 to SHARC+ core data sharing and inter- core communications
• Accelerator and peripheral sources and destination mem- ory to avoid accessing data in the external memory
• A location for DMA descriptors
• Storage for additional data for either the ARM Cortex-A5 or SHARC+ cores to avoid external memory latencies and reduce external memory bandwidth
• Storage for incoming Ethernet traffic to improve performance
• Storage for data coefficient tables cached by the SHARC+ core See System Memory Protection Unit (SMPU) section for options in limiting access by specific cores and DMA masters. The ARM Cortex-A5 core has an L1 instruction and data cache, each of which is 32 kB in size. The core also has an L2 cache controller of 256 kB. When enabling the caches, accesses to all other memory spaces (internal and external) go through the cache. SHARC+ Core L1 Memory in Multiprocessor Space The ARM Cortex-A5 core can access the L1 memory of the SHARC+ core. See Table 6 for the L1 memory address in multi- processor space. The SHARC+ core can access the L1 memory of the other SHARC+ core in the multiprocessor space. One Time Programmable Memory (OTP) The processors feature 7 Kb of one time programmable (OTP) memory which is memory map accessible. This memory can be programmed with custom keys and it supports secure boot and secure operation. I/O Memory Space Mapped I/Os include SPI2 memory address space (see Table 7).

Table 4. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+ ® Addressing Memory Map (Private Address Space) Table 5. L2 Memory Addressing Map 1 All L2 RAM blocks are subdivided into eight banks. 2 For ADSP-SC57x products, the L2 Boot ROM0 byte address space is 0x00000000–0x00007FFF. 3 L2 Boot ROM address for ADSP-2157x products. Table 6. SHARC+ ® L1 Memory in Multiprocessor Space Table 7. Memory Map of Mapped I/Os 1 do not cover the entire byte address space.

• Highly efficient, pipelined bu s transfer protocol for sus- tained throughput
• Full-duplex bus operation for flexibility and reduced latency
• Concurrent bus transfer supp ort to allow multiple bus masters to access bus slaves simultaneously
• Protection model (privileged/secure) support for selective bus interconnect protection Direct Memory Access (DMA) The processors use direct memory access (DMA) to transfer data within memory spaces or between a memory space and a peripheral. The processors can specify data transfer operations and return to normal processing while the fully integrated DMA controller carries out the data transfers independent of proces- sor activity. DMA transfers can occur between memory and a peripheral or between one memory and another memory. Each memory to memory DMA stream uses two channels: the source channel and the destination channel. All DMA channels can transport data to and from all on-chip and off-chip memories. Programs can use two types of DMA transfers: descriptor-based or register-based. Register-based DMA allows the processors to program DMA control registers directly to initiate a DMA transfer. On completion, the DMA control registers automatically update with original setup values for continuous transfer. Descriptor-based DMA transfers require a set of parameters stored within memory to initiate a DMA sequence. Descriptor-based DMA transfers allow multiple DMA sequences to be chained together. Program a DMA channel to set up and start another DMA transfer auto- matically after the current sequence completes. The DMA engine supports the following DMA operations:
• A single linear buffer that stops on completion
• A linear buffer with negative, positive, or zero stride length
• A circular autorefres hing buffer that interrupts when each buffer becomes full
• A similar circular buffer that interrupts on fractional buf- fers, such as at the halfway point
• The 1D DMA uses a set of identical ping pong buffers defined by a linked ring of two-word descriptor sets, each containing a link pointer and an address
• The 1D DMA uses a linked list of four-word descriptor sets containing a link pointer, an address, a length, and a configuration
• The 2D DMA uses an array of one-word descriptor sets, specifying only the base DMA address
• The 2D DMA uses a linked li st of multiword descriptor sets, specifying all configurable parameters Memory Direct Memory Access (MDMA) The processor supports various memory direct memory access (MDMA) operations, including,
• Enhanced bandwidth MDMA channels with CRC protec- tion (32-bit bus width, run on SYSCLK)
• Enhanced bandwidth MDMA channel (32-bit bus width, runs on SYSCLK)
• Maximum bandwidth MDMA ch annel (64-bit bus width, runs on SYCLK) Extended Memory DMA Extended memory DMA supports various operating modes, such as delay line (which allows processor reads and writes to external delay line buffers and to the external memory), with limited core interaction and scatter/gather DMA (writes to and from noncontiguous memory blocks). Cyclic Redundant Code (CRC) Protection The cyclic redundant codes (CRC) protection modules allow system software to calculate the signature of code, data, or both in memory, the content of memory-mapped registers, or

Table 8. DMC Memor y Map do not cover the entire byte address space.

Rev. B | Page 13 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 periodic communication message objects. Dedicated hardware circuitry compares the signature with precalculated values and triggers appropriate fault events. For example, every 100 ms the system software initiates the sig- nature calculation of the entire memory contents and compares these contents with expected, precalculated values. If a mis- match occurs, a fault condition is generated through the processor core or the trigger routing unit. The CRC is a hardware module based on a CRC32 engine that computes the CRC value of the 32-bit data-words presented to it. The source channel of the memory to memory DMA (in memory scan mode) provides data. The data can be optionally forwarded to the destination channel (memory transfer mode). The main features of the CRC peripheral are as follows:

• Memory scan mode
• Memory transfer mode
• Data verify mode
• Data fill mode
• User-programmable CRC32 polynomial
• Bit and byte mirrorin g option (endianness)
• Fault and error interrupt mechanisms
• 1D and 2D fill block to initialize an array with constants
• 32-bit CRC signature of a bl ock of a memory or an MMR block Event Handling The processors provide event handling that supports both nest- ing and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing a higher priority event takes precedence over servicing a lower priority event. The processors provide support for four different types of events:
• An emulation event causes the processors to enter emula- tion mode, allowing command and control of the processors through the JTAG interface.
• A reset event resets the processors.
• An exceptions event occurs sy nchronously to program flow (in other words, the exception is taken before the instruc- tion is allowed to complete). Conditions triggered on the one side by the SHARC+ core, such as data alignment (SIMD or long word) or compute violations (fixed or float- ing point), and illegal instructions cause core exceptions. Conditions triggered on the other side by the SEC, such as error correcting codes (ECC), parity, watchdog, or system clock, cause system exceptions.
• An interrupts event occurs asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. System Event Controller (SEC) Both SHARC+ cores feature a system event controller. The SEC features include the following:
• Comprehensive system event source management, includ- ing interrupt enable, fault enable, priority, core mapping, and source grouping
• A distributed programming model where each system event source control and all status fields are independent of each other
• Determinism where all system events have the same propa- gation delay and provide unique identification of a specific system event source
• A slave control port that provides access to all SEC registers for configuration, status, and interrupt and fault services
• Global locking that supports a register level protection model to prevent writes to locked registers
• Fault management including fault action configuration, time out, external indication, and system reset Trigger Routing Unit (TRU) The trigger routing unit (TRU) provides system level sequence control without core intervention. The TRU maps trigger masters (generators of triggers) to trigger slaves (receivers of triggers). Slave endpoints can be configured to respond to trig- gers in various ways. Common applications enabled by the TRU include,
• Automatically triggering the start of a DMA sequence after a sequence from another DMA channel completes
• Software triggering
• Synchronization of concurrent activities SECURITY FEATURES The following sections describe the security features of the ADSP-SC57x/ADSP-2157x processors. ARM TrustZone The ADSP-SC57x processors provide TrustZone technology that is integrated into the ARM Cortex-A5 processors. The TrustZone technology enables a secure state that is extended throughout the system fabric. Cryptographic Hardware Accelerators The ADSP-SC57x/ADSP-2157x processors support standards- based hardware accelerated encryption, decryption, authentica- tion, and true random number generation. Support for the hardware accelerated cryptographic ciphers includes the following:
• AES in ECB, CBC, ICM, an d CTR modes with 128-bit, 192-bit, and 256-bit keys
• DES in ECB and CBC mode with 56-bit key
• 3DES in ECB and CBC mode with 3x 56-bit key
• ARC4 in stateful, statele ss mode, up to 128-bit key

Rev. B | Page 14 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Support for the hardware accelerated hash functions includes the following:

• S H A - 1
• SHA-2 with 224-bit and 256-bit digests
• HMAC transforms for SHA-1 and SHA-2
• M D 5 Public key accelerator (PKA) is available to offload computation intensive public key cryptography operations. Both a hardware-based nondeterministic random number gen- erator and pseudorandom number generator are available. Secure boot is also available with 224-bit elliptic curve digital signatures ensuring integrity and authenticity of the boot stream. Optionally, ensuring confidentiality through AES-128 encryption is available. Employ secure debug to allow only trusted users to access the system with debug tools. System Protection Unit (SPU) The system protection unit (SPU) guards against accidental or unwanted access to an MMR space of the peripheral by provid- ing a write protection mechanism. The user can choose and configure the protected peripherals as well as configure which of the four system MMR masters (two SHARC+ cores, memory DMA, and CoreSight debug) the peripherals are guarded against. The SPU is also part of the security infrastructure. Along with providing write protection functionality, the SPU is employed to define which resources in the system are secure or nonsecure as well as block access to secure resources from nonsecure masters. System Memory Protection Unit (SMPU) The system memory protection unit (SMPU) provides memory protection against read and/or write transactions to defined regions of memory. There are SMPU units in the ADSP- SC57x/ADSP-2157x processors for each memory space, except for SHARC L1 and SPI direct memory slave. The SMPU is also part of the security infrastructure. It allows the user to protect against arbitrary read and/or write transac- tions and allows regions of memory to be defined as secure and prevent nonsecure masters from accessing those memory regions. SECURITY FEATURES DISCLAIMER To our knowledge, the Security Features, when used in accor- dance with the data sheet and hardware reference manual specifications, provide a secure method of implementing code and data safeguards. However, Analog Devices does not guaran- tee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE SECURITY FEATURES CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. SAFETY FEATURES The ADSP-SC57x/ADSP-2157x processors are designed to sup- port functional safety applications. While the level of safety is mainly dominated by the system concept, the following primi- tives are provided by the processors to build a robust safety concept. Multiparity Bit Protected SHARC+ Core L1 Memories In the SHARC+ core L1 memory space, whether SRAM or cache, multiple parity bits protect each word to detect the single event upsets that occur in all RAMs. Parity also protects the cache tags and BTB. Parity Protected ARM L1 Cache In the ARM Cortex-A5 L1 cache space, each word is protected by multiple parity bits to detect the single event upsets that occur in all RAMs. Parity also protects the cache tags. Error Correcting Codes (ECC) Protected L2 Memories Error correcting codes (ECC) correct single event upsets. A sin- gle error correct/double error detect (SEC/DED) code protects the L2 memory. By default, ECC is enabled, but it can be dis- abled on a per bank basis. Single-bit errors correct transparently. If enabled, dual-bit errors can issue a system event or fault. ECC protection is fully transparent to the user, even if L2 memory is read or written by 8-bit or 16-bit entities. Parity-Protected Peripheral Memories Parity protection is added to all peripheral memories:
• A S R C
• IIR
• F I R
• U S B
• C A N
• CRYPTO
• E M A C
• S D I O
• M L B
• T R A C E CAUTION This product includes security features that can be used to protect embedded nonvolatile memory contents and prevent execution of unauthorized code. When security is enabled on this device (either by the ordering party or the subsequent receiving parties), the ability of Analog Devices to conduct failure analysis on returned devices is limited. Contact Analog Devices for details on the failure analysis limitations for this device.

Rev. B | Page 15 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Cyclic Redundant Code (CRC) Protected Memories While parity bit and ECC protection mainly protect against ran- dom soft errors in L1 and L2 memory cells, the cyclic redundant code (CRC) engines can protect against systematic errors (pointer errors) and static content (instruction code) of L1, L2, and even Level 3 (L3) memories (DDR2, LPDDR). The proces- sors feature two CRC engines that are embedded in the memory to memory DMA controllers. CRC checksums can be calculated or compared automatically during memory transfers, or one or multiple memory regions can be continuously scrubbed by a single DMA work unit as per DMA descriptor chain instructions. The CRC engine also pro- tects data loaded during the boot process. Signal Watchdogs The eight general-purpose (GP) timers feature modes to moni- tor off-chip signals. The watchdog period mode monitors whether external signals toggle with a period within an expected range. The watchdog width mode monitors whether the pulse widths of external signals are within an expected range. Both modes help detect undesired toggling or lack of toggling of system level signals. System Event Controller (SEC) Besides system events, the system event controller (SEC) further supports fault management including fault action configuration as timeout, internal indication by system interrupt, or external indication through the SYS_FAULT pin and system reset. Memory Error Controller (MEC) The memory error controller (MEC) manages memory par- ity/ECC errors and warnings from the cores and peripherals and sends out interrupts and triggers. PROCESSOR PERIPHERALS The following sections describe the peripherals of the ADSP- SC57x/ADSP-2157x processors. Dynamic Memory Controller (DMC) The 16-bit dynamic memory controller (DMC) interfaces to

• LPDDR1 (JESD209A) maximum frequency 200 MHz, DDRCLK (64 Mb to 2 Gb)
• DDR2 (JESD79-2E) maximum frequency 400 MHz, DDRCLK (256 Mb to 4 Gb)
• DDR3 (JESD79-3E) maximum frequency 450 MHz, DDRCLK (512 Mb to 8 Gb)
• DDR3L (1.5 V compatible only) maximum frequency

450 MHz, DDRCLK (512 Mb to 8 Gb)

See Table 8 for the DMC memory map. Digital Audio Interface (DAI) The processors support one mirrored digital audio interface (DAI) unit. The DAI can connect various peripherals to any of the DAI pins (DAI_PIN20–DAI_PIN01). The application code makes these connections using the signal routing unit (SRU), shown in Figure 1. The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to interconnect under software control. This functionality allows easy use of the DAI associated peripherals for a wider variety of applications by using a larger set of algorithms than is possible with nonconfig- urable signal paths. The DAI includes the peripherals described in the following sec- tions (SPORTs, ASRC, S/PDIF, and PCG). DAI Pin Buffers 20 and 19 can change the polarity of the input signals. Most signals of the peripherals belonging to different DAIs cannot be inter- connected, with few exceptions. The DAI_PINx pin buffers can also be used as GPIO pins. DAI input signals allow the triggering of interrupts on the rising edge, falling edge, or both. See the Digital Audio Interface (DAI) chapter of the ADSP- SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for complete information on the use of the DAIs and SRUs. Serial Port (SPORT) The processors feature four synchronous full serial ports (SPORTs). These ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. These devices include Analog Devices AD19xx and ADAU19xx family of audio codecs, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Two data lines, a clock, and frame sync make up the serial ports. The data lines can be programmed to either transmit or receive data and each data line has a dedicated DMA channel. An individual full SPORT module consists of two inde- pendently configurable SPORT halves with identical functionality. Two bidirectional data lines—primary (0) and secondary (1)—are available per SPORT half and are configu- rable as either transmitters or receivers. Therefore, each SPORT half permits two unidirectional streams into or out of the same SPORT. This bidirectional functionality provides greater flexibility for serial communications. For full-duplex configura- tion, one half SPORT provides two transmit signals, while the other half SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in the following six modes:

• Standard DSP serial mode
• Multichannel time division multiplexing (TDM) mode 2S mode
• Packed I 2S mode
• Left justified mode
• Right justified mode Asynchronous Sample Rate Converter (ASRC) The asynchronous sample rate converter (ASRC) contains four ASRC blocks. It is the same core in the AD1896 192 kHz stereo asynchronous sample rate converter. The ASRC provides up to 140 dB signal-to-noise ratio (SNR). The ASRC block performs

Rev. B | Page 16 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The ASRC blocks can also be configured to operate together to convert multichannel audio data without phase mis- matches. Finally, the ASRC can clean up audio data from jittery clock sources such as the S/PDIF receiver. S/PDIF-Compatible Digital Audio Receiver/Transmitter The Sony/Philips Digital Interface Format (S/PDIF) is a stan- dard audio data transfer format that allows the transfer of digital audio signals from one device to another without converting them to an analog signal. There is one S/PDIF transmit/receive block on the processor. The digital audio interface carries three types of information: audio data, nonaudio data (compressed data), and timing information. The S/PDIF interface supports one stereo channel or com- pressed audio streams. The S/PDIF transmitter and receiver are AES3 compliant and support the sample rate from 24 KHz to 192 KHz. The S/PDIF receiver supports professional jitter standards. The S/PDIF receiver/transmitter has no separate DMA chan- nels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/ transmitter can be formatted as left justified, I 2S, or right justi- fied with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from various sources, such as the SPORTs, external pins, and the precision clock generators (PCGs), and are controlled by the SRU control registers. Precision Clock Generators (PCG) The precision clock generators (PCG) consist of two units located in the DAI block. The PCG can generate a pair of signals (clock and frame sync) derived from a clock input signal (CLKIN, SCLK0, or DAI pin buffer). Both units are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Enhanced Parallel Peripheral Interface (EPPI) The processors provide an enhanced parallel peripheral inter- face (EPPI) that supports data widths up to 16 bits for the BGA package and 12 bits for the LQFP package. The EPPI supports direct connection to thin film transistor (TFT) LCD panels, par- allel ADCs and DACs, video encoders and decoders, image sensor modules, and other general-purpose peripherals. The features supported in the EPPI module include the following:

• Programmable data length of 8 bi ts, 10 bits, 12 bits, 14 bits, and 16 bits per clock.
• Various framed, nonframed, and general-purpose operat- ing modes. Frame syncs can be generated internally or can be supplied by an external device.
• ITU-656 status word error detection and correction for ITU-656 receive modes and ITU-656 preamble and status word decoding.
• Optional packing and unpacking of data to/from 32 bits from/to 8 bits and 16 bits. If packing/unpacking is enabled, configure endianness to change the order of pack- ing/unpacking of bytes or words.
• RGB888 can be converted to RGB666 or RGB565 for trans- mit modes.
• Various deinterleaving/interle aving modes for receiving or transmitting 4:2:2 YCrCb data.
• Configurable LCD data enable output available on Frame Sync 3. Universal Asynchronous Receiver/Transmitter (UART) Ports The processors provide three full-duplex universal asynchro- nous receiver/transmitter (UART) ports, fully compatible with PC standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full- duplex, DMA supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits as well as no parity, even parity, or odd parity. Optionally, an additional address bit can be transferred to inter- rupt only addressed nodes in multidrop bus (MDB) systems. A frame is terminated by a configurable number of stop bits. The UART ports support automatic hardware flow control through the clear to send (CTS) input and request to send (RTS) output with programmable assertion first in, first out (FIFO) levels. To help support the Local Interconnect Network (LIN) proto- cols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a pro- grammable interframe space. Serial Peripheral Interface (SPI) Ports The processors have three industry-standard SPI-compatible ports that allow the processors to communicate with multiple SPI-compatible devices. The baseline SPI peripheral is a synchronous, 4-wire interface consisting of two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other SPI-compatible devices. An extra two (optional) data pins are provided to support quad-SPI operation. Enhanced modes of operation, such as flow control, fast mode, and dual-I/O mode (DIOM), are also supported. DMA mode allows for trans- ferring several words with minimal central processing unit (CPU) interaction. With a range of configurable options, the SPI ports provide a glueless hardware interface with other SPI-compatible devices in master mode, slave mode, and multimaster environments. The SPI peripheral includes programmable baud rates, clock phase, and clock polarity. The peripheral can operate in a multi- master environment by interfacing with several other devices,

Rev. B | Page 17 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 acting as either a master device or a slave device. In a multimas- ter environment, the SPI peripheral uses open-drain outputs to avoid data bus contention. The flow control features enable slow slave devices to interface with fast master devices by providing an SPI ready pin (SPI_RDY) which flexibly controls the transfers. The baud rate and clock phase and polarities of the SPI port are programmable. The port has integrated DMA channels for both transmit and receive data streams. Link Port (LP) Two 8-bit wide link ports (LPs) for the BGA package (one link port for the LQFP package) can connect to the link ports of other DSPs or peripherals. Link ports are bidirectional and have eight data lines, an acknowledge line, and a clock line. ADC Control Module (ACM) Interface The ADC control module (ACM) provides an interface that synchronizes the controls between the processors and an ADC. The analog-to-digital conversions are initiated by the proces- sors, based on external or internal events. The ACM allows for flexible scheduling of sampling instants and provides precise sampling signals to the ADC. The ACM synchronizes the ADC conversion process, generat- ing the ADC controls, the ADC conversion start signal, and other signals. The actual data acquisition from the ADC is done by an internal DAI routing of the ACM with the SPORT0 block. The processors interface directly to many ADCs without any glue logic required. Ethernet Media Access Controller (EMAC) The processor features an ethernet media access controller (EMAC): 10/100/1000 AVB Ethernet with precision time proto- col (IEEE 1588). The processors can directly connect to a network through embedded fast EMAC that supports 10Base-T (10 Mb/sec), 100Base-T (100 Mb/sec) and 1000Base-T (1 Gb/sec) operations. Some standard features of the EMAC are as follows:

• Support and MII/RMII/RGM II protocols for external PHYs.
• RGMII support for the BGA package only
• Full-duplex and half-duplex modes
• Media access management (in half-duplex operation)
• Flow control
• Station management, including the generation of MDC/MDIO frames for read/write access to PHY registers Some advanced features of the EMAC include the following:
• Automatic checksum computat ion of IP header and IP payload fields of receive frames
• Independent 32-bit descriptor driven receive and transmit DMA channels
• Frame status delivery to memory through DMA, including frame completion semaphores for efficient buffer queue management in software
• Transmit DMA support for separate descriptors for MAC header and payload fields to eliminate buffer copy operations
• Convenient frame alignment modes
• 47 MAC management statistics counters with selectable clear on read behavior and programmable interrupts on half maximum value
• Advanced power management
• Magic packet detection and wakeup frame filtering
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression Audio Video Bridging (AVB) Support The 10/100/1000 EMAC supports the following audio video bridging (AVB) features:
• Separate channels or queues for AV data transfer in

100 Mbps and 1000 Mbps modes)

• IEEE 802.1-Qav specified credit -based shaper (CBS) algo- rithm for the additional transmit channels
• Configuring up to two additi onal channels (Channel 1 and Channel 2) on the transmit and receive paths for AV traffic. Channel 0 is available by default and carries the legacy best effort Ethernet traffic on the transmit side.
• Separate DMA, transmit and receive FIFO for AVB latency class
• Programmable control to route received VLAN tagged non AV packets to channels or queues Precision Time Protocol (PTP) IEEE 1588 Support The IEEE 1588 standard is a precision clock synchronization protocol for networked measurement and control systems. The processors include hardware support for IEEE 1588 with an integrated precision time protocol synchronization engine (PTP_TSYNC). This engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between PTP nodes. The main features of the engine include the following:
• Support for both IEEE 1588 -2002 and IEEE 1588-2008 pro- tocol standards
• Hardware assisted time stampi ng capable of up to 12.5 ns resolution
• L o c k a d j u s t m e n t
• Automatic detection of IPv4 and IPv6 packets, as well as PTP messages
• Multiple input clock source s (SCLK0, RGMII, RMII, MII clock, and external clock)
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events

Rev. B | Page 18 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Controller Area Network (CAN) There are two controller area network (CAN) modules. A CAN controller implements the CAN 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN pro- tocol is well suited for control applications due to the capability to communicate reliably over a network. This is because the protocol incorporates CRC checking, message error tracking, and fault node confinement. The CAN controller offers the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 configu- rable for receive or transmit)
• Dedicated acceptance masks for each mailbox
• Additional data filtering on the first two bytes
• Support for both the standard (11-bit) and extended (29-bit) identifier (ID) message formats
• Support for remote frames
• Active or passive network support
• Interrupts, including transmit and receive complete, error, and global An additional crystal is not required to supply the CAN clock because it is derived from a system clock through a programma- ble divider. Timers The processors include several timers that are described in the following sections. General-Purpose (GP) Timers (TIMER) There is one general-purpose (GP) timer unit, providing eight GP programmable timers. Each timer has an external pin that can be configured either as PWM or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchro- nized to an external clock input on the TM_TMR[n] pins, an external TM_CLK input pin, or to the internal SCLK0. These timer units can be used in conjunction with the UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software autobaud detect function for the respective serial channels. The GP timers can generate interrupts to the processor core, providing periodic events for synchronization to either the sys- tem clock or to external signals. Timer events can also trigger other peripherals via the TRU (for instance, to signal a fault). Each timer can also be started and/or stopped by any TRU mas- ter without core intervention. Watchdog Timer (WDT) Three on-chip software watchdog timers (WDT) can be used by the ARM Cortex-A5 and/or SHARC+ cores. A software watch- dog can improve system availability by forcing the processors to a known state, via a general-purpose interrupt, or a fault, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts down to zero from the programmed value, protecting the system from remaining in an unknown state where software that normally resets the timer stops running due to an external noise condi- tion or software error. General-Purpose Counters (CNT) A 32-bit counter (CNT) is provided that can operate in general- purpose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or man- ual thumbwheels. Count direction is either controlled by a level- sensitive input pin or by two edge detectors. A third counter input can provide flexible zero marker support and can input the push button signal of thumbwheel devices. All three CNT0 pins have a programmable debouncing circuit. Internal signals forwarded to a GP timer enable the timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by inter- rupts when programmed count values are exceeded. Housekeeping Analog-to-Digital Converter (HADC) The housekeeping analog-to-digital converter (HADC) pro- vides a general-purpose, multichannel successive approximation ADC. It supports the following set of features:
• 12-bit ADC core with built in sample and hold.
• Eight single-ended input channels for the BGA package; four single-ended input channels for the LQFP package.
• Throughput rates up to 1 MSPS.
• Single external reference with analog inputs between 0 V and 3.3 V.
• Selectable ADC clock frequency including the ability to program a prescaler.
• Adaptable conversion type; al lows single or continuous conversion with option of autoscan.
• Autosequencing capability with up to eight autoconver- sions in a single session. Each conversion can be programmed to select one to eight input channels.
• Six data registers (individua lly addressable) to store con- version values USB 2.0 On the Go (OTG) Dual-Role Device Controller (BGA Only) The USB supports high speed/full speed/low speed (HS/FS/LS) USB2.0 on the go (OTG). The USB 2.0 OTG dual-role device controller provides a low cost connectivity solution in industrial applications, as well as consumer mobile devices such as cell phones, digital still cam- eras, and MP3 players. The USB 2.0 controller allows these devices to transfer data using a point to point USB connection without the need for a PC host. The module can operate in a tra- ditional USB peripheral only mode as well as the host mode presented in the OTG supplement to the USB 2.0 specification.

Rev. B | Page 19 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 The USB clock is provided through a dedicated external crystal or crystal oscillator. The USB OTG dual-role device controller includes a phase- locked loop (PLL) with programmable multipliers to generate the necessary internal clocking frequency for the USB. Media Local Bus (MediaLB) The automotive model has a Microchip MediaLB (MLB) slave interface that allows the processors to function as a media local bus device. It includes support for both 3-pin and 6-pin media local bus protocols. The MLB 3-pin configuration supports speeds up to 1024 × FS. The MLB 6-pin configuration supports speed of 2048 × FS. The MLB also supports up to 64 logical channels with up to 468 bytes of data per MLB frame. The MLB interface supports MOST25, MOST50, and MOST150 data rates and operates in slave mode only. 2-Wire Controller Interface (TWI) The processors include three 2-wire interface (TWI) modules that provide a simple exchange method of control data between multiple devices. The TWI module is compatible with the widely used I 2C bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitra- tion. The TWI interface utilizes two pins for transferring clock (TWI_SCL) and data (TWI_SDA) and supports the protocol at speeds up to 400 kb/sec. The TWI interface pins are compatible with 5 V logic levels. Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. General-Purpose I/O (GPIO) Each general-purpose port pin can be individually controlled by manipulating the port control, status, and interrupt registers:

• GPIO direction control register specifies the direction of each individual GPIO pin as input or output.
• GPIO control and status registers have a write one to mod- ify mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins.
• GPIO interrupt mask registers allow each individual GPIO pin to function as an interrupt to the processors. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts.
• GPIO interrupt sensitivity registers specify whether indi- vidual pins are level or edge sensitive and specify, if edge sensitive, whether the rising edge or both the rising and falling edges of the signal are significant. Pin Interrupts Every port pin on the processors can request interrupts in either an edge sensitive or a level sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO opera- tion. Five system level interrupt channels (PINT0–PINT4) are reserved for this purpose. Each of these interrupt channels can manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin by pin basis. Rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. Every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enable half-port assignment and interrupt management. This includes masking, identification, and clearing of requests. These registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. Most control registers feature multiple MMR address entries to write one to set or write one to clear them individually. Mobile Storage Interface (MSI) The mobile storage interface (MSI) controller acts as the host interface for multimedia cards (MMC), secure digital memory cards (SD), and secure digital input/output cards (SDIO). The MSI controller has the following features:
• Support for a single MMC, SD memory, and SDIO card
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit, and 8-bit MMC modes
• Support for eMMC 4.3 embedded NAND flash devices
• An 11-signal external inte rface with clock, command, optional interrupt, and up to eight data lines
• Integrated DMA controller
• Card interface clock generation in the clock distribution unit (CDU)
• SDIO interrupt and read wait features SYSTEM ACCELERATION The following sections describe the system acceleration blocks of the ADSP-SC57x/ADSP-2157x processors. Finite Impulse Response (FIR) Accelerator The finite impulse response (FIR) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the acceler- ator. The FIR accelerator runs at the peripheral clock frequency. The FIR accelerator can access all memory spaces and can run concurrently with the other accelerators on the processor. Infinite Impulse Response (IIR) Accelerator The infinite impulse response (IIR) accelerator consists of a 1440 word coefficient memory for storage of biquad coeffi- cients, a data memory for storing the intermediate data, and one MAC unit. A controller manages the accelerator. The IIR accel- erator runs at the peripheral clock frequency. The IIR accelerator can access all memory spaces and run concurrently with the other accelerators on the processor.

tions can be used for the USB crystal oscillator. tions are valid (refer to the Power-Up Reset Timing section). the processors receive data from external host devices. secure boot is available on all models. access to measure the die temperature variations in real-time.

• On-chip temperature sensing
• Programmable over temperature and under temperature limits
• Programmable conversion rate
• Programmable clock source selection to run the sensor off an independent local clock
• Averaging feature available Power Supplies The processors have separate power supply connections for
• Internal (VDD_INT)
• External (VDD_EXT)
• USB (VDD_USB)
• HADC/TMU (VDD_HADC)
• DMC (VDD_DMC) All power supplies must meet the specifications provided in Operating Conditions section. All external supply pins must be connected to the same power supply. Power Management As shown in Table 10, the processors support four different power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate spec- ifications (see the Specifications section for processor operating conditions). If the feature or the peripheral is not used, refer to Table 25.

Table 9. Boot Modes

000 No boot

001 SPI2 master

010 SPI2 slave

011 UART0 slave

100 Reserved

101 Reserved

110 Link0 slave

1 SYS_BMODE2 pin is applicable only for the BGA package. 2 Link0 slave boot is supported only on the BGA package.

reduction in dynamic power dissipation. does not affect target system loading or timing. debug. These are described in the following sections. interrupt and trigger) outputs. Studio integrated development environment (IDE). CrossCore Embedded Studio is based on the Eclipse framework. IDE of choice for processors, including multicore devices. more information, visit www.analog.com/cces. version of the available IDE(s), a USB cable, and a power supply. custom system utilizing supported Analog Devices processors. Studio IDE once the add in is installed. Table 10. Power Domains

Rev. B | Page 23 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Board Support Packages (BSPs) for Evaluation Hardware Software support for the EZ-KIT Lite evaluation boards and EZ- Extender daughter cards is provided by software add ins called board support packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZ- Extender product. Middleware Packages Analog Devices offers middleware add ins such as real-time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information, see the following web pages:

• www.analog.com/ucos2
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/ucusbh
• www.analog.com/lwip Algorithmic Modules To speed development, Analog Devices offers add ins that per- form popular audio and video processing algorithms. These are available for use with CrossCore Embedded Studio. For more information visit www.analog.com. Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices sup- plies an IEEE 1149.1 JTAG test access port (TAP). In circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the internal features of the processor via the TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emulators require the target board to include a header that sup- ports connection of the JTAG port of the DSP to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see “Analog Devices JTAG Emulation Technical Reference” (EE-68). ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP- SC57x/ADSP-2157x architecture and functionality. For detailed information on the core architecture and instruction set, refer to the SHARC+ Core Programming Reference. RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The application signal chains page in the Circuits from the Lab® site (www.analog.com\\circuits) provides the following:
• Graphical circuit block diag ram presentation of signal chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection guides and application information
• Reference designs applying be st practice design techniques

Table 11 provides a detailed description of each pin. Table 11. ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions ACM_A[n] Output ADC Control Signals. Function varies by mode. ACM_T[n] Input External Trigger n. Input for external trigger events. C1_FLG[n] Output SHARC Core 1 Flag Pin. C2_FLG[n] Output SHARC Core 2 Flag Pin. CAN_RX Input Receive. Typically an external CAN transceiver RX output. CAN_TX Output Transmit. Typically an external CAN transceiver TX input. Count down—this input causes the GP counter to decrement. Gate—stops the GP counter from incrementing or decrementing. signal or a direction signal. Count up—this input causes the GP counter to increment. Direction—selects whether the GP counter is incrementing or decrementing. pins. Programs make these connections using the signal routing unit (SRU). DMC_A[nn] Output Address n. Address bus. EMR2, and/or EMR3) load during the load mode register command. conjunction with other DMC command signals. Connect to the CAS input of dynamic memory. DMC_CK Output Clock. Outputs DCLK to external dynamic memory. DMC_CK Output Clock (Complement). Complement of DMC_CK. DMC_CKE Output Clock Enable. Active high clock enables. Connects to the CKE input of the dynamic memory. DMC_CS[n] Output Chip Select n. Commands are recognized by the memory only when this signal is asserted. DMC_DQ[nn] InOut Data n. Bidirectional data bus. on both edges of the data strobe by the dynamic memory. read data. Can be single-ended or differential depending on register settings. the memory is properly configured). ODT is enabled or disabled regardless of read or write commands. with other DMC command signals. Connect to the RAS input of dynamic memory. DMC_RESET Output Reset (DDR3 Only). DMC_RZQ InOut External Calibration Resistor Connection. on both edges of the data strobe by the dynamic memory. read data. Can be single-ended or differential depending on register settings.

DMC_VREF Input Voltage Reference. Connects to half of the VDD_DMC voltage. Applies to the DMC0_VREF pin. other DMC command signals. Connect to the WE input of dynamic memory. ETH_COL Input MII Collision Detect. Collision detect input signal valid only in MII. ETH_CRS Input MII Carrier Sense. Asserted by the PHY when either the transmit or receive medium is not idle. Deasserted when both are idle. This signal is not used in RMII/RGMII modes. ETH_MDC Output Management Channel Clock. Clocks the MDC input of the PHY for RMII/RGMII. ETH_MDIO InOut Management Channel Serial Data. Bidirectional data bus for PHY control for RMII/RGMII. in the auxiliary time stamp FIFO. ETH_PTPCLKIN[n] Input PTP Clock Input. Optional external PTP clock input. ETH_RXCLK_REFCLK InOut RXCLK (10/100/1000) or REFCLK (10/100). the data on ETH_RXD[n] is valid. ETH_RXD[n] Input Receive Data n. Receive data bus. ETH_RXERR Input Receive Error. ETH_TXCTL_TXEN InOut TXCTL (10/100/1000) or TXEN (10/100). ETH_TXD[n] Output Transmit Data n. Transmit data bus. HADC_VIN[n] Input Analog Input at Channel n. Analog voltage inputs for digital conversion. JTG_TCK Input JTAG Clock. JTAG test access port clock. JTG_TDI Input JTAG Serial Data In. JTAG test access port data input. JTG_TDO Output JTAG Serial Data Out. JTAG test access port data output. JTG_TMS Input JTAG Mode Select. JTAG test access port mode select. JTG_TRST Input JTAG Reset. JTAG test access port reset. LP_ACK InOut Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output. When the link port is configured as a transmitter, ACK is an input. as a transmitter, CLK is an output. LP_D[n] InOut Data n. Data bus. Input when receiving, output when transmitting. MLB_CLK InOut Single Ended Clock. MLB_CLKN InOut Differential Clock (–). MLB_CLKOUT InOut Single Ended Clock Out. MLB_CLKP InOut Differential Clock (+). MLB_DAT InOut Single Ended Data. Table 11. ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions (Continued)

MLB_DATN InOut Differential Data (–). MLB_DATP InOut Differential Data (+). MLB_SIG InOut Single Ended Signal. MLB_SIGN InOut Differential Signal (–). MLB_SIGP InOut Differential Signal (+). MSI_CD Input Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket. MSI_CLK Output Clock. The clock signal applied to the connected device from the MSI. MSI_CMD InOut Command. Sends commands to and receive responses from the connected device. MSI_D[n] InOut Data n. Bidirectional data bus. can be sampled even when the MSI clock to the card is switched off. PPI_CLK InOut Clock. Input in external clock mode, output in internal clock mode. PPI_D[nn] InOut Data n. Bidirectional data bus. SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. SHARC+ Processor Hardware Reference for more details. SPI_CLK InOut Clock. Input in slave mode, output in master mode. SPI_D2 InOut Data 2. Transfers serial data in quad mode. Open-drain when ODM mode is enabled. SPI_D3 InOut Data 3. Transfers serial data in quad mode. Open-drain when ODM mode is enabled. quad modes. Open-drain when ODM mode is enabled. quad modes. Open-drain when ODM mode is enabled. SPI_RDY InOut Ready. Optional flow signal. Output in slave mode, input in master mode. SPI_SEL[n] Output Slave Select Output n. Used in master mode to enable the desired slave. SPI_SS Input Slave Select Input. Slave mode—acts as the slave select input. can be either internally or externally generated. transmit serial data or as an input to receive serial data. transmit serial data or as an input to receive serial data. generated internally or externally. multichannel transmit mode. It is asserted during enabled slots. can be either internally or externally generated. transmit serial data or as an input to receive serial data.

transmit serial data or as an input to receive serial data. generated internally or externally. multichannel transmit mode. It is asserted during enabled slots. SYS_BMODE[n] Input Boot Mode Control n. Selects the boot mode of the processor. SYS_CLKIN0 Input Clock/Crystal Input. SYS_CLKIN1 Input Clock/Crystal Input. of the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for more details. SYS_HWRST Input Processor Hardware Reset Control. Resets the device when asserted. SYS_RESOUT Output Reset Output. Indicates the device is in the reset state. SYS_XTAL0 Output Crystal Output. SYS_XTAL1 Output Crystal Output. TM_ACI[n] Input Alternate Capture Input n. Provides an additional input for WIDCAP , WATCHDOG, and PININT modes. TM_ACLK[n] Input Alternate Clock n. Provides an additional time base for an individual timer. TM_CLK Input Clock. Provides an additional global time base for all GP timers. TM_TMR[n] InOut Timer n. The main input/output signal for each timer. TRACE_CLK Output Trace Clock. Clock output. TRACE_D[nn] Output Trace Data n. Unidirectional data bus. TWI_SCL InOut Serial Clock. Clock output when master, clock input when slave. TWI_SDA InOut Serial Data. Receives or transmits data. UART_CTS Input Clear to Send. Flow control signal. UART_RTS Output Request to Send. Flow control signal. the device being communicated with. of the device being communicated with. specifications for frequency/tolerance information. USB_DM InOut Data –. Bidirectional differential data line. USB_DP InOut Data +. Bidirectional differential data line. is sensed (signifying that the USB controller is the B device). configured as open-drain. Polarity is configurable as well. USB_VBUS InOut Bus Voltage. Connects to bus voltage in host and device modes. USB_XTAL Output Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN.

• The signal name column includ es the signal name for every pin and the GPIO multiplexed pin function, where applicable.
• The description column provides a descriptive name for each signal.
• The port column shows whether or not a signal is multiplexed with other signals on a GPIO port pin.
• The pin name column identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a GPIO pin).
• The DAI pins and their asso ciated signal routing units (SRUs) connect inputs and outputs of the DAI peripherals (SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio Interface (DAI) chapter of the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for complete information on the use of the DAI and SRUs.

Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions

Table 12. ADSP-SC57x/ADSP-2157x 400-Ball CSP_BGA Signal Descriptions (Continued)

1 Signal is routed to the DAI0_PINnn pin thro ugh the DAI0_PBnn pin buffers using the SRU.

Table 13. Signal Multiplexing for Port A Table 14. Signal Multiplexing for Port B

Table 15. Signal Multiplexing for Port C Table 16. Signal Multiplexing for Port D Table 17. Signal Multiplexing for Port E

Table 19 shows the internal timer signal routing. This table applies to both the 400-ball CSP_BGA and 176-lead LQFP packages. Table 18. Signal Multiplexing for Port F Table 19. Internal Timer Signal Routing 1 Not applicable for LQFP package. Table 17. Signal Multiplexing for Port E (Continued)

• The signal name column includ es the signal name for every pin and the GPIO multiplexed pin function, where applicable.
• The description column provides a descriptive name for each signal.
• The port column shows whether or not a signal is multi- plexed with other signals on a GPIO port pin.
• The pin name column identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a GPIO pin).
• The DAI pins and their asso ciated signal routing units (SRUs) connect inputs and outputs of the DAI peripherals (SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio Interface (DAI) chapter of the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference for complete information on the use of the DAIs and SRUs.

Table 20. ADSP-SC57x/ADSP-2157x 176-Lead LQFP Signal Descriptions

Table 20. ADSP-SC57x/ADSP-2157x 176-Lead LQFP Signal Descriptions (Continued)

multiplexed on the GPIO pins of the 176-lead LQFP package. Table 21. Signal Multiplexing for Port A Table 22. Signal Multiplexing for Port B

Table 23. Signal Multiplexing for Port C Table 24. Signal Multiplexing for Port D

• The signal name column includes the signal name for every pin and the GPIO multiplexed pin function, where applicable.
• The type column identifies the I/O type or supply type of the pin. The abbreviations used in this column are analog (a), supply (s), ground (g) and Input, Output, and InOut.
• The driver type column identi fies the driver type used by the corresponding pin. The driver types are defined in the Output Drive Currents section of this data sheet.
• The internal termination column specifies the termination present after the processor is powered up (both during reset and after reset).
• The reset drive column specifies the active drive on the sig- nal when the processor is in the reset state.
• The power domain column specifies the power supply domain in which the signal resides.
• The description and notes column identifies any special requirements or characteristics for a signal. These recom- mendations apply whether or not the hardware block associated with the signal is featured on the product. If no special requirements are listed, the signal can be left uncon- nected if it is not used. For multiplexed GPIO pins, this column identifies the functions available on the pin.

Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference

Table 25. ADSP-SC57x/ADSP-2157x Designer Quick Reference (Continued)

only. Pull down using a 34 Ohm resistor.

Notes: Add external pull-up if used. Notes: Add external pull-up if used. Notes: Add external pull-up if used. Notes: Add external pull-up if used. Notes: Add external pull-up if used. Notes: Add external pull-up if used.

design holds the internal path from the pins at the expected logi c levels. To pull up the external pads to the expected logic l evels, use external resistors.. 4 All HADC0_VINx pins can be connected directly to GND if HADC and TMU are not used. 5 Actively driven by processor otherwise. 6 Guidance also applies to models that do not feature the associated hardware block. See Table 2 or Table 3 for further information.

Rev. B | Page 56 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SPECIFICATIONS For information about product specifications, contact your Analog Devices representative. OPERATING CONDITIONS Parameter Conditions Min Nominal Max Unit VDD_INT Internal (Core) Supply Voltage CCLK ≤ 450 MHz 1.05 1.10 1.15 V CCLK ≤ 500 MHz 1.10 1.15 1.20 V VDD_EXT External (I/O) Supply Voltage 3.13 3.3 3.47 V VDD_HADC Analog Power Supply Voltage 3.13 3.3 3.47 V VDD_DMC1 DDR2/LPDDR Controller Supply Voltage 1.7 1.8 1.9 V DDR3 Controller Supply Voltage 1.425 1.5 1.575 V VDD_USB2 USB Supply Voltage 3.13 3.3 3.47 V VDDR_VREF DDR2 Reference Voltage Applies to the DMC0_VREF pin 0.49 × VDD_DMC 0.50 × VDD_DMC 0.51 × VDD_DMC V VHADC_REF3 HADC Reference Voltage 2.5 3.30 V DD_HADC V VHADC0_VINx HADC Input Voltage 0 V HADC_REF + 0.2 V VIH4 High Level Input Voltage V DD_EXT = 3.47 V 2.0 V VIHTWI5, 6 High Level Input Voltage V DD_EXT = 3.47 V 0.7 × V VBUSTWI VVBUSTWI V VIL4 Low Level Input Voltage V DD_EXT = 3.13 V 0.8 V VILTWI5, 6 Low Level Input Voltage V DD_EXT = 3.13 V 0.3 × V VBUSTWI V VIL_DDR27 Low Level Input Voltage V DD_DMC = 1.7 V V REF – 0.25 V VIL_DDR37 Low Level Input Voltage V DD_DMC = 1.425 V V REF – 0.175 V VIH_DDR27 High Level Input Voltage V DD_DMC = 1.9 V V REF + 0.25 V VIH_DDR37 High Level Input Voltage V DD_DMC = 1.575 V V REF + 0.175 V VIL_LPDDR8 Low Level Input Voltage V DD_DMC = 1.7 V 0.2 × V DD_DMC V VIH_LPDDR8 High Level Input Voltage V DD_DMC = 1.9 V 0.8 × V DD_DMC V TJ Junction Temperature 400-Ball CSP_BGA T AMBIENT = 0°C to +70°C CCLK ≤ 450 MHz 09 5 ° C TJ Junction Temperature 400-Ball CSP_BGA T AMBIENT = –40°C to +100°C CCLK ≤ 450 MHz –40 +125 °C TJ Junction Temperature 176-Lead LQFP-EP T AMBIENT = 0°C to +70°C CCLK ≤ 450 MHz 09 0 ° C TJ Junction Temperature 176-Lead LQFP-EP T AMBIENT = –40°C to +105°C CCLK ≤ 450 MHz –40 +125 °C TJ Junction Temperature 400-Ball CSP_BGA T AMBIENT = 0°C to +70°C CCLK ≤ 500 MHz 01 0 0 ° C TJ Junction Temperature 400-Ball CSP_BGA T AMBIENT = –40°C to +95°C CCLK ≤ 500 MHz –40 +125 °C TJ Junction Temperature 176-Lead LQFP-EP T AMBIENT = 0°C to +70°C CCLK ≤ 500 MHz 09 5 ° C TJ Junction Temperature 176-Lead LQFP-EP T AMBIENT = –40°C to +100°C CCLK ≤ 500 MHz –40 +125 °C

1 Applies to DDR2/DDR3/LPDDR signals. 2 If not used, VDD_USB must be connected to 3.3 V. 3 VHADC_VREF must always be less than VDD_HADC. 4 Parameter value applies to all input and bidirectional pins except the TWI, DMC, USB, and MLB pins. 5 Parameter applies to TWI signals. 6 TWI signals are pulled up to VBUSTWI. See Table 26. 7 This parameter applies to all DM C0 signals in DDR2/DDR3 mode. V REF is the voltage applied to the V REF_DMC pin, nominally VDD_DMC/2. 8 This parameter applies to DM C0 signals in LPDDR mode. 9 Automotive application use profile only. Not supported for nonautomotive use. Cont act Analog Devices for more information. Table 26. TWI_VSEL Selections and V DD_EXT/VBUSTWI 1 Designs must comply with the V DD_EXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.

speed grades except where expressly noted. Table 27. Clock Operating Conditions 1 When using MLB, there is a requirement that the f SYSCLK value must be a minimum of 100 MHz for both 3-pin and 6-pin modes and for all supported speeds.

250 MHz

2 The minimum frequency for SCLK0 applies only when using the USB. 3 fOCLK must not exceed fSCLK0 when selected as SYS_CLKOUT. 4 SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due to the dependency on these factors, the measured jitter can be higher or lower than this typical specification for each end application. 5 The value in the Typ field is the pe rcentage of the SYS_CLKOUT period. section for that peripheral. 7 The peripheral external clock frequency m ust also be less than or equal to the f SCLK (fSCLK0 or fSCLK1) that clocks the peripheral.

Table 28. PLL Operating Conditions Figure 7. Clock Relationships and Divider Values

Rev. B | Page 60 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

ELECTRICAL CHARACTERISTICS

Parameter Conditions Min Typ Max Unit VOH1 High Level Output Voltage At V DD_EXT = minimum, IOH = –1.0 mA2 2.4 V VOL1 Low Level Output Voltage At V DD_EXT = minimum, IOL = 1.0 mA2 0.4 V VOH_DDR23 High Level Output Voltage for DDR2 DS = 40 Ω At VDD_DDR = minimum, IOH = –5.8 mA 1.38 V VOL_DDR23 Low Level Output Voltage for DDR2 DS = 40 Ω At VDD_DDR = minimum, IOL = 5.8 mA 0.32 V VOH_DDR23 High Level Output Voltage for DDR2 DS = 60 Ω At VDD_DDR = minimum, IOH = –3.4 mA 1.38 V VOL_DDR23 Low Level Output Voltage for DDR2 DS = 60 Ω At VDD_DDR = minimum, IOL = 3.4 mA 0.32 V VOH_DDR34 High Level Output Voltage for DDR3 DS = 40 Ω At VDD_DDR = minimum, IOH = –5.8 mA 1.105 V VOL_DDR34 Low Level Output Voltage for DDR3 DS = 40 Ω At VDD_DDR = minimum, IOL = 5.8 mA 0.32 V VOH_DDR34 High Level Output Voltage for DDR3 DS = 60 Ω At VDD_DDR = minimum, IOH = –3.4 mA 1.105 V VOL_DDR34 Low Level Output Voltage for DDR3 DS = 60 Ω At VDD_DDR = minimum, IOL = 3.4 mA 0.32 V VOH_LPDDR5 High Level Output Voltage for LPDDR At VDD_DDR = minimum, IOH = –6.0 mA 1.38 V VOL_LPDDR5 Low Level Output Voltage for LPDDR At VDD_DDR = minimum, IOL = 6.0 mA 0.32 V IIH6, 7 High Level Input Current At V DD_EXT = maximum, VIN = VDD_EXT maximum 10 μA IIL6 Low Level Input Current At V DD_EXT = maximum, VIN = 0 V 10 μA IIL_PU7 Low Level Input Current Pull-Up At VDD_EXT = maximum, VIN = 0 V 200 μA IIH_PD8 High Level Input Current Pull-Down At VDD_EXT = maximum, VIN = VDD_EXT maximum 200 μA IOZH9 Three-State Leakage Current At VDD_EXT/VDD_DDR = maximum, VIN = VDD_EXT/VDD_DDR maximum 10 μA IOZL9 Three-State Leakage Current At VDD_EXT/VDD_DDR = maximum, VIN = 0 V 10 μA CIN10 Input Capacitance T CASE = 25°C 5 pF IDD_IDLE VDD_INT Current in Idle f CCLK =4 5 0 M H z ASFSHARC1 =0 . 3 2 ASFSHARC2 =0 . 3 2 ASFA5 =0 . 2 5 fSYSCLK =2 2 5M H z fSCLK0/1 = 112.5 MHz (Other clocks are disabled) No Peripheral or DMA activity TJ = 25°C VDD_INT = 1.1 V 410 mA

Rev. B | Page 61 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 IDD_IDLE VDD_INT Current in Idle f CCLK =5 0 0 M H z ASFSHARC1 =0 . 3 2 ASFSHARC2 =0 . 3 2 ASFA5 =0 . 2 5 fSYSCLK =2 5 0M H z fSCLK0/1 =1 2 5M H z (Other clocks are disabled) No Peripheral or DMA activity T J = 25°C VDD_INT = 1.15 V 477 mA IDD_TYP VDD_INT Current f CCLK =4 5 0 M H z ASFSHARC1 =1 . 0 ASFSHARC2 =1 . 0 ASFA5 =0 . 6 7 fSYSCLK =2 2 5M H z fSCLK0/1 = 112.5 MHz (Other clocks are disabled) DMA data rate = 600 MB/s T J = 25°C VDD_INT = 1.1 V 890 mA IDD_TYP VDD_INT Current f CCLK =5 0 0 M H z ASFSHARC1 =1 . 0 ASFSHARC2 =1 . 0 ASFA5 =0 . 6 7 fSYSCLK =2 5 0M H z fSCLK0/1 =1 2 5M H z (Other clocks are disabled) DMA data rate = 600 MB/s T J = 25°C VDD_INT = 1.15 V 1031 mA IDD_INT11 VDD_INT Current f CCLK 0 MHz fSCLK0/1  0 MHz See IDD_INT_TOT equation in the Total Internal Power Dissi- pation section. mA 1 Applies to all output and bidirectional pins except TWI, DMC, USB, and MLB. 2 See the Output Drive Currents section for typical drive current capabilities. 3 Applies to all DMC output and bidirectional signals in DDR2 mode. 4 Applies to all DMC output and bidirectional signals in DDR3 mode. 5 Applies to all DMC output and bidirectional signals in LPDDR mode. 6 Applies to input pins: SYS_BMODE0-2, SYS_CLKIN0, SYS_CLKIN1, SYS_HWRST , JTG_TDI, JTG_TMS, and USB0_CLKIN. 7 Applies to input pins with internal pull-ups: JTG_TD I, JTG_TMS, and JTG_TCK. 8 Applies to signals: JTAG_TRST, USB0_VBUS. 9 Applies to signals: PA0-15, PB0-15, PC0-15, PD0-15, PE0-15, PF0-11, DAI0_PINx, DMC0_DQx, DMC0_LDQS, DMC0_UDQS, DMC0_LDQS, DMC0_UDQS, SYS_FAULT, SYS_FAULT, JTG_TDO, USB0_ID, USB0_DM, USB0_DP, and USB0_VBC. 10Applies to all signal pins. 11See “Estimating Power for ADSP-SC57x/2157x SHARC+ Processors” (EE-397) for further information. Parameter Conditions Min Typ Max Unit

1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics for

(VDD_INT) and junction temperature (TJ) in Table 29. Table 29. Static Current—I DD_INT_STATIC (mA) Table 30. Activity Scaling Factors for the SHARC+® Core 1 Table 31. Activity Scaling Factors for the ARM ® Cortex®-A5

operating frequency, and a unique scaling factor. pation, and a single term is added when they are used. Table 32. D y namic Current for E ach SHARC+®Core

500 N/A 347 362 378

Table 33. Dynamic Current for the ARM ® Cortex®-A5 Core

500 N/A 88 92 96

Table 34. HADC Electrical Characteristics 1 See the Operating Conditions section for the HADC0_VINx specification.

3 Pin restrictions required: pins DAI18, DAI19, and DAI20 must be programmed

to inputs and a static (non-switc hing) signal applied to the pins.

10 Bits

Table 36. HADC DC Accuracy for LQFP_EP 1 1 See the Operating Conditions section for the HADC0_VINx specification. to inputs and a static (non-switc hing) signal applied to the pins. Table 37. HADC Timing Specifications

1 Refer to the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference

for additional information about T SAMPLE. Table 38. TMU Characteristics Table 39. TMU Gain and Offset –40°C to +40°C Contact Analog Devices, Inc. 40°C to 85°C Contact Analog Devices, Inc. 85°C to 133°C Contact Analog Devices, Inc.

Table 40. Absolute Maximum Ratings

1 Applies only when the related power supply (V DD_DMC, VDD_EXT, or VDD_USB) is

voltage being applied to that power domain ± 0.2 V. 2 Applies to 100% transient duty cycle. 3 Applies to TWI_SCL and TWI_SDA. 4 If the USB is not used, connect these pins according to Table 25. is below specifications, the range is V DD_HADC ± 0.2 V. ESD (electrostatic discharge) sensitive device. may occur on devices subjected to high energy ESD. avoid performance degradation or loss of functionality.

Specifications are subject to change without notice. (CGU) and reset control unit (RCU). In Figure 8, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, and VDD_HADC. Table 41. Power-Up Reset Timing Figure 8. Power-Up Reset Timing NOTE: VDD_SUPPLIES REFERS TO VDD_INT, VDD_EXT, VDD_DMC, AND VDD_HADC.

instruction rate of the processor. Table 42. C lo ck and Res et Timing 1 Applies to PLL bypass mode and PLL nonbypass mode. 2 The tCKIN period (see Figure 9) equals 1/fCKIN. 3 If the CGU_CTL.DF bit is set, the minimum fCKIN specification is 40 MHz. 4 Applies after power-up sequence is complete. See Table 41 and Figure 8 for power-up reset timing. Figure 9. Clock and Reset Timing

Table 43 and Figure 10 show DDR2 SDRAM clock and control cycle timing, related to the DMC. Table 43. DDR2 SDRAM Clock and Control Cycle Timing, VDD_DMC Nominal 1.8 V

400 MHz1

2 As per JESD79-2E definition. Figure 10. DDR2 SDRAM Clock and Control Cycle Timing NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A0 -A15 AND DMC0_BA0-BA2.

Table 44 and Figure 11 show DDR2 SDRAM read cycle timing, related to the DMC. Table 44. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V Figure 11. DDR2 SDRAM Controller Input AC Timing NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00 -13 AND DMC0_BA0-1.

Table 45 and Figure 12 show DDR2 SDRAM write cycle timing, related to the DMC. Table 45. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V 2 Write command to first DMC0_DQS delay = WL × t CK + tDQSS. Figure 12. DDR2 SDRAM Controller Output AC Timing NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00 -13 AND DMC0_BA0-1.

Table 46 and Figure 13 show mobile DDR SDRAM clock and control cycle timing, related to the DMC. Table 46. Mobile DDR SDRAM Clock and Control Cycle Timing, VDD_DMC Nominal 1.8 V

200 MHz1

Figure 13. Mobile DDR SDRAM Clock and Control Cycle Timing NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A0 -A15 AND DMC0_BA0-BA2.

Table 47 and Figure 14 show mobile DDR SDRAM read cycle timing, related to the DMC. Table 47. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V Figure 14. Mobile DDR SDRAM Controller Input AC Timing

Table 48 and Figure 15 show mobile DDR SDRAM write cycle timing, related to the DMC. Table 48. Mobile DDR SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V 2 Write command to first DMC0_DQS delay = WL × t CK + tDQSS. Figure 15. Mobile DDR SDRAM Controller Output AC Timing NOTE: CONTROL = DMC0_CSx, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00 -13 AND DMC0_BA0-1.

Table 49 and Figure 16 show mobile DDR3 SDRAM clock and control cycle timing, related to the DMC. Table 49. DDR3 SDRAM Clock and Control Cycle Timing, VDD_DMC Nominal 1.5 V

450 MHz1

2 As per JESD79-3F definition. Figure 16. DDR3 SDRAM Clock and Control Cycle Timing NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A0 -A15 AND DMC0_BA0-BA2.

Table 50 and Figure 17 show mobile DDR3 SDRAM read cycle timing, related to the DMC. Table 50. DDR3 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.5 V Figure 17. DDR3 SDRAM Controller Input AC Timing NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00 -13 AND DMC0_BA0-1.

Table 51 and Figure 18 show mobile DDR3 SDRAM output ac timing, related to the DMC. Table 51. DDR3 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.5 V 2 Write command to first DMC0_DQS delay = WL × t CK + tDQSS. Figure 18. DDR3 SDRAM Controller Output AC Timing NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00 -13 AND DMC0_BA0-1.

Table 52. Enhanced Parallel Peripheral Interface (EPPI)—Internal Clock 1 See Table 27 for details on the minimum period that can be programmed for t PCLKPROG.

that can be introduced in LPx_CLK relative to LPx_Dx (hold skew = tLCLKTWL minimum – tHLDCH – tHLDCL). Table 54. LPs—Receive 1 1 Specifications apply to LP0 and LP1. LPx_CLK ideal maximum frequency, see the f LCLKTEXT specification in Table 27. 3 LPx_ACK goes low with tDLALC relative to rise of LPx_CLK after first byte, but does not go low if the link buffe r of the receiver is not about to fill.

Figure 28. LPs—Receive

Table 55. LPs—Transmit1 1 Specifications apply to LP0 and LP1. 2 See Table 27 for details on the minimum period that can be programmed for t LCLKTPROG. Figure 29. LPs—Transmit and tLCLKTWH Max for tHLACH.

ing edge or the falling edge of SPTx_CLK (external or internal) can be used as the active sampling edge. Table 56. SPORTs—E xternal C lo ck1 1 Specifications apply to all four SPORTs. 2 Referenced to sample edge. SPTx_CLK ideal maximum frequency see the f SPTCLKEXT specification in Table 27.

Table 57. SPORTs—Internal C lo ck1 1 Specifications apply to all four SPORTs. 2 Referenced to the sample edge. 4 See Table 27 for details on the minimum period that can be programmed for t SPTCLKPROG.

Figure 30. SPORTs

Table 58. SPORTs—Enable and Three-State1 1 Specifications apply to all four SPORTs. Figure 31. SPORTs—Enable and Three-State

registers) the SPTx_TDV is asserted for communication with external devices. Table 59. SPORTs—Transmit Data Valid (TDV)1 1 Specifications apply to all four SPORTs. Figure 32. SPORTs—Transmit Data Va lid Internal and External Clock

Table 60. SPORTs—External Late Frame Sync1 1 Specifications apply to all four SPORTs. 2 The tDDTLFSE and tDDTENFS parameters apply to left justified as well as standard serial mode and MCE = 1, MFD = 0. Figure 33. External Late Frame Sync

valid at the DAI0_PINx pins. Table 61. ASRC, S erial Input Por t the PCG can be either CLKIN or any of the DAI pins. Figure 34. ASRC Serial Input Port Timing

the falling edge is the drive edge. Figure 35. ASRC Serial Output Port Timing Table 62. ASRC, Serial Output Port the PCG can be either CLKIN, SCLK0, or any of the DAI pins.

Table 63, Table 64, and Figure 36 describe the SPI port master operations. BAUD is a field in the SPIx_CLK register that can be set from 0 to 65535.

• In dual-mode data transmit, the SPIx _MISO signal is also an output.
• In quad-mode data transmit, the SPIx_MISO, SP Ix_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MOSI signal is also an input.
• In quad-mode data receive, the SPIx_MOSI, SP Ix_D2, and SPIx_D3 signals are also inputs.
• Quad-mode is supported by SPI2 only.
• CPHA is a configuration bit in the SPI_CTL register.

Table 63. SPI0, SPI1 Port—Master Timing 1 All specifications apply to SPI0 and SPI1 only. 2 Specification assumes the LEADX and LAGX bits in the SPI_DLY register are 1. 3 See Table 27 for details on the minimum period that can be programmed for t SPICLKPROG. 4 Applies to sequential mode with STOP ≥ 1.

Table 64. SPI2 Port—Master Timing1 1 All specifications apply to SPI2 only. 2 Specification assumes the LEADX and LAGX bits in the SPI_DLY register are 1. 3 See Table 27 for details on the minimum period that may be programmed for t SPICLKPROG. 4 Applies to sequential mode with STOP ≥ 1. Figure 36. SPI Port—Master Timing

• In dual-mode data transmit, the SPIx _MOSI signal is also an output.
• In quad-mode data transmit, the SPIx_MOSI, SP Ix_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MISO signal is also an input.
• In quad-mode data receive, the SPIx_MISO, SP Ix_D2, and SPIx_D3 signals are also inputs.
• In SPI slave mode, the SPI clock is supplied externally and is called f SPICLKEXT:
• Quad mode is supported by SPI2 only.
• CPHA is a configuration bit in the SPI_CTL register.

Table 65. SPI0, SPI1 Port—Slave Timing1 1 All specifications apply to SPI0 and SPI1. SPIx_CLK ideal maximum frequency, see the f SPICLKTEXT specification in Table 27.

Table 66. SPI2 Port—Slave Timing1 1 All specifications apply to SPI2 only. SPIx_CLK ideal maximum frequency, see the f SPICLKTEXT specification in Table 27. Figure 37. SPI Port—Slave Timing

SPIx_RDY provides flow control. CPOL, CPHA, and FCCH are configuration bits in the SPIx_CTL register. Table 67. SPI Port—SPIx_RDY Slave Timing1 1 All specifications apply to all three SPIs. Figure 38. SPIx_RDY Deassertion from Va lid Input SPIx_CLK Edge in Slave Mode

STOP are configuration bits in the SPIx_DLY register. Table 70. SPI Port—SPIx_RDY Master Timing1 1 All specifications apply to all three SPIs. 2 BAUD value is set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1. 3 Specification assumes the LEADX, LAGX, and STOP bits in the SPI_DLY register are zero. Figure 41. SPIx_RDY Setup Before SPIx_CLK

Figure 42. SPIx_CLK Switching Diagram after SPIx_RDY Assertion

external DAI pins (DAI0_PINx). Table 71. PCG (Direct Pin Routing) 1 D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference . Figure 43. PCG (Direct Pin Routing)

Table 72 and Figure 44 describe I/O timing, related to the general-purpose ports (PORT). Table 72. General-Purpose Port Timing Figure 44. General-Purpose Port Timing Table 73. Timer Cycle Timing—Internal Mode 1 The minimum pulse width applies for timer signals in width capture and external clock modes. 2 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 2 to 2 32 – 1). Table 74. Timer Cycle Timing—External Mode 1 The minimum pulse width applies for timer signals in width capture and external clock modes. TMR_CLK maximum frequency, see the f TMRCLKEXT specification in Table 27. 3 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 2 32 – 1).

Table 77 and Figure 48 describe ACM operations. ACM_TC1 register that ranges from 0 to 15. Table 77. ACM Timing 1 See Table 27 for details on the minimum period that can be programmed for t ACLKPROG. Figure 48. ACM Timing

The CAN interface timing is described in the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference. pins (including output characteristics for driver types E, F, and G listed in the ADSP-SC57x/ADSP-2157x Designer Quick Reference). Table 78. USB Clock Timing 1 1 This specification is supported by USB0.

Table 83. 10/100/1000 EMAC Timing—RMII and RGMII Station Management programmable as a multiple of the system clock SCLK0. ETH0_MDIO is a bidirectional data line. Figure 53. 10/100 /1000 Ethernet MAC Controlle r Timing—RMII and RGMII Station Management

Table 84 and Figure 54 describe the RGMII EMAC timing. Table 84. 10/100/1000 EMAC Timing—RGMII Receive and Transmit Signals Figure 54. EMAC Timing—RGMII

The timing requirements for the S/PDIF transmitter are given in Table 88. Input signals are routed to the DAI0_PINx pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI0_PINx pins. Table 88. S/PDIF Transmitter Input Data Timing PCG can be either CLKIN or any of the DAI pins. Figure 58. S/PDIF Transmitter Input Timing Table 89. Oversampling Clock (TxCLK) Switching Characteristics

The following section describes timing as it relates to the S/PDIF receiver. In the internal digital PLL mode, the internal digital PLL generates the 512 × FS clock. Table 90. S/PDIF Receiver Internal Digital PLL Mode Timing Figure 59. S/PDIF Receiver Internal Digital PLL Mode Timing

otherwise specified. Refer to the Media Local Bus Specification version 4.2 for more details. Table 91. 3-Pin MLB Interface Specifications

512 FS/256 FS

1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, mea sured in nanoseconds peak-to-peak.

512 FS/256

meeting the maximum capacitive load listed.

Figure 60. MLB Timing (3-Pin Interface) Table 92. 6-Pin MLB Interface Specifications 1 fMCKE (maximum) and fMCKR (maximum) include maximum cycle to cycle system jitter (t JITTER) of 600 ps for a bit error rate of 10E-9. 2 Receivers must latch MLBSP/ N (MLBDP/N) data within tHD (minimum) of the rising edge of MLBCP/N.

Figure 63. MLB 6-Pin Delay, Setup, and Hold Times

Figure 64. MLB 6-Pin Disable and Enable Turnaround Times

Table 93 and Figure 65 show I/O timing related to the MSI. Table 93. MSI Controller Timing

45 MHz

Figure 65. MSI Controller Timing 1 INPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS. 2 OUTPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS.

Table 94 and Figure 66 provide I/O timing related to the PTM. Table 94. Trace Timing Figure 66. Trace Timing

Table 95 and Figure 67 provide I/O timing related to the debug interface (JTAG Emulator Port). Table 95. JTAG Emu lation Port Timing PE_15-0, PF_11-0, SYS_BMODE2-0, SYS_FAULT, SYS_FAULT , SYS_RESOUT, TWI2-0_SCL, TWI2-0_SDA2. PF_11-0, SYS_BMODE2-0, SYS_CLKOUT, SYS_FAULT, SYS_FAULT , SYS_RESOUT. Figure 67. JTAG Port Timing

TJ = junction temperature (°C). JT = from Table 96 and Table 97. tion section for the method to calculate PD). where TA = ambient temperature (°C). design considerations when an external heat sink is required. measurement complies with MIL-STD-883 (Method 1012.1). Figure 88. Driver Type B and Driver Type C Typical Rise and Fall Times Table 96. Thermal Characteristics for 400 CSP_BGA Table 97. Thermal Characteristics for 176 LQFP_EP

Rev. B | Page 127 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57x/ADSP-2157x 400-BALL BGA BALL ASSIGNMENTS The ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Numerical by Ball Number) table lists the 400-ball BGA pack- age by ball number. The ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) table lists the 400-ball BGA package by pin name. ADSP-SC57x/ADSP-2157x 400-BALL BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER) Ball No. Pin Name A01 GND A02 PA_10 A03 PA_09 A04 PA_11 A05 PE_07 A06 MLB0_CLKN A07 MLB0_CLKP A08 MLB0_SIGN A09 GND A10 SYS_XTAL0 A11 SYS_CLKIN0 A12 GND A13 SYS_XTAL1 A14 SYS_CLKIN1 A15 GND A16 USB0_DP A17 USB0_DM A18 PF_03 A19 PF_05 A20 GND B01 PC_12 B02 GND B03 PA_13 B04 PA_15 B05 PB_01 B06 PB_04 B07 MLB0_DATN B08 MLB0_DATP B09 MLB0_SIGP B10 JTG_TRST B11 USB0_VBUS B12 USB0_XTAL B13 PB_10 B14 JTG_TDO B15 JTG_TMS B16 PF_00 B17 PF_01 B18 PF_06 B19 GND B20 PF_07 C01 PC_11 C02 PC_13 C03 GND C04 PA_12 C05 PA_14 C06 PB_03 C07 PB_02 C08 PE_10 C09 PB_06 C10 PB_05 C11 SYS_HWRST C12 USB0_ID C13 USB0_CLKIN C14 PB_12 C15 PB_13 C16 JTG_TDI C17 PE_14 C18 GND C19 PF_08 C20 PF_11 D01 PC_06 D02 PC_08 D03 PE_04 D04 GND D05 PE_08 D06 PE_11 D07 PE_09 D08 PB_08 D09 PB_07 D10 PB_09 D11 SYS_CLKOUT D12 PB_11 D13 USB0_VBC D14 PB_14 D15 PE_13 D16 PE_12 D17 GND D18 PF_10 D19 DAI0_PIN01 D20 DAI0_PIN04 E01 PC_05 E02 PE_05 Ball No. Pin Name E03 PE_03 E04 PE_02 E05 GND E06 PB_00 E07 VDD_EXT E08 VDD_EXT E09 VDD_EXT E10 VDD_EXT E11 VDD_EXT E12 VDD_EXT E13 VDD_USB E14 JTG_TCK E15 PE_15 E16 GND E17 VDD_EXT E18 PF_04 E19 DAI0_PIN07 E20 DAI0_PIN03 F01 PC_02 F02 PC_03 F03 PC_04 F04 PE_06 F05 VDD_INT F06 GND F07 VDD_INT F08 VDD_INT F09 VDD_INT F10 VDD_INT F11 VDD_INT F12 VDD_INT F13 VDD_INT F14 VDD_INT F15 GND F16 VDD_INT F17 PF_02 F18 PF_09 F19 DAI0_PIN02 F20 DAI0_PIN06 G01 PC_00 G02 PC_14 G03 PC_01 Ball No. Pin Name G04 VDD_EXT G05 VDD_INT G06 GND G07 GND G08 GND G09 GND G10 GND G11 GND G12 GND G13 GND G14 GND G15 GND G16 VDD_INT G17 PB_15 G18 DAI0_PIN08 G19 DAI0_PIN10 G20 DAI0_PIN09 H01 PE_01 H02 PC_09 H03 PC_15 H04 VDD_EXT H05 VDD_INT H06 GND H07 GND H08 GND H09 GND H10 GND H11 GND H12 GND H13 GND H14 GND H15 GND H16 VDD_INT H17 VDD_EXT H18 DAI0_PIN05 H19 DAI0_PIN14 H20 DAI0_PIN11 J01 PE_00 J02 PC_07 J03 PC_10 J04 VDD_EXT Ball No. Pin Name

Rev. B | Page 128 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 J05 VDD_INT J06 GND J07 GND J08 GND J09 GND J10 GND J11 GND J12 GND J13 GND J14 GND J15 GND J16 VDD_INT J17 VDD_EXT J18 DAI0_PIN12 J19 DAI0_PIN13 J20 DAI0_PIN16 K01 PD_14 K02 PD_13 K03 PD_15 K04 VDD_EXT K05 VDD_INT K06 GND K07 GND K08 GND K09 GND K10 GND K11 GND K12 GND K13 GND K14 GND K15 GND K16 VDD_INT K17 VDD_EXT K18 DAI0_PIN15 K19 DAI0_PIN19 K20 DAI0_PIN18 L01 PD_11 L02 PD_10 L03 PD_12 L04 VDD_EXT L05 VDD_INT L06 GND L07 GND L08 GND L09 GND L10 GND L11 GND L12 GND Ball No. Pin Name L13 GND L14 GND L15 GND L16 VDD_INT L17 VDD_EXT L18 DAI0_PIN17 L19 GND L20 DAI0_PIN20 M01 DMC0_A14 M02 DMC0_A15 M03 PD_09 M04 VDD_EXT M05 VDD_INT M06 GND M07 GND M08 GND M09 GND M10 GND M11 GND M12 GND M13 GND M14 GND M15 GND M16 VDD_INT M17 VDD_EXT M18 HADC0_VIN7 M19 HADC0_VIN5 M20 HADC0_VIN6 N01 DMC0_A11 N02 DMC0_A13 N03 DMC0_A12 N04 VDD_DMC N05 VDD_INT N06 GND N07 GND N08 GND N09 GND N10 GND N11 GND N12 GND N13 GND N14 GND N15 GND N16 VDD_INT N17 VDD_EXT N18 HADC0_VIN4 N19 HADC0_VIN3 N20 GND Ball No. Pin Name P01 DMC0_VREF P02 DMC0_RZQ P03 DMC0_A09 P04 DMC0_A10 P05 VDD_INT P06 VDD_INT P07 GND P08 VDD_INT P09 VDD_INT P10 VDD_INT P11 VDD_INT P12 VDD_INT P13 VDD_INT P14 GND P15 VDD_INT P16 VDD_INT P17 HADC0_VIN1 P18 HADC0_VIN0 P19 HADC0_VREFP P20 HADC0_VREFN R01 PD_06 R02 PD_07 R03 PD_08 R04 VDD_INT R05 VDD_INT R06 GND R07 VDD_INT R08 VDD_INT R09 VDD_INT R10 VDD_INT R11 VDD_INT R12 VDD_INT R13 VDD_INT R14 VDD_INT R15 GND R16 VDD_INT R17 VDD_INT R18 DMC0_BA0 R19 HADC0_VIN2 R20 VDD_HADC T01 PD_05 T02 TWI0_SDA T03 TWI0_SCL T04 VDD_EXT T05 GND T06 VDD_DMC T07 VDD_DMC T08 VDD_DMC Ball No. Pin Name T09 VDD_DMC T10 VDD_DMC T11 VDD_DMC T12 VDD_DMC T13 VDD_DMC T14 VDD_DMC T15 VDD_DMC T16 GND T17 VDD_DMC T18 DMC0_A02 T19 DMC0_A01 T20 DMC0_RESET U01 DMC0_DQ15 U02 DMC0_DQ14 U03 TWI1_SDA U04 GND U05 TWI1_SCL U06 VDD_EXT U07 VDD_DMC U08 VDD_DMC U09 VDD_DMC U10 VDD_DMC U11 VDD_DMC U12 VDD_DMC U13 VDD_DMC U14 VDD_DMC U15 DMC0_BA2 U16 DMC0_WE U17 GND U18 DMC0_A06 U19 DMC0_A03 U20 DMC0_A00 V01 TWI2_SDA V02 DMC0_DQ13 V03 GND V04 PD_03 V05 PD_04 V06 PD_01 V07 PA_08 V08 PA_05 V09 PA_03 V10 PA_02 V11 PA_01 V12 PA_00 V13 SYS_RESOUT V14 SYS_FAULT V15 DMC0_CAS V16 DMC0_RAS Ball No. Pin Name

Rev. B | Page 129 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 V17 DMC0_BA1 V18 GND V19 DMC0_A04 V20 DMC0_A05 W01 TWI2_SCL W02 GND W03 DMC0_DQ12 W04 DMC0_DQ11 W05 DMC0_DQ09 W06 PD_02 W07 PD_00 W08 PA_07 W09 PA_06 W10 PA_04 W11 DMC0_DQ05 W12 DMC0_DQ04 W13 DMC0_DQ03 W14 DMC0_DQ02 W15 SYS_FAULT W16 DMC0_ODT W17 DMC0_A08 W18 SYS_BMODE1 W19 GND W20 DMC0_A07 Y01 GND Y02 DMC0_UDQS Y03 DMC0_UDQS Y04 DMC0_DQ10 Y05 DMC0_DQ08 Y06 DMC0_UDM Y07 DMC0_LDM Y08 DMC0_CK Y09 DMC0_CK Y10 DMC0_DQ07 Y11 DMC0_DQ06 Y12 DMC0_LDQS Y13 DMC0_LDQS Y14 DMC0_DQ01 Y15 DMC0_DQ00 Y16 DMC0_CKE Y17 DMC0_CS0 Y18 SYS_BMODE0 Y19 SYS_BMODE2 Y20 GND Ball No. Pin Name

Rev. B | Page 130 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57x/ADSP-2157x 400-BALL BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME) Pin Name Ball No. DAI0_PIN01 D19 DAI0_PIN02 F19 DAI0_PIN03 E20 DAI0_PIN04 D20 DAI0_PIN05 H18 DAI0_PIN06 F20 DAI0_PIN07 E19 DAI0_PIN08 G18 DAI0_PIN09 G20 DAI0_PIN10 G19 DAI0_PIN11 H20 DAI0_PIN12 J18 DAI0_PIN13 J19 DAI0_PIN14 H19 DAI0_PIN15 K18 DAI0_PIN16 J20 DAI0_PIN17 L18 DAI0_PIN18 K20 DAI0_PIN19 K19 DAI0_PIN20 L20 DMC0_A00 U20 DMC0_A01 T19 DMC0_A02 T18 DMC0_A03 U19 DMC0_A04 V19 DMC0_A05 V20 DMC0_A06 U18 DMC0_A07 W20 DMC0_A08 W17 DMC0_A09 P03 DMC0_A10 P04 DMC0_A11 N01 DMC0_A12 N03 DMC0_A13 N02 DMC0_A14 M01 DMC0_A15 M02 DMC0_BA0 R18 DMC0_BA1 V17 DMC0_BA2 U15 DMC0_CAS V15 DMC0_CK Y08 DMC0_CKE Y16 DMC0_CK Y09 DMC0_CS0 Y17 DMC0_DQ00 Y15 DMC0_DQ01 Y14 DMC0_DQ02 W14 DMC0_DQ03 W13 DMC0_DQ04 W12 DMC0_DQ05 W11 DMC0_DQ06 Y11 DMC0_DQ07 Y10 DMC0_DQ08 Y05 DMC0_DQ09 W05 DMC0_DQ10 Y04 DMC0_DQ11 W04 DMC0_DQ12 W03 DMC0_DQ13 V02 DMC0_DQ14 U02 DMC0_DQ15 U01 DMC0_LDM Y07 DMC0_LDQS Y12 DMC0_LDQS Y13 DMC0_ODT W16 DMC0_RAS V16 DMC0_RESET T20 DMC0_RZQ P02 DMC0_UDM Y06 DMC0_UDQS Y03 DMC0_UDQS Y02 DMC0_VREF P01 DMC0_WE U16 GND A01 GND A09 GND A12 GND A15 GND A20 GND B02 GND B19 GND C03 GND C18 GND D04 GND D17 GND E05 GND E16 GND F06 GND F15 GND G06 GND G07 GND G08 GND G09 GND G10 Pin Name Ball No. GND G11 GND G12 GND G13 GND G14 GND G15 GND H06 GND H07 GND H08 GND H09 GND H10 GND H11 GND H12 GND H13 GND H14 GND H15 GND J06 GND J07 GND J08 GND J09 GND J10 GND J11 GND J12 GND J13 GND J14 GND J15 GND K06 GND K07 GND K08 GND K09 GND K10 GND K11 GND K12 GND K13 GND K14 GND K15 GND L06 GND L07 GND L08 GND L09 GND L10 GND L11 GND L12 GND L13 GND L14 GND L15 GND L19 Pin Name Ball No. GND M06 GND M07 GND M08 GND M09 GND M10 GND M11 GND M12 GND M13 GND M14 GND M15 GND N06 GND N07 GND N08 GND N09 GND N10 GND N11 GND N12 GND N13 GND N14 GND N15 GND N20 GND P07 GND P14 GND R06 GND R15 GND T05 GND T16 GND U04 GND U17 GND V03 GND V18 GND W02 GND W19 GND Y01 GND Y20 HADC0_VIN0 P18 HADC0_VIN1 P17 HADC0_VIN2 R19 HADC0_VIN3 N19 HADC0_VIN4 N18 HADC0_VIN5 M19 HADC0_VIN6 M20 HADC0_VIN7 M18 HADC0_VREFN P20 HADC0_VREFP P19 JTG_TCK E14 Pin Name Ball No.

Rev. B | Page 131 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 JTG_TDI C16 JTG_TDO B14 JTG_TMS B15 JTG_TRST B10 MLB0_CLKN A06 MLB0_CLKP A07 MLB0_DATN B07 MLB0_DATP B08 MLB0_SIGN A08 MLB0_SIGP B09 PA_00 V12 PA_01 V11 PA_02 V10 PA_03 V09 PA_04 W10 PA_05 V08 PA_06 W09 PA_07 W08 PA_08 V07 PA_09 A03 PA_10 A02 PA_11 A04 PA_12 C04 PA_13 B03 PA_14 C05 PA_15 B04 PB_00 E06 PB_01 B05 PB_02 C07 PB_03 C06 PB_04 B06 PB_05 C10 PB_06 C09 PB_07 D09 PB_08 D08 PB_09 D10 PB_10 B13 PB_11 D12 PB_12 C14 PB_13 C15 PB_14 D14 PB_15 G17 PC_00 G01 PC_01 G03 PC_02 F01 PC_03 F02 PC_04 F03 Pin Name Ball No. PC_05 E01 PC_06 D01 PC_07 J02 PC_08 D02 PC_09 H02 PC_10 J03 PC_11 C01 PC_12 B01 PC_13 C02 PC_14 G02 PC_15 H03 PD_00 W07 PD_01 V06 PD_02 W06 PD_03 V04 PD_04 V05 PD_05 T01 PD_06 R01 PD_07 R02 PD_08 R03 PD_09 M03 PD_10 L02 PD_11 L01 PD_12 L03 PD_13 K02 PD_14 K01 PD_15 K03 PE_00 J01 PE_01 H01 PE_02 E04 PE_03 E03 PE_04 D03 PE_05 E02 PE_06 F04 PE_07 A05 PE_08 D05 PE_09 D07 PE_10 C08 PE_11 D06 PE_12 D16 PE_13 D15 PE_14 C17 PE_15 E15 PF_00 B16 PF_01 B17 PF_02 F17 PF_03 A18 Pin Name Ball No. PF_04 E18 PF_05 A19 PF_06 B18 PF_07 B20 PF_08 C19 PF_09 F18 PF_10 D18 PF_11 C20 SYS_BMODE0 Y18 SYS_BMODE1 W18 SYS_BMODE2 Y19 SYS_CLKIN0 A11 SYS_CLKIN1 A14 SYS_CLKOUT D11 SYS_FAULT V14 SYS_FAULT W15 SYS_HWRST C11 SYS_RESOUT V13 SYS_XTAL0 A10 SYS_XTAL1 A13 TWI0_SCL T03 TWI0_SDA T02 TWI1_SCL U05 TWI1_SDA U03 TWI2_SCL W01 TWI2_SDA V01 USB0_DM A17 USB0_DP A16 USB0_ID C12 USB0_VBC D13 USB0_VBUS B11 USB0_CLKIN C13 USB0_XTAL B12 VDD_DMC N04 VDD_DMC T06 VDD_DMC T07 VDD_DMC T08 VDD_DMC T09 VDD_DMC T10 VDD_DMC T11 VDD_DMC T12 VDD_DMC T13 VDD_DMC T14 VDD_DMC T15 VDD_DMC T17 VDD_DMC U07 VDD_DMC U08 Pin Name Ball No. VDD_DMC U09 VDD_DMC U10 VDD_DMC U11 VDD_DMC U12 VDD_DMC U13 VDD_DMC U14 VDD_EXT E07 VDD_EXT E08 VDD_EXT E09 VDD_EXT E10 VDD_EXT E11 VDD_EXT E12 VDD_EXT E17 VDD_EXT G04 VDD_EXT H04 VDD_EXT H17 VDD_EXT J04 VDD_EXT J17 VDD_EXT K04 VDD_EXT K17 VDD_EXT L04 VDD_EXT L17 VDD_EXT M04 VDD_EXT M17 VDD_EXT N17 VDD_EXT T04 VDD_EXT U06 VDD_HADC R20 VDD_INT F05 VDD_INT F07 VDD_INT F08 VDD_INT F09 VDD_INT F10 VDD_INT F11 VDD_INT F12 VDD_INT F13 VDD_INT F14 VDD_INT F16 VDD_INT G05 VDD_INT G16 VDD_INT H05 VDD_INT H16 VDD_INT J05 VDD_INT J16 VDD_INT K05 VDD_INT K16 VDD_INT L05 Pin Name Ball No.

Rev. B | Page 132 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 VDD_INT L16 VDD_INT M05 VDD_INT M16 VDD_INT N05 VDD_INT N16 VDD_INT P05 VDD_INT P06 VDD_INT P08 VDD_INT P09 VDD_INT P10 VDD_INT P11 VDD_INT P12 VDD_INT P13 VDD_INT P15 VDD_INT P16 VDD_INT R04 VDD_INT R05 VDD_INT R07 VDD_INT R08 VDD_INT R09 VDD_INT R10 VDD_INT R11 VDD_INT R12 VDD_INT R13 VDD_INT R14 VDD_INT R16 VDD_INT R17 VDD_USB E13 Pin Name Ball No.

Rev. B | Page 134 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57x/ADSP-2157x 176-LEAD LQFP LEAD ASSIGNMENTS The ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assign- ments (Numerical by Lead Number) table lists the 176-lead LQFP package by lead number. The ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assign- ments (Alphabetical by Pin Name) table lists the 176-lead LQFP package by pin name. ADSP-SC57x/ADSP-2157x 176-LEAD LQFP LEAD ASSIGNMENTS (NUMERICAL BY LEAD NUMBER) Lead No. Pin Name

01 VDD_INT

02 GND

03 VDD_INT

04 PA_15

05 PA_14

06 PA_13

07 VDD_INT

08 PA_12

09 VDD_EXT

10 PA_10

11 PA_11

12 PC_15

13 PA_09

14 VDD_INT

15 GND

16 VDD_INT

17 PC_14

18 PC_13

19 PC_12

20 PC_11

21 VDD_EXT

22 PC_10

23 PC_09

24 PC_08

25 PC_07

26 PC_06

27 PC_05

28 PC_04

29 PC_03

30 VDD_INT

31 VDD_EXT

32 PC_02

33 PC_01

34 PC_00

35 PD_15

36 PD_14

37 PD_13

38 VDD_EXT

39 VDD_INT

40 PD_12

41 PD_11

42 PD_10

43 PD_09

44 GND

45 GND

46 VDD_EXT

47 VDD_INT

48 PD_08

49 PD_07

50 PD_06

51 PD_05

52 VDD_INT

53 TWI0_SDA

54 TWI0_SCL

55 TWI1_SDA

56 TWI1_SCL

57 TWI2_SDA

58 TWI2_SCL

59 VDD_INT

60 VDD_EXT

61 PD_04

62 PD_03

63 PD_02

64 PD_01

65 GND

66 VDD_INT

67 PD_00

68 PA_08

69 PA_07

70 PA_06

71 VDD_EXT

72 VDD_INT

73 VDD_INT

74 PA_05

75 PA_04

76 PA_03

77 PA_02

78 VDD_EXT

79 PA_01

80 PA_00

Lead No. Pin Name

81 SYS_RESOUT

82 VDD_INT

83 GND

84 VDD_EXT

85 SYS_FAULT

86 SYS_BMODE0

87 SYS_BMODE1

88 VDD_INT

89 GND

90 VDD_HADC

91 HADC0_VIN0

92 HADC0_VIN1

93 HADC0_VREFN

94 HADC0_VIN2

95 HADC0_VIN3

96 HADC0_VREFP

97 GND

98 VDD_INT

99 GND

100 DAI0_PIN20

101 DAI0_PIN19

102 DAI0_PIN18

103 VDD_INT

104 VDD_EXT

105 DAI0_PIN17

106 DAI0_PIN16

107 DAI0_PIN15

108 DAI0_PIN14

109 VDD_INT

110 DAI0_PIN13

111 DAI0_PIN12

112 DAI0_PIN11

113 DAI0_PIN10

114 VDD_INT

115 VDD_EXT

116 DAI0_PIN09

117 DAI0_PIN08

118 DAI0_PIN06

119 DAI0_PIN07

120 DAI0_PIN05

Lead No. Pin Name

121 DAI0_PIN03

122 DAI0_PIN04

123 DAI0_PIN01

124 VDD_INT

125 GND

126 VDD_EXT

127 DAI0_PIN02

128 PB_15

129 VDD_INT

130 VDD_INT

131 GND

132 VDD_INT

133 GND

134 VDD_INT

135 JTG_TCK

136 JTG_TDO

137 JTG_TDI

138 JTG_TMS

139 VDD_INT

140 VDD_EXT

141 PB_14

142 PB_13

143 VDD_EXT

144 PB_12

145 VDD_INT

146 PB_11

147 VDD_EXT

148 PB_10

149 VDD_EXT

150 VDD_INT

151 SYS_HWRST

152 VDD_EXT

153 JTG_TRST

154 SYS_CLKIN0

155 SYS_XTAL0

156 VDD_INT

157 SYS_CLKOUT

158 VDD_EXT

159 PB_09

160 VDD_EXT

Lead No. Pin Name

Rev. B | Page 135 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

161 PB_08

162 PB_07

163 VDD_INT

164 VDD_EXT

165 PB_06

166 PB_05

167 VDD_EXT

168 PB_04

169 PB_03

170 VDD_INT

171 VDD_EXT

172 PB_02

173 PB_01

174 PB_00

175 VDD_INT

176 GND

1 GND

1 Pin177 is the GND supply (see Figure 91)

for the processor; this pad must connect to GND. Lead No. Pin Name

Rev. B | Page 136 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ADSP-SC57X/ADSP-2157X 176-LEAD LQFP LEAD ASSIGNMENTS (ALPHABETICAL BY PIN NAME) Pin Name Lead No. DAI0_PIN01 123 DAI0_PIN02 127 DAI0_PIN03 121 DAI0_PIN04 122 DAI0_PIN05 120 DAI0_PIN06 118 DAI0_PIN07 119 DAI0_PIN08 117 DAI0_PIN09 116 DAI0_PIN10 113 DAI0_PIN11 112 DAI0_PIN12 111 DAI0_PIN13 110 DAI0_PIN14 108 DAI0_PIN15 107 DAI0_PIN16 106 DAI0_PIN17 105 DAI0_PIN18 102 DAI0_PIN19 101 DAI0_PIN20 100 GND 02 GND 15 GND 44 GND 45 GND 65 GND 83 GND 89 GND 97 GND 99 GND 125 GND 131 GND 133 GND 176 GND 177 HADC0_VIN0 91 HADC0_VIN1 92 HADC0_VIN2 94 HADC0_VIN3 95 HADC0_VREFN 93 HADC0_VREFP 96 JTG_TCK 135 JTG_TDI 137 JTG_TDO 136 JTG_TMS 138 JTG_TRST 153 PA_00 80 PA_01 79 PA_02 77 PA_03 76 PA_04 75 PA_05 74 PA_06 70 PA_07 69 PA_08 68 PA_09 13 PA_10 10 PA_11 11 PA_12 08 PA_13 06 PA_14 05 PA_15 04 PB_00 174 PB_01 173 PB_02 172 PB_03 169 PB_04 168 PB_05 166 PB_06 165 PB_07 162 PB_08 161 PB_09 159 PB_10 148 PB_11 146 PB_12 144 PB_13 142 PB_14 141 PB_15 128 PC_00 34 PC_01 33 PC_02 32 PC_03 29 PC_04 28 PC_05 27 PC_06 26 PC_07 25 PC_08 24 PC_09 23 PC_10 22 PC_11 20 PC_12 19 PC_13 18 PC_14 17 Pin Name Lead No. PC_15 12 PD_00 67 PD_01 64 PD_02 63 PD_03 62 PD_04 61 PD_05 51 PD_06 50 PD_07 49 PD_08 48 PD_09 43 PD_10 42 PD_11 41 PD_12 40 PD_13 37 PD_14 36 PD_15 35 SYS_BMODE0 86 SYS_BMODE1 87 SYS_CLKIN0 154 SYS_CLKOUT 157 SYS_FAULT SYS_HWRST 151 SYS_RESOUT 81 SYS_XTAL0 155 TWI0_SCL 54 TWI0_SDA 53 TWI1_SCL 56 TWI1_SDA 55 TWI2_SCL 58 TWI2_SDA 57 VDD_EXT 09 VDD_EXT 21 VDD_EXT 31 VDD_EXT 38 VDD_EXT 46 VDD_EXT 60 VDD_EXT 71 VDD_EXT 78 VDD_EXT 84 VDD_EXT 104 VDD_EXT 115 VDD_EXT 126 VDD_EXT 140 VDD_EXT 143 VDD_EXT 147 Pin Name Lead No. VDD_EXT 149 VDD_EXT 152 VDD_EXT 158 VDD_EXT 160 VDD_EXT 164 VDD_EXT 167 VDD_EXT 171 VDD_HADC 90 VDD_INT 01 VDD_INT 03 VDD_INT 07 VDD_INT 14 VDD_INT 16 VDD_INT 30 VDD_INT 39 VDD_INT 47 VDD_INT 52 VDD_INT 59 VDD_INT 66 VDD_INT 72 VDD_INT 73 VDD_INT 82 VDD_INT 88 VDD_INT 98 VDD_INT 103 VDD_INT 109 VDD_INT 114 VDD_INT 124 VDD_INT 129 VDD_INT 130 VDD_INT 132 VDD_INT 134 VDD_INT 139 VDD_INT 145 VDD_INT 150 VDD_INT 156 VDD_INT 163 VDD_INT 170 VDD_INT 175

1 Pin 177 is the GND supply (see Figure 91)

for the processor; this pad must connect to GND. Pin Name Lead No.

Dimensions in Figure 92 (for the 400-ball BGA) and Figure 93 (for the 176-lead LQFP) are shown in millimeters. Figure 92. 400-Ball Chip Scale Pa ckage Ball Grid Array [CSP_BGA]

Surface-Mount Design and Land Pattern Standard. Figure 93. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] Table 98. CSP_BGA Data for Use with Surface-Mount Design

8.20 BSC

0.08 MAX

1.00 REF

Rev. B | Page 140 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 AUTOMOTIVE PRODUCTS The following models are available with controlled manufactur- ing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 99 are available for use in automotive applica- tions. Contact your local Analog Devices account representative for specific product ordering information and to obtain the spe- cific Automotive Reliability reports for these models. Table 99. Automotive Pro ducts

Description

AD21571WCSWZ4xx 450 MHz N/A –40°C to +105°C N/A 2 0 176-Lead LQFP_EP SW-176-5 AD21571WCSWZ5xx 500 MHz N/A –40°C to +105°C N/A 2 0 176-Lead LQFP_EP SW-176-5 AD21573WCBCZ4xx 450 MHz N/A –40°C to +105° C N/A 2 1 Pad 400-Ball CSP_BGA BC-400-2 AD21573WCBCZ5xx 500 MHz N/A –40°C to +105° C N/A 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSC570WCSWZ42xx 450 MHz 225 MHz –40°C to +105°C 1 1 0 176-Lead LQFP_EP SW-176-5 ADSC570WCSWZ4xx 450 MHz 450 MHz –40°C to +105°C 1 1 0 176-Lead LQFP_EP SW-176-5 ADSC571WCSWZ3xx 300 MHz 300 MHz –40°C to +105°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSC571WCSWZ4xx 450 MHz 450 MHz –40°C to +105°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSC571WCSWZ5xx 500 MHz 500 MHz –40°C to +105°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSC572WCBCZ42xx 450 MHz 225 MHz –40°C to + 105°C 1 1 1 Pad 400-Ball CSP_BGA BC-400-2 ADSC572WCBCZ4xx 450 MHz 450 MHz –40°C to + 105°C 1 1 1 Pad 400-Ball CSP_BGA BC-400-2 ADSC573WCBCZ3xx 300 MHz 300 MHz –40°C to + 105°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSC573WCBCZ4xx 450 MHz 450 MHz –40°C to + 105°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSC573WCBCZ5xx 500 MHz 500 MHz –40°C to + 105°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2 1 Z = RoHS Compliant Part. 2 xx denotes the current die revision. 3 For evaluation of all models, order the ADZS-SC573-EZLITE evaluation board. 4 N/A means not applicable. 5 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see the Operating Conditions section for the junction temperature (T J) specification which is the only temperature specification.

Rev. B | Page 141 of 142 | June 2018 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 ORDERING GUIDE Model1, 2 1 Z =RoHS Compliant Part. 2 For evaluation of all models, order the ADZS-SC573-EZLITE evaluation board. Processor Instruction Rate (Max) ARM Instruction Rate (Max) 3 N/A means not applicable. Temperature Range 4 Referenced temperature is ambient temperature. The ambi ent temperature is not a specification. Please see the Operating Conditions section for the junction temperature (T J) specification which is the only temperature specification. ARM Cores3 SHARC+ Cores External Memory Ports Package ADSP-21571KSWZ-4 450 MHz N/A 0°C to + 70°C N/A 2 0 176-Lead LQFP_EP SW-176-5 ADSP-21571BSWZ-4 450 MHz N/A –40°C to +85°C N/A 2 0 176-Lead LQFP_EP SW-176-5 ADSP-21571CSWZ-4 450 MHz N/A –40°C to +105°C N/A 2 0 176-Lead LQFP_EP SW-176-5 ADSP-21571KSWZ-5 500 MHz N/A 0°C to +70°C N/A 2 0 176-Lead LQFP_EP SW-176-5 ADSP-21571BSWZ-5 500 MHz N/A –40°C to +85°C N/A 2 0 176-Lead LQFP_EP SW-176-5 ADSP-21571CSWZ-5 500 MHz N/A –40°C to +100°C N/A 2 0 176-Lead LQFP_EP SW-176-5 ADSP-21573KBCZ-4 450 MHz N/A 0°C to +70° C N/A 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-21573BBCZ-4 450 MHz N/A –40°C to +85° C N/A 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-21573CBCZ-4 450 MHz N/A –40°C to +100° C N/A 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-21573KBCZ-5 500 MHz N/A 0°C to +70° C N/A 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-21573BBCZ-5 500 MHz N/A –40°C to + 85°C N/A 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-21573CBCZ-5 500 MHz N/A –40°C to + 95°C N/A 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC570KSWZ-42 450 MHz 225 MHz 0°C to +70°C 1 1 0 176-Lead LQFP_EP SW-176-5 ADSP-SC570BSWZ-42 450 MHz 225 MHz –40°C to +85°C 1 1 0 176-Lead LQFP_EP SW-176-5 ADSP-SC570CSWZ-42 450 MHz 225 MHz –40°C to +105°C 1 1 0 176-Lead LQFP_EP SW-176-5 ADSP-SC570KSWZ-4 450 MHz 450 MHz 0°C to +70°C 1 1 0 176-Lead LQFP_EP SW-176-5 ADSP-SC570BSWZ-4 450 MHz 450 MHz –40°C to +85°C 1 1 0 176-Lead LQFP_EP SW-176-5 ADSP-SC570CSWZ-4 450 MHz 450 MHz –40°C to +105°C 1 1 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571KSWZ-3 300 MHz 300 MHz 0°C to +70°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571BSWZ-3 300 MHz 300 MHz –40°C to +85°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571CSWZ-3 300 MHz 300 MHz –40°C to +105°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571KSWZ-4 450 MHz 450 MHz 0°C to +70°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571BSWZ-4 450 MHz 450 MHz –40°C to +85°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571CSWZ-4 450 MHz 450 MHz –40°C to +105°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571KSWZ-5 500 MHz 500 MHz 0°C to +70°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571BSWZ-5 500 MHz 500 MHz –40°C to +85°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC571CSWZ-5 500 MHz 500 MHz –40°C to +100°C 1 2 0 176-Lead LQFP_EP SW-176-5 ADSP-SC572KBCZ-42 450 MHz 225 MHz 0°C to +70°C 1 1 1 Pad 400-Bal l CSP_BGA BC-400-2 ADSP-SC572BBCZ-42 450 MHz 225 MHz –40°C to +85°C 1 1 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC572CBCZ-42 450 MHz 225 MHz –40°C to +100°C 1 1 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC572KBCZ-4 450 MHz 450 MHz 0°C to +70°C 1 1 1 Pad 400-Bal l CSP_BGA BC-400-2 ADSP-SC572BBCZ-4 450 MHz 450 MHz –40°C to +85°C 1 1 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC572CBCZ-4 450 MHz 450 MHz –40°C to +100°C 1 1 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC573KBCZ-3 300 MHz 300 MHz 0°C to +70°C 1 2 1 Pad 400-Bal l CSP_BGA BC-400-2 ADSP-SC573BBCZ-3 300 MHz 300 MHz –40°C to +85°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC573CBCZ-3 300 MHz 300 MHz –40°C to +100°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC573KBCZ-4 450 MHz 450 MHz 0°C to +70°C 1 2 1 Pad 400-Bal l CSP_BGA BC-400-2 ADSP-SC573BBCZ-4 450 MHz 450 MHz –40°C to +85°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC573CBCZ-4 450 MHz 450 MHz –40°C to +100°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC573KBCZ-5 500 MHz 500 MHz 0°C to +70°C 1 2 1 Pad 400-Bal l CSP_BGA BC-400-2 ADSP-SC573BBCZ-5 500 MHz 500 MHz –40°C to +85°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2 ADSP-SC573CBCZ-5 500 MHz 500 MHz –40°C to +95°C 1 2 1 Pad 400-Ball CSP_BGA BC-400-2

Rev. B | Page 142 of 142 | June 2018 ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16121-0-6/18(B) ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).