ADS92X4R

Texas Instruments

Dual, Low Latency, Simultaneous-Sampling SAR ADC

Manufacturer: Texas Instruments

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ADVANCE□INFORMATION ADC ADC Host Reference Position Encoder sine cosine Low Latency SAR Absolute/Incremental Encoder ADC ADC I Q Low Latency SAR 90° Local Oscillator Baseband Signal Host SONAR Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. ADS9224R SBAS876 – AUGUST 2018 ADS92x4RDual,LowLatency,Simultaneous-SamplingSARADC

1 Features

1• High Resolution, High Throughput: – ADS9224R: 16 Bit, 3 MSPS – ADS9234R: 14 Bit, 3 MSPS

Fast Response Time With Low Latency: 333 ns
Higher Performance Over Wide Analog Bandwidth: – ADS9224R: 83-dB SINAD at 1.4 MHz – ADS9234R: 80-dB SINAD at 1.4 MHz
Two Simultaneously Sampled channels
Unipolar, Fully Differential Inputs
Wide Common-Mode Voltage Range
Excellent DC and AC Performance: – ADS9224R: – 16-Bit NMC DNL, ±2-LSB Max INL – 93.5-dB SNR, –110-dB THD – 80-dB CMRR – ADS9234R: – 14-Bit NMC DNL, ±1-LSB Max INL – 85.6-dB SNR, –106-dB THD – 75-dB CMRR
Integrated Reference and Reference Buffers
Integrated REFby2 Buffer for Setting Common Mode
Integrated Data Averaging
Enhanced-SPI Interface for MCUs and FPGAs: – Wide Read Cycle to Read Data With MCUs – CRT for Data Transfers With Digital Isolators – DDR Modes for FPGAs
Parallel Byte Mode for Easy Interface
Extended Temperature Range: –40°C to +125°C
Small Footprint: 5-mm × 5-mm VQFN

2 Applications

Optical Encoders: Incremental and Absolute
SONAR Receivers
Optical Networking: EDFA Gain Control Loop
Power Quality Measurement
Digital Power Supply
I/Q Demodulators
Medical Imaging: CT Scanners, MRI Scanners

3 Description

The ADS92x4R is a pin-compatible, high-speed, dual, simultaneous-sampling, analog-to-digital converters (ADC) with an integrated reference and reference buffer. The device can operate on a single 5-V supply and supports unipolar, fully differential analog input signals with excellent DC and AC specifications. The device supports SPI-compatible serial (enhanced-SPI) and byte-wide parallel interfaces, making the device easy to pair with a diversity of microcontrollers, digital signal processors (DSPs), and field-programmable gate arrays (FPGAs). The device comes in a space-saving, 5-mm × 5-mm, VQFN package. The ADS92x4R is specified for the extended temperature range of –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADS92x4R VQFN (32) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Diagram

11.2 Receiving Notification of Documentation Updates 46

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES August 2018 * Initial release.

ADVANCE□INFORMATION

32 REFM_A9REFM_B

1AINP_A 24 SDO-0/0A

31 REFP_A10REFP_B

2AINM_A 23 SDO-1/1A

30 GND11GND

29 AVDD12AVDD

28 DVDD13CONVST

27 GND14CS

26 PD/RST15SDI

7AINP_B 18 SDO-6/2B

25 READY/STROBE16SCLK

5 Pin Configuration and Functions

5-mm × 5-mm, 32-Pin VQFN Top View Pin Functions PIN FUNCTION DESCRIPTIONNAME NO. AINM_A 2 Analog input Negative analog input for channel A. AINP_A 1 Analog input Positive analog input for channel A. AINM_B 8 Analog input Negative analog input for channel B. AINP_B 7 Analog input Positive analog input for channel B. AVDD 12, 29 Power supply Analog power-supply pin. Connect a 1-µF decoupling capacitor between pin 12 and pin 11. Connect pins 12 and 29 together. Connect a 1-µF decoupling capacitor between pin 29 and pin 30. CONVST 13 Digital input Conversion start input pin. A CONVST rising edge starts the conversion for ADC_A and ADC_B. CS 14 Digital input Chip-select input pin; active low. The device takes control of the data bus when CS is low. The SDO-x pins go to Hi-Z when CS is high. DVDD 28 Power supply Interface power-supply pin. Connect a 1-µF decoupling capacitor between pin 27 and pin 28. GND 4, 11, 27, 30 Power supply Ground NC 6 — No external connection PD/RST 26 Digital input Asynchronous reset or power-down input pin. See the Reset or Power-Down section. READY/STROBE 25 Digital output Indicates data ready or strobe output for data capture.

ADVANCE□INFORMATION ADS9224R SBAS876 – AUGUST 2018 www.ti.com Product Folder Links: ADS9224R Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN FUNCTION DESCRIPTIONNAME NO. REFby2 3 Analog output REFby2 buffer output. Connect a 1-µF decoupling capacitor between pin 3 and pin 4. REFOUT 5 Analog output Internal reference output. Connect a 1-µF decoupling capacitor between pin 5 and pin 4. REFM_A 32 Analog output Negative output of reference buffer A. Negative reference input for ADC_A. Externally connect to the device GND. REFM_B 9 Analog output Negative output of reference buffer B. Negative reference input for ADC_B. Externally connect to the device GND. REFP_A 31 Analog output Positive output of reference buffer A. Positive reference input for ADC_A. Connect a 10-µF decoupling capacitor between pin 31 and pin 32. REFP_B 10 Analog output Positive output of reference buffer B. Positive reference input for ADC_B. Connect a 10-µF decoupling capacitor between pin 9 and pin 10. SCLK 16 Digital input Clock input pin for the serial interface. SDI 15 Digital input Serial data input pin. This pin is used to program the device registers. SDO-0/0A 24 Digital output SPI mode: data output 0 for channel A. Parallel byte mode: least significant bit (LSB) from the data byte. SDO-1/1A 23 Digital output SPI mode: data output 1 for channel A. Parallel byte mode: LSB+1 from the data byte. SDO-2/2A 22 Digital output SPI mode: data output 2 for channel A. Parallel byte mode: LSB+2 from the data byte. SDO-3/3A 21 Digital output SPI mode: data output 3 for channel A. Parallel byte mode: LSB+3 from the data byte. SDO-4/0B 20 Digital output SPI mode: data output 0 for channel B. Parallel byte mode: LSB+4 from the data byte. SDO-5/1B 19 Digital output SPI mode: data output 1 for channel B. Parallel byte mode: LSB+5 from the data byte. SDO-6/2B 18 Digital output SPI mode: data output 2 for channel B. Parallel byte mode: LSB+6 from the data byte. SDO-7/3B 17 Digital output SPI mode: data output 3 for channel B. Parallel byte mode: most significant bit (MSB) from the data byte. Thermal pad Pad Power supply Exposed thermal pad. TI recommends connecting this pin to the printed circuit board (PCB) ground.

ADVANCE□INFORMATION ADS9224R www.ti.com SBAS876 – AUGUST 2018 Product Folder Links: ADS9224R Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Analog supply voltage AVDD to GND –0.3 6 V Digital supply voltage DVDD to GND –0.3 6 V Digital input voltage CS, CONVST, SDI, SCLK, PD/RST to GND –0.3 DVDD + 0.3 V Analog input voltage AINP_A, AINP_B to GND –0.3 AVDD + 0.3 V Analog input voltage AINM_A, AINM_B to GND –0.3 AVDD + 0.3 V Input or output current to any pin except power supply pin –10 10 mA Maximum virtual junction temperature TJ 150 °C Storage temperature Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog supply voltage 4.5 5 5.5 V DVDD Digital supply voltage operating range 1.65 3.3 5.5 V Digital supply voltage for SCLK > 20 MHz 2.35 3.3 5.5 V TA Ambient temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) ADS92x4R UNITRHB (VQFN)

32 PINS

RθJA Junction-to-ambient thermal resistance 29 °C/W RθJC(top) Junction-to-case (top) thermal resistance 17.1 °C/W RθJB Junction-to-board thermal resistance 9.4 °C/W ΨJT Junction-to-top characterization parameter 0.2 °C/W ΨJB Junction-to-board characterization parameter 9.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 °C/W

ADVANCE□INFORMATION ADS9224R SBAS876 – AUGUST 2018 www.ti.com Product Folder Links: ADS9224R Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Ideal input span; does not include gain or offset error. (2) Does not include the variation in voltage resulting from solder shift effects.

6.5 Electrical Characteristics: ADS92x4R

all minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.35 to 5.5 V and fSAMPLE = 3 MSPS (unless otherwise noted); Typical values are at TA= 25°C, AVDD = 5 V, and DVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT FSR Full-scale input voltage(1) VREF = 2.5 V -4.096 4.096 V VIN Absolute input voltage (AINP or AINM to GND) VREF = 2.5 V 0 4.096 V VCM Common-mode input range VREF = 2.5 V 1.848 2.248 V IIN Analog input leakage current ±1 µA Ci Input capacitance Sample Mode 16 pF Hold Mode 1 SAMPLING DYNAMICS tCYCLE Cycle time 333 ns fSAMPLE Sampling rate 3 MSPS tACQ Acquisition time 140 ns tA Aperture delay 8 ns tA mismatch 40 ps tJITTER Aperture jitter 2 ps BW Analog input bandwidth -3dB Input Signal 100 MHz -0.1 dB Input Signal 20 MHz VOLTAGE REFERENCE OUTPUT VREF (2) REFOUT voltage TA = 25°C 2.498 2.5 2.502 V ΔVREF/ΔT VREF drift 5 20 ppm/°C ΔVREF/ΔAVDD VREF line regulation AVDD variation 4.5 V to

5.5 V 200 µV/V

IREFOUT REFOUT output current capability |ΔVREF| < 2 mV 1.5 µA CREFOUT REFOUT capacitor For specified performance 1 µF twkup- REFOUT REFOUT wake-up time CREFOUT = 1 µF 10 ms INTERNAL REFERENCE BUFFER GREFBUF Reference buffer Gain 1.6384 V/V EO-REFBUF Reference buffer output offset (VREFP_x - VREF) At TA = 25°C ±500 µV TA = -40°C to 125°C –1 0 1 mV ΔEO-REFBUF/ΔT Reference buffer output offset temperature drift 10 µV/℃ (VREFP_A - VREFP_B) Reference buffer output mismatch TA = -40°C to 125°C –500 ±50 500 µV CREFP_x Reference buffer output capacitor For specified performance, between each pair of REFP and REFM 7 10 27 µF tREFBUF-SETTLE Reference buffer output settling time CREFP_x = 10 µF 25 ms REFby2 OUTPUT VREFby2 REFby2 uutput voltage EN_REFBY2_OFFSET = 0, VREF = 2.5 V 2.043 2.048 2.053 V EN_REFBY2_OFFSET = 1, VREF = 2.5 V 2.133 2.148 2.163 V IREFby2 REFby2 output current capability ±3 mA REFby2 output capacitor 1 µF

ADVANCE□INFORMATION ADS9224R www.ti.com SBAS876 – AUGUST 2018 Product Folder Links: ADS9224R Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated all minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.35 to 5.5 V and fSAMPLE = 3 MSPS (unless otherwise noted); Typical values are at TA= 25°C, AVDD = 5 V, and DVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (3) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full- scale, unless otherwise specified. REFby2 output noise With specified output capacitor 10 µVRMS Digital Outputs VOH High level output voltage IOH = 500 µA source 0.8 × DVDD DVDD V VOL Low level output voltage IOL = 500 µA sink 0 0.2 × DVDD V Digital Inputs VIH High level input voltage DVDD > 2.3 V 0.7 × DVDD DVDD +0.3 V VIL Low level intput voltage –0.3 0.3 × DVDD V VIH High level input voltage DVDD ≤ 2.3 V 0.8 × DVDD DVDD +0.3 V VIL Low level intput voltage –0.3 0.2 × DVDD V Power Supply AVDD Analog supply voltage 4.5 5 5.5 V DVDD Digital supply voltage 1.65 3.3 5.5 V IAVDD Analog supply current AVDD = 5 V, fSAMPLE =

3 MSPS 24 mA

AVDD = 5 V, No Conversion 8 mA AVDD = 5 V, Power down (PD/RST Low) 1 µA IDVDD Digital supply current DVDD = 3.3 V, CSDO-x/y = 10 pF 0.75 mA PSRR(3) Power supply rejection ratio 100mVp-p Ripple on AVDD of frequency < 100kHz 70 dB (1) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full- scale, unless otherwise specified.

6.6 Electrical Characteristics: ADS9224R

ADVANCE□INFORMATION ADS9224R SBAS876 – AUGUST 2018 www.ti.com Product Folder Links: ADS9224R Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated all minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.35 to 5.5 V, and fSAMPLE = 3 MSPS (unless otherwise noted); Typical values are at TA= 25°C, AVDD = 5 V, and DVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Calculated on the first nine harmonics of the input frequency. SINAD(1) (2) Signal-to-noise plus distortion FIN = 2 kHz 90.8 dB FIN = 100 kHz 90.3 dB FIN = 1400 kHz 83 dB THD(1) (2) Total harmonic distortion FIN = 2 kHz –110 dB FIN = 100 kHz –105 dB FIN = 1400 kHz -85 dB SFDR(1) Spurious-free dynamic range FIN = 2 kHz 115 dB FIN = 100 kHz 110 dB FIN = 1400 kHz 90 dB ISOXT(1) Channel-to-channel isolation FIN_ADCA = 15 kHz at 10% FSR, FIN_ADCB = 25 kHz at 100% FSR –110 dB (1) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full- scale, unless otherwise specified. (2) Calculated on the first nine harmonics of the input frequency.

6.7 Electrical Characteristics: ADS9234R

all minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.35 to 5.5 V, and fSAMPLE = 3 MSPS (unless otherwise noted); Typical values are at TA= 25°C, AVDD = 5 V, and DVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC ACCURACY Resolution, no missing codes 14 bit DNL Differential nonlinearity –0.99 ±0.15 0.99 LSB INL Integral nonlinearity –1 ±0.3 1 LSB EO Offset error –2.5 ±0.8 2.5 LSB GE Cummulative gain error for ADC_x and REFBUF_x –0.05 ±0.01 0.05 %FSR ΔGE/ΔT Gain drift 5 ppm/°C Transition noise Mid-code, PFS-1000, NFS+1000 TBD LSB CMRR(1) Common mode rejection ratio FIN = dc to 1-MHz, VIN = 100 mVp-p 75 dB AC ACCURACY SNR(1) Signal-to-noise ratio FIN = 2 kHz 82 85.6 dB FIN = 100 kHz 84 dB FIN = 1400 kHz 82 dB SINAD(1) (2) Signal-to-noise plus distortion FIN = 2 kHz 85.6 dB FIN = 100 kHz 84 dB FIN = 1400 kHz 80 dB THD(1) (2) Total harmonic distortion FIN = 2 kHz –106 dB FIN = 100 kHz –105 dB FIN = 1400 kHz –85 dB SFDR(1) Spurious-free dynamic range FIN = 2 kHz 108 dB FIN = 100 kHz 107 dB FIN = 1400 kHz 90 dB ISOXT(1) Channel-to-channel isolation FIN_ADCA = 15 kHz at 10% FSR, FIN_ADCB = 25 kHz at 100% FSR –110 dB

ADVANCE□INFORMATION ADS9224R www.ti.com SBAS876 – AUGUST 2018 Product Folder Links: ADS9224R Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) See Switching Characteristics (2) See Protocols for Reading From the Device for tREAD (3) Other parameters are the same as the SPI-compatible and Parallel Byte Protocols.

6.8 Timing Requirements

all minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.35 V to 5.5 V, and fSAMPLE = 3 MSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V MIN NOM MAX UNIT Conversion Control and Data Transfer (See Figure 1 and Figure 2) tD_CONVST_CS Delay time: CONVST high to CS Falling for zero cycle latency (zone 1 transfer) tDRDY (1) ns tD_CONVST_CS Delay time: CONVST high to CS falling for zone 2 transfer 15 180 ns tWL_CONVST Pulse duration : CONVST low 15 ns tWH_CONVST Pulse duration : CONVST high 15 ns tCYCLE Time between two adjacent CONVST rising edges for zero cycle latency (zone 1 transfer) tDRDY+tREAD (2) ns tCYCLE Time between two adjacent CONVST rising edges for zone 2 transfer 333 ns SPI-compatible and Parallel Byte Protocols (See Figure 3) tCLK Serial clock time period 1/ fCLK tPH_CLK SCLK high time 0.45 × tCLK 0.55 × tCLK ns tPL_CLK SCLK low time 0.45 × tCLK 0.55 × tCLK ns tSU_CSCK Setup time: CS faling to first SCLK capture edge 12 ns tSU_CKDI Setup Time: SDI data valid to SCLK capture edge 1.5 ns tHT_CKDI Hold Time: SCLK capture edge to previous data valid on SDI 1.5 ns tHT_CKCS Delay Time: last SCLK capture edge to CS rising 7 ns fCLK Serial clock frequecny for SPI protocols with single data rate 60 MHz fCLK Serial clock frequecny for SPI protocols with double data rate 22 MHz fCLK Serial clock frequecny for parallel byte protocol 45 MHz Clock Re-Timer protocol with STROBE = SCLK (External Clock)(3)(See Figure 4) fCLK Serial clock frequency with single data rate 60 MHz fCLK Serial clock frequency with double data rate 22 MHz Asynchronous Reset and Power Down Timing (See Figure 6) tWL-RST Pulse duration (Low) for reset 50 500 ns tWL-PD-min Minimum pulse duration (Low) for power down 1000 ns

6.9 Switching Characteristics

all minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.35 V to 5.5 V, and fSample = 3 MSPS (unless otherwise noted); typical values are at TA= 25°C, AVDD = 5 V, and DVDD = 3.3 V MIN TYP MAX UNIT Conversion Control and Data Transfer (See Figure 1 and Figure 2) tDRDY Data ready time for present sample: CONVST high to READY high with zero cycle latency (zone 1 transfer) for ADS9224x (16-bit) 300 ns Data ready time for present sample: CONVST high to READY high with zero cycle latency (zone 1 transfer) for ADS9234x (14-bit) 285 ns SPI-compatible and Parallel Byte Protocols (See Figure 3) tDEN_CSDO Delay time: CS falling to data valid on SDO-x 12 ns tDZ_CSDO Delay time: CS rising edge to SDO-x tristate 12 ns tD_CKDO Delay time: SCLK launch edge to next data valid on SDO-x for SPI-compatible protocols with single data rate TBD 15.8 ns tD_CKDO Delay time: SCLK launch edge to next data valid on SDO-x for SPI-compatible protocols with double data rate TBD 21 ns tD_CKDO Delay time: SCLK launch edge to next data valid on SDO-x for parallel byte protocol TBD 21 ns Clock Re-Timer protocol with STROBE = SCLK (External Clock)(1)(See Figure 4) tOFF_STROBE_DO Time offset: STROBE edge to next data valid on SDO-x -2.5 2.5 ns tD_CS_READY Delay time: CS rising to READY displaying internal device state 13.5 ns tD_CKSTROBE_r Delay time: SCLK rising edge to STROBE rising 21.5 ns tD_CKSTROBE_f Delay time: SCLK falling edge to STROBE falling 21.5 ns tPH_STROBE Strobe output high time 0.45 × tSTR 0.55 × tSTR ns tPL_STROBE Strobe output low time 0.45 × tSTR 0.55 × tSTR ns Clock Re-Timer protocol with STROBE = Internal Clock.(1)(See Figure 5) tD_CS_STROBE Delay time : CS falling to 1st STROBE rising 15 50 ns tOFF_STROBE_DO Time offset : STROBE edge to next data valid on SDO-x -2.5 2.5 ns tD_CS_READY Delay time: CS rising to READY displaying internal device state 13.5 ns tINTCLK INTCLK period 15 ns tSTR STROBE period (INTCLK) 15 ns INTCLK/2 30 ns INTCLK/4 60 ns tWH_STR STROBE high period 0.45 × tSTR 0.55 × tSTR ns tWL_STR STROBE low period 0.45 × tSTR 0.55 × tSTR ns Asynchronous Reset and Power Down Timing (See Figure 6) tRST-WKUP Wake up time from reset 1 µs tPD-WKUP (2) Wake up time from power down 25 ms

ADVANCE□INFORMATION REFBUF_A Serial Interface PD/RST AINP_A AVDD DVDD REFP_B Reference Voltage 2.5 V AINM_A ADC_A AINP_B AINM_B ADC_B REFBUF_B AVDD AVDD REFP_A REFOUT REFOUT REFM_B REFM_A CONVST CS SCLK SDI READY/STROBE SDO-x/y SDO-x/y AVDD GND REFby2REFby2 AVDD ADS9224R SBAS876 – AUGUST 2018 www.ti.com Product Folder Links: ADS9224R Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The device belongs to a family of dual, high-speed, simultaneous-sampling, analog-to-digital converters (ADCs). The device supports fully differential input signals and a full-scale input range equal to 3.2678 × VREF. When a conversion is initiated, the input between the AINP_x and AINM_x pins is sampled on the internal capacitor array. The device uses an internal clock to perform conversions. During the conversion process, both analog inputs are disconnected from the internal circuit. At the end of conversion process, the device reconnects the sampling capacitors to the AINP_x and AINM_x pins and enters an acquisition phase. The device includes reference buffers to provide the charge required by the ADCs during conversion. The device includes a reference voltage for the ADCs. The enhanced serial programming interface (SPI) digital interface is backward-compatible with traditional SPI protocols. Configurable features simplify board layout, timing, and firmware and support high throughput at lower clock speeds, thus allowing an easy interface with a variety of microcontrollers, digital signal processors (DSPs), and field-programmable gate arrays (FPGAs). The device also provides a byte mode and a wide read cycle to reduce the clock frequency required for data transfer. The device includes a clock re-timer (CRT) to enable data transfer through digital isolators. The device also supports double data rate (DDR) with SPI-compatible serial interface modes and with a clock re-timer.

7.2 Functional Block Diagram

7.3 Feature Description

as shown in the Functional Block Diagram section. voltage is used by the converters for conversion process.

7.3.1 Converter Modules

from the interface module, and output the ADCST signal and the conversion result back to the interface module. Figure 7. Converter Modules

7.3.1.1 Analog Input With Sample-and-Hold

120 Ω) in series with an ideal switch (SW1 and SW2). The sampling capacitors, CS1 and CS2, are typically 16 pF. Figure 8. Analog Input Structure for Converter Module

at the analog inputs for reference voltage (VREF) on the REFOUT pin.

7.3.1.2 ADC Transfer Function

This device supports unipolar, fully differential input signals. The device output is in two's compliment format.

1 LSB = FSR / 2R

FSR is defined in Equation 1
R = Resolution of the device (3)

Figure 9. Ideal Transfer Characteristics Table 1. Transfer Characteristics

7.3.2 Internal Reference Voltage

Figure 10. Connection Diagram for Reference and Reference Buffers

7.3.3 Reference Buffers

REFM_x pin as close to the device as possible.

7.3.4 REFby2 Buffer

The device includes a REFby2 buffer for setting the common-mode voltage required by the converter modules. The REFby2 output can be provided to the VOCM pin of the fully differential amplifiers (similar to the THS4551).

Figure 11. REFby2 Buffer

7.3.5 Data Averaging

configure the data averaging, configure the DATA_AVG_CFG register.

7.3.5.1 Averaging of Two Samples

Figure 12. Timing for Averaging of Two Samples

7.3.5.2 Averaging of Four Samples

Figure 13. Timing for Averaging of Four Samples

7.4 Device Functional Modes

Figure 14. Device Functional States

7.4.1 ACQ State

7.4.2 CNV State

subsequent start of conversions.

7.4.3 Reset or Power-Down

decides the state for the device (reset or power-down). Figure 15 provides the timing diagram for these states. Protocols for Configuring the Device sections for details. Figure 15. Reset or Power Down

7.4.3.1 Reset

(see the Register Maps section) are reset to their default values.

7.4.3.2 Power-Down

section) are reset to their default values. powers up and enters ACQ state.

7.4.4 Conversion Control and Data Transfer Frame

transfer) and another with a wide read cycle (zone 2 transfer).

7.4.4.1 Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)

In this mode of conversion control and data transfer, the device starts conversion on the rising edge of CONVST. rising edge of the READY/STROBE pin indicates that the data are ready and the data can be read by the host. minimum delay time of tD_CONVST_CS (= tDRDY) between the rising edge of CONVST and the falling edge of CS. between two adjacent rising edges of the CONVST signal (tCYCLE) is determined as tCYCLE = tDRDY + tREAD. re-timer (CRT) protocols. See the READY/STROBE Output section for details. (2) For tREAD with different data transfer protocols; see the Protocols for Reading From the Device section. Figure 16. Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)

7.4.4.2 Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)

In this mode of conversion control and data transfer, the device starts conversion on the rising edge of CONVST. permissible value. The data for the previous sample (sample N-1) is provided by the device on the SDO pins. and for getting conversion results from the device. (CRT) protocols. See the READY/STROBE Output section for details. (2) For tREAD with different data transfer protocols; see the Protocols for Reading From the Device section. Figure 17. Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer) the Device section for details on different protocols for reading the data.

(1) The device provides register data in the output data word during register read operation. (2) When a fixed pattern data is enabled, the device provides a fixed pattern in the output data word.

7.5 READY/STROBE Output

The READY/STROBE pin has multiple functions. The READY and STROBE signals are multiplexed to this pin. When CS is low, STROBE is output and when CS is high, READY is output.

7.5.1 READY Output

of 0.9 ms, this signal goes low, indicating that the device is initialized and the registers can be configured. READY_MASK bit in the OUTPUT_DATA_WORD_CFG register.

7.5.2 STROBE Output

7.6 Programming

7.6.1 Output Data Word

output data word. The output data word is provided on data lines (SDO-xx) for each ADC. Table 2. Output Data Word output data word. With right alignment, the device appends MSBs in the beginning of the output data word. Figure 18 shows the data alignment in the data output word. Figure 18. Data Alignment for ADS9234R Devices

(1) For legacy SPI-compatible protocols, set the SDO_PROTOCOL bits in PROTOCOL_CFG register to 000b. (2) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA. (3) With SCLK ≥ 30 MHz, TI recommends data capture on the launch edge for the next bit. (4) With SCLK < 30 MHz, data can be captured either on the same edge as the SCLK phase or on the launch edge for the next bit. (5) tREAD is the read time for reading the 16-bit output data word. k = (tSU_CSCK + tHT_CKCS). (6) For ADS9234R devices, the read time for reading the 14-bit output data word is [13.5 × tCLK + k].

7.6.2 Data Transfer Protocols

Increase the width of the output data bus (dual SDO, quad SDO, or parallel byte)
Enable double data rate (DDR) transfer
Wider read cycle by extending the data transfer window (zone 2 transfer) These three options can be combined to achieve further reduction in SCLK speed.

7.6.2.1 Protocols for Reading From the Device

Legacy, SPI-compatible protocols (SPI-xy-S-SDR)
SPI-compatible protocols with bus width options and single data rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)
SPI-compatible protocols with bus width options and double data rate (SPI-x1-S-DDR, SPI-x1-D-DDR, and
Clock re-timer (CRT) protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, and
Parallel byte protocol (PB-xy-AB-SDR, PB-xy-AA-SDR)

7.6.2.1.1 Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)

provides the details of different legacy SPI protocols to read data from the device. Table 3. SPI-xy-S-SDR Protocols for Reading From Device

(1) For SPI-compatible protocols with bus width options and SDR, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 000b. (2) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA. (3) With SCLK ≥ 30 MHz, TI recommends data capture on the launch edge for the next bit. (4) With SCLK < 30 MHz, data can be captured either on the same edge as the SCLK phase or on the launch edge for the next bit. (5) For configuring the bus width, configure the BUS_WIDTH register. (6) tREAD is the read time for reading the 16-bit output data word. k = (tSU_CSCK + tHT_CKCS). SDR protocols, respectively. Figure 19. SPI-00-S-SDR and SPI-10-SDR Protocols Figure 20. SPI-01-S-SDR and SPI-11-SDR Protocols

7.6.2.1.2 SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)

protocols with bus width options and single data rate to read data from the device. Table 4. SPI-xy-D-SDR and SPI-xy-Q-SDR Protocols for Reading From Device

(1) For SPI-compatible protocols with bus width options and DDR, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 001b. compatible protocols with bus width options and DDR. (3) For configuring the bus width, configure the BUS_WIDTH register. (4) tREAD is the read time for reading the 16-bit output data word. k = (tSU_CSCK + tHT_CKCS). bus width of 2, and [3 × tCLK + k] for a bus width of 4.

7.6.2.1.3 SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR,

options and double data rate to read data from the device. Table 5. SPI-x1-S-DDR, SPI-x1-D-DDR, and SPI-x1-Q-DDR Protocols for Reading From Device D-DDR and SPI-11-D-DDR, and SPI-01-Q-DDR and SPI-11-Q-DDR protocols, respectively. Figure 25. SPI-01-S-DDR and SPI-11-S-DDR Protocols Figure 26. SPI-01-D-DDR and SPI-11-D-DDR Protocols

Figure 27. SPI-01-Q-DDR and SPI-11-Q-DDR Protocols

the SDO_PROTOCOL bits to 011b in the PROTOCOL_CFG register. (2) The device only supports CPOL = 0 for CRT protocols with an external clock. (3) For configuring the bus width, configure the BUS_WIDTH register.

7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-

the details of different CRT protocols to read data from the device. Table 6. CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, and CRT-Q-DDR Protocols for DDR, CRT-Q-SDR, and CRT-Q-DDR protocols, respectively. Figure 28. CRT-S-SDR Protocol Figure 29. CRT-S-DDR Protocol

(1) For parallel byte protocols, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 1xxb. (2) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA. OUTPUT_DATA_WORD_CFG register. (4) tREAD is the read time for reading the 16-bit output data word. k = (tSU_CSCK + tHT_CKCS).

7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR

parallel byte protocols to read data from the device. Table 7. PB-xy-AB-SDR, PB-xy-AA-SDR Protocols for Reading Data and PB-11-AA-SDR, respectively. Figure 34. PB-00-AB-SDR and PB-10-AB-SDR Protocols Figure 35. PB-01-AB-SDR and PB-11-AB-SDR Protocols

(1) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA. (2) tWRITE is the write time for writing the 16-bit data word. k = (tSU_CSCK + tHT_CKCS). Figure 36. PB-00-AA-SDR and PB-10-AA-SDR Protocols Figure 37. PB-01-AA-SDR and PB-11-AA-SDR Protocols

7.6.2.2 Protocols for Configuring the Device

The device supports an SPI protocol for writing into the device with all combinations of clock polarity and phase. 10-S, or SPI-11-S) to write data to the device. Table 8. SPI Protocols for Configuring the Device

(1) Register data for READ command is provided by device in the next frame.

7.6.3 Reading and Writing Registers

details of commands for reading and writing registers. Figure 40. Command Frame C[15:0] Table 9. Commands for Reading and Writing Registers

0000 NOP0 Command for conversion control and reading conversion

0001 WRITE Command for writing registers 4-bit register

0010 READ(1) Command for reading registers 4-bit register

0101 Set bit Command for setting specific bits in a register without

0110 Clear bit Command for clearing specific bits in a register without

1111 NOP1 Command for conversion control and reading conversion

7.7 Register Maps

Table 10 lists the access codes for the ADS9224R, ADS9234R registers. Table 10. ADS9224R, ADS9234R Access Type Codes

7.7.1 DEVICE_STATUS Register (address = 0h) [reset = 00h]

This register provides the error status of averaging mode and the status of zone 2 data transfer mode. Figure 41. DEVICE_STATUS Table 11. DEVICE_STATUS Field Descriptions 7-3 RESERVED R 00000b Reserved bits. Do not write. Reads return 00000b.

2 ZONE2_TRANSFER R/W 0b This bit is set when the device operates in zone 2 transfer mode

1 AVG_ERROR R/W 0b This bit is set when the device receives a falling edge of CS

sticky bit. Write 1 to this bit to clear. 0 RESERVED R 00000b Reserved bits. Do not write. Reads return 00000b.

7.7.2 POWER_DOWN_CFG Register (address = 1h) [reset = 00h]

This register powers down different blocks in the device. Figure 42. POWER_DOWN_CFG Table 12. POWER_DOWN_CFG Field Descriptions 7-6 RESERVED R 00b Reserved bits. Do not write. Reads return 00b. 5 PD_REFby2 R/W 0b This bit powers down the REFby2 output. 4 RESERVED R 0b Reserved bits. Do not write. Reads return 00b. 3 PD_ADCB R/W 0b This bit powers down the ADC_B and REFBUF_B. 2 RESERVED R 0b Reserved bits. Do not write. Reads return 00b. 1 PD_ADCA R/W 0b This bit powers down the ADC_A and REFBUF_A. 0 PD_REF R/W 0b This bit powers down the internal reference voltage.

7.7.3 PROTOCOL_CFG Register (address = 2h) [reset = 00h]

reading data from the device. Figure 43. PROTOCOL_CFG

0 SDO_PROTOCOL 0 0 SPI_CPOL SPI_CPHA

Table 13. PROTOCOL_CFG Field Descriptions 7 RESERVED R 0b Reserved bits. Do not write. Reads return 0b. 6-4 SDO_PROTOCOL R/W 000b These bits set the protocol for reading data from the device. 1xx: Parallel byte protocols. 3-2 RESERVED R 00b Reserved bits. Do not write. Reads return 00b.

1 SPI_CPOL R/W 0b This bit sets the clock polarity for reading data from the device

and writing data into the device.

0 SPI_CPHA R/W 0b This bit sets the clock phase for reading data from the device

and writing data into the device.

7.7.4 BUS_WIDTH Register (address = 3h) [reset = 00h]

This register configures the bus width (number of SDO Lines) for reading data from the device. Figure 44. BUS_WIDTH Table 14. BUS_WIDTH Field Descriptions 7-2 RESERVED R 000000b Reserved bits. Do not write. Reads return 000000b. SDO lines as per the parallel byte protocol.

7.7.5 CRT_CFG Register (address = 4h) [reset = 00h]

This register selects the clock source for the strobe output for clock re-timer (CRT) protocols. Figure 45. CRT_CFG Table 15. CRT_CFG Field Descriptions 7-2 RESERVED R 000000b Reserved bits. Do not write. Reads return 000000b. INTCLK is generated from the internal oscillator of the device.

7.7.6 OUTPUT_DATA_WORD_CFG Register (address = 5h) [reset = 00h]

selects the format for the output data word in the parallel byte protocol. Figure 46. OUTPUT_DATA_WORD_CFG Table 16. OUTPUT_DATA_WORD_CFG Field Descriptions 7-6 RESERVED R 00b Reserved bits. Do not write. Reads return 00b. 5 READY_MASK R/W 0b This bit masks the READY output. Cycle (Zone 2 Transfer) section.

4 PARALLEL_MODE_DATA_FORMAT R/W 0b This bit selects the format for the output data word in the

3-2 RESERVED R 00b Reserved bits. Do not write. Reads return 00b. 1 FIXED_PATTERN_DATA R/W 0b This bit enables a fixed pattern in the output data word.

0 DATA_RIGHT_ALIGNED R/W 0b This bit enables the right alignment in the output data word for

7.7.7 DATA_AVG_CFG Register (address = 6h) [reset = 00h]

This register configures the averaging of conversion results. Figure 47. DATA_AVG_CFG Table 17. DATA_AVG_CFG Field Descriptions 7-2 RESERVED R 000000b Reserved bits. Do not write. Reads return 000000b. 1-0 EN_DATA_AVG R/W 00b These bits enable averaging of conversion results.

7.7.8 REFby2_OFFSET (address = 7h) [reset = 00h]

This register enables the offset for the REFby2 output. Figure 48. REFby2_OFFSET Table 18. REFby2_OFFSET Field Descriptions 7-1 RESERVED R 0000000b Reserved bits. Do not write. Reads return 000000b. 0 EN_REFby2_OFFSET R/W 0b This bit enables the offset for the REFby2 output.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 ADC Input Driver

circuit is critical to meet the linearity and noise performance of the ADS92x4R.

8.1.1.1 Charge-Kickback Filter

input sampling capacitance is equal to 16 pF; therefore, for optimal performance, keep CFLT greater than 320 pF. provides the most stable electrical properties over voltage, frequency, and temperature changes. Figure 49. Charge Kickback Filter resistors less than 1% to keep the inputs balanced.

ADVANCE□INFORMATION uuduSu uu 20 dBSNR REF dB 3 RMS_ n PP _AMP_f1 G 10 V 1f2e6 . 6 V dB10THDTHD ADCAMP d FLT FLT 1UGB 4 2 R CS ADS9224R SBAS876 – AUGUST 2018 www.ti.com Product Folder Links: ADS9224R Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Application Information (continued)

8.1.2 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type, as well as the performance goals, of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the ADC are:

Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the ADC sample-and-hold capacitor and the RC filter (the charge-kickback filter) at the inputs of the ADC. Higher bandwidth amplifiers offer faster settling times when driving the capacitive load of the charge-kickback filter, thus reducing harmonic distortion at higher input frequencies. Equation 4 describes the unity gain bandwidth (UGB) of the amplifier to be selected in order to maintain the overall stability of the input driver circuit: (4)
Distortion. Both the ADC and the input driver introduce distortion in a data acquisition block. Equation 5 shows that to make sure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver must be at least 10 dB less than the distortion of the ADC: (5)
Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in SNR performance of the system. Generally, to make sure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be kept below 20% of the input-referred noise of the ADC. Equation 6 explains that noise from the input driver circuit is band-limited by designing a low cutoff frequency, charge-kickback filte: where
V1 / f_AMP_PP is the peak-to-peak flicker noise in μV
en_RMS is the amplifier broadband noise density in nV/√Hz
f–3dB is the 3-dB bandwidth of the charge-kickback filter
NG is the noise gain of the front-end circuit that is equal to 1 in a buffer configuration (6)
Settling Time. For DC signals with fast transients that are common in a multiplexed application, the input signal must settle within an 16-bit accuracy at the device inputs during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 16-bit accuracy. Therefore, always verify the settling behavior of the input driver by TINA-TI SPICE simulations before selecting the amplifier.

8.2 Typical Application

Figure 50. DAQ Circuit for Lowest Distortion and Noise With the ADS92x4R for a 100-kHz Input Signal

8.2.1 Design Requirements

The design parameters are listed in Table 19 for this example. Table 19. Design Parameters

8.2.2 Detailed Design Procedure

capacitor and connected to each FDA VOCM input pin. Each VOCM pin is decoupled using a 0.1-µF capacitor. digital converter evaluation module tool folder.

8.2.3 Application Curves

Figure 51. Typical FFT With 100-kHz Signal Figure 52. Typical INL

9 Power Supply Recommendations

voltage, and converter modules (ADC_A and ADC_B) operate on AVDD. The serial interface operates on DVDD. AVDD and DVDD can be independently set to any value within their permissible ranges. a 1-µF decoupling capacitor between pin 28 (DVDD) and pin 27 (GND). Figure 53. Power-Supply Decoupling

10 Layout

10.1 Layout Guidelines

This section provides some layout guidelines for achieving optimum performance with the ADS92x4R.

10.1.1 Signal Path

As illustrated in Figure 54, the analog input signals are routed in opposite directions to the digital connections. The reference decoupling components are kept away from the switching digital signals. This arrangement prevents noise generated by digital switching activity from coupling to sensitive analog signals.

10.1.2 Grounding and PCB Stack-Up

Low inductance grounding is critical for achieving optimum performance. Grounding inductance is kept below 1 nH with 15-mil grounding vias and a printed circuit board (PCB) layout design that has at least four layers. Place all critical components of the signal chain on the top layer with a solid analog ground from subsequent inner layers to minimize via length to ground.

10.1.3 Decoupling of Power Supplies

Place the decoupling capacitors on AVDD and DVDD within 20 mil from the respective pins, and use a 15-mil via to ground from each capacitor. Avoid placing vias between any supply pin and the respective decoupling capacitor.

10.1.4 Reference Decoupling

Dynamic currents are present at the REFP_x and REFM_x pins during the conversion phase, and excellent decoupling is required to achieve optimum performance. Place a 10-µF, X7R-grade, ceramic capacitor with at least a 10-V rating, as illustrated in Figure 54. Select 0603- or 0805-size capacitors to keep equivalent series inductance (ESL) low. Connect the REFM_x pins to the decoupling capacitor before a ground via. Also place decoupling capacitors on the REFOUT and REFby2 pins.

10.1.5 Differential Input Decoupling

Dynamic currents are also present at the differential analog inputs of the ADS92x4R. Use C0G- or NPO-type capacitors to decouple these inputs because with these type of capacitors, capacitance stays almost constant over the full input voltage range. Lower-quality capacitors (such as X5R and X7R) have large capacitance changes over the full input-voltage range that may cause degradation in the performance of the device.

10.2 Layout Example

Figure 54. Example Layout for the ADS92x4R

11 Device and Documentation Support

11.1 Related Documentation

For related documentation see the following:

THS4551 Low-Noise, Precision, 150-MHz, Fully Differential Amplifier
TI Precision Designs: Verified Design 12 Bit 1 MSPS Single Supply Dual Channel Data Acquisition System for Optical Encoders in Motor Control Application
REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference
OPAx350 High-Speed, Single-Supply, Rail-to-Rail Operational Amplifiers MicroAmplifier Series
THS452x Very Low Power, Negative Rail Input, Rail-To-Rail Output, Fully Differential Amplifier
ADS9224REVM-PDK User's Guide

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

TINA-TI, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 24-Aug-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADS9224RIRHBR PREVIEW VQFN RHB 32 3000 TBD Call TI Call TI -40 to 125 XDS9224RIRHBR ACTIVE VQFN RHB 32 3000 TBD Call TI Call TI -40 to 125 XDS9234RIRHBR ACTIVE VQFN RHB 32 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 24-Aug-2018 Addendum-Page 2

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Product Information

ADS92X4R specifications and overview.

Summary

Dual, Low Latency, Simultaneous-Sampling SAR ADC

Description

Dual, Low Latency, Simultaneous-Sampling SAR ADC

Source title ADS92X4R Datasheet(PDF) - Texas Instruments

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