ADS902 TI1 | Alldatasheet
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Technical content
FEATURES
G HIGH SNR: 57dB G EXTERNAL REFERENCE G LOW POWER: 140mW G ADJUSTABLE FULL SCALE RANGE G POWER DOWN G SSOP-28 PACKAGE
DESCRIPTION
The ADS902 is a high speed pipelined Analog-to-Digital Converter (ADC) that is specified to operate from a single +5V supply. This converter includes a wide bandwidth track/hold and a 10-bit quantizer. The performance is speci- fied with a single-ended input range of 2.25V to 3.25V, or 2V to 4V. The input range is set by the external reference values. The ADS902 employs digital error correction techniques to provide excellent differential linearity for demanding imag- ing applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. This high performance ADC is specified to operate at a 30MHz sampling rate. The ADS902 is available in a SSOP-28 package. 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM
APPLICATIONS
G BATTERY POWERED EQUIPMENT G CAMCORDERS G PORTABLE TEST EQUIPMENT G COMPUTER SCANNERS G COMMUNICATIONS ADS902E ADS902 SBAS063A – MARCH 2001 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PARAMETER CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS Resolution 10 10 Bits Specified Temperature Range Ambient Air –40 +85 –40 +85 °C ANALOG INPUT Specified Full Scale Input Range(1) 1 2 Vp-p Common-Mode Voltage (Midscale) +2.75 3 V Analog Input Bias Current 1 ✻ µA Input Impedance 1.25 || 5 ✻ M Ω || pF DIGITAL INPUTS Logic Family High Input Voltage, V IH +2.0 +V S ✻✻ V Low Input Voltage, VIL +0.8 ✻ V High Input Current, IIH ±10 ✻ µA Low Input Current, IIL ±10 ✻ µA Input Capacitance 5 ✻ pF CONVERSION CHARACTERISTICS Sample Rate Full 10k 30M ✻✻ Samples/s Data Latency 5 ✻ Clk Cyc
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified. 1Vp-p 2Vp-p TTL/HCT Compatible CMOSTTL/HCT Compatible CMOS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA ADS902E SSOP-28 324 –40 °C to +85°C ADS902E ADS902E Rails "" " " ADS902E ADS902E/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “ADS902E/1K” will get a single 1000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION
PARAMETER CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified. 1Vp-p 2Vp-p DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz Full ±0.3 ±1.0 ✻✻ LSB f = 12.5MHz Full ±0.3 ✻ LSB No Missing Codes Full Guaranteed Guaranteed Spurious-Free Dynamic Range f = 12.5MHz (–1dBFS(2) input) Full 53 50 58 dBFS Integral Nonlinearity Error, f = 500kHz Full ±2.0 ±4.5 ✻✻ LSB Signal-to-Noise Ratio (SNR) Referred to Sinewave Input Signal f = 500kHz (–1dBFS input) Full 53 dB f = 12.5MHz (–1dBFS input) Full 48 53 52 57 dB Maximum SNR Referred to DC FS Input Signal f = 9MHz (–1dBFS input) 62 66 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) Full 50 dB f = 3.58MHz (–1dBFS input) Full 50 dB f = 12.5MHz (–1dBFS) input) Full 45 49 47 53 dB Effective Number of Bits (3), f =12.5MHz 7.8 Bits Output Noise Input Grounded 0.2 ✻ LSB rms Aperture Delay Time 4 ✻ ns Aperture Jitter 7 ✻ ps rms Analog Input Bandwidth Small Signal –20dBFS Input +25 °C 350 ✻ MHz Full Power 0dBFS Input +25 °C 100 ✻ MHz DIGITAL OUTPUTS C L = 15pF Logic Family Logic Coding High Output Voltage, V OH +2.4 LV DD ✻✻ V Low Output Voltage, VOL +0.4 ✻ V 3-State Enable Time OE = L 20 40 ✻✻ ns 3-State Disable Time OE = H 18 10 ✻✻ ns OE Internal Pull-Down to Gnd 50 ✻ kΩ Power-Down Enable Time Pwrdn = L 133 ✻ ns Power-Down Disable Time Pwrdn = H 18 ✻ ns Power-Down Internal Pull-Down to Gnd 50 ✻ kΩ ACCURACY fS = 2.5MHz Gain Error Full 0.5 1 %FS Input Offset Error(4) Full 1.4 ✻ %FS Power Supply Rejection (Gain) ∆ VS = ±5% Full 56 ✻ dB Power Supply Rejection (Offset) ∆ VS = ±5% Full 68 ✻ dB External REFT Voltage Range Full REFB +0.5 +3.25 V S–0.8 ✻ +4 ✻ V External REFB Voltage Range Full +0.8 +2.25 REFT –0.5 ✻ +2 ✻ V Reference Input Resistance REFT to REFB 4 ✻ kΩ POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Full +4.25 +5.0 +5.25 ✻✻ ✻ V Supply Current: +IS Full 28 ✻ mA Power Dissipation Full 140 160 ✻✻ mW Power Dissipation (Power Down) Full 15 ✻ mW Thermal Resistance, θJA SSOP-28 89 ✻ °C/W ✻ Specification same as 1Vp-p. NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) dBFS means dB relative to Full Scale. (3) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (4) Offset deviation from ideal negative full scale. TTL/HCT Compatible CMOS Straight Offset Binary TTL/HCT Compatible CMOS Straight Offset Binary
5 Clock Cycles
N –5N –4N –3N –2N –1 N N+1 N+2Data Out Clock Analog In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 33 100 µsn s tL Clock Pulse Low 15.5 16.5 ns tH Clock Pulse High 15.5 16.5 ns tD Aperture Delay 2 ns t1 Data Hold Time, CL = 0pF 4 ns t2 New Data Delay Time, CL = 15pF max 12 ns TIMING DIAGRAM PIN CONFIGURATION Top VIew SSOP PIN DESIGNATOR DESCRIPTION 1+ V S Analog Supply 2L V DD Output Logic Driver Supply Voltage
3 Bit 10 Data Bit 10 (D0, LSB)
4 Bit 9 Data Bit 9 (D1)
5 Bit 8 Data Bit 8 (D2)
6 Bit 7 Data Bit 7 (D3)
7 Bit 6 Data Bit 6 (D4)
8 Bit 5 Data Bit 5 (D5)
9 Bit 4 Data Bit 4 (D6)
10 Bit 3 Data Bit 3 (D7)
11 Bit 2 Data Bit 2 (D8)
12 Bit 1 Data Bit 1 (D9, MSB)
13 GND Analog Ground
14 GND Analog Ground
15 CLK Convert Clock Input
16 OE Output Enable, Active Low
17 Pwrdn Power Down Pin
19 GND Analog Ground
20 GND Analog Ground
21 LpBy Positive Ladder Bypass
22 REFT Top Reference
23 NC No Connection
24 REFB Bottom Reference
25 LnBy Negative Ladder Bypass
26 CM Common-Mode Voltage Output
27 IN Analog Input
+VS LVDD (LSB) Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (MSB) Bit 1 GND GND S IN CM LnBY REFB NC REFT LpBY GND GND S Pwrdn OE CLK ADS902
Frequency (MHz) –20 –40 –60 –80 –100 –120 Amplitude (dB) fIN = 12.5MHz 2Vp-p UNDERSAMPLING Frequency (MHz) –20 –40 –60 –80 –100 –120 Amplitude (dB) fIN = 40MHz fS = 28MHz VIN = 1Vp-p SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 Amplitude (dB) fIN = 12.5MHz VIN = 1Vp-p TYPICAL CHARACTERISTICS At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, and Sampling Rate = 30MHz, unless otherwise specified. DIFFERENTIAL LINEARITY ERROR Output Code DLE (LSB) fIN = 12.5MHz 2Vp-p 0 256 512 768 1024 DIFFERENTIAL LINEARITY ERROR Output Code DLE (LSB) fIN = 12.5MHz VIN = 1Vp-p 0 256 512 768 1024 FREQUENCY SPECTRUM Frequency (MHz) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 2.50 5.00 7.50 10.00 Magnitude (dBFSR) f1 = 3.5MHz at –7dB f2 = 3.6MHz at –7dB 2f1 – f2 = 69.5dBFS 2f2 – f1 = 68.4dBFS
Input Amplitude (dBFS) 120 100 SFDR fIN = 12.5MHz 2Vp-p OFFSET ERROR vs TEMPERATURE Temperature (°C) 1.6 1.5 1.4 1.3 1.2 1.1 –50 –25 0 25 75 50 100 Offset (%FS) VIN = 1Vp-p TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = Logic VDD = +5V, REFB = 2.25V, REFT = 3.25V, Sampling Rate = 30MHz, unless otherwise specified. SWEPT POWER SFDR Input Amplitude (dBFS) 100 SFDR fIN = 12.5MHz 1Vp-p –80 –60 –40 –20 0 INTEGRAL LINEARITY ERROR Output Code –10 ILE (LSB) fIN = 500kHz VIN = 1Vp-p 0 256 512 768 1024 dBFS dBc dBc dBFS GAIN ERROR vs TEMPERATURE Temperature (°C) 0.2 0.4 0.6 –50 –25 0 25 75 50 100 Gain Error (%FS) VIN = 1Vp-p
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