ADS902 BURR-BROWN | Alldatasheet
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Technical content
1 ADS902
FEATURES
l HIGH SNR: 57dB l EXTERNAL REFERENCE l LOW POWER: 140mW l ADJUSTABLE FULL SCALE RANGE l POWER DOWN l 28-PIN SSOP PACKAGE
DESCRIPTION
The ADS902 is a high speed pipelined analog-to- digital converter that is specified to operate from a single +5V supply. This converter includes a wide bandwidth track/hold and a 10-bit quantizer. The per- formance is specified with a single-ended input range of 2.25V to 3.25V, or 2V to 4V. The input range is set by the external reference values. The ADS902 employs digital error correction tech- niques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for tele- communications, video and test instrumentation appli- cations. This high performance A/D converter is speci- fied to operate at a 30MHz sampling rate. The ADS902 is available in a 28-pin SSOP package. 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 TM
APPLICATIONS
l BATTERY POWERED EQUIPMENT l CAMCORDERS l PORTABLE TEST EQUIPMENT l COMPUTER SCANNERS l COMMUNICATIONS ADS902E © 1996 Burr-Brown Corporation PDS-1359B Printed in U.S.A., February, 1997
At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified. ADS902E PARAMETER CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS Resolution 10 10 Bits Specified Temperature Range Ambient Air –40 +85 –40 +85 °C ANALOG INPUT Specified Full Scale Input Range(1) 1 2 Vp-p Common-Mode Voltage (Midscale) +2.75 3 V Track-Mode Input Bandwidth 350 [ MHz Analog Input Bias Current 1 [ µA Input Impedance 1.25 || 5 [ M Ω || pF DIGITAL INPUTS Logic Family High Input Voltage, V IH +2.0 +V S [[ V Low Input Voltage, VIL +0.8 [ V High Input Current, IIH ±10 [ µA Low Input Current, IIL ±10 [ µA Input Capacitance 5 [ pF CONVERSION CHARACTERISTICS Sample Rate Full 10k 30M [[ Samples/s Data Latency 5 [ Clk Cyc DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz Full ±0.3 ±1.0 [[ LSB f = 12.5MHz Full ±0.3 ±1.0 [[ LSB No Missing Codes Full Guaranteed Guaranteed Spurious-Free Dynamic Range f = 12.5MHz (–1dBFS(2) input) Full 53 50 58 dB Integral Nonlinearity Error, f = 500kHz Full ±2.0 ±4.5 [[ LSB Signal-to-Noise Ratio (SNR) Referred to Sinewave Input Signal f = 500kHz (–1dBFS input) Full 48 53 dB f = 12.5MHz (–1dBFS input) Full 48 53 52 57 dB Maximum SNR Referred to DC FS Input Signal f = 9MHz (–1dBFS input) 62 66 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) Full 46 50 dB f = 3.58MHz (–1dBFS input) Full 45 50 dB f = 12.5MHz (–1dBFS) input) Full 45 49 47 53 dB Effective Number of Bits (3), f =12.5MHz 7.8 Bits Output Noise Input Grounded 0.2 [ LSB rms Aperture Delay Time 4 [ ns Aperture Jitter 7 [ ps rms DIGITAL OUTPUTS C L = 15pF Logic Family Logic Coding High Output Voltage, V OH +2.4 LV DD [[ V Low Output Voltage, VOL +0.4 [ V 3-State Enable Time OE = L 20 40 [[ ns 3-State Disable Time OE = H 18 10 [[ ns OE Internal Pull-Down to Gnd 50 [ kΩ Power-Down Enable Time Pwrdn = L 133 [ ns Power-Down Disable Time Pwrdn = H 18 [ ns Power-Down Internal Pull-Down to Gnd 50 [ kΩ ACCURACY Gain Error Full 0.5 1 %FS Input Offset Error(4) Full 1.4 [ %FS Power Supply Rejection (Gain) Δ VS = ±5% Full 42 56 [[ dB Power Supply Rejection (Offset) Δ VS = ±5% Full 42 68 [[ dB External REFT Voltage Range Full REFB +0.5 +3.25 V S–0.8 [ +4 [ V External REFB Voltage Range Full +0.8 +2.25 REFT –0.5 [ +2 [ V Reference Input Resistance REFT to REFB 4 [ kΩ 1Vp-p 2Vp-p TTL/HCT Compatible CMOSTTL/HCT Compatible CMOS The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. TTL/HCT Compatible CMOS Straight Offset Binary TTL/HCT Compatible CMOS Straight Offset Binary
3 ADS902
SPECIFICATIONS (CONT) At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified. ADS902E PARAMETER CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS 1Vp-p 2Vp-p POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Full +4.25 +5.0 +5.25 [[ [ V Supply Current: +IS Full 28 [ mA Power Dissipation Full 140 160 [[ mW Power Dissipation (Power Down) Full 15 [ mW Thermal Resistance, θJA 28-Pin SSOP 50 [ °C/W [ Specification same as 1Vp-p. NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) dBFS means dB relative to Full Scale. (3) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (4) Offset deviation from ideal negative full scale. PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER (1) RANGE ADS902E 28-Pin SSOP 324 –40 °C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN CONFIGURATION Top VIew SSOP PIN DESIGNATOR DESCRIPTION 1+ V S Analog Supply 2L V DD Output Logic Driver Supply Voltage
3 Bit 10 Data Bit 10 (D0, LSB)
4 Bit 9 Data Bit 9 (D1)
5 Bit 8 Data Bit 8 (D2)
6 Bit 7 Data Bit 7 (D3)
7 Bit 6 Data Bit 6 (D4)
8 Bit 5 Data Bit 5 (D5)
9 Bit 4 Data Bit 4 (D6)
10 Bit 3 Data Bit 3 (D7)
11 Bit 2 Data Bit 2 (D8)
12 Bit 1 Data Bit 1 (D9, MSB)
13 GND Analog Ground
14 GND Analog Ground
15 CLK Convert Clock Input
16 OE Output Enable, Active Low
17 Pwrdn Power Down Pin
19 GND Analog Ground
20 GND Analog Ground
21 LpBy Positive Ladder Bypass
22 REFT Top Reference
23 NC No Connection
24 REFB Bottom Reference
25 LnBy Negative Ladder Bypass
26 CM Common-Mode Voltage Output
27 IN Analog Input
PACKAGE/ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS +V S LVDD (LSB) Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (MSB) Bit 1 GND GND S IN CM LnBY REFB NC REFT LpBY GND GND S Pwrdn OE CLK ADS902
5 Clock Cycles
N–5 N–4 N–3 N–2 N–1 N N+1 N+2Data Out Clock Analog In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 33 100 µsn s tL Clock Pulse Low 15.5 16.5 ns tH Clock Pulse High 15.5 16.5 ns tD Aperture Delay 2 ns t1 Data Hold Time, CL = 0pF 4 ns t2 New Data Delay Time, CL = 15pF max 12 ns TIMING DIAGRAM
5 ADS902
Frequency (MHz) –20 –40 –60 –80 –100 –120 Amplitude (dB) fIN = 12.5MHz 2Vp-p UNDERSAMPLING Frequency (MHz) –20 –40 –60 –80 –100 –120 Amplitude (dB) fIN = 40MHz fS = 28MHz VIN = 1Vp-p SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 Amplitude (dB) fIN = 12.5MHz VIN = 1Vp-p TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, and Sampling Rate = 30MHz, unless otherwise specified. DIFFERENTIAL LINEARITY ERROR Output Code DLE (LSB) fIN = 12.5MHz 2Vp-p 0 256 512 768 1024 DIFFERENTIAL LINEARITY ERROR Output Code DLE (LSB) fIN = 12.5MHz VIN = 1Vp-p 0 256 512 768 1024 FREQUENCY SPECTRUM Frequency (MHz) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 2.50 5.00 7.50 10.00 Magnitude (dBFSR) f1 = 3.5MHz at –7dB f2 = 3.6MHz at –7dB 2f1 – f2 = 69.5dBFS 2f2 – f1 = 68.4dBFS
Input Amplitude (dBFS) 120 100 SFDR fIN = 12.5MHz 2Vp-p OFFSET ERROR vs TEMPERATURE Temperature (°C) 1.6 1.5 1.4 1.3 1.2 1.1 –50 –25 0 25 75 50 100 Offset (%FS) VIN = 1Vp-p TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = Logic VDD = +5V, REFB = 2.25V, REFT = 3.25V, Sampling Rate = 30MHz, unless otherwise specified. SWEPT POWER SFDR Input Amplitude (dBFS) 100 SFDR fIN = 12.5MHz 1Vp-p –80 –60 –40 –20 0 INTEGRAL LINEARITY ERROR Output Code –10 ILE (LSB) fIN = 500kHz VIN = 1Vp-p 0 256 512 768 1024 dBFS dBc dBc dBFS GAIN ERROR vs TEMPERATURE Temperature (°C) 0.2 0.4 0.6 –50 –25 0 25 75 50 100 Gain Error (%FS) VIN = 1Vp-p
7 ADS902
FIGURE 2. Pipeline A/D Architecture. FIGURE 1. Input Track/Hold Configuration with Timing
9 ADS902
- Possible op amps for A1 are CLC452, EL2180
output, may considerably improve its distortion performance. noise. Its value is usually between 10Ω and 100Ω . around the common-mode voltage of +2.75V. out degrading the typical performance. to set the correct current through the ladder (see Figure 6). supply voltage, different resistor values might be selected. FIGURE 5. DC-Coupled, Single-Supply Interface Circuit. FIGURE 6. Low Cost Solution to Supply External Reference Voltages.
11 ADS902
converter does not accurately process the sampled signal. from the following 5 clock cycles is invalid (data latency). and limit the achievable performance. the supply and reference pins be sufficiently bypassed. should be located as close to the supply pins as possible. FIGURE 9. Recommended Bypassing for Analog Supply