ADS901 TI | Alldatasheet
Document overview
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Technical content
DESCRIPTION
The ADS901 is a high-speed pipelined analog-to-digital converter that operates from a +3V power supply. This complete converter includes a wide bandwidth track/hold and a 10-bit quantizer. The full scale input range is set by external references. The ADS901 employs digital error correction techniques to provide excellent differential linearity for demanding imag- ing applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. The ADS901 is available in an SSOP-28 package. 10-Bit, 20MHz, +3V Supply ANALOG-TO-DIGITAL CONVERTER
APPLICATIONS
G BATTERY POWERED EQUIPMENT G CAMCORDERS G DIGITAL CAMERAS G COMPUTER SCANNERS G COMMUNICATIONS
FEATURES
G LOW POWER: 48mW at +3V G SUPPLY RANGE: +2.7V to +3.7V G ADJUSTABLE FULL SCALE RANGE WITH EXTERNAL REFERENCES G NO MISSING CODES G WIDEBAND TRACK/HOLD: 350MHz G POWER DOWN: 15mW G SSOP-28 PACKAGE TM ADS901E ADS901 SBAS054A – MAY 2001 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = LVDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified. ABSOLUTE MAXIMUM RATINGS ADS901E PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS Resolution 10 Bits Specified Temperature Range Ambient Air –40 +85 °C ANALOG INPUT Specified Full Scale Input Range(1) 1Vp-p V Common-Mode Voltage (Midscale) 1.5 V Analog Input Bias Current 1 µA Input Impedance 1.25 || 5 M Ω || pF DIGITAL INPUT Logic Family CMOS Compatible Convert Command (Start Conversion) Start Conversion Rising Edge of Convert Clock CONVERSION CHARACTERISTICS Sample Rate Full 10k 20M Samples/s Data Latency 5 Clk Cyc ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA ADS901E SSOP-28 324 –40 °C to +85°C ADS901E ADS901E Rail ADS901E SSOP-28 324 –40 °C to +85°C ADS901E ADS901E/1K Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “ADS901E/1K” will get a single 1000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION
PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = LVDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified. DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz Full ±0.8 LSB f = 9MHz Full ±0.9 ±1.0 LSB No Missing Codes Full Guaranteed Integral Nonlinearity Error, f = 500kHz Full ±3.5 LSB Spurious Free Dynamic Range (2) f = 500kHz (–1dBFS(3) input) Full 50 dBFS (3) f = 9MHz (–1dBFS input) Full 45 49 dBFS Signal-to-Noise Ratio (SNR) Referred to Sinewave Input Signal f = 500kHz (–1dBFS input) Full 53 dB f = 9MHz (–1dBFS input) Full 48 53 dB Maximum SNR Referred to DC Full Scale Input Signal f = 9MHz (–1dBFS input) 62 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) Full 50 dB f = 3.58MHz (–1dBFS input) Full 50 dB f = 9MHz (–1dBFS input) Full 45 49 dB Effective Number of Bits (4) fIN = 3.58MHz 8.0 Bits Differential Gain Error NTSC, PAL 2.3 % Differential Phase Error NTSC, PAL 1.0 degrees Output Noise Input Grounded 0.2 LSB rms Aperture Delay Time 3n s Aperture Jitter 7 ps rms Analog Input Bandwidth Small Signal –20dBFS Input 350 MHz Full Power 0dBFS Input 100 MHz Overvoltage Recovery Time (5) 2n s DIGITAL OUTPUTS C L = 15pF Logic Family CMOS Compatible Logic Coding Straight Offset Binary High Output Voltage, VOH +2.4 LV DD V Low Output Voltage, VOL +0.4 V 3-State Enable Time OE = L 20 40 ns 3-State Disable Time OE = H 18 10 ns Internal Pull-Down to Gnd 50 k Ω Power-Down Enable Time Pwrdn = L 133 ns Power-Down Disable Time Pwrdn = H 18 ns Internal Pull-Down to Gnd 50 k Ω ACCURACY f S = 2.5MHz Gain Error Full 2.5 %FS Input Offset(6) Full 0.4 %FS Power Supply Rejection (Gain) ∆ VS = +10% Full 56 dB Power Supply Rejection (Offset) Full 68 dB External REFT Voltage Range Full REFB +0.5 2 V S–0.8 V External REFB Voltage Range Full 0.8 1 REFT –0.5 V Reference Input Resistance 4k Ω POWER SUPPLY REQUIREMENTS Supply Voltage: +V S Operating Full +2.7 +3.0 +3.7 V Supply Current: +IS Operating Full 16 mA Power Dissipation Operating Full 49 60 mW Power Dissipation (Power Down) Operating Full 15 mW Thermal Resistance, θJA 28-Lead SSOP 89 °C/W NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic.
5 Clock Cycles
N –5N –4N –3N –2N –1 N N+1 N+2Data Out Clock Analog In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 TOP VIEW SSOP PIN CONFIGURATION PIN DESIGNATOR DESCRIPTION 1+ V S Analog Supply 2L V DD Output Logic Driver Supply Voltage
3 Bit 10 Data Bit 10 (D0) (LSB)
4 Bit 9 Data Bit 9 (D1)
5 Bit 8 Data Bit 8 (D2)
6 Bit 7 Data Bit 7 (D3)
7 Bit 6 Data Bit 6 (D4)
8 Bit 5 Data Bit 5 (D5)
9 Bit 4 Data Bit 4 (D6)
10 Bit 3 Data Bit 3 (D7)
11 Bit 2 Data Bit 2 (D8)
12 Bit 1 Data Bit 1 (D9) (MSB)
13 GND Analog Ground
14 GND Analog Ground
15 CLK Convert Clock Input
16 OE Output Enable, Active Low
17 Pwrdn Power Down Pin
19 GND Analog Ground
20 GND Analog Ground
21 LpBy Positive Ladder Bypass
22 REFT Top Reference Input
23 NC No Connection
24 REFB Bottom Reference Input
25 LnBy Negative Ladder Bypass
26 CM Common-Mode Voltage Output
27 IN Analog Input
SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 50 100 µsn s tL Clock Pulse Low 24 25 ns tH Clock Pulse High 24 25 ns tD Aperture Delay 3 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12 ns +VS LVDD (LSB) Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (MSB) Bit 1 GND GND S IN CM LnBy REFB NC REFT LpBy GND GND S Pwrdn OE CLK ADS901
Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 9MHz SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 500kHz DIFFERENTIAL LINEARITY ERROR Output Code 0 256 512 768 1024 DLE (LSB) fIN = 500kHz TYPICAL CHARACTERISTICS At TA = +25°C, VS = Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified. SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 3.58MHz TWO-TONE INTERMODULATION Frequency (MHz) –20 –40 –60 –80 –100 0 2.5 5 7.5 10 Amplitude (dB) f1 = 4.5MHz f2 = 5.0MHz DIFFERENTIAL LINEARITY ERROR Output Code DLE (LSB) fIN = 9MHz 0 256 512 768 1024
Frequency (MHz) –20 –40 –60 –80 –100 –120 Amplitude (dB) fIN = 20MHz fS = 16MHz TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified. INTEGRAL LINEARITY ERROR Output Code –10 ILE (LSB) fIN = 500kHz 0 256 512 768 1024 DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE Temperature (°C) 0.9 0.8 0.7 0.6 –50 0 25–25 50 75 100 DLE (LSB) fIN = 9MHz fIN = 500kHz SWEPT POWER SFDR Input Amplitude (dBFS) 100 SFDR (dBc, dBFS) dBFS dBc SPURIOUS FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE Temperature (°C) –50 0 25–25 50 75 100 SFDR (dBFS) fIN = 500kHz fIN = 9MHz DYNAMIC PERFORMANCE vs INPUT FREQUENCY Frequency (MHz) 0.1 1 10 SFDR (dBFS), SNR (dB) SNR SFDR
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS, Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified. POWER DISSIPATION vs TEMPERATURE Temperature (°C) –50 0 25–25 50 75 100 Power Dissipation (mW) OFFSET ERROR vs TEMPERATURE Temperature (°C) –50 0 25–25 50 75 100 Offset Error (% FS) 0.6 0.5 0.4 0.3 OUTPUT NOISE HISTOGRAM (DC Input) Output Code N-2 N-1 N+1 N N+2 Counts (x105) SIGNAL-TO-NOISE RATIO vs TEMPERATURE Temperature (°C) –50 0 25–25 50 75 100 SNR (dB) fIN = 9MHz fIN = 500kHz GAIN ERROR vs TEMPERATURE Temperature (°C) 2.8 2.7 2.6 2.5 2.4 –50 0 25–25 50 75 100 Gain Error (%FS) POWER DISSIPATION vs SAMPLING FREQUENCY Frequency (MHz) 1 10 100 Power Dissipation (mW)
neous current to internal nodes. FIGURE 5. Low Cost Solution to Supply External Reference Voltages and Recommended Reference Bypassing. advanced CMOS logic should be used (HC/HCT, AC/ACT). TABLE I. Coding Table for the ADS901.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS901E Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS901E ADS901E.B Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS901E ADS901EG4.B Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS901E (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADS901E DB SSOP 28 50 530 10.5 4000 4.1 ADS901E.B DB SSOP 28 50 530 10.5 4000 4.1 ADS901EG4.B DB SSOP 28 50 530 10.5 4000 4.1 Pack Materials-Page 1
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