ADS900E

ADS900 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 15

Technical content

FEATURES

G +2.7V TO +3.7V SUPPLY OPERATION G INTERNAL REFERENCE G LOW POWER: 52mW at +3V G SINGLE-ENDED INPUT RANGE: 1V to 2V G WIDEBAND TRACK/HOLD: 350MHz G SSOP-28 PACKAGE

DESCRIPTION

The ADS900 is a high-speed pipelined Analog-to-Digital Converter (ADC). This complete converter includes a high bandwidth track-and-hold, a 10-bit quantizer, and an inter- nal reference. The ADS900 employs digital error correction techniques to provide excellent differential linearity for demanding im- aging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. This high-performance ADC is specified for performance at a 20MHz sampling rate. The ADS900 is available in an SSOP-28 package. 10-Bit, 20MHz, +3V Supply ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

G PORTABLE INSTRUMENTATION G IF AND BASEBAND COMMUNICATIONS G CABLE MODEMS G SET-TOP BOXES G PORTABLE TEST EQUIPMENT G COMPUTER SCANNERS TM Pipeline A/D Internal Reference Timing Circuitry Error Correction 3-State OutputsT/H 10-Bit Digital Data CLK ADS900 LVDD OEPwrdn1VREFLnByCMLpBy IN IN (Opt.) ADS900 SBAS058A – MAY 2001 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ADS900E

ELECTRICAL CHARACTERISTICS

At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS ADS900E PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS Resolution 10 Bits Specified Temperature Range Ambient Air –40 +85 °C ANALOG INPUT Single-Ended Full Scale Input Range (1Vp-p) +1.0 +2.0 V Differential Full Scale Input Range (0.5Vp-pX 2) +1.25 +1.75 V Common-Mode Voltage 1.5 V Analog Input Bias Current 1 µA Input Impedance 1.25 || 5 M Ω || pF DIGITAL INPUTS Logic Family TTL/HCT COMPATIBLE CMOS High Input Voltage, VIH 2.0 V DD V Low Input Voltage, VIL 0.8 V High Input Current, IIH ±10 µA Low Input Current, IIL ±10 µA Input Capacitance 5p F CONVERSION CHARACTERISTICS Start Conversion RISING EDGE OF CONVERT CLOCK Sample Rate Full 10k 20M Samples/s Data Latency 5 Clk Cyc PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA ADS900E SSOP-28 324 –40 °C to +85°C ADS900E ADS900E Rails "" " " ADS900E ADS900E/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “ADS900E/1K” will get a single 1000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. ADS900E PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz (Largest Code Error) Full ±0.7 LSBs f = 10MHz (Largest Code Error) Full ±0.7 ±1.0 LSBs No Missing Codes Full Guaranteed Integral Nonlinearity Error, f = 500kHz Full ±3.5 LSBs Spurious Free Dynamic Range (1) f = 500kHz (–1dBFS(2) input) Full 53 dBFS (2) f = 10MHz (–1dBFS(2) input) Full 47 53 dBFS Two-Tone Intermodulation Distortion(3) f = 4.5MHz and 5.0MHz (–7dBFS each tone) +25 °C 50 dBc Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) Full 49 dB f = 10MHz (–1dBFS input) Full 45 49 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) Full 48 dB f = 3.58MHz (–1dBFS input) Full 48 dB f = 10MHz (–1dBFS input) Full 44 48 dB Differential Gain Error NTSC, PAL 2.3 % Differential Phase Error NTSC, PAL 1 degrees Output Noise Input Grounded 0.2 LSBs rms Aperture Delay Time 2n s Aperture Jitter 7 ps rms Analog Input Bandwidth Small Signal –20dBFS Input +25 °C 350 MHz Full Power 0dBFS Input +25 °C 100 MHz Overvoltage Recovery Time (4) 1.5X FS Input +25 °C2 n s DIGITAL OUTPUTS C L = 15pF Logic Family TTL/HCT COMPATIBLE CMOS Logic Coding Straight Offset Binary High Output Voltage, VOH +2.4 LV DD V Low Output Voltage, VOL +0.4 V 3-State Enable Time OE = L 20 40 ns 3-State Disable Time OE = H 2 10 ns Internal Pull-Down 50 k Ω Power-Down Enable Time PwrDn = L 133 ns Power-Down Disable Time PwrDn = H 18 ns Internal Pull-Down 50 k Ω ACCURACY f S = 2.5MHz Gain Error +25°C8 ±10 %FS Input Offset Referred to Ideal Midscale Full 15 ±60 mV Power Supply Rejection (Gain) ∆ VS = +10% Full 55 dB Power Supply Rejection (Offset) Full 62 dB Internal Positive Reference Voltage Full +1.75 V Internal Negative Reference Voltage Full +1.25 V POWER SUPPLY REQUIREMENTS Supply Voltage: +V S Operating Full +2.7 +3 +3.7 V Supply Current: +IS Operating Full 18 22 mA Power Dissipation Operating, +3V Full 54 66 mW 25°C5 2 m W Power Dissipation (Power Down) +3V Full 10 mW Thermal Resistance, θJA SSOP-28 89 °C/W NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) No rollover of bits.

5 Clock Cycles

N –5N –4N –3N –2N –1 N N+1 N+2Data Out Clock Analog In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 PIN CONFIGURATION PIN DESIGNATOR DESCRIPTION 1+ V S Analog Supply 2L V DD Output Logic Driver Supply Voltage

3 Bit 10 Data Bit 10 (D0) (LSB)

4 Bit 9 Data Bit 9 (D1)

5 Bit 8 Data Bit 8 (D2)

6 Bit 7 Data Bit 7 (D3)

7 Bit 6 Data Bit 6 (D4)

8 Bit 5 Data Bit 5 (D5)

9 Bit 4 Data Bit 4 (D6)

10 Bit 3 Data Bit 3 (D7)

11 Bit 2 Data Bit 2 (D8)

12 Bit 1 Data Bit 1 (D9) (MSB)

13 GND Analog Ground

14 GND Analog Ground

15 CLK Convert Clock Input

16 OE Output Enable, Active Low

17 Pwrdn Power Down Pin

19 GND Analog Ground

20 GND Analog Ground

21 LpBy Positive Ladder Bypass

22 NC No Connection

24 IN Complementary Input

25 LnBy Negative Ladder Bypass

26 CM Common-Mode Voltage Output

27 IN Analog Input

SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 50 100 µsn s tL Clock Pulse Low 24 25 ns tH Clock Pulse High 24 25 ns tD Aperture Delay 2 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12 ns +VS LVDD LSB Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 MSB Bit 1 GND GND S IN CM LnBy IN REF NC LpBy GND GND S Pwrdn OE CLK ADS900

Frequency (MHz) –20 –40 –60 –80 –100 024 8 61 0 Magnitude (dBFS) f1 = 3.5MHz at –7dBFS f2 = 3.4MHz at –7dBFS SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 9MHz SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 3MHz SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 500kHz 0 256 512 768 1024 DIFFERENTIAL LINEARITY ERROR Output Code 2.0 1.0 0.0 –1.0 –2.0 Error (LSB) fIN = 10MHz DIFFERENTIAL LINEARITY ERROR Output Code 2.0 1.0 0.0 –1.0 –2.0 0 256 512 768 1024 DLE (LSB) fIN = 500kHz TYPICAL CHARACTERISTICS At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified.

UNDERSAMPLING (With Differential Input) Frequency (MHz) –20 –40 –60 –80 –100 –120 02468 Amplitude (dB) fIN = 20MHz fS = 16MHz INTEGRAL LINEARITY ERROR Output Code 10.0 5.0 –5.0 –10.0 0 200 400 600 800 1000 ILE (LSB) fIN = 500kHz TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. SWEPT POWER SFDR Input Amplitude SFDR (dBFS, dBc) dBFS dBc DYNAMIC PERFORMANCE vs INPUT FREQUENCY Frequency (MHz) 0.1 1 10 100 SFDR, SNR (dB) SFDR SNR DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE Temperature (°C) 0.8 0.7 0.6 0.5 –50 0 25–25 50 75 100 DLE (LSBs) fIN = 500kHz fIN = 10MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE Temperature (°C) –50 0 25–25 50 75 100 SFDR (dBFS) fIN = 500kHz fIN = 10MHz

TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. GAIN ERROR vs TEMPERATURE Temperature (°C) 6.5 6.0 5.5 5.0 4.5 –50 0 25–25 50 75 100 Gain (%FSR) OFFSET ERROR vs TEMPERATURE Temperature (°C) –25 –30 –35 –40 –45 –50 0 25–25 50 75 100 Offset Error (mV) POWER DISSIPATION vs TEMPERATURE Temperature (°C) –50 0 25–25 50 75 100 Power (mW) OUTPUT NOISE HISTOGRAM (DC Input) Output Code 500 400 300 200 100 N-3 N-1 NN-2 N+1 N+2 N+3 Counts SIGNAL-TO-NOISE RATIO (SNR) vs TEMPERATURE Temperature (°C) 02 5–25–50 50 75 100 SNR (dB) fIN = 10MHz fIN = 500kHz

offset adjustment can be accomplished. should be limited to approximately 1mA. and no bypassing components are required. advanced CMOS logic should be used (HC/HCT, AC/ACT). noise and degrading the performance. FIGURE 7. Internal Reference Structure and Recommended Reference Bypassing.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS900E Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS900E ADS900E.B Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS900E ADS900E/1K Active Production SSOP (DB) | 28 1000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 ADS900E ADS900E/1K.B Active Production SSOP (DB) | 28 1000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 ADS900E ADS900EG4.B Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS900E (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADS900E DB SSOP 28 50 530 10.5 4000 4.1 ADS900E.B DB SSOP 28 50 530 10.5 4000 4.1 ADS900EG4.B DB SSOP 28 50 530 10.5 4000 4.1 Pack Materials-Page 1

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated