ADS900

ADS900 BURR-BROWN | Alldatasheet

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Technical content

© 1997 Burr-Brown Corporation PDS-1347B Printed in U.S.A. January, 1997 Pipeline A/D Internal Reference Timing Circuitry Error Correction 3-State OutputsT/H 10-Bit Digital Data CLK ADS900 LVDD OEPwrdn1VREFLnByCMLpBy IN IN (Opt.) ADS900

FEATURES

l +2.7V TO +3.7V SUPPLY OPERATION l INTERNAL REFERENCE l LOW POWER: 52mW at +3V l SINGLE-ENDED INPUT RANGE: 1V to 2V l WIDEBAND TRACK/HOLD: 350MHz l 28-LEAD SSOP PACKAGE

DESCRIPTION

The ADS900 is a high speed pipelined analog-to- digital converter. This complete converter includes a high bandwidth track/hold, a 10-bit quantizer and an internal reference. The ADS900 employs digital error correction tech- niques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. This high performance A/D converter is specified for performance at a 20MHz sampling rate. The ADS900 is available in a 28-lead SSOP package. 10-Bit, 20MHz, +3V Supply ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

l PORTABLE INSTRUMENTATION l IF AND BASEBAND COMMUNICATIONS l CABLE MODEMS l SET-TOP BOXES l PORTABLE TEST EQUIPMENT l COMPUTER SCANNERS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ADS900E TM

At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ADS900E PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS Resolution 10 Bits Specified Temperature Range Ambient Air –40 +85 °C ANALOG INPUT Single-Ended Full Scale Input Range (1Vp-p) 1.0 to 2.0 V Differential Full Scale Input Range (0.5Vp-pX 2) 1.25 to 1.75 V Common-Mode Voltage 1.5 V Analog Input Bias Current 1 µA Input Impedance 1.25 || 5 M Ω || pF Analog Input Bandwidth Small Signal –20dBFS Input +25 °C 350 MHz Full Power 0dBFS Input +25 °C 100 MHz DIGITAL INPUTS Full Logic Family TTL/HCT COMPATIBLE CMOS High Input Voltage, VIH 2.0 V DD V Low Input Voltage, VIL 0.8 V High Input Current, IIH ±10 µA Low Input Current, IIL ±10 µA Input Capacitance 5p F CONVERSION CHARACTERISTICS Start Conversion RISING EDGE OF CONVERT CLOCK Sample Rate Full 10k 20M Samples/s Data Latency 5 Clk Cyc DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz (Largest Code Error) Full ±0.7 ±1.0 LSBs f = 10MHz (Largest Code Error) Full ±0.7 ±1.0 LSBs No Missing Codes Full Guaranteed Integral Nonlinearity Error, f = 500kHz Full ±3.5 LSBs Spurious Free Dynamic Range(1) f = 500kHz (–1dBFS(2) input) Full 47 53 dBFS (2) f = 10MHz (–1dBFS(2) input) Full 47 53 dBFS Two-Tone Intermodulation Distortion(3) f = 4.5MHz and 5.0MHz (–7dBFS each tone) +25 °C 50 dBc Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) Full 45 49 dB f = 10MHz (–1dBFS input) Full 45 49 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) Full 44 48 dB f = 3.58MHz (–1dBFS input) Full 44 48 dB f = 10MHz (–1dBFS input) Full 44 48 dB Differential Gain Error NTSC, PAL 2.3 % Differential Phase Error NTSC, PAL 1 degrees Output Noise Input Grounded 0.2 LSBs rms Aperture Delay Time 2n s Aperture Jitter 7 ps rms Overvoltage Recovery Time (4) 1.5X FS Input +25 °C2 n s DIGITAL OUTPUTS C L = 15pF Logic Family TTL/HCT COMPATIBLE CMOS Logic Coding Straight Offset Binary High Output Voltage, VOH +2.4 LV DD V Low Output Voltage, VOL +0.4 V 3-State Enable Time OE = L 20 40 ns 3-State Disable Time OE = H 2 10 ns Internal Pull-Down 50 k Ω Power-Down Enable Time PwrDn = L 133 ns Power-Down Disable Time PwrDn = H 18 ns Internal Pull-Down 50 k Ω

Gain Error +25°C8 ±10 %FS Input Offset Referred to Ideal Midscale Full 15 ±60 mV Power Supply Rejection (Gain) Δ VS = +10% Full 42 55 dB Power Supply Rejection (Offset) Full 42 62 dB Internal Positive Reference Voltage Full +1.75 V Internal Negative Reference Voltage Full +1.25 V POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Operating Full +2.7 +3 +3.7 V Supply Current: +IS Operating Full 18 22 mA Power Dissipation Operating, +3V Full 54 66 mW 25°C5 2 m W Power Dissipation (Power Down) +3V Full 10 mW Thermal Resistance, θJA 28-Lead SSOP 50 °C/W NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) No rollover of bits. SPECIFICATIONS (CONT) At TA = +25°C, VS = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. ADS900E PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER (1) RANGE ADS900E 28-Lead SSOP 324 –40 °C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS

5 Clock Cycles

N–5 N–4 N–3 N–2 N–1 N N+1 N+2Data Out Clock Analog In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 PIN CONFIGURATION PIN DESIGNATOR DESCRIPTION 1+ V S Analog Supply 2L V DD Output Logic Driver Supply Voltage

3 Bit 10 Data Bit 10 (D0) (LSB)

4 Bit 9 Data Bit 9 (D1)

5 Bit 8 Data Bit 8 (D2)

6 Bit 7 Data Bit 7 (D3)

7 Bit 6 Data Bit 6 (D4)

8 Bit 5 Data Bit 5 (D5)

9 Bit 4 Data Bit 4 (D6)

10 Bit 3 Data Bit 3 (D7)

11 Bit 2 Data Bit 2 (D8)

12 Bit 1 Data Bit 1 (D9) (MSB)

13 GND Analog Ground

14 GND Analog Ground

15 CLK Convert Clock Input

16 OE Output Enable, Active Low

17 Pwrdn Power Down Pin

19 GND Analog Ground

20 GND Analog Ground

21 LpBy Positive Ladder Bypass

22 NC No Connection

23 1V REF 1V Reference Output

24 IN Complementary Input

25 LnBy Negative Ladder Bypass

26 CM Common-Mode Voltage Output

27 IN Analog Input

SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 50 100 µsn s tL Clock Pulse Low 24 25 ns tH Clock Pulse High 24 25 ns tD Aperture Delay 2 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12 ns +VS LVDD LSB Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 MSB Bit 1 GND GND S IN CM LnBy IN REF NC LpBy GND GND S Pwrdn OE CLK ADS900

Frequency (MHz) –20 –40 –60 –80 –100 024 8 61 0 Magnitude (dBFS) f1 = 3.5MHz at –7dBFS f2 = 3.4MHz at –7dBFS SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 9MHz SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 3MHz SPECTRAL PERFORMANCE Frequency (MHz) –20 –40 –60 –80 –100 02468 1 0 Amplitude (dB) fIN = 500kHz 0 256 512 768 1024 DIFFERENTIAL LINEARITY ERROR Output Code 2.0 1.0 0.0 –1.0 –2.0 Error (LSB) fIN = 10MHz DIFFERENTIAL LINEARITY ERROR Output Code 2.0 1.0 0.0 –1.0 –2.0 0 256 512 768 1024 DLE (LSB) fIN = 500kHz TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified.

UNDERSAMPLING (With Differential Input) Frequency (MHz) –20 –40 –60 –80 –100 –120 02468 Amplitude (dB) fIN = 20MHz fS = 16MHz INTEGRAL LINEARITY ERROR Output Code 10.0 5.0 –5.0 –10.0 0 200 400 600 800 1000 ILE (LSB) fIN = 500kHz TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. SWEPT POWER SFDR Input Amplitude SFDR (dBFS, dBc) dBFS dBc DYNAMIC PERFORMANCE vs INPUT FREQUENCY Frequency (MHz) 0.1 1 10 100 SFDR, SNR (dB) SFDR SNR DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE Temperature (°C) 0.8 0.7 0.6 0.5 –50 0 25–25 50 75 100 DLE (LSBs) fIN = 500kHz fIN = 10MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE Temperature (°C) –50 0 25–25 50 75 100 SFDR (dBFS) fIN = 500kHz fIN = 10MHz

TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. GAIN ERROR vs TEMPERATURE Temperature (°C) 6.5 6.0 5.5 5.0 4.5 –50 0 25–25 50 75 100 Gain (%FSR) OFFSET ERROR vs TEMPERATURE Temperature (°C) –25 –30 –35 –40 –45 –50 0 25–25 50 75 100 Offset Error (mV) POWER DISSIPATION vs TEMPERATURE Temperature (°C) –50 0 25–25 50 75 100 Power (mW) OUTPUT NOISE HISTOGRAM (DC Input) Output Code 500 400 300 200 100 N-3 N-1 NN-2 N+1 N+2 N+3 Counts SIGNAL-TO-NOISE RATIO (SNR) vs TEMPERATURE Temperature (°C) 02 5–25–50 50 75 100 SNR (dB) fIN = 10MHz fIN = 500kHz

offset adjustment can be accomplished. should be limited to approximately 1mA. and no bypassing components are required. advanced CMOS logic should be used (HC/HCT, AC/ACT). frequency noise and degrading the performance. FIGURE 7. Internal Reference Structure and Recommended Reference Bypassing.