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Integrated, Quad RF Transceiver with Observation Path Data Sheet ADRV9029 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
4 differential transmitters 4 differential receivers 2 observation receivers with 2 inputs each Center frequency: 75 MHz to 6000 MHz Fully integrated DPD adaptation engine for power amplifier linearization Crest factor reduction engine Maximum receiver bandwidth: 200 MHz Maximum transmitter large signal bandwidth: 200 MHz Maximum transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated independent fractional-N radio frequency synthesizers Fully integrated clock synthesizer Multichip phase synchronization for all local oscillators and baseband clocks Support for TDD and FDD applications
24.33 Gbps JESD204B/JESD204C digital interface
APPLICATIONS
3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations GENERAL DESCRIPTION The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital- to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors. The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9029 is powered directly from 1.0 V, 1.3 V, and
1.8 V regulators and is controlled via a standard serial
peripheral interface (SPI) serial port. Comprehensive power- down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm × 14 mm, 289-ball chip scale ball grid array (CSP_BGA).
Rev. 0 | Page 2 of 133 TABLE OF CONTENTS Synthesizers, Auxiliary Converters, and Clock References .. 11
REVISION HISTORY
12/2020—Revision 0: Initial Version
Rev. 0 | Page 3 of 133 FUNCTIONAL BLOCK DIAGRAM SERDOUTA± SERDOUTB± SYNCOUT1± SYNCOUT2± ORX_CTRL_x RXx_EN GPINT2 GPINT1 TXx_EN RESET TEST_EN SPI_DIO SPI_DO SPI_EN SPI_CLK SYSREF± DEVCLK± GPIO_x AUXADC_x GPIO_ANA_x JESD204B/ JESD204C SERIAL INTERFACE RX1+ RX1– RX2+ RX2– RX3+ RX3– RX4+ RX4– ADC ADC Rx1 Rx2 RX1, RX2, TX1, TX2, ORX1/ORX2 RX3, RX4, TX3, TX4, ORX3/ORX4 90° MUX LO 1 LO 2 MUX LO 1 LO 2 MUX LO 3 DECIMATION, pFIR, AGC, DC-OFFSET, QEC, TUNING, RSSI, OVERLOAD TX1+ TX1– TX2+ TX2– TX3+ TX3– TX4+ TX4– DAC DAC Tx1 Tx2 pFIR, LO LEAKAGE, QEC, TUNING, INTERPOLATION CFR DPD ORX1+ ORX1– ORX2+ ORX2– ORX3+ ORX3– ORX4+ ORX4– VIF VDIG_1P0 EXT_LO1± EXT_LO2± VDDA_1P32 VDDA_1P03 VDDA_1P81 ADC ADC ORx1/ORx2 DECIMATION, pFIR, DC-OFFSET, QEC, TUNING, OVERLOAD POWER MANAGEMENT CLOCK GENERATION AND SYNCHRONIZATION GPIO AUXILIARY ADC AUXILIARY DAC SPI PORT CONTROL INTERFACE RF SYNTHESIZER LO 3 MICROPROCESSOR SERDOUTC± SERDOUTD± SYNCIN1± SYNCIN2± SYNCIN3± SERDINA± SERDINB± SERDINC± SERDIND± RF SYNTHESIZER RF SYNTHESIZER LO 1 LO 2 1VDDA_1P8 REPRESENTS VCONV1_1P8, VCONV2_1P8, VANA1_1P8, VANA2_1P8, VANA3_1P8, VANA4_1P8, AND VJVCO_1P8. 2VDDA_1P3 REPRESENTS VANA1_1P3, VANA2_1P3, VCONV1_1P3, VCONV2_1P3, VRFVCO1_1P3, VRFVCO2_1P3, VAUXVCO_1P3, VCLKVCO_1P3, VRFSYN1_1P3, VRFSYN2_1P3, VCLKSYN_1P3, VAUXSYN_1P3, VRXLO_1P3, AND VTXLO_1P3. 3VDDA_1P0 REPRESENTS VJSYN_1P0, VDES_1P0, VTT_DES, AND VSER_1P0. 90° 90° ADRV9029 25607-001 Figure 1.
Rev. 0 | Page 4 of 133 SPECIFICATIONS Electrical characteristics at ambient temperature range. Power supplies are as follows: VDDA_1P8 = 1.8 V, VIF = 1.8 V, VDDA_1P3 = 1.3 V, VDDA_1P0 = 1.0 V, and VDIG_1P0 = 1.0 V. VDDA_1P8 represents VCONV1_1P8, VCONV2_1P8, VANA1_1P8, VANA2_1P8, VANA3_1P8, VANA4_1P8, and VJVCO_1P8. VDDA_1P3 represents VANA1_1P3, VANA2_1P3, VCONV1_1P3, VCONV2_1P3, VRFVCO1_1P3, VRFVCO2_1P3, VAUXVCO_1P3, VCLKVCO_1P3, VRFSYN1_1P3, VRFSYN2_1P3, VCLKSYN_1P3, VAUXSYN_1P3, VRXLO_1P3, and VTXLO_1P3. VDDA_1P0 represents VJSYN_1P0, VDES_1P0, VTT_DES, and VSER_1P0. All RF specifications are based on measurements that include printed circuit board (PCB) and matching circuit losses, unless otherwise noted. Device configuration profile: Receiver = 200 MHz bandwidth, I/Q rate = 245.76 MHz, transmitter = 200 MHz large signal bandwidth plus 450 MHz synthesis bandwidth, I/Q rate = 491.52 MHz, observation receiver (ORX) = 450 MHz bandwidth, I/Q rate = 491.52 MHz, device clock = 245.76 MHz, unless otherwise noted. Characterization at 75 MHz followed this profile: Receiver = 62.5 MHz bandwi dth, I/Q rate = 76.8 MHz, transmitter = 62.5 MHz large signal bandwidth plus 141 MHz synthesis bandwidth, I/Q rate = 153.6 MHz, observation receiver = 141 MHz bandwidth, I/Q rate = 153.6 MHz, device clock = 153.6 MHz. Note: if signals are placed outside of the primary bandwidth, degradation in linearity, image rejection, and flatness may be observed. TRANSMITTERS AND RECEIVERS Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments TRANSMITTERS Tx Center Frequency 75 6000 MHz Tx Synthesis Bandwidth 450 MHz Tx Large Signal Bandwidth 200 MHz Zero intermediate frequency (IF) mode Peak-to-Peak Gain Deviation 1.0 dB 450 MHz bandwidth, includes compensation by programmable finite impulse response (FIR) filter 0.1 dB Any 20 MHz bandwidth span, includes compensation by programmable FIR filter (pFIR) Deviation from Linear Phase 1 Degrees 450 MHz bandwidth Maximum Output Power 0 dBFS, 1 MHz signal input, 50 Ω load, 0 dB transmitter attenuation 75 MHz 7.0 dBm 800 MHz 6.7 dBm 1800 MHz 6.6 dBm 2600 MHz 6.3 dBm 3800 MHz 6.4 dBm 4800 MHz 6.1 dBm 5700 MHz 6.4 dBm Power Control Range 32 dB Power Control Resolution 0.05 dB Attenuation Accuracy Integral Nonlinearity (Gain) INL 0.1 dB Valid over full power control range for any 4 dB step Differential Nonlinearity (Gain) DNL ±0.04 dB Monotonic Output Power Temperature Slope −4.5 mdB/°C Valid over full power control range LO Delay Temperature Slope 1.05 ps/°C Valid over full power control range Adjacent Channel Leakage Power Ratio (ACLR) Long Term Evolution (LTE)
20 MHz LTE at −12 dBFS
75 MHz −64 dB
800 MHz −68 dB
1800 MHz −67 dB
2600 MHz −66 dB
3800 MHz −65 dB
4800 MHz −65 dB
5700 MHz −65 dB
Rev. 0 | Page 5 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments In Band Noise Floor −154.5 dBFS/Hz 0 dB attenuation; in band noise falls 1 dB for each decibel of attenuation for attenuation settings between 0 dB and 20 dB Interpolation Images −76 dBc Tx to Tx Isolation: All Tx Output Effects on All Other Tx Outputs
800 MHz 78 dB
2600 MHz 77 dB
3800 MHz 71 dB
4800 MHz 70 dB
5700 MHz 65 dB
Within 200 MHz Large Signal Bandwidth QEC active up to 20 dB of attenuation, continuous wave tone swept across the large signal bandwidth
75 MHz 80 dB
800 MHz 76 dB
1800 MHz 75 dB
2600 MHz 73 dB
3800 MHz 65 dB
4800 MHz 64 dB
5700 MHz 61 dB
Assumes that distortion power density is 25 dB below desired power density
800 MHz 40 dB
1800 MHz 38 dB
2600 MHz 34 dB
3800 MHz 37 dB
4800 MHz 37 dB
5700 MHz 37 dB
Output Impedance ZOUT 50 Ω Differential—nominal Maximum Output Load Voltage Standing Wave Ratio VSWR 3 Maximum value to ensure adequate calibration Output Return Loss 10 dB Output Third-Order Intercept Point OIP3 0 dB transmitter attenuation
75 MHz 30 dBm
800 MHz 29 dBm
1800 MHz 29 dBm
2600 MHz 28 dBm
3800 MHz 26.5 dBm
4800 MHz 29 dBm
5700 MHz 27 dBm
Carrier Leakage With LO leakage correction active, 0 dB transmitter attenuation, scales decibel for decibel with attenuation Carrier Offset from LO
75 MHz LO −84 dBFS/MHz
800 MHz LO −84 dBFS/MHz
1800 MHz LO −84 dBFS/MHz
2600 MHz LO −83 dBFS/MHz
3800 MHz LO −84 dBFS/MHz
4800 MHz LO −84 dBFS/MHz
5700 MHz LO −83 dBFS/MHz
Rev. 0 | Page 6 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Carrier on the LO −71 dBFS/MHz Measured using an LTE 20 MHz signal Error Vector Magnitude EVM PLL optimized for narrow-band noise, measured using LTE 20 MHz signal 75 MHz LO 0.25 % 50 kHz PLL bandwidth 800 MHz LO 0.38 % 50 kHz PLL bandwidth 1800 MHz LO 0.60 % 50 kHz PLL bandwidth 2600 MHz LO 0.44 % 500 kHz PLL bandwidth 3800 MHz LO 0.53 % 200 kHz PLL bandwidth 4800 MHz LO 0.63 % 400 kHz PLL bandwidth 5700 MHz LO 0.84 % 500 kHz PLL bandwidth Transmitter Time Division Duplex TDD Time from SPI_EN Going High to Change in Tx Attenuation tSCH 12 ns Time Between Consecutive Microattenuation Steps tACH 20 ns A large change in attenuation can be segmented into a series of smaller attenuation changes Attenuation Overshoot During Transition 0.1 dB Change in Attenuation per Microstep 0.1 dB RECEIVERS Rx Center Frequency 75 6000 MHz Gain Range 30 dB Attenuation Accuracy Analog Gain Step 0.5 dB Attenuator steps from 0 dB to 6 dB 1 dB Attenuator steps from 6 dB to 30 dB Residual Gain Step Error 0.1 dB Gain Temperature Slope −6.4 mdB/°C Internal LO Delay Temperature Slope 1.0 ps/°C Frequency Response Peak-to-Peak Gain Deviation 1 dB 200 MHz bandwidth, includes compensation by programmable FIR filter 0.2 dB Any 20 MHz span, includes compensation by programmable FIR filter Rx Bandwidth 200 MHz Zero IF mode Rx Alias Band Rejection 80 dB Due to digital filters Maximum Useable Input Level P HIGH This continuous wave signal level corresponds to the input power that produces −2 dBFS at the digital output with 0 dB channel attenuation 75 MHz −11.7 dBm 800 MHz −12.4 dBm 1800 MHz −12.7 dBm 2600 MHz −11.9 dBm 3800 MHz −11.0 dBm 4800 MHz −12.0 dBm 5700 MHz −11.1 dBm Maximum Source VSWR 3 Input Impedance ZIN 100 Ω Differential Input Port/Return Loss 10 dB Unmatched differential port return loss
Rev. 0 | Page 7 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Noise Figure NF 0 dB receiver attenuation, measured at single- ended input, matching circuit included
75 MHz 12 dB
800 MHz 11 dB
1800 MHz 11.5 dB 2600 MHz 11.9 dB 3800 MHz 12.8 dB 4800 MHz 13.3 dB 5700 MHz 14.5 dB Noise Figure Ripple 1.5 dB At band edge Second-Order Input Intermodulation Intercept Point IIP2 0 dB attenuation, complex
75 MHz 70 dBm
800 MHz 65 dBm
1800 MHz 65 dBm
2600 MHz 65 dBm
3800 MHz 62 dBm
4800 MHz 62 dBm
5700 MHz 58 dBm
Wideband Third-Order Input Intermodulation Intercept Point, Difference Product IIP3 WB_DIFF Two tones near the band edge, test condition: P HIGH − 9 dB/tone
75 MHz 14 dBm
800 MHz 15 dBm
1800 MHz 17 dBm
2600 MHz 17 dBm
3800 MHz 17 dBm
4800 MHz 17 dBm
5700 MHz 18 dBm
Intermodulation Intercept Point, Difference Product IIP3 MB_DIFF Two tones near the middle of the band; test condition: P HIGH − 9 dB/tone
75 MHz 20 dBm
800 MHz 18 dBm
1800 MHz 22 dBm
2600 MHz 21 dBm
3800 MHz 22 dBm
4800 MHz 22 dBm
5700 MHz 20 dBm
Wideband Third-Order Input Intermodulation Intercept Point, Sum Product IIP3 WB_SUM Two tones approximately bandwidth ÷ 6 offset from the LO; test condition: P HIGH – 9 dB/tone
75 MHz 15 dBm
800 MHz 17 dBm
2600 MHz 20 dBm
3800 MHz 23 dBm
4800 MHz 23 dBm
Maximum Input HD2MAX −72 dBc PHIGH continuous wave signal, harmonic distortion tones falling within 100 MHz of the LO Recommended Input HD2 −75 dBc PHIGH − 3 dB continuous wave signal, harmonic distortion tones falling within 100 MHz of the LO
Rev. 0 | Page 8 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Third-Order Harmonic Distortion Maximum Input HD3MAX −66 dBc PHIGH continuous wave signal, harmonic distortion tones falling within 100 MHz of the LO Recommended Input HD3 −72 dBc PHIGH − 3 dB continuous wave signal, harmonic distortion tones falling within 100 MHz of the LO Fourth-Order Harmonic Distortion Maximum Input HD4MAX −90 dBc PHIGH continuous wave signal, harmonic distortion tones falling within 100 MHz of the LO Recommended Input HD4 −90 dBc PHIGH − 3 dB continous wave signal, harmonic distortion tones falling within 100 MHz of the LO Fifth-Order Harmonic Distortion Maximum Input HD5MAX −87 dBc PHIGH continuous wave signal, harmonic distortion tones falling within 100 MHz of the LO Recommended Input HD5 −90 dBc PHIGH − 3 dB continuous wave signal, harmonic distortion tones falling within 100 MHz of the LO Image Rejection 75 dB QEC active, within 200 MHz receiver bandwidth Rx to Rx Signal Isolation
800 MHz 75 dB
1800 MHz 70 dB
2600 MHz 70 dB
4800 MHz 62 dB
5700 MHz 60 dB
Rx Band Spurs Referenced to RF Input at Maximum Gain −95 dBm No more than one spur at this level per 10 MHz of receiver bandwidth; excludes harmonics of the reference clock Spurious-Free Dynamic Range SFDR 81 dBc PHIGH continuous wave signal anywhere inside the band ±20 MHz, excludes harmonic distortion products Rx Input LO Leakage at Maximum Gain Leakage decreased decibel for decibel with attenuation for first 12 decibels
75 MHz −68 dBm
800 MHz −68 dBm
1800 MHz −68 dBm
2600 MHz −65 dBm
3800 MHz −65 dBm
4800 MHz −58 dBm
5700 MHz −54 dBm
Tx to Rx Signal Isolation: All Tx Output Effects on all Rx Inputs
800 MHz 80 dB
2600 MHz 75 dB
4800 MHz 65 dB
Center Frequency 75 6000 MHz Gain Range 30 dB Attenuation Accuracy Analog Gain Step 0.5 dB Attenuator steps from 0 dB to 6 dB 1 dB Attenuator steps from 6 dB to 30 dB
Rev. 0 | Page 9 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Peak-to-Peak Gain Deviation 1 dB 450 MHz RF bandwidth, compensation by programmable FIR filter 0.1 dB Any 20 MHz bandwidth span, compensation by programmable FIR filter Deviation from Linear Phase 1 Degrees 450 MHz RF bandwidth ORx Bandwidth 450 MHz ORx Alias Band Rejection 60 dB Due to digital filters Maximum Useable Input Level P HIGH This continuous wave signal level corresponds to the input power that produces −2 dBFS at the digital output with 0 dB channel attenuation 75 MHz −11.4 dBm 800 MHz −12.7 dBm 1800 MHz −11.5 dBm 2600 MHz −10.6 dBm 3800 MHz −12.0 dBm 4800 MHz −11.3 dBm 5700 MHz −9.5 dBm Input Impedance ZIN 100 Ω Differential Input Source VSWR 3 Input Port Return Loss 10 dB Unmatched differential port return loss Integrated Noise 450 MHz Bandwidth −58.5 dBFS Sample rate at maximum value integrated from 500 kHz to 225 MHz, no input signal 491.52 MHz Bandwidth (Nyquist) −57.5 dBFS Sample rate at maximum value integrated from 500 kHz to 245.76 MHz, no input signal Second-Order Input Intermodu- lation Intercept Point IIP2 Maximum observation receiver gain; test condition: PHIGH − 11 dB/tone
75 MHz 55 dBm
800 MHz 55 dBm
1800 MHz 53 dBm
2600 MHz 55 dBm
3800 MHz 48 dBm
4800 MHz 45 dBm
5700 MHz 55 dBm
Third-Order Input Intermodulation Intercept Point IIP3 Maximum observation receiver gain; test condition: PHIGH − 11 dB/tone Narrow Band IIP3NB IM3 product < 130 MHz at baseband; test condition: P HIGH − 11 dB/tone, 491.52 MSPS
75 MHz 11 dBm
800 MHz 13.6 dBm
1800 MHz 15 dBm
2600 MHz 16.5 dBm
3800 MHz 18 dBm
4800 MHz 18 dBm
Wide Band IIP3WB IM3 products > 130 MHz at baseband; test condition: P HIGH −11 dB/tone, 491.52 MSPS 800 MHz 7.8 dBm
1800 MHz 13 dBm
2600 MHz 11 dBm
3800 MHz 13 dBm
4800 MHz 13 dBm
5700 MHz 14 dBm
Rev. 0 | Page 10 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Third-Order Intermodulation Product IM3 Narrow Band IM3NB IM3 product < 130 MHz at baseband; test condition: two tones, each at PHIGH − 11 dB,
491.52 MSPS
800 MHz −74 dBc
1800 MHz −79 dBc
2600 MHz −78.6 dBc 3800 MHz −80.4 dBc 4800 MHz −79.8 dBc
5700 MHz −76 dBc
Wide Band IM3WB IM3 product > 130 MHz at baseband; test condition: two tones, each at P HIGH − 11 dB, 800 MHz −62.4 dBc
1800 MHz −70 dBc
2600 MHz −67.6 dBc 3800 MHz −70.4 dBc 4800 MHz −69.8 dBc
5700 MHz −66 dBc
Fifth-Order Intermodulation Product IM5 Narrow Band IM5NB IM5 product < 130 MHz at baseband; test condition: two tones, each at P HIGH − 11 dB,
800 MHz −83 dBc
1800 MHz −87 dBc
2600 MHz −84 dBc
3800 MHz −80 dBc
4800 MHz −78 dBc
5700 MHz −81 dBc
Wide Band IM5WB IM5 product > 130 MHz at baseband; test condition:two tones, each at P HIGH − 11 dB,
1800 MHz −96 dBc
2600 MHz −85 dBc
4800 MHz −77 dBc
5700 MHz −85 dBc
Seventh-Order Intermodulation Product IM7 Narrow Band IM7NB IM7 product < 130 MHz at baseband; test condition: two tones, each at P HIGH − 11 dB,
1800 MHz −78 dBc
2600 MHz −75 dBc
3800 MHz −73 dBc
5700 MHz −75 dBc
Rev. 0 | Page 11 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Wide Band IM7WB IM7 product > 130 MHz at baseband; test condition: two tones, each at PHIGH − 11 dB,
1800 MHz −82 dBc
2600 MHz −83 dBc
3800 MHz −83 dBc
4800 MHz −85 dBc
Spurious-Free Dynamic Range SFDR 64 dB Nonintermodulation related spurs; does not in- clude harmonic distortion; input set at P HIGH − 8 dB Second-Order Harmonic Distortion HD2 Input set at PHIGH − 8 dB In Band −80 dBc In-band harmonic distortion falls within ±100 MHz Out of Band −73 dBc Out of band harmonic distortion falls within ±225 MHz Third-Order Harmonic Distortion HD3 Input set at PHIGH − 8 dB In Band −70 dBc Harmonic distortion falls within ±100 MHz Out of Band −65 dBc Harmonic distortion falls within ±225 MHz Image Rejection 75 dB After online tone calibration, QEC active Tx to ORx Signal Isolation: All Tx Output Effects on all ORx Inputs 75 dB SYNTHESIZERS, AUXILIARY CONVERTERS, AND CLOCK REFERENCES Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments LO1 and LO2 SYNTHESIZER LO1, LO2 Frequency Step 7.3 Hz 1.6 GHz to 3.2 GHz, 245.76 MHz phase frequency detector (PFD) frequency Spectral Purity −80 dBc Integrated Phase Noise Integrated from 1 kHz to 100 MHz Narrow Bandwidth Optimized PLL bandwidth optimized to minimize phase noise at offsets > 200 kHz 800 MHz 0.12 °rms 1800 MHz 0.27 °rms 2600 MHz 0.66 °rms 3800 MHz 0.53 °rms 4800 MHz 0.91 °rms 5700 MHz 1.57 °rms Wide Bandwidth Optimized PLL bandwidth optimized for integrated phase noise and phase noise at offsets > 1 MHz and phase noise at offsets > 1 MHz 800 MHz 0.07 °rms 1800 MHz 0.11 °rms 2600 MHz 0.17 °rms 3800 MHz 0.26 °rms 4800 MHz 0.30 °rms 5700 MHz 0.42 °rms Spot Phase Noise: Narrow Band PLL bandwidth optimized to minimize phase noise at offsets > 200 kHz
800 MHz LO1 and LO2
100 kHz Offset −115 dBc/Hz
1 MHz Offset −141 dBc/Hz
10 MHz Offset −162 dBc/Hz
Rev. 0 | Page 12 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
1800 MHz LO1 and LO2
100 kHz Offset −107 dBc/Hz 200 kHz Offset −115 dBc/Hz 400 kHz Offset −123 dBc/Hz 600 kHz Offset −128 dBc/Hz 800 kHz Offset −131 dBc/Hz
1.2 MHz Offset −136 dBc/Hz
1.8 MHz Offset −140 dBc/Hz
6 MHz Offset −151 dBc/Hz
10 MHz Offset −156 dBc/Hz
2600 MHz LO1 and LO2
100 kHz Offset −97 dBc/Hz
1 MHz Offset −124 dBc/Hz
10 MHz Offset −150 dBc/Hz
3800 MHz LO1 and LO2
100 kHz Offset −100 dBc/Hz
1 MHz Offset −126 dBc/Hz
10 MHz Offset −149 dBc/Hz
4800 MHz LO1 and LO2
100 kHz Offset −94 dBc/Hz
1 MHz Offset −120 dBc/Hz
10 MHz Offset −145 dBc/Hz
5700 MHz LO1 and LO2
100 kHz Offset −89 dBc/Hz
1 MHz Offset −115 dBc/Hz
10 MHz Offset −141 dBc/Hz
Spot Phase Noise: Wideband PLL bandwidth optimized for integrated phase noise and phase noise at offsets > 1 MHz 100 kHz Offset −114 dBc/Hz 100 kHz Offset −112 dBc/Hz
1 MHz Offset −133 dBc/Hz
100 kHz Offset −112 dBc/Hz
3800 MHz LO
100 kHz Offset −104 dBc/Hz
1 MHz Offset −125 dBc/Hz
100 kHz Offset −106 dBc/Hz
1 MHz Offset −117 dBc/Hz
10 MHz Offset −144 dBc/Hz
100 kHz Offset −104 dBc/Hz
1 MHz Offset −112 dBc/Hz
10 MHz Offset −140 dBc/Hz
Rev. 0 | Page 13 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments AUXILIARY SYNTHESIZER LO3 Frequency Step 1.8 Hz 1.625 GHz to 3.25 GHz, 61.44 MHz PFD frequency Spectral Purity −65 dBc |f RFLO − fAUXLO| > 15 MHz Integrated Phase Noise Integrated from 1 kHz to 100 MHz, PLL bandwidth optimized for integrated phase noise 800 MHz LO3 0.18 °rms 1800 MHz LO3 0.22 °rms 2600 MHz LO3 0.46 °rms 3800 MHz LO3 0.43 °rms 4800 MHz LO3 0.70 °rms 5700 MHz LO3 1.12 °rms Spot Phase Noise
800 MHz LO3
100 kHz Offset −112 dBc/Hz
1 MHz Offset −121 dBc/Hz
1800 MHz LO3
100 kHz Offset −110 dBc/Hz
10 MHz Offset −134 dBc/Hz
2600 MHz LO3
100 kHz Offset −103 dBc/Hz
1 MHz Offset −114 dBc/Hz
10 MHz Offset −132 dBc/Hz
3800 MHz LO3
100 kHz Offset −104 dBc/Hz
10 MHz Offset −128 dBc/Hz
4800 MHz LO3
100 kHz Offset −100 dBc/Hz
1 MHz Offset −110 dBc/Hz
10 MHz Offset −127 dBc/Hz
5700 MHz LO3
100 kHz Offset −95 dBc/Hz
1 MHz Offset −106 dBc/Hz
10 MHz Offset −126 dBc/Hz
Initial Phase Sync Accuracy 0.9 ps CLOCK SYNTHESIZER
4915.2 MHz Sample Clock
Integrated Phase Noise 0.69 °rms 1 kHz to 10 MHz, PLL bandwidth optimized for integrated phase noise Spot Phase Noise PLL bandwidth optimized for integrated phase noise 100 kHz Offset −96 dBc/Hz
1 MHz Offset −113 dBc/Hz
3932.16 MHz Sample Clock
Integrated Phase Noise 0.89 °rms 1 kHz to 10 MHz, PLL bandwidth optimized to minimize phase noise at offsets >200 kHz
Rev. 0 | Page 14 of 133 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Spot Phase Noise PLL bandwidth optimized to minimize phase noise at offsets >200 kHz 100 kHz Offset −91 dBc/Hz
10 MHz Offset −143 dBc/Hz
(DEV_CLK± INPUT SIGNAL) DEV_CLK+, DEV_CLK− Frequency Range 15 1000 MHz Signal Level (Differential) 0.2 1.0 V p-p AC-coupled, common-mode voltage internally supplied; for optimal spurious performance and to meet the specified PLL performance parameters, use a 1 V p-p input clock SYSTEM REFERENCE INPUTS SYSREF+, SYSREF− Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1800 mV p-p External 100 Ω differential termination Input Common-Mode Voltage 0.675 2.0 V Input Resistance (Differential) 18 kΩ Input Capacitance (Differential) 1 pF AUXILIARY CONVERTERS ADC Resolution 10 Bits Input Voltage Minimum 0.05 V Maximum 0.95 V AUXDAC_0 Resolution 12 Bits Output Voltage Minimum 0.2 V Maximum VDDA_1P8 − 0.25 V AUXDAC_1 To AUXDAC_7 Resolution 12 Bits Output Voltage Minimum 0.1 V Maximum VDDA_1P8 − 0.1 V Drive Capability 10 mA DIGITAL SPECIFICATIONS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL SPECIFICATIONS— SINGLE-ENDED SIGNALS Applies to the following pins: GPIO_x, GPINTx, TXx_EN, RXx_EN, ORX_CTRL_x, TEST_EN, RESET , SPI_EN, SPI_CLK, SPI_DO, and SPI_DIO Logic Inputs Input Voltage High Level VIF × 0.65 VIF + 0.18 V Low Level −0.30 VIF × 0.35 V
Table 4. Power Supply Voltages
Rev. 0 | Page 16 of 133 CURRENT CONSUMPTION In Table 5, Table 6, and Table 7, the first row contains the data for the UC13-NLS profile and subsequent rows provide UC13-NLS profile details. Note that all current measurements reported in Table 5, Table 6, and Table 7 are obtained at room temperature without a heat sink. TDD Operation—Four Receiver Channels Enabled Maximum gain and typical values. Table 5. Supply (A) Total Average Power (W) 75% Tx, 25% Rx Average Power (W) Profile Conditions 1.0 V 1.3 V 1.8 V
245.76 MSPS Tx/ORx Data Rate
122.88 MSPS Rx Data Rate
245.76 MHz Device Clock
TDD Operation—Four Transmitter and One Observation Receiver Channels Enabled Maximum gain, 0 dB attenuation, typical values. Table 6. Supply (A) Total Average Power (W) 75% Tx , 25% Rx Average Power (W) Profile Conditions 1.0 V 1.3 V 1.8 V FDD Operation—LO1 and LO2, Four Receiver, Four Transmitter, and One Observation Receiver Channels Enabled Maximum gain, 0 dB attenuation, typical values. Table 7. Supply (A) Total Average Power (W) Profile Conditions 1.0 V 1.3 V 1.8 V USE CASE UC13-NLS (16 BITS) 1.664 2.929 0.762 6.86
Rev. 0 | Page 17 of 133 DIGITAL INTERFACE AND TIMING SPECIFICATIONS Table 8. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SERIAL PERIPHERAL INTERFACE (SPI) TIMING SPI_CLK Period tCP 40 ns SPI_CLK Pulse Width tMP 10 ns SPI_EN Setup to First SPI_CLK Rising Edge tSC 4 ns Last SPI_CLK Falling Edge to SPI_EN Hold tHC 0 ns SPI_DIO Data Input Setup to SPI_CLK tS 4 ns SPI_DIO Data Input Hold to SPI_CLK tH 0 ns SPI_CLK Falling Edge to Output Data Delay tCO 10 8 ns 3- or 4-wire mode Bus Turnaround Time After Baseband Processor Drives Last Address Bit tHZM t H t CO ns Bus Turnaround Time After ADRV9029 Drives Last Address Bit tHZS 0 t CO ns DIGITAL TIMING TXx_EN Pulse Width 10 μs RXx_EN Pulse Width 10 μs ORX_CTRL_x Pulse Width 10 μs TXx_EN to Valid Data 2 μs RXx_EN to Valid Data 2 μs ORX_CTRL_x to Valid Data 3 μs JESD204B/JESD204C DATA OUTPUT TIMING Unit Interval UI 41.1 333 ps Data Rate per Channel (No Return to Zero (NRZ)) 3000 24330.24 Mbps Rise Time tR 17 20 ps 20% to 80% in 100 Ω load Fall Time tF 17 20 ps 20% to 80% in 100 Ω load Output Common-Mode Voltage VCM 0 1.8 V AC-coupled Differential Output Voltage VDIFF 475 1050 mV p-p Short-Circuit Current IDSHORT −100 +100 mA Differential Termination Impedance ZRDIFF 80 100 120 Ω SYSREF± Input Signal Setup Time to DEV_CLK± Input Signal tS 200 ps SYSREF± Input Signal Hold Time to DEV_CLK± Input Signal tH 200 ps JESD204B/C DATA INPUT TIMING Unit Interval UI 41.1 333 ps Data Rate per Channel (NRZ) 3000 24330.24 Mbps Input Common-Mode Voltage VCM 0.05 1.65 V AC-coupled Termination Voltage = 1.0 V VTT 720 1200 mV DC-coupled (not recommended) Differential Input Voltage VDIFF 110 1050 mV VTT Source Impedance ZTT 7.5 30 Ω Differential Termination Impedance ZRDIFF 80 100 120 Ω VTT AC-Coupled 0.95 1.05 V DC-Coupled 0.95 1.05 V
the Junction Temperature section for more details. operational section of this specification is not implied. extended periods may affect product reliability. AF is the acceleration factor. 100°C for 4.5 hours to offset the time operating above 110°C. Table 10. Acceleration Factors for High Temperature Operation Table 11. Maximum Input Power into RF Ports vs. Lifetime reflow temperature is 260°C. (PCB, heat sink, airflow, and so forth) improves thermal resistance. Table 12. Thermal Resistance Values
- NIC = NOT INTERNALLY CONNECTED. THESE PINS MUST REMAIN DISCONNECTED.
Figure 2. Pin Configuration
Table 13. Pin Function Descriptions unused, do not connect these pins. A7 VTXLO_1P3 I 1.3 V Supply Input. A9 VRXLO_1P3 I 1.3 V Supply Input. A13, A14 TX2+, TX2− O Differential Output for Transmitter Channel 2. When unused, do not connect. unused, connect these pins to VSSA. B4 VANA3_1P8 I 1.8 V Supply Input. B14 VANA2_1P8 I 1.8 V Supply Input. unused, connect these pins to VSSA. C6 VAUXSYN_1P3 I 1.3 V Supply Input. C8, C9 DEVCLK+, DEVCLK− I Device Clock Differential Input. C11 VAUXVCO_1P3 I 1.3 V Supply Input. Pin C15 and analog ground (VSSA). D3 VANA2_1P3 I 1.3 V Supply Input. D15 VANA1_1P3 I 1.3 V Supply Input. Channel 3. Connect to VSSA if unused. E7 TX3_EN I Enable Input for Transmitter Channel 3.
Rev. 0 | Page 21 of 133 Pin No. Mnemonic Type 1 Description H11, K11, N11, E10, F10, G10, H10, J10, K10, E9, F9, E8, F8, G8, H8, J8, K8, H7, K7 GPIO_0 to GPIO_18 I/O General-Purpose Digital Inputs and Outputs. See Figure 2 to match the ball location to the GPIO_x signal name. If unused, these pins can be connected to VSSA with a 10 kΩ resistor or configured as outputs, driven low, and left disconnected. E11 TX2_EN I Enable Input for Transmitter Channel 2. Connect to VSSA if unused. E13, E14 ORX1+, ORX1− I Differential Input for Observation Receiver Channel 1. Connect to VSSA if unused. E16, F16 EXT_LO1+, EXT_LO1− I/O Differential External LO Input/Output 1. If used for the external LO input, the input frequency must be 2× the desired carrier frequency. Do not connect if unused. External LO functionality not currently supported. E17 AUXADC_1 I Auxiliary ADC 1 Input. Do not connect if unused. F1 AUXADC_2 I Auxiliary ADC 2 Input. Do not connect if unused. F7, F11, L7, L11 ORX_CTRL_C, ORX_CTRL_B, ORX_CTRL_D, ORX_CTRL_A I Determine Active Observation Receiver Path. Connect to VSSA directly or with a pull-down resistor if unused. F17 AUXADC_0 I Auxiliary ADC 0 Input. Do not connect if unused. G3 VRFVCO2_1P3 I 1.3 V Supply Input. G5 VRFVCO2_1P0 O 1.0 V Internal Supply Node. Bypass this pin with a 4.7 μF capacitor. G7 RX3_EN I Enable Input for Receiver Channel 3. Connect to VSSA if unused. G9, J9, L9 VDIG_1P0 I 1.0 V Digital Supply Input. G11 RX2_EN I Enable Input for Receiver Channel 2. Connect to VSSA if unused. G13 VRFVCO1_1P0 O 1.0 V Internal Supply Node. Bypass this pin with a 4.7 μF capacitor. G15 VRFVCO1_1P3 I 1.3 V Supply Input. H1, J1 RX4−, RX4+ I Differential Input for Receiver Channel 4. If unused, connect to VSSA. H3 VCONV2_1P8 I 1.8 V Supply Input. H9, K9, M9 VSSD I Digital Ground. H15 VCONV1_1P8 I 1.8 V Supply Input. H17, J17 RX1+, RX1− I Differential Input for Receiver Channel 1. If unused, connect to VSSA. J3 VCONV2_1P3 I 1.3 V Supply Input. J5 VRFSYN2_1P3 I 1.3 V Supply Input. J7 RX4_EN I Enable Input for Receiver Channel 4. If unused, connect to VSSA. J11 RX1_EN I Enable Input for Receiver Channel 1. If unused, connect to VSSA. J13 VRFSYN1_1P3 I 1.3 V Supply Input. J15 VCONV1_1P3 I 1.3 V Supply Input. K3 VCONV2_1P0 O 1.0 V Internal Supply Node. Bypass this pin with a 4.7 μF capacitor. K15 VCONV1_1P0 O 1.0 V Internal Supply Node. Bypass this pin with a 4.7 μF capacitor. L4, L5 ORX4+, ORX4− I Differential Input for Observation Receiver Channel 4. If unused, connect to VSSA.
Rev. 0 | Page 22 of 133 Pin No. Mnemonic Type 1 Description L8 SPI_DIO I/O Serial Data Input. SPI_DIO is the serial data input in 4-wire mode or input/output in 3-wire mode. L10 SPI_EN I Serial Data Bus Chip Select. Active low. L13, L14 ORX2+, ORX2− I Differential Input for Observation Receiver Channel 2. If unused, connect to VSSA. M7 TX4_EN I Enable Input for Transmitter Channel 4. If unused, connect to VSSA. M8 SPI_DO O Serial Data Output. M10 SPI_CLK I Serial Data Bus Clock Input. M11 TX1_EN I Enable Input for Transmitter Channel 1. If unused, connect to VSSA. N1, P1 TX4−, TX4+ O Differential Output for Transmitter Channel 4. If unused, do not connect. N2 VANA4_1P8 I 1.8 V Supply Input. N5 VCLKVCO_1P3 I 1.3 V Supply Input. N6, P6 SYNCIN3+, SYNCIN3− I LVDS Sync Signal Input 3. If unused, connect to VSSA. N7 GPINT2 O General-Purpose Interrupt Output 2. If unused, do not connect. N8 GPINT1 O General-Purpose Interrupt Output 1. If unused, do not connect. N9 VIF I 1.8 V Interface Supply Input. N10 RESET I Active Low Chip Reset. N12, N13 SYNCIN1+, SYNCIN1− I LVDS Sync Signal Input 1. If unused, connect to VSSA. N14, N15 SYNCOUT2+, SYNCOUT2− O LVDS Sync Signal Output 2. If unused, do not connect. N16 VANA1_1P8 I 1.8 V Supply Input. N17, P17 TX1+, TX1− O Differential Output for Transmitter Channel 1. Do not connect if unused. P5 VCLKVCO_1P0 O 1.0 V Internal Supply Node. Bypass this pin with a 4.7 μF capacitor. P7, P8 SYNCIN2+, SYNCIN2− I LVDS Sync Signal Input 2. If unused, connect to VSSA. P10 TEST_EN I Test Input for JTAG Boundary Scan. Pull high to enable boundary scan. If unused, tie to VSSA. P11 VJVCO_1P8 I 1.8 V Supply Input. P12, P13 VDES_1P0 I 1.0 V Analog Supply Input. P14 VTT_DES I 1.0 V Analog Supply Input. P15, R15 SYNCOUT1+, SYNCOUT1− O LVDS Sync Signal Output 1. If unused, do not connect. R3, R4 VSER_1P0 I 1.0 V Analog Supply Input. R7 VCLKSYN_1P3 I 1.3 V Supply Input. R9 VJSYN_1P0 I 1.0 V Analog Supply Input. T3, T4 SERDOUTC+, SERDOUTC− O SERDES Differential Output C. If unused, do not connect. T7, T8 SERDOUTA+, SERDOUTA− O SERDES Differential Output A. If unused, do not connect. T10, T11 SERDINA−, SERDINA+ I SERDES Differential Input A. If unused, do not connect. T14, T15 SERDINC−, SERDINC+ I SERDES Differential Input C. If unused, do not connect. U1, U2 SERDOUTD+, SERDOUTD- O SERDES Differential Output D. If unused, do not connect. U5, U6 SERDOUTB+, SERDOUTB− O SERDES Differential Output B. If unused, do not connect.
Rev. 0 | Page 23 of 133 Pin No. Mnemonic Type 1 Description U12, U13 SERDINB+, SERDINB− I SERDES Differential Input B. If unused, do not connect. U16, U17 SERDIND+, SERDIND− I SERDES Differential Input D. If unused, do not connect. 1 I is input, O is output, I/O is input/output, and N/A is not applicable.
clock = 153.6 MHz, unless otherwise noted.
75 MHZ BAND
The temperature settings refer to the die temperature. All LO frequencies set to 75 MHz, unless otherwise noted. Figure 3. Transmitter Continuous Wave Output Power vs. Transmitter LO Figure 4. Transmitter Output Power Spectrum, Tx1, 5 MHz LTE,
10 MHz Offset, −10 dBFS RMS, 1 MHz Resolution Bandwidth, TJ = 25°C
Figure 5. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 6. Transmitter Noise vs. Transmitter Attenuation, 10 MHz Offset Figure 7. Transmitter Pass Band Flatness vs. Baseband Offset Frequency Figure 8. Adjacent Channel Power Level vs. Transmitter Attenuation, 21 MHz
Figure 9. Adjacent Channel Power Level vs. Transmitter Attenuation,
44 MHz Baseband Offset, 5 MHz LTE, PAR = 12 dB
Figure 10. Transmitter Second-Order Harmonic Distortion (HD2) vs. Figure 11. Transmitter Third-Order Harmonic Distortion (HD3) vs. Figure 12. Transmitter Attenuator Step Error vs. Transmitter Attenuation,
10 MHz Offset
Figure 13. Transmitter Error Vector Magnitude vs. Transmitter Attenuation, 5 Figure 14. Transmitter OIP3, 2f1 − f2 vs. Transmitter Attenuation, 15 dB
Figure 27. Receiver Gain Step Error vs. Receiver Attenuation,
10 MHz Offset, −5 dBFS Input Signal
Figure 28. Receiver Image vs. Baseband Offset Frequency, Figure 29. Receiver Image vs. Receiver Attenuation, 10 MHz Offset, Tracking Figure 30. Receiver DC Offset vs. Receiver Attenuation, 10 MHz Offset, Figure 31. Receiver DC Offset vs. Receiver LO Frequency, 10 MHz Offset, Figure 32. Receiver HD2, Left Side vs. Baseband Offset Frequency,
800 MHz BAND
The temperature settings refer to the die temperature. All LO frequencies set to 800 MHz, unless otherwise noted. Figure 76. Transmitter Continuous Wave Output Power vs. Transmitter LO Figure 77. Transmitter Output Power Spectrum, Tx1, 5 MHz LTE, Figure 78. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 79. Transmitter Noise vs. Transmitter Attenuation, 10 MHz Offset Figure 80. Transmitter Pass Band Flatness vs. Baseband Offset Frequency Figure 81. Adjacent Channel Power Level vs. Transmitter Attenuation,
Figure 82. Adjacent Channel Power Level vs. Transmitter Attenuation,
90 MHz Baseband Offset, 20 MHz LTE, PAR = 12 dB
Figure 83. Transmitter Second-Order Harmonic Distortion (HD2) vs. Figure 84. Transmitter Third-Order Harmonic Distortion (HD3) vs. Figure 85. Transmitter Attenuator Step Error vs. Transmitter Attenuation, Figure 86. Transmitter Error Vector Magnitude vs. Transmitter Attenuation, Figure 87. Transmitter OIP3, 2f1 − f2 vs. Transmitter Attenuation, 15 dB
Figure 100. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 101. Receiver LO Leakage vs. Receiver LO Frequency, Figure 102. Receiver Gain vs. Receiver Attenuation, 20 MHz Offset, 200 MHz Figure 103. Receiver Gain vs. Receiver LO Frequency, 200 MHz Bandwidth, Figure 104. Receiver Gain Step Error vs. Receiver Attenuation,
20 MHz Offset, −5 dBFS Input Signal
Figure 105. Normalized Receiver Flatness vs. Baseband Offset Frequency,
1800 MHz BAND
The temperature settings refer to the die temperature. All LO frequencies set to 1800 MHz, unless otherwise noted. Figure 163. Transmitter Continuous Wave (CW) Output Power vs. Figure 164. Transmitter Output Power Spectrum, TX1, 5 MHz LTE, Figure 165. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 166. Transmitter Noise vs. Transmitter Attenuation, 10 MHz Offset Figure 167. Transmitter Pass Band Flatness vs. Baseband Offset Frequency Figure 168. Adjacent Channel Power Level vs. Transmitter Attenuation,
Figure 169. Adjacent Channel Power Level vs. Transmitter Attenuation, Figure 170. Transmitter Second Harmonic Distortion (HD2) vs. Transmitter Figure 171. Transmitter Third Harmonic Distortion (HD3) vs. Transmitter Figure 172. Transmitter Attenuator Step Error vs. Transmitter Attenuation, Figure 173. Transmitter Error Vector Magnitude vs. Transmitter Attenuation, Figure 174. Transmitter OIP3, 2f1 − f2 vs. Transmitter Attenuation, 15 dB
Figure 187. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 188. Receiver LO Leakage vs. Receiver LO Frequency, Figure 189. Receiver Gain vs. Receiver Attenuation, 20 MHz Offset, 200 MHz Figure 190. Receiver Gain vs. Receiver LO Frequency, 200 MHz Bandwidth, Figure 191. Receiver Gain Step Error vs. Receiver Attenuation, Figure 192. Normalized Receiver Flatness vs. Baseband Offset Frequency,
Figure 223. Observation Receiver Gain vs. Observation Receiver LO Figure 224. Observation Receiver Gain Step Error vs. Observation Receiver Figure 225. Normalized Observation Receiver Flatness vs. Baseband Offset Figure 226. Observation Receiver Image vs. Baseband Offset Frequency, Figure 227. Observation Receiver Image vs. Observation Receiver Attenuation,
45 MHz Offset, Tracking Calibration Active,
Figure 228. Observation Receiver DC Offset vs. Observation Receiver
2600 MHz BAND
The temperature settings refer to the die temperature. All LO frequencies set to 2600 MHz, unless otherwise noted. Figure 250. Transmitter Continuous Wave Output Power vs. Transmitter LO Figure 251. Transmitter Output Power Spectrum, Tx1, 5 MHz LTE, Figure 252. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 253. Transmitter Noise vs. Transmitter Attenuation, 10 MHz Offset Figure 254. Transmitter Pass Band Flatness vs. Baseband Offset Frequency Figure 255. Adjacent Channel Power Level vs. Transmitter Attenuation,
Figure 256. Adjacent Channel Power Level vs. Transmitter Attenuation, Figure 257. Transmitter Second Harmonic Distortion (HD2) vs. Transmitter Figure 258. Transmitter Third Harmonic Distortion (HD3) vs. Transmitter Figure 259. Transmitter Attenuator Step Error vs. Transmitter Attenuation, Figure 260. Transmitter Error Vector Magnitude vs. Transmitter Attenuation, Figure 261. Transmitter OIP3, 2f1 − f2 vs. Transmitter Attenuation, 15 dB
Figure 274. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 275. Receiver LO Leakage vs. Receiver LO Frequency, Figure 276. Receiver Gain vs. Receiver Attenuation, 20 MHz Offset, 200 MHz Figure 277. Receiver Gain vs. Receiver LO Frequency, 200 MHz Bandwidth, Figure 278. Receiver Gain Step Error vs. Receiver Attenuation, Figure 279. Normalized Receiver Flatness vs. Baseband Offset Frequency,
Figure 310. Observation Receiver Gain vs. Observation Receiver LO Figure 311. Observation Receiver Gain Step Error vs. Observation Receiver Figure 312. Normalized Observation Receiver Flatness vs. Baseband Offset Figure 313. Observation Receiver Image vs. Baseband Offset Frequency, Figure 314. Observation Receiver Image vs. Observation Receiver Attenuation, Figure 315. Observation Receiver DC Offset vs. Observation Receiver
3800 MHZ BAND
The temperature settings refer to the die temperature. All LO frequencies set to 3800 MHz, unless otherwise noted. Figure 337. Transmitter Continuous Wave Output Power vs. Transmitter LO Figure 338. Transmitter Output Power Spectrum, Tx1, 5 MHz LTE,
10 MHz Offset, −10 dBFS RMS, 1 MHz Resolution Bandwidth, TJ = 25°C (Step
Figure 339. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 340. Transmitter Noise vs. Transmitter Attenuation,
10 MHz Offset Frequency
Figure 341. Transmitter Pass Band Flatness vs. Baseband Offset Frequency Figure 342. Adjacent Channel Power Level vs. Transmitter Attenuation,
Figure 343. Adjacent Channel Power Level vs. Transmitter Attenuation, Figure 344. Transmitter Second Harmonic Distortion (HD2) vs. Transmitter Figure 345. Transmitter Third Harmonic Distortion (HD3) vs. Transmitter Figure 346. Transmitter Attenuator Step Error vs. Transmitter Attenuation, Figure 347. Transmitter Error Vector Magnitude vs. Transmitter Attenuation, 20 Figure 348. Transmitter OIP3, 2f1 − f2 vs. Transmitter Attenuation,
Figure 361. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 362. Receiver LO Leakage vs. Receiver LO Frequency, Attenuation = Figure 363. Receiver Gain vs. Receiver Attenuation, 20 MHz Offset, 200 MHz Figure 364. Receiver Gain vs. Receiver LO Frequency, 200 MHz Bandwidth, Figure 365. Receiver Gain Step Error vs. Receiver Attenuation, Figure 366. Normalized Receiver Flatness vs. Baseband Offset Frequency,
Figure 397. Observation Receiver Gain vs. Observation Receiver Figure 398. Observation Receiver Gain Step Error vs. Observation Receiver Figure 399. Normalized Observation Receiver Flatness vs. Baseband Offset Figure 400. Observation Receiver Image vs. Baseband Offset Frequency, Figure 401. Observation Receiver Image vs. Observation Receiver Attenuation, Figure 402. Observation Receiver DC Offset vs. Observation Receiver
4800 MHZ BAND
The temperature settings refer to the die temperature. All LO frequencies set to 4800 MHz, unless otherwise noted. Figure 424. Transmitter CW Output Power vs. Transmitter LO Frequency,
10 MHz Offset, 0 dB Attenuation
Figure 425. Transmitter Output Power Spectrum, Tx1, 5 MHz LTE, Figure 426. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 427. Transmitter Noise vs. Transmitter Attenuation, Figure 428. Transmitter Pass Band Flatness vs. Baseband Offset Frequency Figure 429. Adjacent Channel Power Level vs. Transmitter Attenuation,
Figure 430. Adjacent Channel Power Level vs. Transmitter Attenuation, Figure 431. Transmitter Second Harmonic Distortion (HD2) vs. Transmitter Figure 432. Transmitter Third Harmonic Distortion (HD3) vs. Transmitter Figure 433. Transmitter Attenuator Step Error vs. Transmitter Attenuation, Figure 434. Transmitter Error Vector Magnitude vs. Transmitter Attenuation, Figure 435. Transmitter OIP3, 2f1 − f2 vs. Transmitter Attenuation,
Figure 448. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 449. Receiver LO Leakage vs. Receiver LO Frequency, Figure 450. Receiver Gain vs. Receiver Attenuation, 20 MHz Offset, 200 MHz Figure 451. Receiver Gain vs. Receiver LO Frequency, 200 MHz Bandwidth, Figure 452. Receiver Gain Step Error vs. Receiver Attenuation, Figure 453. Normalized Receiver Flatness vs. Baseband Offset Frequency,
Figure 484. Observation Receiver Gain vs. Observation Receiver Figure 485. Observation Receiver Gain Step Error vs. Observation Receiver Figure 486. Normalized Observation Receiver Flatness vs. Baseband Offset Figure 487. Observation Receiver Image vs. Baseband Offset Frequency, Figure 488. Observation Receiver Image vs. Observation Receiver Attenuation, Figure 489. Observation Receiver DC Offset vs. Observation Receiver
5700 MHZ BAND
The temperature settings refer to the die temperature. All LO frequencies set to 5700 MHz, unless otherwise noted. Figure 511. Transmitter Continuous Wave Output Power vs. Transmitter LO Figure 512. Transmitter Output Power Spectrum, Tx1, 5 MHz LTE, Figure 513. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 514. Transmitter Noise vs. Transmitter Attenuation, Figure 515. Transmitter Pass Band Flatness vs. Baseband Offset Frequency Figure 516. Adjacent Channel Power Level vs. Transmitter Attenuation,
Figure 517. Adjacent Channel Power Level vs. Transmitter Attenuation, Figure 518. Transmitter Second Harmonic Distortion (HD2) vs. Transmitter Figure 519. Transmitter Third Harmonic Distortion (HD3) vs. Transmitter Figure 520. Transmitter Attenuator Step Error vs. Transmitter Attenuation, Figure 521. Transmitter Error Vector Magnitude vs. Transmitter Attenuation, Figure 522. Transmitter OIP3, 2f1 − f2 vs. Transmitter Attenuation,
Figure 535. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 536. Receiver LO Leakage vs. Receiver LO Frequency, Figure 537. Receiver Gain vs. Receiver Attenuation, 20 MHz Offset, 200 MHz Figure 538. Receiver Gain vs. Receiver LO Frequency, 200 MHz Bandwidth, Figure 539. Receiver Gain Step Error vs. Receiver Attenuation, Figure 540. Normalized Receiver Flatness vs. Baseband Offset Frequency,
division duplex (TDD) modes. (JESD204B Subclass 1 compliant and supports JESD204C). chain is connected to the digital-to-analog converter (DAC). optimize signal-to-noise ratio (SNR). The ADRV9029 provides four independent receiver channels. conversion system that supports up to a bandwidth of 200 MHz. and serialized for transmission to the baseband processor. combinations of transmitter and observation channels. Table 14. Possible Transmitter-Observation Channel
Rev. 0 | Page 128 of 133 SYNTHESIZERS The ADRV9029 contains four fractional-N PLLs to generate the RF LO for the signal paths and all internal clock sources. This group of PLLs includes two RF PLLs for transmit and receive LO generation, an auxiliary PLL that can be used by the observation receivers, and a clock PLL. Each PLL is independently controlled with no need for external components to set frequencies. RF Synthesizers The two RF synthesizers use fractional-N PLLs to generate RF LOs for multiple receiver and transmitter channels. The fractional- N PLL incorporates a four-core internal voltage controlled oscillator (VCO) and loop filter, capable of generating low phase noise signals with no external components required. An internal LO multiplexer (mux) enables each PLL to supply LOs to any or all receivers and transmitters (for example, LO1 to all transmitters, LO2 to all receivers), resulting in maximum flexibility when configuring the device for TDD operation. The LOs on multiple devices can be phase synchronized to support active antenna systems and beam forming applications. Auxiliary Synthesizer The auxiliary synthesizer uses a single core VCO fractional-N PLL to generate the signals necessary to calibrate the device. The output of this block uses a separate mux system to route LOs for calibrating different functions during initialization. The auxiliary synthesizer can also be used to generate LO signals for the observation receivers or as an offset LO used in the receiver signal chains. Clock Synthesizer The ADRV9029 contains a single core VCO fractional-N PLL synthesizer that generates all baseband related clock signals and SERDES clocks. This fractional-N PLL is programmed based on the data rate and sample rate requirements of the system, which typically require the system to operate in integer mode. For JESD204B configurations with Np = 12 and JESD204C configurations, a dedicated PLL included in the SERDES block generates the SERDES clocks. SPI INTERFACE The ADRV9029 uses a SPI to communicate with the baseband processor. This interface can be configured as a 4-wire interface with dedicated receive and transmit ports, or the interface can be configured as a 3-wire interface with a bidirectional data communications port. This bus allows the baseband processor to set all device control parameters using a simple address data serial bus protocol. Write commands follow a 24-bit format. The first bit sets the bus direction of the bus transfer. The next 15 bits set the address where data is written. The final eight bits are the data being transferred to the specific register address. Read commands follow a similar format with the exception that the first 16 bits are transferred on the SPI_DIO pin, and the final eight bits are read from the ADRV9029, either on the SPI_DO pin in 4-wire mode or on the SPI_DIO pin in 3-wire mode. GPIO_X PINS The ADRV9029 provides 19 general-purpose input/output signals (GPIOs) referenced to VIF that can be configured for numerous functions. When configured as outputs, certain pins can provide real-time signal information to the baseband processor, allowing the baseband processor to determine receiver performance. A pointer register selects what information is output to these pins. Signals used for manual gain mode, calibration flags, state machine status, and various receiver parameters are among the outputs that can be monitored on the GPIO pins. Additionally, certain GPIO pins can be configured as inputs and used for various functions, such as setting the receiver gain in real time. AUXILIARY CONVERTERS GPIO_ANA_x/AUXDAC_x The ADRV9029 contains eight analog GPIOs (the GPIO_ANA_x pins) that are multiplexed with eight identical auxiliary DACs (AUXDAC_x). The analog GPIO ports can be used to control other analog devices or receive control inputs referenced to the VDDA_1P8 supply. The auxiliary DACs are 12-bit converters capable of supplying up to 10 mA. These outputs are typically used to supply bias current or variable control voltages for other related components with analog control inputs. AUXADC_x The ADRV9029 contains two auxiliary ADCs with four total input pins (AUXADC_x). These auxiliary ADCs provide 10-bit monotonic outputs with an input voltage range of 0.05 V to 0.95 V. When enabled, each auxiliary ADC is free running. An application programming interface (API) command latches the ADC output value to a register. The ADRV9029 also contains an ADC that supports a built-in diode-based temperature sensor. DIGITAL PREDISTORTION (DPD) The ADRV9029 provides a fully integrated DPD system that linearizes the output of the transmitter power amplifier by altering the digital waveform to compensate for nonlinearities in the power amplifier response. Both the DPD actuator and coefficient calculation engine are integrated within the device. This system uses an ORx channel to monitor the output of the power amplifier and calculates the appropriate predistortion that must be inserted into the transmitter datapath to linearize the output. The integrated DPD capability allows the system to drive the power amplifier closer to saturation, enabling a higher efficiency power amplifier while maintaining linearity. The DPD is optimized for power amplifiers with rms output powers in the 250 mW to 10 W range. The DPD engine is highly configurable and can operate over a range of clock rates, which allows the DPD system to scale so this system can support different carrier configurations within the transmitter bandwidth. The additional
channel (maximum bandwidth).
20 MHz LTE signal and in Figure 599 for a 100 MHz 5G NR
degrades as signal bandwidth increases.
100 MHz 5G NR signal to demonstrate the ACLR improvement
degrades as signal bandwidth increases. Figure 598. Transmitter Output Spectrum for Normal Operation (Red) and Figure 599. Transmitter Output Spectrum for Normal Operation (Red) and Figure 600. Transmitter Output Spectrum for Normal Operation (Red) and Figure 601. Transmitter Output Spectrum for Normal Operation (Red) and
Figure 602. Transmitter Output Spectrum for Normal Operation (Red) and Table 15. 20 MHz LTE Waveform ACLR Comparison With and Without DPD
20 MHz Offset (dBc) 40 MHz Offset (dBc)
2600 MHz
3500 MHz
output at LO = 2600 MHz, and 37 dBm output at LO = 3500 MHz. Table 16. 100 MHz 5G NR Waveform ACLR Comparison With and Without DPD
100 MHz Offset (dBc) 200 MHz Offset (dBc)
and 37 dBm output at LO = 3500 MHz. Table 17. 2 × 100 MHz 5G NR Waveform ACLR Comparison With and Without DPD
200 MHz Offset (dBc)
The ADRV9029 provides support for a JTAG boundary scan. configured in the software (differential or single-ended mode). Table 18. Dual Function Boundary Scan Test Pins Table 19. JTAG Modes
0 XXX 1 Normal operation
activated. The VIF supply can be powered up at any time. signal after power has stabilized. power down all supplies simultaneously. rates reported in Table 20, Table 21, and Table 22. Table 20. Example Receiver Interface Rates with Four Channels Active (M = 8) Table 21. Transmitter Interface Rates with Four Channels Active (M = 8) Table 22. Observation Path Interface Rates with 1 Channel Active (M = 2)
0.60 BSC
12.80 REF
8.708 REF
8.87 REF
Figure 603. 289-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 2 The ADS9-V2EBZ motherboard (ordered separately) must be used with the ADRV9029-HB/PCBZ, ADRV9029-MB/PCBZ, or ADRV9020-LB/PCBZ evaluation board. 3 See the Junction Temperature section. registered trademarks are the prop erty of their respective owners.