ADS808Y/250

ADS808 BURR-BROWN | Alldatasheet

Document overview

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Technical content

OutputsT&H D11

• •• +VS ADS808 CLK CLK OESEL2 REFBVREFREFT VDRV IN1Vp-p 1Vp-p CM (+2.5V) SEL1 DV OVR IN 12-Bit, 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER

FEATURES

G DYNAMIC RANGE: SNR: 64dB at 10MHz fIN SFDR: 68dB at 10MHz fIN G PREMIUM TRACK-AND-HOLD: Low Jitter: 0.25ps rms Differential or Single-Ended Inputs Selectable Full-Scale Input Range G FLEXIBLE CLOCKING: Differential or Single-Ended Accepts Sine or Square Wave Clocking Down to 0.5Vp-p Variable Threshold Level

DESCRIPTION

The ADS808 is a high-dynamic range, 12-bit, 70MHz, pipelined Analog-to-Digital Converter (ADC). It includes a high-bandwidth linear track-and-hold that has a low jitter of only 0.25ps rms, leading to excellent SNR performance. The clock input can accept a low-level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels. The ADS808 has a 2Vp-p differential input range (1Vp-p • 2 inputs) for optimum signal-to-noise ratio. The differential operation gives the lowest even-order harmonic compo- nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be selected using the internal references, further optimizing SFDR. Alternatively, a single-ended input range can be used by tying the IN input to the common-mode voltage, if desired. The ADS808 also provides an over-range flag that indicates when the input signal has exceeded the converter’s full-scale range. This flag can also be used to reduce the gain of the front-end signal conditioning circuitry. It also employs digital error-correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS808 is available in a small TQFP-48 PowerPAD™ thermally en- hanced package.

APPLICATIONS

G BASESTATION WIDEBAND RADIOS: CDMA, GSM, TDMA, 3G, AMPS, and NMT G TEST INSTRUMENTATION G CCD IMAGING ADS808 SBAS179C – DECEMBER 2000 – REVISED SEPTEMBER 2002 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments.

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ELECTRICAL CHARACTERISTICS

At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, VS = +5V, and internal reference, unless otherwise noted. SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR (1) RANGE MARKING NUMBER MEDIA, QUANTITY ADS808Y TQFP-48 PHP –40°C to +85°C ADS808Y ADS808Y/250 Tape and Reel, 250 "" " " " ADS808Y/2K Tape and Reel, 2000 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PACKAGE/ORDERING INFORMATION NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS (1) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper han- dling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ADS808Y PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 12 Tested Bits SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C ANALOG INPUT Standard Differential Input Range (1Vp-p • 2, +10dBm) 1 2 V Single-Ended Input Voltage 1Vp-p 2 3 V Common-Mode Voltage 2.5 V Optional Input Ranges Selectable 1Vp-p or 1.5Vp-p V Analog Input Bias Current 1 µA Track-Mode Input Bandwidth –3dBFS 1 GHz Input Impedance Static, No Clock 1.25 || 9 M Ω || pF CONVERSION CHARACTERISTICS Sample Rate 1M 70M Samples/s Data Latency 5 Clk Cyc DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz ±0.7 +1.7/ –1.0 LSB No Missing Codes Tested Integral Nonlinearity Error, f = 1MHz ±4.0 ±7.0 LSBs Spurious-Free Dynamic Range(1) f = 1MHz 72 dBFS (2) f = 10MHz 65 68 dBFS 2-Tone Intermodulation Distortion fIN = 19.4MHz and 20.4MHz (–7dB each tone) –77 dBFS Signal-to-Noise Ratio (SNR) f = 1MHz 64.5 dBFS f = 10MHz 64 dBFS Signal-to-(Noise + Distortion) (SINAD) f = 2.2MHz 64 dBFS f = 10MHz 63 dBFS Output Noise Input AC-Grounded 0.3 LSBs rms Aperture Delay Time 3n s Aperture Jitter 0.25 ps rms Over-Voltage Recovery Time 2n s Full-Scale Step Acquisition Time 5n s DIGITAL INPUTS Logic Family +3V/+5V Logic Compatible CMOS Convert Command Start Conversion Rising Edge of Convert Clock High-Level Input Current (V IN = 5V)(3) 100 µA Low-Level Input Current (VIN = 0V) ±10 µA High-Level Input Voltage +2.0 V Low-Level Input Voltage +1.0 V Input Capacitance 5p F

SBAS179C www.ti.com ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, VS = +5V, and internal reference, unless otherwise noted. ADS808Y PARAMETER CONDITIONS MIN TYP MAX UNITS +3V/+5V Compatible CMOS Straight Offset Binary DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (I OL = 50µA to 1.6mA) VDRV = 3V +0.2 V High Output Voltage, (IOH = 50µA to 0.5mA) +2.5 V Low Output Voltage, (IOL = 50µA to 1.6mA) VDRV = 5V +0.2 V High Output Voltage, (IOH = 50µA to 1.6mA) +2.5 V 3-State Enable Time OE = LOW 20 40 ns 3-State Disable Time OE = HIGH 2 10 ns Output Capacitance 5p F ACCURACY (Internal Reference, = 2V, Unless Otherwise Noted) Zero Error (Midscale) at 25 °C 0.5 %FS Zero Error Drift (Midscale) 12 ppm/ °C Gain Error(4) at 25°C ±1.5 %FS Gain Error Drift(4) 38 ppm/ °C Gain Error(5) at 25°C ±0.75 %FS Gain Error Drift(5) 20 ppm/ °C Power-Supply Rejection of Gain ∆VS = ±5% 68 dB Internal REF Tolerance (VREFP – VREFN ) Deviation from Ideal ±10 ±40 mV Reference Input Resistance 660 Ω POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Operating +4.75 +5.0 +5.25 V Supply Current: +IS Operating 142 mA Output Driver Supply Current (VDRV) 10 mA Power Dissipation: VDRV = 5V Internal Reference 740 mW VDRV = 3V Internal Reference 720 770 mW VDRV = 5V External Reference 720 mW VDRV = 3V External Reference 700 mW Power Down Operating 20 mW Thermal Resistance, θJA TQFP-48 28.8 °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) A 50kΩ pull-down resistor is inserted internally. (4) Includes internal reference. (5) Excludes internal reference.

SBAS179Cwww.ti.com

26 VDRV Output Bit Driver Voltage Supply

27 GND Ground

OE Output Enable: HI = High Impedance; LO or Floating: Normal Operation

29 I PD Power Down: HI = Power Down; LO = Normal

30 I BTC HI = Binary Two ’s Complement;

LO = Straight Binary

31 GND Ground

32 SEL2 Reference Select 2: See Table on Page 5. 33 SEL1 Reference Select 1: See Table on Page 5. 34 V REF Internal Reference Voltage

35 GND Ground

36 GND Ground

37 GND Ground

38 GND Ground

39 REFB Bottom Reference Voltage Bypass

40 CM Common-Mode Voltage (mid-scale)

41 REFT Top Reference Voltage Bypass

42 GND Ground

43 GND Ground

IN Complementary Analog Input

45 GND Ground

46 I IN Analog Input

1 BYP Bypass Point

5 GND Ground

6 I CLK Clock Input

8 GND Ground

9 GND Ground

10 O OVR Over-Range Indicator

11 O DV Data Valid Pulse: HI = Data Valid

12 NC No Connection

13 NC No Connection

14 O D11 Data Bit 11, (MSB)

15 O D10 Data Bit 10

16 O D9 Data Bit 9

17 O D8 Data Bit 8

18 O D7 Data Bit 7

19 O D6 Data Bit 6

20 O D5 Data Bit 5

21 O D4 Data Bit 4

22 O D3 Data Bit 3

23 O D2 Data Bit 2

24 O D1 Data Bit 1

25 O D0 Data Bit 0, (LSB)

V REF SEL1 SEL2 GND BTC PD OE GND VDRV D0 (LSB) +V S +V S IN GND IN GND GND REFT CM REFB GND GND NC D11 (MSB) D10 BYP +VS +VS +VS GND CLK CLK GND GND OVR DV NC 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 ADS808Y PIN I/O DESIGNATOR DESCRIPTION PIN I/O DESIGNATOR DESCRIPTION PIN DESCRIPTIONS PIN DIAGRAM Top View TQFP

SBAS179C www.ti.com DESIRED INTERNAL FULL-SCALE RANGE SEL1 SEL2 V REF 1Vp-p V REF GND 0.5V 1.5Vp-p GND +V S 0.75V 2Vp-p GND GND 1.0V REFERENCE AND FULL-SCALE RANGE SELECT NOTE: For external reference operation, tie VREF to +VS and apply REFT and REFB externally. Internal voltage buffer of CM is powered up. The full-scale input range is equal to 2x the reference value (REFT – REFB). TIMING DIAGRAM SYMBOL DESCRIPTION MIN (1) TYP MAX (1) UNITS tCONV Convert Clock Period 14.3 1 µsn s tH Clock Pulse HIGH 7 t CONV /2 ns tL Clock Pulse LOW 7 t CONV /2 ns tA Aperture Delay 4.6 6.1 ns tDV Data Valid Pulse Delay(2) 11.5 14 ns t1 Data Hold Time, CL = 0pF 4 5 ns t2 New Data Delay Time, CL = 15pF max 9 11 ns NOTES: (1) Timing values based on simulation at room temperature. Min/Max values provided for design estimation only. (2) Measured from the 50% point of the clock to the time when signals are within valid logic levels. tA tCONV tH N – 5N – 4N – 3N – 2N – 1 N N + 1Data Bits Out Data Valid Pulse Clock N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7Analog In tL tDV

5 Clock Cycles

SBAS179Cwww.ti.com TYPICAL CHARACTERISTICS At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted. –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 SPECTRAL PERFORMANCE (Differential, 2Vp-p) Frequency (MHz) 0 5 10 15 20 25 30 35 Amplitude (dBFS) fIN = 1MHz (–1.0dBFS) SFDR = 71.40dBFS SNR = 64.41dBFS SINAD = 63.33dBFS DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY Sampling Frequency (MHz) 30 35 40 45 55 50 60 65 70 75 80 SFDR, SNR, and SINAD (dBFS) fIN = 1MHz SNR SINAD SFDR DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (2Vp-p, Differential) Sample Frequency (MHz) 30 35 40 45 55 50 60 65 70 75 80 SFDR, SNR, and SINAD (dBFS) fIN = 10MHz SNR SINAD SFDR DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (2Vp-p, Differential) Sample Frequency (MHz) 40 45 50 60 55 65 70 75 80 SFDR, SNR, and SINAD (dBFS) fIN = 20MHz SNR SINAD SFDR 760 740 720 700 680 660 640 620 600 580 560 540 520 500 TOTAL POWER vs SAMPLING FREQUENCY Sampling Frequency (MHz) 30 35 40 50 45 55 60 70 65 80 75 Power (mW) fIN = 10MHz fIN = 1MHz DYNAMIC PERFORMANCE vs INPUT FREQUENCY Input Frequency (MHz) 1 6 11 16 21 31 26 SFDR, SNR, and SINAD (dBFS) SNR SINAD SFDR

SBAS179C www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted. 300k 250k 200k 150k 100k 50k OUTPUT NOISE HISTOGRAM (2Vp-p, Grounded Input) Code N – 1 N N + 1 N + 2 Counts N – 2 0.8 0.6 0.4 0.3 –0.2 –0.4 –0.6 –0.8 DIFFERENTIAL LINEARITY ERROR Code 0 1024 2048 3072 4096 DLE (LSB) INTEGRAL LINEARITY ERROR Code 0 1024 2048 3072 4096 ILE (LSB)

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APPLICATION INFORMATION

The ADS808 is a high-speed, high-performance, CMOS ADC built with a fully differential, 9-stage pipeline architec- ture. Each stage contains a low-resolution quantizer and digital error-correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The conversion process is initiated by a rising edge of the external convert clock. Once the signal is captured by the input track-and-hold amplifier, the bits are sequentially en- coded starting with the MSB. This process results in a data latency of five clock cycles, after which the output data is available as a 12-bit parallel word either coded in a straight binary or binary two’s complement format. The analog input of the ADS808 consists of a differential track-and-hold circuit, as shown in Figure 1. The differential topology produces a high level of AC-performance at high sampling rates. It also results in a very high usable input bandwidth that is especially important for IF, or undersampling applications. Both inputs (IN, IN) require external biasing up to a common-mode voltage that is typically at the mid-supply level (+V S/2). This is because the on-resistance of the CMOS switches is lowest at this voltage, minimizing the effects of the signal dependent nonlinearity of R ON . The track-and-hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. For ease of use, the ADS808 incorporates a selectable voltage reference, a ver- satile clock input, and a logic output driver designed to interface to 3V or 5V logic. particularly suited for communication systems that digitize wideband signals. Features on the ADS808, like the input range selector or the option of an external reference, provide the needed flexibility to accommodate a wide range of applications. In any case, the analog interface/driver require- ments should be carefully examined before selecting the appropriate circuit configuration. The circuit definition should include considerations on the input frequency spectrum and amplitude, single-ended versus differential driver configura- tion, as well as the available power supplies. Differential versus Single-Ended The ADS808 input structure allows it to be driven either single-ended or differentially. Differential operation of the ADS808 requires an input signal that consists of an in-phase and a 180° out-of-phase component simultaneously applied to the inputs (IN, IN). Differential signals offer a number of advantages that in many applications will be instrumental in achieving the best harmonic performance of the ADS808:

• The signal amplitude is half of that required for the single- ended operation and is, therefore, less demanding to achieve while maintaining good linearity performance from the signal source.
• The reduced signal swing allows for more headroom of the interface circuitry and, therefore, a wider selection of the best suitable driver amplifier.
• Even-order harmonics are minimized.
• Improves the noise immunity based on the converter’s common-mode input rejection. For the single-ended mode, the signal is applied to one of the inputs while the other input is biased with a DC voltage to the required common-mode level. Both inputs are identical in terms of their impedance and performance except that apply- ing the signal to the complementary input ( IN) instead of the IN-input will invert the orientation of the input signal relative to the output code. For example, if the input driver operates in inverting mode using IN as the signal input, it will restore the phase of the signal to its original orientation. Time- domain applications may benefit from a single-ended inter- face configuration and a reduced circuit complexity. Driving the ADS808 with a single-ended signal will result in a trade- off of the excellent distortion performance, while maintaining a good signal-to-noise ratio (SNR). The trade-off of the differential input configuration over the single-ended is its increase in circuit complexity. In either case, the selection of the driver amplifier should be such that the amplifier’s perfor- mance will not degrade the A/D converter’s performance. Input Full-Scale Range versus Performance Employing dual-supply amplifiers and AC-coupling will usually yield the best results. DC-coupling and/or single-supply ampli- fiers impose additional design constrains due to their head- room requirements, especially when selecting the 2Vp-p input range. The full-scale input range of the ADS808 is defined either by the settings of the reference select pins (SEL1, SEL2) or by an external reference voltage (see Table I). T&H C IN C IN IN IN Tracking Phase: S1, S2, S3, S4 Closed; S5, S6 Open Hold Phase: S1, S2, S3, S4 Open; S5, S6 Closed ADS808

FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier.

closely matched source impedances. off some of the wideband noise. possible reference options and pin configurations. FIGURE 6. Wideband Differential A/D Converter Driver. TABLE I. Reference Pin Configurations and Corresponding Voltage on the Reference Pins.

FIGURE 13. Recommended Supply Decoupling Scheme. sponding to the particular sampled analog input voltage. as the digital data (5 clock cycles). output lines as low as possible, preferably below 15pF. from coupling back high-frequency noise. supply pin, denoted VDRV (see the following section). least one 0.1µF ceramic chip capacitor, forming a pi-filter. S pins and +3.0V on the output driver pin (VDRV). board parasitics and optimize component placement. convenient component placement. plane that covers the pc-board area under the converter. frequencies, should also be used on the main supply pins.

SBAS179Cwww.ti.com If the analog inputs to the ADS808 are driven differentially, it is especially important to optimize towards a highly symmetri- cal layout. Small trace length differences may create phase shifts compromising a good distortion performance. For this reason, the use of two single op amps (rather than one dual amplifier) enables a more symmetrical layout and a better match of parasitic capacitances. The pin orientation of the ADS808 package follows a “flow-through” design with the analog inputs located on one side of the package while the digital outputs are located on the opposite side of the quad- flat package. This provides a good physical isolation be- tween the analog and digital connections. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. Also, try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. Single- ended clock lines must be short and should not cross any other signal traces. Short-circuit traces on the digital outputs will minimize ca- pacitive loading. Trace length should be kept short to the receiving gate (< 2") with only one CMOS gate connected to one digital output. If possible, the digital data outputs should be buffered (with a 74LCX571, for example). Dynamic perfor- mance may also be improved with the insertion of series resistors at each data output line. This sets a defined time constant and reduces the slew rate that would otherwise flow, due to the fast edge rate. The resistor value may be chosen to result in a time constant of 15% to 25% of the used data rate. LAYOUT OF PCB WITH PowerPAD THERMALLY ENHANCED PACKAGES The ADS808 is housed in a 48-lead PowerPAD thermally enhanced package. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. Please refer to SLMA004 PowerPAD brief “PowerPAD Made Easy ” on our web site at www.ti.com, which addresses the specific considerations required when integrating a PowerPAD pack- age into the PCB design. For more detailed information, including thermal modeling and repair procedures, please see SLMA002 technical brief “PowerPAD Thermally En- hanced Package” (www.ti.com).

SBAS179C www.ti.com PACKAGE DRAWING PHP (S-PQFP-G48) PowerPAD  PLASTIC QUAD FLATPACK Thermal Pad (see Note D) Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 4146927/A 01/98 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,50 M0,08 0,08 0°–7° 0,05 0,15 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) ADS808Y/250 ACTIVE TQFP PFB 48 250 None CU NIPDAU Level-3-220C-168 HR ADS808Y/2K ACTIVE TQFP PFB 48 2000 None CU NIPDAU Level-3-220C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 Addendum-Page 1

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