ADS807E

ADS807 TI | Alldatasheet

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Technical content

12-Bit, 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER

FEATURES

G SPURIOUS-FREE DYNAMIC RANGE: 82dB at 10MHz fIN G HIGH SNR: 67.5dB (2Vp-p), 69dB (3Vp-p) G LOW POWER: 335mW G INTERNAL OR EXTERNAL REFERENCE G LOW DNL: 0.5LSB G FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p G SSOP-28 PACKAGE

DESCRIPTION

The ADS807 is a high-speed, high dynamic range, 12-bit pipelined Analog-to-Digital (A/D) converter. This con- verter includes a high-bandwidth track-and-hold that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of this track-and-hold and A/D converter circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity. The track-and-hold can also be operated single-ended. The ADS807 provides for setting the full-scale range of the converter without any external reference circuitry. The inter- nal reference can be disabled allowing low drive, internal references to be used for improved tracking in multichannel systems. The ADS807 provides an over-range indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front end gain control circuitry. There is also an output enable pin to allow for multiplexing and testability on a PC board. The ADS807 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications.

APPLICATIONS

G COMMUNICATIONS IF PROCESSING G COMMUNICATIONS BASESTATIONS G TEST EQUIPMENT G MEDICAL IMAGING G VIDEO DIGITIZING G CCD DIGITIZING ADS807E Pipelined A/D Converter Internal Reference Optional External Reference Timing Circuitry Error Correction Logic 3-State OutputsT/H D11 CLK ADS807 OE IN INT/EXT IN CM +2.5V +2.5V +3V +2V +2V +3V FS SEL (Opt.) ADS807 SBAS072A – JANUARY 1999 – REVISED JULY 2002 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SBAS072Awww.ti.com PIN DESIGNATOR DESCRIPTION

1 GND Ground

2 Bit 1 Data Bit 1 (MSB)

3 Bit 2 Data Bit 2

4 Bit 3 Data Bit 3

5 Bit 4 Data Bit 4

6 Bit 5 Data Bit 5

7 Bit 6 Data Bit 6

8 Bit 7 Data Bit 7

9 Bit 8 Data Bit 8

10 Bit 9 Data Bit 9

11 Bit 10 Data Bit 10

12 Bit 11 Data Bit 11

13 Bit 12 Data Bit 12 (LSB)

14 CLK Convert Clock

16 FS SEL HI = 3V, LO = 2V

17 OTR Out-of-Range Indicator

18 INT/EXT Reference Select: HIGH or Floating = Exter-

nal LOW = Internal 50kΩ pull-up.

19 OE Output Enable

20 GND Ground

21 REFB Bottom Reference/Bypass

22 REFT Top Reference/Bypass

23 CM Common-Mode Voltage Output

24 IN Complementary Analog Input

25 IN Analog Input

26 GND Ground

28 VDRV Logic Driver Supply Voltage

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS (1) Top View SSOP PIN CONFIGURATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. GND Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 (LSB) CLK VDRV S GND IN IN CM REFT REFB GND OE INT/EXT OTR FS SEL +VS ADS807E SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR (1) RANGE MARKING NUMBER MEDIA, QUANTITY ADS807E SSOP-28 DB –40°C to +85°C ADS807E ADS807E Tube, 50 "" " " " ADS807E/1K Tape and Reel, 1000 NOTE: (1) For the most current specifications and package information refer to our web site at www.ti.com. PACKAGE/ORDERING INFORMATION

SBAS072A www.ti.com ADS807E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 12 Tested Bits SPECIFIED TEMPERATURE RANGE Ambient Air –40 +85 °C ANALOG INPUT 2V Full-Scale Input Range (Differential) 2Vp-p, INT or EXT Ref 2 3 V 2V Full-Scale Input Range (Single-Ended) 2Vp-p, INT or EXT Ref 1.5 3.5 V 3V Full-Scale Input Range (Differential) 3Vp-p, INT or EXT Ref 1.75 3.25 V 3V Full-Scale Input Range (Single-Ended) 3Vp-p, INT or EXT Ref 1 4 V Analog Input Bias Current 1 µA Analog Input Bandwidth 270 MHz Input Impedance 1.25 || 3 M Ω || pF CONVERSION CHARACTERISTICS Sample Rate 10k 53M Samples/s Data Latency 6 Clock Cycles DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz ±0.5 ±1.0 LSB f = 10MHz f S = 40MHz ±0.5 ±1.0 LSB No Missing Codes f S = 50MHz,TA = +25°C Tested No MIssing Codes f S = 40MHz, Full Temp Tested Integral Nonlinearity Error, f = 1MHz ±2.0 ±4.0 LSBs Spurious-Free Dynamic Range(1) f = 1MHz (–1dB input) 83 dBFS (2) f = 10MHz (–1dB input) 67 82 dBFS f = 20MHz (–1dB input) 76 dBFS f = 40MHz (undersampling) 76 dBFS f = 1MHz to 10MHz, fS = 40MHz 2Vp-p, Single-Ended Input 62 69 dBFS 2-Tone Intermodulation Distortion(3) f = 12MHz and 13MHz (–7dB each tone) 71 dBc Signal-to-Noise Ratio (SNR) f = 1MHz (–1dB input) 63 68 dB f = 10MHz (–1dB input) 63 68 dB f = 20MHz (–dB input) 66 dB f = 40MHz (undersampling) 67 dB f = 1MHz to 10MHz, fS = 40MHz 63 67.5 dB f = 1MHz to 10MHz, fS = 40MHz 2Vp-p, Single-Ended Input 60 67 dB f = 1MHz (–1dB input) 3Vp-p 69 dB f = 10MHz (–1dB input) 3Vp-p 69 dB Signal-to-(Noise + Distortion) (SINAD)(4) f = 1MHz (–1dBFS input) 61 67 dB f = 10MHz (–1dBFS input) 61 67 dB f = 20MHz (–1dBFS input) 67 dB f = 1MHz to 10MHz, fS = 40MHz 63 67 dB f = 1MHz to 10MHz, fS = 40MHz 2Vp-p, Single-Ended Input 60 64 dB f = 1MHz (–1dBFS input) 3Vp-p 69 dB f = 10MHz (–dBFS Input) 3Vp-p 69 dB Output Noise Input Grounded 0.2 LSBs rms Aperture Delay Time 2n s Aperture Jitter 1.2 ps rms Over-Voltage Recovery Time 2n s DIGITAL INPUTS Logic Family Convert Command Start Conversion High Level Input Current (5) (VIN = 5V) +50 µA Low Level Input Current (VIN = 0V) +10 µA High Level Input Voltage +2.4 V Low Level Input Voltage +1.0 V Input Capacitance 5p F

ELECTRICAL CHARACTERISTICS

At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted. CMOS Rising Edge of Convert Clock

SBAS072Awww.ti.com ADS807E PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted. CMOS Straight Offset Binary DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (I OL = 50µA) VDRV = 5V +0.1 V Low Output Voltage, (IOL = 1.6mA) VDRV = 5V +0.2 V High Output Voltage, (IOH = 50µA) VDRV = 5V +4.9 V High Output Voltage, (IOH = 0.5mA) VDRV = 5V +4.8 V Low Output Voltage, (IOL = 50µA) VDRV = 3V +0.1 V High Output Voltage, (IOH = 50µA) VDRV = 3V +2.8 V 3-State Enable Time OE = L (5) 20 40 ns 3-State Disable Time OE = H (5) 21 0 n s Output Capacitance 5p F ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) Zero Error (Referred to –FS) at 25 °C ±1.0 ±2.0 %FS Zero Error Drift (Referred to –FS) 16 ppm/ °C Gain Error(6) at 25°C ±1.5 ±2.5 %FS Gain Error Drift(6) 66 ppm/ °C Gain Error(7) at 25°C ±1.0 ±1.5 %FS Gain Error Drift(7) 23 ppm/ °C Power-Supply Rejection of Gain ∆VS = ±5% 50 70 dB REFT Tolerance 2V Full-Scale Deviation From Ideal 3.0V ±10 ±65 mV 3V Full-Scale Deviation From Ideal 3.25V ±20 ±100 mV REFB Tolerance 2V Full-Scale Deviation From Ideal 2.0V ±10 ±65 mV 3V Full-Scale Deviation From Ideal 1.75V ±20 ±100 mV External REFT Voltage Range REFB + 0.4 3 V S – 1.70 V External REFB Voltage Range 1.70 2 REFT – 0.4 V Reference Input Resistance 1k Ω POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Operating +4.75 +5.0 +5.25 V Supply Current: +IS Operating 60 mA Power Dissipation: VDRV = 5V External Reference 305 360 mW VDRV = 3V External Reference 290 350 mW VDRV = 5V Internal Reference 350 390 mW VDRV = 3V Internal Reference 335 380 mW Thermal Resistance, θJA SSOP-28 50 °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (7) Excludes internal reference.

SBAS072A www.ti.com TIMING DIAGRAM

6 Clock Cycles

N – 6N – 5N – 4N – 3N – 2N – 1 N N + 1Data Out Clock Analog In N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 18.87 100 µsn s tL Clock Pulse LOW 9.4 t CONV /2 ns tH Clock Pulse HIGH 9.4 t CONV /2 ns tD Aperture Delay 2 ns t1(1) Data Hold Time, CL = 0pF 2.7 ns t2 (1) New Data Delay Time, CL = 15pF max 12 ns NOTE: (1) t1 and t2 times are valid for VDRV voltages of +2.7V to +5V.

SBAS072Awww.ti.com SPECTRAL PERFORMANCE Frequency (MHz) 0 5 10 15 20 25 Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 21MHz SNR = 68dBFS SFDR = 77dBFS SPECTRAL PERFORMANCE Frequency (MHz) 0 5 10 15 20 25 Magnitude (dBFS) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 fIN = 10MHz SNR = 68dBFS SFDR = 82dBFS SPECTRAL PERFORMANCE Frequency (MHz) 0 5 10 15 20 25 Magnitude (dBFS) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 fIN = 1MHz SNR = 68dBFS SFDR = 83dBFS SPECTRAL PERFORMANCE (Single-Ended, 2Vp-p) Frequency (MHz) 0 4.5 9.0 13.5 Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 10MHz SNR = 68dBFS SFDR = 62dBFS SPECTRAL PERFORMANCE (Sampling Frequency = 27MHz) Frequency (MHz) 0 4.5 9.0 13.5 Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 10MHz SNR = 68dBFS SFDR = 81dBFS TYPICAL CHARACTERISTICS At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted. 2-TONE INTERMODULATION DISTORTION Frequency (MHz) 0 5 10 15 20 25 Magnitude (dBc) –20 –40 –60 –80 –100 f1 = 12MHz f2 = 13MHz IMD(3) = –71dBc

SBAS072A www.ti.com SPECTRAL PERFORMANCE (Sampling Frequency = 53MHz) Frequency (MHz) Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 21MHz SNR = 68dBFS SFDR = 72dBFS SWEPT POWER SFDR Input Amplitude (dBFS) SFDR (dBFS, dBc) 100 fIN = 10MHz dBc dBFS UNDERSAMPLING (Sampling Frequency = 27MHz) Frequency (MHz) 0 4.5 9.0 13.5 Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 50MHz SNR = 65dBFS SFDR = 73dBFS TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted. DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (Differential Input) Sampling Frequency (MHz) SFDR, SNR (dB) 35 40 45 50 55 60 SNR (3Vp-p) SNR (2Vp-p) SFDR (2Vp-p) SFDR (3Vp-p) fIN = 5MHz SINAD vs SAMPLING FREQUENCY (Differential Input) Sampling Frequency (MHz) SINAD (dB) 35 40 45 50 55 60 3Vp-p 2Vp-p fIN = 5MHz 800k 600k 400k 200k OUTPUT NOISE HISTOGRAM (DC INPUT) Counts N – 2N – 1 N N + 1 N + 2 Code 3V Full-Scale

SBAS072Awww.ti.com DIFFERENTIAL LINEARITY ERROR (Single-Ended, Input Sampling Frequency = 40MHz) Output Codes DLE (LSB) 1.000 0.500 –0.500 –1.000 10240 2048 3072 4096 fIN = 10MHz INTEGRAL LINEARITY ERROR (Sampling Frequency = 40MHz) Output Codes ILE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 10240 2048 3072 4096 fIN = 10MHz INTEGRAL LINEARITY ERROR Output Codes ILE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 10240 2048 3072 4096 fIN = 10MHz DIFFERENTIAL LINEARITY ERROR Output Codes DLE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 10240 2048 3072 4096 fIN = 10MHz INTEGRAL LINEARITY ERROR Output Codes ILE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 0 1024 2048 3072 4096 fIN = 1MHz DIFFERENTIAL LINEARITY ERROR Output Codes DLE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 10240 2048 3072 4096 fIN = 1MHz TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted.

SBAS072A www.ti.com

• improves the noise immunity based on the converter’s common-mode input rejection Using the single-ended mode, the signal is applied to one of the inputs, while the other input is biased with a DC voltage to the required common-mode level. Both inputs are equal in terms of their impedance and performance, except that applying the signal to the complementary input (IN) instead of the IN input will invert the input signal relative to the output code. For example, in case the input driver operates in inverting mode, using IN as the signal input will restore the phase of the signal to its original orientation. Time-domain applications may benefit from a single-ended interface con- figuration and its reduced circuit complexity. While maintain- ing good SNR, driving the ADS807 with a single-ended signal will result in a reduction of the distortion performance. Employing dual-supply amplifiers and AC-coupling will usu- ally yield the best results, while DC-coupling and/or single- supply amplifiers impose additional design constraints due to their headroom requirements, especially when selecting the 3Vp-p input range. However, single-supply amplifiers have the advantage of inherently limiting their output swing to within the supply rails. Alternatively, a voltage-limiting ampli- fier, like the OPA688, may be considered to set fixed-signal limits and avoid any severe over-range condition for the A/D converter. The full-scale input range of the ADS807 is defined by the reference voltages. For example, setting the range select pin to FS SEL = LOW, and using the internal references (REFT = +3.0V and REFTB = +2.0V), the full-scale range is defined to: FSR = 2 • (REFT – REFB) = 2Vp-p. The trade-off of the differential input configuration versus the single-ended is its higher complexity. In either case, the selection of the driver amplifier should be such that the amplifier’s performance will not degrade the A/D converter’s performance. The ADS807 operates on a single power supply, which requires a level shift to a ground-based bipolar input signals to comply with its input voltage range require- ments. The input of the ADS807 is of a capacitive nature and the driving source needs to provide the current to charge or discharge the input sampling capacitor while the track-and- hold is in track mode. This effectively results in a dynamic input impedance which depends on the sampling frequency. It most applications, it is recommended to add a series resistor, typically 20Ω to 50Ω , between the drive source and the converter inputs. This will isolate the capacitive input from the source, which can be crucial to avoid gain peaking when using wideband operational amplifiers. Secondly, it will create a 1st-order, low-pass filter in conjunction with the specified input capacitance of the ADS807. Its cutoff fre- quency can be adjusted even further by adding an external shunt capacitor from each signal input to ground. The opti- mum values of this R-C network depend on a variety of factors which include the ADS807 sampling rate, the se- lected op amp, the interface configuration, and the particular application (time domain versus frequency domain). Gener- ally, increasing the size of the series resistor and/or capacitor

APPLICATION INFORMATION

The ADS807 is a high-speed, CMOS A/D converter which employs a pipelined converter architecture consisting of 12 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 12-bit level. The output data becomes valid after the rising clock edge (see Timing Dia- gram). The pipeline architecture results in a data latency of 6 clock cycles. The analog input of the ADS807 consists of a differential track-and-hold circuit. The differential topology along with tightly matched poly-poly capacitors produce a high level of AC performance at high sampling rates and in undersampling applications. Both inputs (IN, IN) require external biasing using a com- mon-mode voltage that is typically at the mid-supply level (+V S/2). DRIVING THE ANALOG INPUTS The analog inputs of the ADS807 are a very high impedance. They should be driven through an R-C network designed to pass the highest frequency of interest. This prevents high- frequency noise in the input from affecting SFDR and SNR. The ADS807 can be used in a wide variety of applications and deciding on the best performing analog interface circuit depends on the type of application. The circuit definition should include considerations of input frequency spectrum and amplitude, single-ended or differential drive, and avail- able power supplies. For example, communication (frequency domain) applications process frequency bands not including DC. In imaging (time domain) applications, the input DC component must be maintained into the A/D converter. Features of the ADS807, including full-scale select (FS SEL ), external reference, and CM output provide flexibility to ac- commodate a wide range of applications. The ADS807 should be configured to meet application objectives while observing the headroom requirements of the driving amplifi- ers to yield the best overall performance. The ADS807 input structure allows it to be driven either single-ended or differentially. Differential operation of the ADS807 requires an in-phase input signal and a 180° out-of- phase part simultaneously applied to the inputs (IN, IN). The differential operation offers a number of advantages which, in most applications, will be instrumental in achieving the best dynamic performance of the ADS807:

• the signal swing is half of that required for the single- ended operation and therefore, is less demanding to achieve while maintaining good linearity performance from the signal source
• the reduced signal swing allows for more headroom in the interface circuitry and therefore, a wider selection of the best suitable driver op amp
• even-order harmonics are minimized

the R-C values for the specific application is encouraged. improved distortion performance. (RG ) for good power transfer and VSWR. can be employed for either single- or dual-supply operation. also to avoid DC loading of the op amp’s output stage. affecting the driver circuit. specifically designed to maximize the dynamic performance. sufficient headroom to the supply rails can be maintained. voltage of approximately +2.5V. FIGURE 1. Converting a Single-Ended Input Signal into a Differential Signal Using a RF-Transformer.

SBAS072Awww.ti.com INPUT REFERENCE IN (Pin-25) IN (Pin-24) REFT REFB 2Vp-p Differential Internal 2V to 3V 3V to 2V +3V +2V 1Vp-p Times 2 Inputs or External 2Vp-p Single-Ended Internal 1.5V to 3.5V 2.5V DC +3V +2V 2Vp-p Times 1 Input or External 1.5Vp-p Times 2 Inputs or External 3Vp-p Single-Ended Internal 1V to 4V 2.5V DC +3.25V +1.75V 3Vp-p Times 1 Input or External TABLE III. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage. TABLE II. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage. If it is desired to switch between internal and external refer- ences, disconnect switches must be added between the exter- nal references and the ADS807. DIGITAL INPUTS AND OUTPUTS Clock Input Requirements Clock jitter is critical to the SNR performance of high-speed, high-resolution A/D converters. Clock jitter leads to aperture jitter (tA), which adds noise to the signal being converted. The ADS807 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation. If this value is near your system require- ments, input clock jitter must be reduced. Jitter SNR t rms signaltormsnoise IN A = ƒ20 1 2log π where: ƒIN is input signal frequency tA is rms clock jitter Particularly in undersampling applications, special consider- ation should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have 50% duty cycle (t H = tL), along with fast rise and fall times of 2ns or less. Over-Range Indicator (OTR) If the analog input voltage exceeds the set full-scale range, an over-range condition exists. The ‘OTR ’ pin of the ADS807 can be used to monitor any such out-of-range condition. This ‘OTR ’ output is updated along with the data output corre- sponding to the particular sampled analog input voltage. Therefore, the OTR data is subject to the same pipeline delay as the digital data. The OTR output is LOW when the input voltage is within the defined input range. It will go to HIGH if the applied signal exceeds the full-scale range. Data Outputs The output data format of the ADS807 is in positive Straight Offset Binary code, as shown in Table II and Table III. This format can easily be converted into the Binary Two’s Comple- ment code by inverting the MSB. It is recommended that the capacitive loading on the data lines be as low as possible (< 15pF). Higher capacitive SINGLE-ENDED INPUT STRAIGHT OFFSET BINARY (IN = CM, Pin-23) (SOB) +FS – 1LSB (IN = CMV + FSR/2) 1111 1111 1111 +1/2 FS 1100 0000 0000 Bipolar Zero (IN = VCM ) 1000 0000 0000 –1/2 FS 0100 0000 0000 –FS (IN = CMV – FSR/2) 0000 0000 0000 STRAIGHT OFFSET BINARY DIFFERENTIAL INPUT (SOB) +FS – 1LSB (IN = +3V, IN = +2V) 1111 1111 1111 +1/2 FS 1100 0000 0000 Bipolar Zero (IN = IN = VCM ) 1000 0000 0000 –1/2 FS 0100 0000 0000 –FS (IN = +2V, IN = +3V) 0000 0000 0000 TABLE I. Reference Voltages for Input Signal Ranges. loading will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the analog portion of the ADS807 and affect the performance. If necessary, external buffers or latches close to the converter’s output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS807 from high-frequency digital noise on the bus coupling back into the converter. Digital Output Driver Supply (VDRV) The ADS807 features a dedicated supply pin for the output logic drivers, VDRV, which is not internally connected to the other supply pins. Setting the voltage at VDRV to +5V or +3V, the ADS807 produces corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS807 with +3V logic supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the AC performance of the converter. In some applica- tions, it might be advantageous to decouple the VDRV pin with additional capacitors or a pi-filter. GROUNDING AND DECOUPLING Proper grounding, bypassing, short trace lengths, and the use of power and ground planes are particularly important for high-frequency designs. Multilayer PC boards are recom- mended for best performance since they offer distinct advan- tages such as minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS807 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable

FIGURE 8. Recommended Bypassing for the Supply Pins.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS807E Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS807E ADS807E.B Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS807E ADS807E/1K Active Production SSOP (DB) | 28 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS807E ADS807E/1K.B Active Production SSOP (DB) | 28 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS807E (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADS807E DB SSOP 28 50 530 10.5 4000 4.1 ADS807E.B DB SSOP 28 50 530 10.5 4000 4.1 Pack Materials-Page 1

www.ti.com PACKAGE OUTLINE C 26X 0.65 8.45 28X 0.38 0.22 8.2

7.4 TYP

0.05 MIN

0.25 GAGE PLANE 0 -8

2 MAX

B 5.6 5.0 NOTE 4 A 10.5 9.9 NOTE 3 0.95 0.55 (0.15) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018

0.15 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 14 15 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 14 15

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