ADS807

ADS807 BURR-BROWN | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

12-Bit, 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER

FEATURES

l SPURIOUS FREE DYNAMIC RANGE: 82dB at 10MHz fIN l HIGH SNR: 67.5dB (2Vp-p), 69dB (3Vp-p) l LOW POWER: 335mW l INTERNAL OR EXTERNAL REFERENCE l LOW DNL: 0.5LSB l FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p l 28-LEAD SSOP PACKAGE TM

DESCRIPTION

The ADS807 is a high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter. This con- verter includes a high-bandwidth track-and-hold that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of this track- and-hold and A/D circuitry minimizes even-order har- monics and gives excellent common-mode noise immu- nity. The track-and-hold can also be operated single- ended. The ADS807 provides for setting the full-scale range of the converter without any external reference cir- cuitry. The internal reference can be disabled allowing low drive, internal references to be used for improved tracking in multichannel systems. The ADS807 provides an overrange indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front end gain control circuitry. There is also an output enable pin to allow for multiplexing and testability on a PC board. The ADS807 employs digital error correction tech- niques to provide excellent differential linearity for demanding imaging applications.

APPLICATIONS

l COMMUNICATIONS IF PROCESSING l COMMUNICATIONS BASESTATIONS l TEST EQUIPMENT l MEDICAL IMAGING l VIDEO DIGITIZING l CCD DIGITIZING © 1998 Burr-Brown Corporation PDS-1396C Printed in U.S.A. January, 1999 ADS807E Pipelined A/D Internal Reference Optional External Reference Timing Circuitry Error Correction Logic 3-State OutputsT/H D11 CLK ADS807 OE IN INT/EXT IN CM +2.5V +2.5V +3V +2V +2V +3V FS SEL (Opt.) International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 12 Guaranteed Bits Specified Temperature Range Ambient Air –40 +85 °C ANALOG INPUT 2V Full-Scale Input Range (Differential) 2Vp-p, INT or EXT Ref 2 3 V 2V Full-Scale Input Range (Single-Ended) 2Vp-p, INT or EXT Ref 1.5 3.5 V 3V Full-Scale Input Range (Differential) 3Vp-p, INT or EXT Ref 1.75 3.25 V 3V Full-Scale Input Range (Single-Ended) 3Vp-p, INT or EXT Ref 1 4 V Analog Input Bias Current 1 mA Analog Input Bandwidth 270 MHz Input Impedance 1.25 || 3 M W || pF CONVERSION CHARACTERISTICS Sample Rate 10k 53M Samples/s Data Latency 6 Clock Cycles DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz –0.5 –1.0 LSB f = 10MHz f S = 40MHz –0.5 –1.0 LSB No Missing Codes f S = 50MHz,TA = +25°C Guaranteed No MIssing Codes f S = 40MHz, Full Temp Guaranteed Integral Nonlinearity Error, f = 1MHz –2.0 –4.0 LSBs Spurious Free Dynamic Range(1) f = 1MHz (–1dB input) 83 dBFS (2) f = 10MHz (–1dB input) 67 82 dBFS f = 20MHz (–1dB input) 76 dBFS f = 40MHz (undersampling) 76 dBFS f = 1MHz to 10MHz, fS = 40MHz 2Vp-p, Single-Ended Input 62 69 dBFS Two-Tone Intermodulation Distortion(3) f = 12MHz and 13MHz (–7dB each tone) 71 dBc Signal-to-Noise Ratio (SNR) f = 1MHz (–1dB input) 63 68 dB f = 10MHz (–1dB input) 63 68 dB f = 20MHz (–dB input) 66 dB f = 40MHz (undersampling) 67 dB f = 1MHz to 10MHz, fS = 40MHz 63 67.5 dB f = 1MHz to 10MHz, fS = 40MHz 2Vp-p, Single-Ended Input 60 67 dB f = 1MHz (–1dB input) 3Vp-p 69 dB f = 10MHz (–1dB input) 3Vp-p 69 dB Signal-to-(Noise + Distortion) (SINAD)(4) f = 1MHz (–1dBFS input) 61 67 dB f = 10MHz (–1dBFS input) 61 67 dB f = 20MHz (–1dBFS input) 67 dB f = 1MHz to 10MHz, fS = 40MHz 63 67 dB f = 1MHz to 10MHz, fS = 40MHz 2Vp-p, Single-Ended Input 60 64 dB f = 1MHz (–1dBFS input) 3Vp-p 69 dB f = 10MHz (–dBFS Input) 3Vp-p 69 dB Output Noise Input Grounded 0.2 LSBs rms Aperture Delay Time 2n s Aperture Jitter 1.2 ps rms Overvoltage Recovery Time 2n s DIGITAL INPUTS Logic Family Convert Command Start Conversion High Level Input Current (5) (VIN = 5V) +50 mA Low Level Input Current (VIN = 0V) +10 mA High Level Input Voltage +2.4 V Low Level Input Voltage +1.0 V Input Capacitance 5p F SPECIFICATIONS At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted. CMOS Rising Edge of Convert Clock

At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted. ADS807E PARAMETER CONDITIONS MIN TYP MAX UNITS The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. CMOS Straight Offset Binary DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50mA) VDRV = 5V +0.1 V Low Output Voltage, (IOL = 1.6mA) VDRV = 5V +0.2 V High Output Voltage, (IOH = 50mA) VDRV = 5V +4.9 V High Output Voltage, (IOH = 0.5mA) VDRV = 5V +4.8 V Low Output Voltage, (IOL = 50mA) VDRV = 3V +0.1 V High Output Voltage, (IOH = 50mA) VDRV = 3V +2.8 V 3-State Enable Time OE = L (5) 20 40 ns 3-State Disable Time OE = H (5) 21 0 n s Output Capacitance 5p F ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) Zero Error (Referred to –FS) at 25 °C –1.0 –2.0 %FS Zero Error Drift (Referred to –FS) 16 ppm/ °C Gain Error(6) at 25°C –1.5 –2.5 %FS Gain Error Drift(6) 66 ppm/ °C Gain Error(7) at 25°C –1.0 –1.5 %FS Gain Error Drift(7) 23 ppm/ °C Power Supply Rejection of Gain D VS = –5% 50 70 dB REFT Tolerance 2V Full Scale Deviation From Ideal 3.0V –10 –65 mV 3V Full Scale Deviation From Ideal 3.25V –20 –100 mV REFB Tolerance 2V Full Scale Deviation From Ideal 2.0V –10 –65 mV 3V Full Scale Deviation From Ideal 1.75V –20 –100 mV External REFT Voltage Range REFB + 0.4 3 V S – 1.70 V External REFB Voltage Range 1.70 2 REFT – 0.4 V Reference Input Resistance 1k W POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Operating +4.75 +5.0 +5.25 V Supply Current: +IS Operating 60 mA Power Dissipation: VDRV = 5V External Reference 305 360 mW VDRV = 3V External Reference 290 350 mW VDRV = 5V Internal Reference 350 390 mW VDRV = 3V Internal Reference 335 380 mW Thermal Resistance, qJA 28-Lead SSOP 50 °C/W NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (7) Excludes internal reference.

PIN DESIGNATOR DESCRIPTION

1 GND Ground

2 Bit 1 Data Bit 1 (MSB)

3 Bit 2 Data Bit 2

4 Bit 3 Data Bit 3

5 Bit 4 Data Bit 4

6 Bit 5 Data Bit 5

7 Bit 6 Data Bit 6

8 Bit 7 Data Bit 7

9 Bit 8 Data Bit 8

10 Bit 9 Data Bit 9

11 Bit 10 Data Bit 10

12 Bit 11 Data Bit 11

13 Bit 12 Data Bit 12 (LSB)

14 CLK Convert Clock

16 FS SEL HI = 3V, LO = 2V

17 OTR Out of Range Indicator

18 INT/EXT Reference Select: HIGH or Floating = Exter-

nal LOW = Internal 50kW pull up

19 OE Output Enable

20 GND Ground

21 REFB Bottom Reference/Bypass

22 REFT Top Reference/Bypass

23 CM Common-Mode Voltage Output

24 IN Complementary Analog Input

25 IN Analog Input

26 GND Ground

28 VDRV Logic Driver Supply Voltage

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. GND Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 (LSB) CLK VDRV S GND IN IN CM REFT REFB GND OE INT/EXT OTR FS SEL +V S ADS807E PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER (1) RANGE MARKING NUMBER (2) MEDIA ADS807E 28-Lead SSOP 324 –40 °C to +85°C ADS807E ADS807E Tube " " " " " ADS807E/1K Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book or download from www.burr- pieces of “ADS807E/1K” will get a single 1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION

6 Clock Cycles

N–6 N–5 N–4 N–3 N–2 N–1 N N+1Data Out Clock Analog In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 18.87 100 msn s tL Clock Pulse Low 9.4 t CONV /2 ns tH Clock Pulse High 9.4 t CONV /2 ns tD Aperture Delay 2 ns t1(1) Data Hold Time, CL = 0pF 2.7 ns t2(1) New Data Delay Time, CL = 15pF max 12 ns NOTE: (1) t1 and t2 times are valid for VDRV voltages of +2.7V to +5V.

Frequency (MHz) 0 5 10 15 20 25 Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 21MHz SNR = 68dBFS SFDR = 77dBFS SPECTRAL PERFORMANCE Frequency (MHz) 0 5 10 15 20 25 Magnitude (dBFS) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 fIN = 10MHz SNR = 68dBFS SFDR = 82dBFS SPECTRAL PERFORMANCE Frequency (MHz) 0 5 10 15 20 25 Magnitude (dBFS) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 fIN = 1MHz SNR = 68dBFS SFDR = 83dBFS SPECTRAL PERFORMANCE (Single-Ended, 2Vp-p) Frequency (MHz) 0 4.5 9.0 13.5 Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 10MHz SNR = 68dBFS SFDR = 62dBFS SPECTRAL PERFORMANCE (Sampling Frequency = 27MHz) Frequency (MHz) 0 4.5 9.0 13.5 Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 10MHz SNR = 68dBFS SFDR = 81dBFS TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted. TWO-TONE INTERMODULATION DISTORTION Frequency (MHz) 0 5 10 15 20 25 Magnitude (dBc) –20 –40 –60 –80 –100 f1 = 12MHz f2 = 13MHz IMD(3) = –71dBc

(Sampling Frequency = 53MHz) Frequency (MHz) Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 21MHz SNR = 68dBFS SFDR = 72dBFS SWEPT POWER SFDR Input Amplitude (dBFS) SFDR 100 fIN = 10MHz dBc dBFS UNDERSAMPLING (Sampling Frequency = 27MHz) Frequency (MHz) 0 4.5 9.0 13.5 Magnitude (dBFS) –20 –40 –60 –80 –100 fIN = 50MHz SNR = 65dBFS SFDR = 73dBFS TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted. DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (Differential Input) Sampling Frequency (MHz) SFDR, SNR (dB) 35 40 45 50 55 60 SNR (3Vp-p) SNR (2Vp-p) SFDR (2Vp-p) SFDR (3Vp-p) fIN = 5MHz SINAD vs SAMPLING FREQUENCY (Differential Input) Sampling Frequency (MHz) SINAD (dB) 35 40 45 50 55 60 3Vp-p 2Vp-p fIN = 5MHz 800k 600k 400k 200k OUTPUT NOISE HISTOGRAM (DC INPUT) Counts N-2 N-1 N N+1 N+2 Code 3V Full Scale

DIFFERENTIAL LINEARITY ERROR (Single-Ended, Input Sampling Frequency = 40MHz) Output Codes DLE (LSB) 1.000 0.500 –0.500 –1.000 10240 2048 3072 4096 fIN = 10MHz INTEGRAL LINEARITY ERROR (Sampling Frequency = 40MHz) Output Codes ILE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 10240 2048 3072 4096 fIN = 10MHz INTEGRAL LINEARITY ERROR Output Codes ILE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 10240 2048 3072 4096 fIN = 10MHz DIFFERENTIAL LINEARITY ERROR Output Codes DLE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 10240 2048 3072 4096 fIN = 10MHz INTEGRAL LINEARITY ERROR Output Codes ILE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 0 1024 2048 3072 4096 fIN = 1MHz DIFFERENTIAL LINEARITY ERROR Output Codes DLE (LSB) 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 10240 2048 3072 4096 fIN = 1MHz TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted.

• even-order harmonics are minimized
• improves the noise immunity based on the converter’s common-mode input rejection Using the single-ended mode, the signal is applied to one of the inputs, while the other input is biased with a DC voltage to the required common-mode level. Both inputs are equal in terms of their impedance and performance, except that applying the signal to the complementary input (IN) instead of the IN input will invert the input signal relative to the output code. For example, in case the input driver operates in inverting mode, using IN as the signal input will restore the phase of the signal to its original orientation. Time- domain applications may benefit from a single-ended inter- face configuration and its reduced circuit complexity. While maintaining good signal-to-noise ratio (SNR), driving the ADS807 with a single-ended signal will result in a reduction of the distortion performance. Employing dual supply am- plifiers and AC-coupling will usually yield the best results, while DC-coupling and/or single-supply amplifiers impose additional design constraints due to their headroom require- ments, especially when selecting the 3Vp-p input range. However, single-supply amplifiers have the advantage of inherently limiting their output swing to within the supply rails. Alternatively, a voltage limiting amplifier, like the OPA688, may be considered to set fixed-signal limits and avoid any severe overrange condition for the A/D converter. The full-scale input range of the ADS807 is defined by the reference voltages. For example, setting the range select pin to FS SEL = LOW, and using the internal references (REFT = +3.0V and REFTB = +2.0V), the full-scale range is defined to: FSR = 2 • (REFT – REFB) = 2Vp-p. The trade-off of the differential input configuration versus the single-ended is its higher complexity. In either case, the selection of the driver amplifier should be such that the amplifier’s performance will not degrade the A/D’s perfor- mance. The ADS807 operates on a single power supply, which requires a level shift to a ground-based bipolar input signals to comply with its input voltage range requirements. The input of the ADS807 is of a capacitive nature and the driving source needs to provide the current to charge or discharge the input sampling capacitor while the track-and- hold is in track mode. This effectively results in a dynamic input impedance which depends on the sampling frequency. It most applications, it is recommended to add a series resistor, typically 20W to 50W , between the drive source and the converter inputs. This will isolate the capacitive input from the source, which can be crucial to avoid gain peaking when using wideband operational amplifiers. Secondly, it will create a first-order, low-pass filter in conjunction with the specified input capacitance of the ADS807. Its cut-off frequency can be adjusted even further by adding an external shunt capacitor from each signal input to ground. The optimum values of this R-C network depend on a variety of factors which include the ADS807 sampling rate, the se- lected op amp, the interface configuration and the particular application (time domain versus frequency domain). Gener- ally, increasing the size of the series resistor and/or capacitor

APPLICATION INFORMATION

The ADS807 is a high-speed CMOS A/D converter which employs a pipelined converter architecture consisting of 12 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 12-bit level. The output data be- comes valid after the rising clock edge (see Timing Dia- gram). The pipeline architecture results in a data latency of 6 clock cycles. The analog input of the ADS807 consists of a differential track-and-hold circuit. The differential topology along with tightly matched poly-poly capacitors produce a high level of AC performance at high sampling rates and in undersampling applications. Both inputs (IN, IN) require external biasing using a com- mon-mode voltage that is typically at the mid-supply level (+V S/2). DRIVING THE ANALOG INPUTS The analog inputs of the ADS807 are a very high imped- ance. They should be driven through an R-C network designed to pass the highest frequency of interest. This prevents high frequency noise in the input from affecting SFDR and SNR. The ADS807 can be used in a wide variety of applications and deciding on the best performing analog interface circuit depends on the type of application. The circuit definition should include considerations of input frequency spectrum and amplitude, single-ended or differ- ential drive and available power supplies. For example, communication (frequency domain) applications process frequency bands not including DC. In imaging (time do- main) applications, the input DC component must be main- tained into the A/D converter. Features of the ADS807, including full-scale select (FS SEL ), external reference, and CM output provide flexibility to accommodate a wide range of applications. The ADS807 should be configured to meet application objectives while observing the headroom re- quirements of the driving amplifiers to yield the best overall performance. The ADS807 input structure allows it to be driven either single-ended or differentially. Differential operation of the ADS807 requires an in-phase input signal and a 180° out-of- phase part simultaneously applied to the inputs (IN, IN). The differential operation offers a number of advantages which, in most applications, will be instrumental in achiev- ing the best dynamic performance of the ADS807:

• the signal swing is half of that required for the single- ended operation and therefore, is less demanding to achieve while maintaining good linearity performance from the signal source
• the reduced signal swing allows for more headroom in the interface circuitry and therefore, a wider selection of the best suitable driver op amp

INPUT REFERENCE IN (Pin-25) IN (Pin-24) REFT REFB 2Vp-p Differential Internal 2V to 3V 3V to 2V +3V +2V 1Vp-p Times 2 Inputs or External 2Vp-p Single-Ended Internal 1.5V to 3.5V 2.5V DC +3V +2V 2Vp-p Times 1 Input or External 1.5Vp-p Times 2 Inputs or External 3Vp-p Single-Ended Internal 1V to 4V 2.5V DC +3.25V +1.75V 3Vp-p Times 1 Input or External TABLE III. Coding Table for Single-Ended Input Config- uration with IN Tied to the Common-Mode Voltage. TABLE II. Coding Table for Single-Ended Input Configura- tion with IN Tied to the Common-Mode Voltage. DIGITAL INPUTS AND OUTPUTS Clock Input Requirements Clock jitter is critical to the SNR performance of high speed, high resolution A/D converters. Clock jitter leads to aperture jitter (t A ), which adds noise to the signal being converted. The ADS807 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation. If this value is near your system requirements, input clock jitter must be reduced. where: ƒ IN is input signal frequency tA is rms clock jitter Particularly in undersampling applications, special consider- ation should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have 50% duty cycle (t H = tL), along with fast rise and fall times of 2ns or less. Over Range Indicator (OTR) If the analog input voltage exceeds the set full-scale range, an over range condition exists. The ‘OTR’ pin of the ADS807 can be used to monitor any such out-of-range condition. This ‘OTR’ output is updated along with the data output corre- sponding to the particular sampled analog input voltage. Therefore, the OTR data is subject to the same pipeline delay as the digital data. The OTR output is LOW when the input voltage is within the defined input range. It will go to HIGH if the applied signal exceeds the full-scale range. Data Outputs The output data format of the ADS807 is in positive Straight Offset Binary code, see Table II and Table II. This format can easily be converted into the Two’s Binary Complement code by inverting the MSB. It is recommended that the capacitive loading on the data lines be as low as possible (< 15pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the analog portion of the ADS807 and affect the performance. If necessary, external buffers or latches close SINGLE-ENDED INPUT STRAIGHT OFFSET BINARY (IN = CM, Pin-23) (SOB) +FS–1LSB (IN = CMV + FSR/2) 1111 1111 1111 +1/2 FS 1100 0000 0000 Bipolar Zero (IN = VCM ) 1000 0000 0000 –1/2 FS 0100 0000 0000 –FS (IN = CMV – FSR/2) 0000 0000 0000STRAIGHT OFFSET BINARY DIFFERENTIAL INPUT (SOB) +FS-1LSB (IN = +3V, IN = +2V) 1111 1111 1111 +1/2 FS 1100 0000 0000 Bipolar Zero (IN = IN = VCM ) 1000 0000 0000 –1/2 FS 0100 0000 0000 –FS (IN = +2V, IN = +3V) 0000 0000 0000 Jitter SNR t rms signal torms noise IN A = ƒ20 1 2log p TABLE I. Reference Voltages for Input Signal Ranges. to the converter’s output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS807 from high frequency digital noise on the bus coupling back into the converter. Digital Output Driver Supply (VDRV) The ADS807 features a dedicated supply pin for the output logic drivers, VDRV, which is not internally connected to the other supply pins. Setting the voltage at VDRV to +5V or +3V, the ADS807 produces corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recom- mended to use the ADS807 with +3V logic supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the AC performance of the converter. In some applications, it might be advantageous to decouple the VDRV pin with additional capacitors or a pi-filter. GROUNDING AND DECOUPLING Proper grounding, bypassing, short trace lengths, and the use of power and ground planes are particularly important for high frequency designs. Multilayer PC boards are recom- mended for best performance since they offer distinct advan- tages such as minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS807 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable performance. All ground connections on the ADS807 are internally joined together obviating the design of split ground planes. The ground pins (1, 20, 26) should directly connect

FIGURE 8. Recommended Bypassing for the Supply Pins.