ADS805_V01 TI | Alldatasheet
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Technical content
12-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER
FEATURES
G HIGH SFDR: 74dB at 9.8MHz fIN G HIGH SNR: 68dB G LOW POWER: 300mW G LOW DLE: 0.25LSB G FLEXIBLE INPUT RANGE G OVER-RANGE INDICATOR
APPLICATIONS
G IF AND BASEBAND DIGITIZATION G COPIERS G TEST INSTRUMENTATION
DESCRIPTION
The ADS805 is a 20MHz, high dynamic range, 12-bit, pipelined Analog-to-Digital Converter ADC. This converter includes a high-bandwidth track-and-hold that gives excellent spurious performance up to and beyond the Nyquist rate. This high- bandwidth, linear track-and-hold minimizes harmonics and has low jitter, leading to excellent Signal-to-Noise Ratio (SNR) performance. The ADS805 is also pin-compatible with the 10MHz ADS804 and the 5MHz ADS803. The ADS805 provides an internal reference or an external reference can be used. The ADS805 can be programmed for a 2Vp-p input range which is the easiest to drive with a single op amp and provides the best spurious performance. Alter- natively, the 5Vp-p input range can be used for the lowest input-referred noise of 0.09LSBs rms giving superior imaging performance. There is also the capability to set the input range between 2Vp-p and 5Vp-p, either single-ended or differential. The ADS805 also provides an over-range flag that indicates when the input signal has exceeded the converter’s full-scale range. This flag can also be used to reduce the gain of the front end signal conditioning circuitry. The ADS805 employs digital error techniques to provide excellent differential linearity for demanding imaging applica- tions. Its low distortion and high SNR give the extra margin needed for communications, medical imaging, video, and test instrumentation applications. The ADS805 is available in an SSOP-28 package. 12-Bit Pipelined ADC Core Reference and Mode Select Reference Ladder and Driver Timing Circuitry Error Correction Logic 3-State OutputsT&H D11
- •• CLK+V S ADS805 VDRV OESEL REFBVREFREFT INVIN IN CM OVR ADS805 SBAS073B – JANUARY 1997 – REVISED NOVEMBER 2002 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ADS805E
SBAS073Bwww.ti.com ABSOLUTE MAXIMUM RATINGS (1) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ADS805E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 12 Bits Tested SPECIFIED TEMPERATURE RANGE –40 to +85 °C CONVERSION CHARACTERISTICS Sample Rate 10k 20M Samples/s Data Latency 6 Clk Cycles ANALOG INPUT Standard Single-Ended Input Range 1.5 3.5 V Optional Single-Ended Input Range 0 5 V Standard Common-Mode Voltage 2.5 V Standard Optional Common-Mode Voltage 1 V Input Capacitance 20 pF Analog Input Bandwidth –3dBFS Input 270 MHz DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz ±0.25 ±0.75 LSB No Missing Codes Tested Spurious-Free Dynamic Range (1) f = 9.8MHz 65 74 dBFS (2) 2-Tone Intermodulation Distortion(3) f = 7.7MHz and 7.9MHz (–7dB each tone) –70 dBc Signal-to-Noise Ratio (SNR) f = 9.8MHz 63 68 dBFS Signal-to-(Noise + Distortion) (SINAD) f = 9.8MHz 62 66 dBFS Effective Number of Bits at 9.8MHz(4) 10.7 Bits Input Referred Noise 0V to 5V Input 0.09 LSBs rms 1.5V to 3.5V Input 0.23 LSBs rms Integral Nonlinearity Error f = 500kHz ±1 ±2L S B Aperture Delay Time 3n s Aperture Jitter 4 ps rms Over-Voltage Recovery Time 1.5x FS Input 2 ns Full-Scale Step Acquisition Time 20 ns
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, and single-ended input and sampling rate = 20MHz, unless otherwise specified. NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full-scale. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (4) Effective SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR (1) RANGE MARKING NUMBER (2) MEDIA, QUANTITY ADS805 SSOP-28 DB –40°C to +85°C ADS805E ADS805E Rails, 48 " """ " ADS805E/1K Tape and Reel, 1000 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PACKAGE/ORDERING INFORMATION NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
SBAS073B www.ti.com ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, and single-ended input and sampling rate = 20MHz, unless otherwise specified. ADS805E PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Logic Family CMOS Compatible Convert Command Start Conversion Rising Edge of Convert Clock High Level Input Current (V IN = 5V)(5) ±100 µA Low Level Input Current (VIN = 0V) 10 µA High Level Input Voltage +3.5 V Low Level Input Voltage +1.0 V Input Capacitance 5p F DIGITAL OUTPUTS Logic Family CMOS/TTL Compatible Logic Coding Straight Offset Binary Low Output Voltage (I OL = 50µA) 0.1 V Low Output Voltage (I OL = 1.6mA) 0.4 V High Output Voltage (I OH = 50µA) +4.5 V High Output Voltage (I OH = 0.5mA) +2.4 V 3-State Enable Time OE = L 20 40 ns 3-State Disable Time OE = H 2 10 ns Output Capacitance 5p F ACCURACY (5Vp-p Input Range) fS = 2.5MHz Zero-Error (Referred to –FS) At 25 °C 0.3 ±1.5 %FS Zero-Error Drift (Referred to –FS) ±5 ppm/ °C Gain Error(6) At 25°C 0.7 ±2.0 %FS Gain Error Drift(6) ±18 ppm/ °C Gain Error(7) At 25°C 0.2 ±1.5 %FS Gain Error Drift(7) ±10 ppm/ °C Power-Supply Rejection of Gain ∆VS = ±5% 60 70 dB Reference Input Resistance 1.6 k Ω Internal Voltage Reference Tolerance (VREF = 2.5V) At 25°C ±35 mV Internal Voltage Reference Tolerance (VREF = 1.0V) At 25°C ±14 mV POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Operating +4.75 +5.0 +5.25 V Supply Current: +IS Operating 60 69 mA Power Dissipation Operating 300 345 mW Thermal Resistance, θJA SSOP-28 50 °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full-scale. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (4) Effective
SBAS073Bwww.ti.com
6 Clock Cycles
N – 6N – 5N – 4N – 3N – 2N – 1 N N + 1Data Out Clock Analog In N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 PIN CONFIGURATION PIN DESIGNATOR DESCRIPTION
1 OVR Over-Range Indicator
2 B1 Data Bit 1 (D11) (MSB)
3 B2 Data Bit 2 (D10)
4 B3 Data Bit 3 (D9)
5 B4 Data Bit 4 (D8)
6 B5 Data Bit 5 (D7)
7 B6 Data Bit 6 (D6)
8 B7 Data Bit 7 (D5)
9 B8 Data Bit 8 (D4)
10 B9 Data Bit 9 (D3)
11 B10 Data Bit 10 (D2)
12 B11 Data Bit 11 (D1)
13 B12 Data Bit 12 (D0) (LSB)
14 CLK Convert Clock Input
15 OE Output Enable. H = High Impedance State. L = LOW or floating, normal operation (internal pull-down resistor). 16 +V S +5V Supply
17 GND Ground
18 SEL Input Range Select
REF Reference Voltage Select
20 REFB Bottom Reference
21 CM Common-Mode Voltage
22 REFT Top Reference
23 IN Complementary Analog Input
24 GND Ground
25 IN Analog Input (+)
26 GND Ground
28 VDRV Output Driver Voltage
SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 50 100 µsn s tL Clock Pulse LOW 24 25 ns tH Clock Pulse HIGH 24 25 ns tD Aperture Delay 3 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12 ns Top View SSOP OVR B10 B11 B12 CLK VDRV S GND IN GND IN REFT CM REFB V REF SEL GND S OE ADS805
SBAS073B www.ti.com TYPICAL CHARACTERISITCS At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 20MHz, unless otherwise specified. SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 fIN = 500kHz SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 fIN = 9.8MHz 2-TONE INTERMODULATION DISTORTION Frequency (MHz) Magnitude (dBFS) –20 –40 –60 –80 –100 –120 0 2.5 5.0 7.5 10.0 f7 = 7.7MHz at –7dBFS f2 = 7.9MHz at –7dBFS IMD (3) = –70dBc DIFFERENTIAL LINEARITY ERROR Output Code Code Width Error (LSB) 0 1024 2048 3072 4096 fIN = 9.8MHz 1.0 0.5 –0.5 –1.0 INTEGRAL LINEARITY ERROR Output Code ILE (LSB) 0 1024 2048 3072 4096 4.0 2.0 –2.0 –4.0 fIN = 500kHz 100 SWEPT POWER SFDR SFDR (dBFS, dBc) Input Amplitude (dBFS) dBFS dBc fIN = 9.8MHz
SBAS073Bwww.ti.com TYPICAL CHARACTERISITCS (Cont.) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 20MHz, unless otherwise specified. DYNAMIC PERFORMANCE vs INPUT FREQUENCY SFDR, SNR (dBFS) 0.1 1 Frequency (MHz) SFDR SNR 0.6 0.4 0.2 DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE DLE (LSB) –50 –25 0 25 50 75 100 Temperature (°C) fIN = 9.8MHz fIN = 500kHz SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE SFDR (dBFS) –50 –25 0 25 50 100 75 Temperature (°C) fIN = 500kHz fIN = 9.8MHz SIGNAL-TO-NOISE RATIO vs TEMPERATURE SNR (dBFS) –50 –25 0 25 50 75 100 Temperature (°C) fIN = 9.8MHz fIN = 500kHz SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE SINAD (dBFS) –50 –25 0 25 50 75 100 Temperature (°C) fIN = 9.8MHz fIN = 500kHz 305 300 295 290 POWER DISSIPATION vs TEMPERATURE Power (mW) –50 –25 0 25 50 100 75 Temperature (°C)
SBAS073B www.ti.com TYPICAL CHARACTERISITCS (Cont.) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 20MHz, unless otherwise specified. 800k 600k 400k 200k OUTPUT NOISE HISTOGRAM (DC Input) Counts N – 2N – 1 N N + 1 N + 2 Code 800k 600k 400k 200k OUTPUT NOISE HISTOGRAM (DC Input, V IN = 5Vp-p Range) Counts N – 2N – 1 N N + 1 N + 2 Code –20 –40 –60 –80 –100 –120 UNDERSAMPLING (Differential Input, 2Vp-p) Magnitude (dB) Frequency (MHz) fS = 20MHz fIN = 41MHz SNR = 63.2dBFS SFDR = 76.3dBFS
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS805E Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS805E ADS805E.B Active Production SSOP (DB) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS805E ADS805E/1K Active Production SSOP (DB) | 28 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS805E ADS805E/1K.B Active Production SSOP (DB) | 28 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS805E ADS805E/1K1G4 Active Production SSOP (DB) | 28 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS805E ADS805E/1K1G4.B Active Production SSOP (DB) | 28 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS805E (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 7-Oct-2025 Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS805E/1K SSOP DB 28 1000 350.0 350.0 43.0 ADS805E/1K1G4 SSOP DB 28 1000 350.0 350.0 43.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADS805E DB SSOP 28 50 530 10.5 4000 4.1 ADS805E.B DB SSOP 28 50 530 10.5 4000 4.1 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 26X 0.65 8.45 28X 0.38 0.22 8.2
7.4 TYP
0.05 MIN
0.25 GAGE PLANE 0 -8
2 MAX
B 5.6 5.0 NOTE 4 A 10.5 9.9 NOTE 3 0.95 0.55 (0.15) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018
0.15 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 1.500
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 14 15 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 14 15
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