ADS805

ADS805 BURR-BROWN | Alldatasheet

Document overview

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Technical content

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-1397C Printed in U.S.A. October, 1998 12-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM

FEATURES

l HIGH SFDR: 74dB at 9.8MHz fIN l HIGH SNR: 68dB l LOW POWER: 300mW l LOW DLE: 0.25LSB l SMALL 28-LEAD SSOP AND SOIC PACKAGES l FLEXIBLE INPUT RANGE l OVER-RANGE INDICATOR

APPLICATIONS

l IF AND BASEBAND DIGITIZATION l COPIERS l TEST INSTRUMENTATION

DESCRIPTION

The ADS805 is a 20MHz, high dynamic range, 12-bit pipelined analog-to-digital converter. This converter includes a high-band- width track/hold that gives excellent spurious performance up to and beyond the Nyquist rate. This high-bandwidth, linear track/hold minimizes harmonics and has low jitter, leading to excellent SNR performance. The ADS805 is also pin-compatible with the 10MHz ADS804 and the 5MHz ADS803. The ADS805 provides an internal reference or an external reference can be used. ADS805 can be programmed for a 2Vp-p input range which is the easiest to drive with a single op amp and provides the best spurious performance. Alternatively, the 5Vp-p input range can be used for the lowest input-referred noise of 0.09 LSBs rms giving ADS805U ADS805E superior imaging performance. There is also the capability to set the input range between 2Vp-p and 5Vp-p, either single-ended or differential. The ADS805 also provides an overrange flag that indicates when the input signal has exceeded the converter’s full scale range. This flag can also be used to reduce the gain of the front end signal conditioning circuitry. The ADS805 employs digital error techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for commu- nications, medical imaging, video and test instrumentation applica- tions. The ADS805 is available in 28-lead SSOP and SOIC pack- ages. 12-Bit Pipelined A/D Core Reference and Mode Select Reference Ladder and Driver Timing Circuitry Error Correction Logic 3-State OutputsT/H D11

• •• CLK+VS ADS805 VDRV OESEL REFBVREFREFT INVIN IN CM OVR

At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 20MHz, unless otherwise specified. ADS805U ADS805E PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 Bits Guaranteed [ (1) Bits SPECIFIED TEMPERATURE RANGE –40 to +85 –40 to +85 °C CONVERSION CHARACTERISTICS Sample Rate 10k 20M [[ Samples/s Data Latency 6 [ Clk Cycles ANALOG INPUT Standard Single-Ended Input Range 1.5 3.5 [[ V Optional Single-Ended Input Range 0 5 [[ V Standard Common-Mode Voltage 2.5 [ V Standard Optional Common-Mode Voltage 1 [ V Input Capacitance 20 [ pF Track-Mode Input Bandwidth –3dBFS Input 270 [ MHz DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz ±0.25 ±0.75 [[ LSB No Missing Codes Guaranteed Guaranteed Spurious Free Dynamic Range(2) f = 9.8MHz 65 74 [[ dBFS Two-Tone Intermodulation Distortion(4) f = 7.7MHz and 7.9MHz (–7dB each tone) –70 [ dBc Signal-to-Noise Ratio (SNR) f = 9.8MHz 63 68 [[ dBFS Signal-to-(Noise + Distortion) (SINAD) f = 9.8MHz 62 66 [[ dBFS Effective Number of Bits at 9.8MHz(5) 10.7 [ Bits Input Referred Noise 0V to 5V Input 0.09 [ LSBs rms 1.5V to 3.5V Input 0.23 [ LSBs rms Integral Nonlinearity Error f = 500kHz ±1 ±2 [[ LSB Aperture Delay Time 3 [ ns Aperture Jitter 4 [ ps rms Overvoltage Recovery Time 1.5X FS Input 2 [ ns Full-Scale Step Acquisition Time 20 20 ns DIGITAL INPUTS Logic Family Convert Command Start Conversion High Level Input Current (V Low Level Input Current (VIN = 0V) 10 [ µA High Level Input Voltage +3.5 [ V Low Level Input Voltage +1.0 [ V Input Capacitance 5 [ pF DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (I OL = 50µA) 0.1 [ V Low Output Voltage (I OL = 1.6mA) 0.4 [ V High Output Voltage (I OH = 50µA) +4.5 [ V High Output Voltage (I OH = 0.5mA) +2.4 [ V 3-State Enable Time OE = L 20 40 [[ ns 3-State Disable Time OE = H 2 10 [[ ns Output Capacitance 5 [ pF ACCURACY (5Vp-p Input Range) Zero Error (Referred to –FS) At 25 °C 0.3 ±1.5 [[ %FS Zero Error Drift (Referred to –FS) ±5 [ ppm/°C Gain Error(7) At 25°C 0.7 ±2.0 [ %FS Gain Error Drift(7) ±18 [ ppm/°C Gain Error(8) At 25°C 0.2 ±1.5 [ %FS Gain Error Drift(8) ±10 [ ppm/°C Power Supply Rejection of Gain Δ VS = ±5% 60 70 [[ dB Reference Input Resistance 1.6 [ kΩ Internal Voltage Reference Tolerance (VREF = 2.5V) At 25°C ±35 [ mV Internal Voltage Reference Tolerance (VREF = 1.0V) At 25°C ±14 [ mV CMOS/TTL Compatible Straight Offset Binary CMOS/TTL Compatible Straight Offset Binary CMOS Compatible Rising Edge of Convert Clock CMOS Compatible Rising Edge of Convert Clock

Supply Voltage: +VS Operating +4.75 +5.0 +5.25 [[[ V Supply Current: +IS Operating 60 69 [[ mA Power Dissipation Operating 300 345 [[ mW Thermal Resistance, θJA 28-Lead SOIC 75 °C/W 28-Lead SSOP 50 °C/W NOTES: (1) An asterisk ([ ) indicates same specifications as the ADS805U. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to full scale. (4) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (6) Internal 50kΩ pull down resistor. (7) Includes internal reference. (8) Excludes internal reference. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. SPECIFICATIONS (CONT) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 20MHz, unless otherwise specified. ADS805U ADS805E PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PRODUCT DEMO BOARD ADS805U DEM-ADS80xU DEMO BOARD ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER (1) RANGE MARKING NUMBER MEDIA ADS805U SO-28 Surface Mount 217 –40 °C to +85°C ADS805U ADS805U Rails ADS805E SSOP-28 Surface Mount 324 –40 °C to +85°C ADS805E ADS805E Rails " " " " " ADS805E/1K Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. For detailed Tape and Reel mechanical information refer to Appendix B of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION

6 Clock Cycles

N–6 N–5 N–4 N–3 N–2 N-1 N N+1Data Out Clock Analog In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 PIN CONFIGURATION PIN DESIGNATOR DESCRIPTION

1 OVR Over Range Indicator

2 B1 Data Bit 1 (D11) (MSB)

3 B2 Data Bit 2 (D10)

4 B3 Data Bit 3 (D9)

5 B4 Data Bit 4 (D8)

6 B5 Data Bit 5 (D7)

7 B6 Data Bit 6 (D6)

8 B7 Data Bit 7 (D5)

9 B8 Data Bit 8 (D4)

10 B9 Data Bit 9 (D3)

11 B10 Data Bit 10 (D2)

12 B11 Data Bit 11 (D1)

13 B12 Data Bit 12 (D0) (LSB)

14 CLK Convert Clock Input

15 OE Output Enable. H = High Impedance State. L = LOW or floating, normal operation (internal pull-down resistor). 16 +V S +5V Supply

17 GND Ground

18 SEL Input Range Select

REF Reference Voltage Select

20 REFB Bottom Reference

21 CM Common-Mode Voltage

22 REFT Top Reference

23 IN Complementary Analog Input

24 GND Ground

25 IN Analog Input (+)

26 GND Ground

28 VDRV Output Driver Voltage

SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 50 100 µsn s tL Clock Pulse Low 24 25 ns tH Clock Pulse High 24 25 ns tD Aperture Delay 3 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12 ns Top View SOIC/SSOP OVR B10 B11 B12 CLK VDRV S GND IN GND IN REFT CM REFB V REF SEL GND S OE ADS805

ILE (LSB) 0 1024 2048 3072 4096 4.0 2.0 –2.0 –4.0 fIN = 500kHz TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 20MHz, unless otherwise specified. SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 fIN = 500kHz SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 fIN = 9.8MHz FREQUENCY SPECTRUM Frequency (MHz) Magnitude (dBFSR) –20 –40 –60 –80 –100 –120 0 2.5 5.0 7.5 10.0 f7 = 7.7MHz at –7dBFS f2 = 7.9MHz at –7dBFS IMD (3) = –70dBc DIFFERENTIAL LINEARITY ERROR Output Code Code Width Error (LSB) 0 1024 2048 3072 4096 fIN = 9.8MHz 1.0 0.5 –0.5 –1.0 100 SWEPT POWER SFDR SFDR (dBFS, dBc) Input Amplitude (dBFS) dBFS dBc fIN = 9.8MHz

TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 20MHz, unless otherwise specified. 0.6 0.4 0.2 DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE DLE (LSB) –50 –25 0 25 50 75 100 Temperature (°C) fIN = 9.8MHz fIN = 500kHz SIGNAL-TO-NOISE RATIO vs TEMPERATURE SNR (dBFS) –50 –25 0 25 50 75 100 Temperature (°C) fIN = 9.8MHz fIN = 500kHz SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE SINAD (dBFS) –50 –25 0 25 50 75 100 Temperature (°C) fIN = 9.8MHz fIN = 500kHz 305 300 295 290 POWER DISSIPATION vs TEMPERATURE Power (mW) –50 –25 0 25 50 100 75 Temperature (°C) DYNAMIC PERFORMANCE vs INPUT FREQUENCY SFDR, SNR (dBFS) 0.1 1 Frequency (MHz) SFDR SNR SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE SFDR (dBFS) –50 –25 0 25 50 100 75 Temperature (°C) fIN = 500kHz fIN = 9.8MHz

–20 –40 –60 –80 –100 –120 UNDERSAMPLING (Differential Input, 2Vp-p) Magnitude (dB) Frequency (MHz) fS = 20MHz fIN = 41MHz SNR = 63.2dBFS SFDR = 76.3dBFS TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 20MHz, unless otherwise specified. 800k 600k 400k 200k OUTPUT NOISE HISTOGRAM (DC INPUT) Counts N-2 N-1 N N+1 N+2 Code 800k 600k 400k 200k OUTPUT NOISE HISTOGRAM (DC Input, V IN = 5Vp-p Range) Counts N-2 N-1 N N+1 N+2 Code

APPLICATION INFORMATION

The ADS805 allows its analog inputs to be driven either single-ended or differentially. The focus of the following discussion is on the single-ended configuration. Typically, its implementation is easier to achieve and the rated speci- fications for the ADS805 are characterized using the single- ended mode of operation. AC-COUPLED INPUT CONFIGURATION Given in Figure 1 is the circuit example of the most common interface configuration for the ADS805. With the V REF pin connected to the SEL pin, the full-scale input range is defined to be 2Vp-p. This signal is ac-coupled in single- ended form to the ADS805 using the low distortion voltage- feedback amplifier OPA642. As is generally necessary for single-supply components, operating the ADS805 with a full-scale input signal swing requires a level-shift of the amplifier’s zero centered analog signal to comply with the A/D converter’s input range requirements. Using a DC blocking capacitor between the output of the driving ampli- fier and the converter’s input, a simple level-shifting scheme can be implemented. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3V and +2V, respectively. Here, two resistor pairs (2 x 2kΩ ) are used to create a common-mode voltage of approxi- mately +2.5V to bias the inputs of the ADS805 (IN, IN) to the required DC voltage. An advantage of ac-coupling is that the driving amplifier still operates with a ground-based signal swing. This will keep the distortion performance at its optimum since the signal swing stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. Consider using the inverting gain configuration to eliminate CMR induced errors of the amplifier. The addition of a small series resistor (R S) between the output of the op amp and the input of the ADS805 will be beneficial in almost all interface configurations. This will decouple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion perfor- mance, the resistor value should be kept below 100Ω . Furthermore, the series resistor, together with the 100pF capacitor, establish a passive low-pass filter, limiting the bandwidth for the wideband noise, thus help improving the signal-to-noise performance. DC-COUPLED WITHOUT LEVEL SHIFT In some applications the analog input signal may already be biased at a level which complies with the selected input range and reference level of the ADS805. In this case, it is only necessary to provide an adequately low source imped- ance to the selected input, IN or IN. Always consider wideband op amps since their output impedance will stay low over a wide range of frequencies. DC-COUPLED WITH LEVEL SHIFT Several applications may require that the bandwidth of the signal path includes DC, in which case the signal has to be DC-coupled to the A/D converter. In order to accomplish this, the interface circuit has to provide a DC-level shift. The circuit shown in Figure 2 utilizes the single-supply, current feedback op amp OPA681 (A1), to sum the ground centered input signal with a required DC offset. The ADS805 typi- cally operates with a +2.5V common-mode voltage, which is established with resistors R 3 and R4 and connected to the IN input of the converter. Amplifier A1 operates in inverting configuration. Here, resistors R 1 and R2 set the DC-bias level for A1. Because of the op amp’s noise gain of +2V/V, assuming R F = RIN, the DC offset voltage applied to its non- inverting input has to be divided down to +1.25V, resulting in a DC output voltage of +2.5V. DC voltage differences between the IN and IN inputs of the ADS805 effectively will produce an offset, which can be corrected for by adjusting FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal Top and Bottom Reference.

line may help maintain the ac performance of the ADS805. change from L to H or H to L. depends on the proximity to the individual supply pin. ity to the converter circuit. FIGURE 11. External Logic for Decoding Underrange and clock signal may cause degradation of the performance. VDRV, the digital output levels will vary respectively. 3V-logic with the VDRV pin tied to the +3V digital supply. demand higher charging currents as the output are changing.