ADS803U

ADS803 BURR-BROWN | Alldatasheet

Document overview

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Technical content

12-Bit, 5MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM

FEATURES

l HIGH SFDR: 82dB at NYQUIST l HIGH SNR: 69dB l LOW POWER: 115mW l LOW DLE: 0.25LSB l SMALL 28-LEAD SSOP AND SOIC PACKAGES l FLEXIBLE INPUT RANGE l OVER-RANGE INDICATOR

APPLICATIONS

l IF AND BASEBAND DIGITIZATION l CCD IMAGING SCANNERS l TEST INSTRUMENTATION

DESCRIPTION

The ADS803 is a high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter. This converter includes a high-band- width track/hold that gives excellent spurious performance up to and beyond the Nyquist rate. This high-bandwidth, linear track/hold minimizes harmonics and has low jitter, leading to excellent SNR performance. The ADS803 is also pin-compatible with the 10MHz ADS804 and the 20MHz ADS805. The ADS803 provides an internal reference and can be programmed for a 2Vp-p input range for the best spurious performance and ease of driving. Alternatively, the 5Vp-p input range can be used for the lowest input referred noise of 0.09 LSBs rms giving superior imaging performance. There is also a capability to set the input range in between the 2Vp-p and 5Vp-p input ranges or to use external reference. The ADS803 also provides an overrange indica- tor flag to indicate an input range that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of the front end gain-ranging circuitry. The ADS803 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for communications, medical imaging, video and test instrumentation applications. The ADS803 is available in 28-lead SSOP and SOIC packages. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-1398C Printed in U.S.A. October, 1998 12-Bit Pipelined A/D Core Reference and Mode Select Reference Ladder and Driver Timing Circuitry Error Correction Logic 3-State OutputsT/H D11

• •• CLK+V S ADS803 VDRV OESEL REFBVREFREFT INVIN IN CM OVR

At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified. CMOS/TTL Compatible Straight Offset Binary CMOS/TTL Compatible Straight Offset Binary CMOS Compatible Rising Edge of Convert Clock CMOS Compatible Rising Edge of Convert Clock ADS803U ADS803E PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 Guaranteed [ (1) Bits SPECIFIED TEMPERATURE RANGE –40 to +85 –40 to +85 °C CONVERSION CHARACTERISTICS Sample Rate 10k 5M [[ Samples/s Data Latency 6 [ Clk Cycles ANALOG INPUT Single-Ended Input Range 1.5 3.5 [[ V Standard Optional Single-Ended Input Range 0 5 [[ V Common-Mode Voltage 2.5 [ V Standard Optional Common-Mode Voltage 1 [ V Input Capacitance 20 [ pF Track-Mode Input Bandwidth –3dBFS Input 270 [ MHz DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz ±0.25 ±0.75 [[ LSB No Missing Codes Guaranteed Guaranteed Spurious Free Dynamic Range(2) f = 2.48MHz (–1dB input) 74 82 [[ dBFS Two-Tone Intermodulation Distortion(4) 74 [ dBc f = 1.8M and 1.9M (–7dBFS each tone) Signal-to-Noise Ratio (SNR) f = 2.48MHz (–1dB input) 66.5 69 [[ dB Signal-to-(Noise + Distortion) (SINAD) f = 2.48MHz (–1dB input) 65 68 [[ dB Effective Number of Bits at 2.48MHz(5) 11 [ Bits Input Referred Noise 0V to 5V Input 0.09 [ LSBs rms 1.5V to 3.5V Input 0.23 [ LSBs rms Integral Nonlinearity Error f = 500kHz ±1 ±2 [[ LSB Aperture Delay Time 1 [ ns Aperture Jitter 4 [ ps rms Overvoltage Recovery Time 1.5 x FS Input 2 [ ns Full-Scale Step Acquisition Time 50 [ ns DIGITAL INPUTS Logic Family Convert Command Start Conversion High Level Input Current (V IN = 5V)(6) 100 [ µA Low Level Input Current (VIN = 0V) ±10 [ µA High Level Input Voltage +3.5 [ V Low Level Input Voltage +1.0 [ V Input Capacitance 5 [ pF DIGITAL OUTPUTS Logic Family V Logic Coding Low Output Voltage (I OL = 50µA) 0.1 [ V Low Output Voltage (I OL = 1.6mA) 0.4 [ V High Output Voltage (I OH = 50µA) +4.5 [ V High Output Voltage (I OH = 0.5mA) +2.4 [ V 3-State Enable Time OE = L 20 40 [[ ns 3-State Disable Time OE = H 2 10 [[ ns Output Capacitance 5 [ pF ACCURACY (5Vp-p Input Range) Zero Error (Referred to –FS) At 25 °C 0.2 ±1.5 [[ %FS Zero Error Drift (Referred to –FS) ±5 [ ppm/°C Gain Error(7) At 25°C ±2.0 [ %FS Gain Error Drift(7) ±15 [ ppm/°C Gain Error(8) At 25°C ±1.5 [ %FS Gain Error Drift(8) ±15 [ ppm/°C Power Supply Rejection of Gain Δ VS = ±5% 60 82 [[ dB Reference Input Resistance 1.6 [ kΩ Internal Voltage Reference Tolerance (VREF = 2.5V) At 25°C ±35 [ mV Internal Voltage Reference Tolerance (VREF = 1.0V) At 25°C ±14 [ mV

Supply Voltage: +VS Operating +4.7 +5.0 5.3 [[[ V Supply Current: +IS Operating 23 27 [[ mA Power Dissipation Operating 115 135 [[ mW Thermal Resistance, θJA 28-Lead SOIC 75 °C/W 28-Lead SSOP 50 °C/W NOTES: (1) An asterisk ([ ) indicates same specifications as the ADS803U. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to full scale. (4) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (6) Internal 50kΩ pull- down resistor. (7) Includes internal reference. (8) Excludes internal reference. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. SPECIFICATIONS (CONT) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified. ADS803U ADS803E PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PRODUCT DEMO BOARD ADS803U DEM-ADS80xU DEMO BOARD ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER (1) RANGE MARKING NUMBER MEDIA ADS803U SO-28 Surface Mount 217 –40 °C to +85°C ADS803U ADS803U Rails ADS803E SSOP-28 Surface Mount 324 –40 °C to +85°C ADS803E ADS803E Rails " " " " " ADS803E/1K Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. For detailed Tape and Reel mechanical information refer to Appendix B of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION

PIN DESIGNATOR DESCRIPTION

1 OVR Over Range Indicator

2 B1 Data Bit 1 (MSB)

3 B2 Data Bit 2

4 B3 Data Bit 3

5 B4 Data Bit 4

6 B5 Data Bit 5

7 B6 Data Bit 6

8 B7 Data Bit 7

9 B8 Data Bit 8

10 B9 Data Bit 9

11 B10 Data Bit 10

12 B11 Data Bit 11

13 B12 Data Bit 12 (LSB)

14 CLK Convert Clock Input

15 OE Output Enable

17 GND Ground

18 SEL Input Range Select

REF Reference Voltage Select

20 REFB Bottom Reference

21 CM Common-Mode Voltage

22 REFT Top Reference

23 IN Complementary Analog Input

24 GND Analog Ground

25 IN Analog Input (+)

26 GND Analog Ground

28 VDRV Output Driver Voltage

6 Clock Cycles

N–6 N–5 N–4 N–3 N–2 N-1 N N+1Data Out Clock Analog In N N+1 N+2 N+3 N+4 N+5 N+6 N+7 TIMING DIAGRAM SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 200 100 µsn s tL Clock Pulse Low 96 99 ns tH Clock Pulse High 96 99 ns tD Aperture Delay 3 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12 ns OVR B10 B11 B12 CLK VDRV S GND IN GND IN REFT CM REFB VREF SEL GND S OE ADS803

Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 fIN = 500kHz FREQUENCY SPECTRUM Frequency (MHz) Magnitude (dBFSR) –20 –40 –60 –80 –100 –120 f1 = 1.8MHz at –7dB f2 = 1.9MHz at –7dB IMD (3) = –74dBc INTEGRAL LINEARITY ERROR Output Code ILE (LSB) 0 1024 2048 3072 4096 4.0 2.0 –2.0 –4.0 fIN = 500kHz DIFFERENTIAL LINEARITY ERROR Output Code DLE (LSB) 0 1024 2048 3072 4096 1.0 0.5 –0.5 –1.0 fIN = 500kHz SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 fIN = 2.48MHz 100 SWEPT POWER SFDR SFDR (dBFS, dBc) Input Amplitude (dBFS) dBFS dBc fIN = 2.48MHz TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified.

TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified. 117 116 115 114 POWER DISSIPATION vs TEMPERATURE Power (mW) –50 –25 0 25 50 100 75 Temperature (°C) 0.40 0.30 0.20 0.10 DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE DLE (LSB) –50 –25 0 25 50 75 100 Temperature (°C) fIN = 500kHz fIN = 2.48MHz SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE SFDR (dBFS) –50 –25 0 25 50 100 75 Temperature (°C) fIN = 500kHz fIN = 2.48MHz SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE SINAD, SNR (dBFS) –50 –25 0 25 50 75 100 Temperature (°C) fIN = 2.48MHz fIN = 2.48MHz fIN = 500kHz fIN = 500kHz SNR SINAD DYNAMIC PERFORMANCE vs INPUT FREQUENCY SFDR, SNR (dBFS) 0.1 1 Frequency (MHz) SFDR SNR DYNAMIC PERFORMANCE vs INPUT FREQUENCY (Differential Input, VIN = 5Vp-p) SFDR, SNR (dBFS) 0.1 1 Frequency (MHz) SFDR SNR

TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified. 800k 600k 400k 200k OUTPUT NOISE HISTOGRAM (DC Input, V IN = 2Vp-p) Counts N-2 N-1 N N+1 N+2 Code 800k 600k 400k 200k OUTPUT NOISE HISTOGRAM (DC Input, V IN = 5Vp-p Range) Counts N-2 N-1 N N+1 N+2 Code

APPLICATION INFORMATION

The ADS803 allows its analog inputs to be driven either single-ended or differentially. The focus of the following discussion is on the single-ended configuration. Typically, its implementation is easier to achieve and the rated speci- fications for the ADS803 are characterized using the single- ended mode of operation. AC-COUPLED INPUT CONFIGURATION Given in Figure 1 is the circuit example of the most common interface configuration for the ADS803. With the V REF pin connected to the SEL pin, the full-scale input range is defined to be 2Vp-p. This signal is ac-coupled in single- ended form to the ADS803 using the low-distortion voltage feedback amplifier OPA642. As is generally necessary for single-supply components, operating the ADS803 with a full-scale input signal swing requires a level-shift of the amplifier’s zero centered analog signal to comply with the A/D’s input range requirements. Using a DC blocking ca- pacitor between the output of the driving amplifier and the converter’s input, a simple level-shifting scheme can be implemented. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3V and +2V, respectively. Here, two resistor pairs (2x 2kΩ ) are used to create a common-mode voltage of approximately +2.5V to bias the inputs of the ADS803 (IN, IN) to the required DC voltage. An advantage of ac-coupling is that the driving amplifier still operates with a ground-based signal swing. This will keep the distortion performance at its optimum since the signal swing stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. Consider using the inverting gain configuration to eliminate CMR induced errors of the amplifier. The addition of a small series resistor (R S) between the output of the op amp and the input of the ADS803 will be beneficial in almost all interface configurations. This will de-couple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 50Ω . Furthermore, the series resistor together with the 100pF capacitor, establish a passive low-pass filter, limiting the bandwidth for the wideband noise thus help improving the SNR performance. DC-COUPLED WITHOUT LEVEL SHIFT In some applications the analog input signal may already be biased at a level which complies with the selected input range and reference level of the ADS803. In this case, it is only necessary to provide an adequately low source imped- ance to the selected input, IN or IN. Always consider wideband op amps since their output impedance will stay low over a wide range of frequencies. For those applications requiring the driving amplifier to provide a signal amplifica- tion, with a gain ≥ 3, consider using the decompensated voltage feedback op amp OPA643. DC-COUPLED WITH LEVEL SHIFT Several applications may require that the bandwidth of the signal path includes DC, in which case the signal has to be DC-coupled to the A/D converter. In order to accomplish this, the interface circuit has to provide a DC-level shift. The circuit shown in Figure 2 employs an op amp, A1, to sum the ground centered input signal with a required DC offset. The ADS803 typically operates with a +2.5V common-mode voltage, which is established at the center tap of the ladder and connected to the IN input of the converter. Amplifier A1 operates in inverting configuration. Here resistors R 1 and R 2 set the DC-bias level for A1. Because of the op amp’s noise gain of +2V/V, assuming RF = RIN, the DC offset voltage applied to its non-inverting input has to be divided down to +1.25V, resulting in a DC output voltage of +2.5V. FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal Top and Bottom Reference.