ADS802 BURR-BROWN | Alldatasheet

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Technical content

FEATURES

G LOW POWER: 250mW G INTERNAL REFERENCE G WIDEBAND TRACK-AND-HOLD: 65MHz G SINGLE +5V SUPPLY

DESCRIPTION

The ADS802 is a low-power, monolithic 12-bit, 10MHz Ana- log-to-Digital (A/D) converter utilizing a small geometry CMOS process. This complete converter includes a 12-bit quantizer, wideband track-and-hold, reference, and three-state outputs. It operates from a single +5V power supply and can be configured to accept either differential or single-ended input signals. The ADS802 employs digital error correction in order to provide excellent Nyquist differential linearity performance for demanding imaging applications. Its low distortion, high SNR, and high oversampling capability give it the extra margin needed for telecommunications, test instrumentation, and video applications. This high-performance A/D converter is specified for AC and DC performance at a 10MHz sampling rate. The ADS802 is available in an SO-28 package. 12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

G IF AND BASEBAND DIGITIZATION G DATA ACQUISITION CARDS G TEST INSTRUMENTATION G CCD IMAGING Copiers Scanners Cameras G VIDEO DIGITIZING G GAMMA CAMERAS ADS802 SBAS039B – MAY 1995 – REVISED FEBRUARY 2005 www.ti.com Copyright © 1995-2005, Texas Instruments Incorporated Pipeline A/D Converter Timing Circuitry Error Correction Logic 3-State OutputsT/H 12-Bit Digital Data CLK +1.25V +3.25V MSBI OE IN IN REFT CM REFB PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ADS802U Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

SBAS039Bwww.ti.com ABSOLUTE MAXIMUM RATINGS (1) ADS802U PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS

ELECTRICAL CHARACTERISTICS

At TA = +25°C, VS = +5V, and Sampling Rate = 10MHz, and with a 50% duty cycle clock having 2ns rise-and-fall time, unless otherwise noted. RESOLUTION 12 Bits Specified Temperature Range T AMBIENT –40 +85 °C ANALOG INPUT Differential Full-Scale Input Range Both Inputs +1.25 +3.25 V Common-Mode Voltage +2.25 V Analog Input Bandwidth (–3dB) Small-Signal –20dBFS (1) Input +25 °C 400 MHz Full-Power 0dBFS Input +25 °C6 5 M H z Input Impedance 1.25 || 4 M Ω || pF DIGITAL INPUT Logic Family TTL/HCT Compatible CMOS Convert Command Start Conversion Falling Edge ACCURACY (2) fS = 2.5MHz Gain Error +25°C ±0.6 ±1.5 % Full ±1.0 ±2.5 % Gain Tempco ±85 ppm/ °C Power-Supply Rejection of Gain ∆ +VS = ±5% +25 °C 0.03 0.1 %FSR/% Input Offset Error Full ±2.1 ±3.0 % Power-Supply Rejection of Offset ∆ +VS = ±5% +25 °C 0.05 0.1 %FSR/% CONVERSION CHARACTERISTICS Sample Rate 10k 10M Sample/s Data Latency 6.5 Convert Cycle DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz +25 °C ±0.3 ±1.0 LSB 0°C to +85°C ±0.4 ±1.0 LSB f = 5MHz +25 °C ±0.4 ±1.0 LSB 0°C to +85°C ±0.4 ±1.0 LSB No Missing Codes 0 °C to +85°C Tested LSB Integral Linearity Error at f = 500kHz Best Fit 0 °C to +85°C ±1.7 ±2.75 LSB Spurious-Free Dynamic Range (SFDR) f = 500kHz (–1dBFS input) +25 °C 67 77 dBFS Full 66 75 dBFS f = 5MHz (–1dBFS input) +25 °C 63 67 dBFS Full 62 66 dBFS NOTE: (1) Stresses above these ratings may permanently damage the device. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY ADS802U SO-28 DW –40°C to +85°C ADS802U ADS802U Rails, 28 ADS802U "" " ADS802U ADS802U/1K Tape and Reel, 1000 PACKAGE/ORDERING INFORMATION (1) NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits.

SBAS039B www.ti.com ADS802U PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, and Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. DYNAMIC CHARACTERISTICS (Cont.) 2-Tone Intermodulation Distortion (IMD)(3) f = 4.4MHz and 4.5MHz (–7dBFS each tone) +25 °C –65 dBc Full –64 dBc Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) +25 °C6 5 6 7 d B Full 64 67 dB f = 5MHz (–1dBFS input) +25 °C6 4 6 6 d B Full 62 66 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) +25 °C6 3 6 6 d B Full 61 65 dB f = 5MHz (–1dBFS input) +25 °C6 1 6 3 d B Full 60 62 dB Differential Gain Error NTSC or PAL +25 °C 0.5 % Differential Phase Error NTSC or PAL +25 °C 0.1 Degrees Aperture Delay Time +25 °C2 n s Aperture Jitter +25 °C 7 ps rms Over-Voltage Recovery Time(4) 1.5x Full-Scale Input +25 °C2 n s OUTPUTS Logic Family TTL/HCT Compatible CMOS Logic Coding Logic Selectable SOB or BTC Logic Levels Logic LOW Full 0 0.4 V Logic HIGH Full 2.0 +V S V 3-State Enable Time Full 20 40 ns 3-State Disable Time Full 2 10 ns POWER-SUPPLY REQUIREMENTS Supply Voltage: +V S Operating Full +4.75 +5.0 +5.25 V Supply Current: +IS Operating +25 °C5 0 6 2 m A Operating Full 52 62 mA Power Consumption Operating +25 °C 250 310 mW Operating Full 260 310 mW Thermal Resistance, θJA SO-28 75 °C/W NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits.

SBAS039Bwww.ti.com PIN DESIGNATOR DESCRIPTION

1 GND Ground

2 B1 Bit 1, Most Significant Bit (MSB)

3 B2 Bit 2

4 B3 Bit 3

5 B4 Bit 4

6 B5 Bit 5

7 B6 Bit 6

8 B7 Bit 7

9 B8 Bit 8

10 B9 Bit 9

11 B10 Bit 10

12 B11 Bit 11

13 B12 Bit 12, Least Significant Bit (LSB)

14 GND Ground

16 CLK Convert Clock Input, 50% Duty Cycle

18 OE HIGH: High-Impedance State. LOW or Floating: Normal Operation. Internal pull-down resistors.

19 MSBI Most Significant Bit Inversion, HIGH: MSB in-

verted for complementary output. LOW or Float- ing: Straight output. Internal pull-down resistors. 20 +V S +5V Power Supply 21 REFB Bottom Reference Bypass. For external bypass- ing of internal +1.25V reference. 22 CM Common-Mode Voltage. It is derived by (REFT + REFB)/2. 23 REFT Top Reference Bypass. For external bypassing of internal +3.25V reference. 24 +V S +5V Power Supply

25 GND Ground

26 IN Input

27 IN Complementary Input

28 GND Ground

PIN DESCRIPTIONSPIN CONFIGURATION Top View SO TIMING DIAGRAM SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 100 100 µsn s tL Clock Pulse LOW 48 50 ns tH Clock Pulse HIGH 48 50 ns tD Aperture Delay 2 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12.5 ns NOTE: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates. GND B10 B11 B12 GND GND IN IN GND S REFT CM REFB S MSBI OE S CLK S ADS802 Track Hold “N ” Hold “N + 1” Hold “N + 2” Hold “N + 3” Hold “N + 4” Hold “N + 5” Hold “N + 6”Track Data Valid N – 7 Data Valid N – 6 Internal Track-and-Hold Convert Clock Output Data tD DATA LATENCY (6.5 Clock Cycles) tCONV tL tH Track Track Track Track N – 3N – 5N – 4N – 2N – 1 N Track Track Data Valid N – 8 (1) Data Invalid

SBAS039B www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 fIN = 500kHz SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 fIN = 1MHz SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 3fO 2fO –20 –40 –60 –80 –100 –120 2-TONE INTERMODULATION Amplitude (dB) Frequency (MHz) f1 = 4.5MHz f2 = 4.4MHz 0 1.0 2.0 3.0 4.0 2.0 1.0 –1.0 –2.0 DIFFERENTIAL LINEARITY ERROR Code DLE (LSB) fIN = 500kHz 0 1.0 2.0 3.0 4.0 2.0 1.0 –1.0 –2.0 DIFFERENTIAL LINEARITY ERROR Code DLE (LSB) fIN = 5MHz

SBAS039Bwww.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. OUTPUT NOISE HISTOGRAM (NO SIGNAL) Counts 800k 600k 400k 200k 0.0 Code N – 2N – 1 N N + 1 N + 2 100 Input Amplitude (dBm) SFDR (dBFS) SWEPT POWER SFDR fIN = 10MHz Input Amplitude (dBm) SWEPT POWER SNR SNR (dB) fIN = 5MHz 4.0 2.0 –2.0 –4.0 INTEGRAL LINEARITY ERROR ILE (LSB) 0 1.0 2.0 3.0 4096 Code fIN = 500kHz DYNAMIC PERFORMANCE vs SINGLE-ENDED FULL-SCALE INPUT RANGE 432 1 5 Single-Ended Full-Scale Range (Vp-p) Dynamic Range (dB) SNR (fIN = 5MHz) SFDR (fIN = 5MHz) DYNAMIC PERFORMANCE vs DIFFERENTIAL FULL-SCALE INPUT RANGE 432 1 5 Differential Full-Scale Input Range (Vp-p) Dynamic Range (dB) SFDR (fIN = 5MHz) SNR (fIN = 5MHz)

SBAS039B www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 50250 –25 75 100 Temperature (°C) DLE (LSBs) 1.0 0.8 0.6 0.4 0.2 0.1 fIN = 5MHz fIN = 500kHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE Temperature (°C) SFDR (dBFS) –50 –25 0 25 50 75 100 fIN = 5MHz fIN = 500kHz SIGNAL-TO-NOISE RATIO vs TEMPERATURE Temperature (°C) SNR (dB) –50 –25 0 25 50 75 100 fIN = 500kHz fIN = 5MHz SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE Temperature (°C) SINAD (dB) –50 –25 0 25 50 75 100 fIN = 500kHz fIN = 5MHz SUPPLY CURRENT vs TEMPERATURE Temperature (°C) IQ (mA) –50 –25 0 25 50 75 100 POWER DISSIPATION vs TEMPERATURE Temperature (°C) PD (mW) 265 260 255 250 –50 –25 0 25 50 75 100

SBAS039Bwww.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. GAIN ERROR vs TEMPERATURE Temperature (°C) Gain (%FSR) –0.05 –0.55 –1.05 –1.55 –50 –25 0 25 50 75 100 OFFSET ERROR vs TEMPERATURE Temperature (°C) Offset (%FSR) –1.25 –1.5 –2.0 –2.5 –50 –25 0 25 50 75 100 TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH Frequency (Hz) Track-Mold Input Response (dB) 10k 100k 1M 10M 100M 1G DYNAMIC PERFORMANCE vs INPUT FREQUENCY Frequency (Hz) SFDR, SNR (dB) 100k 1M 10M SNR SFDR

FIGURE 8. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp. NOTE: (1) Use parts alternatively for adjustment capability. ceramic capacitors as close to the pin as possible. converter and cause clipping on signal peaks.

  1. Signal-to-Noise-and-Distortion Ratio (SINAD):
  2. Signal-to-Noise Ratio (SNR):
  3. Intermodulation Distortion (IMD):

in dynamic signal processing applications.

FIGURE 9. ADS802 Interface Schematic with AC-Coupling and External Buffers. NOTE: (1) All capacitors should be located as close to the pins as the manufacturingprocess will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) ADS802E OBSOLETE SSOP DB 28 TBD Call TI Call TI ADS802E/1K OBSOLETE SSOP DB 28 TBD Call TI Call TI ADS802U ACTIVE SOIC DW 28 28 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS802UG4 ACTIVE SOIC DW 28 28 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2006 Addendum-Page 1

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