ADS801 TI1 | Alldatasheet
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Technical content
12-Bit, 25MHz Sampling ANALOG-TO-DIGITAL CONVERTER
FEATURES
G LOW POWER: 270mW G INTERNAL REFERENCE G WIDEBAND TRACK-AND-HOLD: 65MHz G SINGLE +5V SUPPLY
DESCRIPTION
The ADS801 is a low-power, monolithic 12-bit, 25MHz Ana- log-to-Digital (A/D) converter utilizing a small geometry CMOS process. This complete converter includes a 12-bit quantizer, wideband track-and-hold, reference, and three-state outputs. It operates from a single +5V power supply and can be configured to accept either single-ended or differential input signals. The ADS801 employs digital error correction to provide excellent Nyquist differential linearity performance for de- manding imaging applications. Its low distortion, high SNR, and high oversampling capability give it the extra margin needed for telecommunications, instrumentation, and video applications. This high-performance A/D converter is specified over tem- perature for AC and DC performance at a 25MHz sampling rate. The ADS820 is available in an SO-28 package.
APPLICATIONS
G IF AND BASEBAND DIGITIZATION G DIGITAL COMMUNICATIONS G TEST INSTRUMENTATION G CCD IMAGING Copiers Scanners Cameras G VIDEO DIGITIZING G GAMMA CAMERAS Pipeline A/D Converter Timing Circuitry Error Correction Logic 3-State OutputsT/H 12-Bit Digital Data CLK +1.25V +3.25V MSBI OE IN IN REFT CM REFB ADS801 SBAS036B – MAY 1995 – REVISED FEBRUARY 2005 www.ti.com Copyright © 1995-2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ADS801U All trademarks are the property of their respective owners.
SBAS036Bwww.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ABSOLUTE MAXIMUM RATINGS (1) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper han- dling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above these ratings may permanently damage the device. SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY ADS801U SO-28 DW –40 °C to +85°C ADS801U ADS801U Rails, 28 ADS801U """ " ADS801U/1K Tape and Reel, 1000 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PACKAGE/ORDERING INFORMATION (1) ADS800U PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS Resolution 12 Bits Specified Temperature Range T AMBIENT –40 +85 °C ANALOG INPUT Differential Full-Scale Input Range Both Inputs, +1.25 +3.25 V 180° Out-of-Phase Common-Mode Voltage +2.25 V Analog Input Bandwidth (–3dB) Small-Signal –20dBFS (1) Input +25 °C 400 MHz Full-Power 0dBFS Input +25 °C6 5 M H z Input Impedance 1.25 || 4 M Ω || pF DIGITAL INPUT Logic Family TTL/HCT Compatible CMOS Convert Command Start Conversion Falling Edge ACCURACY (2) fS = 2.5MHz Gain Error +25 °C ±0.6 ±1.5 % Full ±1.0 ±2.5 % Gain Tempco ±85 ppm/ °C Power-Supply Rejection of Gain ∆ +VS = ±5% +25 °C 0.03 0.15 %FSR/% Input Offset Error Full ±2.1 ±3.0 % Power-Supply Rejection of Offset ∆ +VS = ±5% +25 °C 0.05 0.15 %FSR/% CONVERSION CHARACTERISTICS Sample Rate 10k 25M Sample/s Data Latency 6.5 Convert Cycle DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz +25 °C ±0.3 ±1.0 LSB 0°C to +85°C ±0.4 ±1.0 LSB f = 10MHz +25 °C ±0.3 ±1.0 LSB 0°C to +85°C ±0.4 ±1.0 LSB No Missing Codes 0 °C to +85°C Tested LSB Integral Linearity Error at f = 500kHz Full ±1.7 LSB Spurious-Free Dynamic Range (SFDR) f = 500kHz (–1dBFS input) +25 °C 63 77 dBFS Full 62 73 dBFS f = 10MHz (–1dBFS input) +25 °C 57 61 dBFS Full 55 61 dBFS NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits.
SBAS036B www.ti.com ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits. ADS800U PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS (Cont.) 2-Tone Intermodulation Distortion (IMD)(3) f = 4.4MHz and 4.5MHz (–7dBFS each tone) +25 °C –64 dBc Full –63 dBc Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) +25 °C6 4 6 6 d B Full 61 64 dB f = 10MHz (–1dBFS input) +25 °C6 2 6 5 d B Full 58 64 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) +25 °C6 3 6 6 d B Full 60 63 dB f = 10MHz (–1dBFS input) +25 °C5 6 5 9 d B Full 54 58 dB Differential Gain Error NTSC or PAL +25 °C 0.5 % Differential Phase Error NTSC or PAL +25 °C 0.1 degrees Aperture Delay Time +25 °C2 n s Aperture Jitter +25 °C 7 ps rms Over-Voltage Recovery Time(4) 1.5x Full-Scale Input +25 °C2 n s OUTPUTS Logic Family TTL/HCT Compatible CMOS Logic Coding Logic Selectable Falling Edge Logic Levels Logic LOW, Full 0 0.4 V C L = 15pF max Logic HIGH, Full +2.5 +V S V C L = 15pF max 3-State Enable Time 20 40 ns 3-State Disable Time Full 2 10 ns POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Operating Full +4.75 +5.0 +5.25 V Supply Current: +IS Operating +25 °C5 4 6 5 m A Operating Full 54 68 mA Power Consumption Operating +25 °C 270 325 mW Operating Full 270 340 mW Thermal Resistance, θJA SO-28 75 °C/W
SBAS036Bwww.ti.com PIN CONFIGURATION Top View SO TIMING DIAGRAM SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 40 100 µsn s tL Clock Pulse LOW 19 20 ns tH Clock Pulse HIGH 19 20 ns tD Aperture Delay 2 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12.5 ns PIN DESIGNATOR DESCRIPTION
1 GND Ground
2 B1 Bit 1, Most Significant Bit (MSB)
3 B2 Bit 2
4 B3 Bit 3
5 B4 Bit 4
6 B5 Bit 5
7 B6 Bit 6
8 B7 Bit 7
9 B8 Bit 8
10 B9 Bit 9
11 B10 Bit 10
12 B11 Bit 11
13 B12 Bit 12, Least Significant Bit (LSB)
14 GND Ground
16 CLK Convert Clock Input, 50% Duty Cycle
18 OE HIGH: High-Impedance State. LOW or Floating: Normal Operation. Internal pull-down resistors.
19 MSBI Most Significant Bit Inversion, HIGH: MSB in-
verted for complementary output. LOW or Float- ing: Straight output. Internal pull-down resistors. 20 +V S +5V Power Supply 21 REFB Bottom Reference Bypass. For external bypass- ing of internal +1.25V reference. 22 CM Common-Mode Voltage. It is derived by (REFT + REFB)/2. 23 REFT Top Reference Bypass. For external bypassing of internal +3.25V reference. 24 +V S +5V Power Supply
25 GND Ground
26 IN Input
27 IN Complementary Input
28 GND Ground
NOTE: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates. GND B10 B11 B12 GND GND IN IN GND S REFT CM REFB S MSBI OE S CLK S ADS801 Track Hold “N ” Hold “N + 1” Hold “N + 2” Hold “N + 3” Hold “N + 4” Hold “N + 5” Hold “N + 6”Track Data Valid N – 7 Data Valid N – 6 Internal Track-and-Hold Convert Clock Output Data tD DATA LATENCY (6.5 Clock Cycles) tCONV tL tH Track Track Track Track N – 3N – 5N – 4N – 2N – 1 N Track Track Data Valid N – 8 (1) Data Invalid
SBAS036B www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. SPECTRAL PERFORMANCE Amplitude (dB) Frequency (MHz) –20 –40 –60 –80 –100 –120 fIN = 500kHz SPECTRAL PERFORMANCE Amplitude (dB) Frequency (MHz) –20 –40 –60 –80 –100 –120 fIN = 10MHz 2.0 1.0 –1.0 –2.0 DIFFERENTIAL LINEARITY ERROR Code DLE (LSB) 0 1024 2048 3072 4096 fIN = 500kHz 0 1024 2048 3072 4096 2.0 1.0 –1.0 –2.0 DIFFERENTIAL LINEARITY ERROR Code DLE (LSB) fIN = 10MHz –20 –40 –60 –80 –100 –120 2-TONE INTERMODULATION Amplitude (dB) Frequency (MHz) f1 = 4.5MHz f2 = 4.4MHz INPUT FREQUENCY vs DYNAMIC PERFORMANCE Frequency (MHz) SFDR, SNR (dB) 0.1 1 10 100 SFDR SNR
SBAS036Bwww.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. Counts 800k 600k 400k 200k 0.0 Code N – 2N – 1 N N + 1 N + 2 OUTPUT NOISE HISTOGRAM (NO SIGNAL) 100 Input Amplitude (dBm) SFDR (dBFS) SWEPT POWER SFDR fIN = 10MHz Input Amplitude (dBm) SWEPT POWER SNR SNR (dB) fIN = 10MHz 4.0 2.0 –2.0 –4.0 INTEGRAL LINEARITY ERROR ILE (LSB) 0 1024 2048 3072 4096 Code fIN = 500kHz DYNAMIC PERFORMANCE vs SINGLE-ENDED FULL-SCALE INPUT RANGE Dynamic Range (dB) 12 3 4 5 Single-Ended Full-Scale Input Range (Vp-p) SFDR (fIN = 10MHz) SNR (fIN = 10MHz) DYNAMIC PERFORMANCE vs DIFFERENTIAL FULL-SCALE INPUT RANGE Dynamic Range (dB) 12 3 4 5 Differential Full-Scale Input Range (Vp-p) SFDR (fIN = 10MHz) SNR (fIN = 10MHz)
SBAS036B www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE Temperature (°C) DLE (LSBs) 0.5 0.4 0.3 0.2 0.1 –50 –25 0 25 50 75 100 fIN = 10MHz fIN = 500kHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE Temperature (°C) SFDR (dBFS) –50 –25 0 25 50 75 100 fIN = 500kHz fIN = 10MHz SIGNAL-TO-NOISE RATIO vs TEMPERATURE Temperature (°C) SNR (dB) –50 –25 0 25 50 75 100 fIN = 500kHz fIN = 10MHz SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE Temperature (°C) SINAD (dB) –50 –25 0 25 50 75 100 fIN = 500kHz fIN = 10MHz SUPPLY CURRENT vs TEMPERATURE Temperature (°C) IQ (mA) –50 –25 0 25 50 75 100 POWER DISSIPATION vs TEMPERATURE Temperature (°C) Power (mW) 265 260 255 250 245 –50 –25 0 25 50 75 100
SBAS036Bwww.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. GAIN ERROR vs TEMPERATURE Temperature (°C) Gain (% FSR) –0.05 –0.55 –1.05 –1.55 –50 –25 0 25 50 75 100 OFFSET ERROR vs TEMPERATURE Temperature (°C) Offset (% FSR) –1.50 –1.75 –2.0 –2.25 –50 –25 0 25 50 75 100 TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH Frequency (Hz) Track-Mode Input Response (dB) 10k 100k 1M 10M 100M 1G
converter and cause clipping on signal peaks.
- Signal-to-Noise-and-Distortion Ratio (SINAD):
- Signal-to-Noise Ratio (SNR):
- Intermodulation Distortion (IMD):
in dynamic signal processing applications. FIGURE 8. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp. NOTE: (1) Use parts alternatively for adjustment capability.
FIGURE 9. ADS801 Interface Schematic with AC-Coupling and External Buffers. NOTE: (1) All capacitors should be located as close to the pins as the manufacturingprocess will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.
www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples ADS801E OBSOLETE SSOP DB 28 TBD Call TI Call TI -40 to 85 ADS801E/1K OBSOLETE SSOP DB 28 TBD Call TI Call TI -40 to 85 ADS801U ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS801U ADS801UG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS801U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01
28 PINS SHOWN
8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
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