ADS800 BURR-BROWN | Alldatasheet
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Technical content
12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER
FEATURES
G LOW POWER: 390mW G INTERNAL REFERENCE G WIDEBAND TRACK-AND-HOLD: 65MHz G SINGLE +5V SUPPLY
DESCRIPTION
The ADS800 is a low-power, monolithic 12-bit, 40MHz Ana- log-to-Digital (A/D) converter utilizing a small geometry CMOS process. This complete converter includes a 12-bit quantizer, wideband track-and-hold, reference, and three-state outputs. It operates from a single +5V power supply and can be configured to accept either differential or single-ended input signals. The ADS800 employs digital error correction to provide excellent Nyquist differential linearity performance for de- manding imaging applications. Its low distortion, high SNR, and high oversampling capability give it the extra margin needed for telecommunications, test instrumentation, and video applications. This high-performance A/D converter is specified over tem- perature for AC and DC performance at a 40MHz sampling rate. The ADS800 is available in an SO-28 package. Pipeline A/D Converter Timing Circuitry Error Correction Logic 3-State OutputsT/H 12-Bit Digital Data CLK +1.25V +3.25V MSBI OE IN IN REFT CM REFB
APPLICATIONS
G IF AND BASEBAND DIGITIZATION G DIGITAL COMMUNICATIONS G ULTRASOUND IMAGING G GAMMA CAMERAS G TEST INSTRUMENTATION G CCD IMAGING Copiers Scanners Cameras G VIDEO DIGITIZING ADS800 SBAS035B – FEBRUARY 1995 – REVISED FEBRUARY 2005 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995-2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ADS800U All trademarks are the property of their respective owners.
SBAS035Bwww.ti.com ADS800U PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ABSOLUTE MAXIMUM RATINGS (1) NOTE: (1) Stresses above these ratings may permanently damage the device. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper han- dling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Resolution 12 Bits Specified Temperature Range T AMBIENT 0 +70 °C Operating Temperature Range T AMBIENT –40 +85 °C ANALOG INPUT Differential Full-Scale Input Range Both Inputs, +1.25 +3.25 V 180° Out-of-Phase Common-Mode Voltage +2.25 V Analog Input Bandwidth (–3dB) Small-Signal –20dBFS (1) Input +25 °C 400 MHz Full-Power 0dBFS Input +25 °C6 5 M H z Input Impedance 1.25 || 4 M Ω || pF DIGITAL INPUT Logic Family TTL/HCT Compatible CMOS Convert Command Start Conversion Falling Edge ACCURACY (2) fS = 2.5MHz Gain Error +25 °C ±0.4 ±1.5 % Full ±0.6 ±2.5 % Gain Drift ±95 ppm/ °C Power-Supply Rejection of Gain ∆ +VS = ±5% +25 °C 0.01 0.15 %FSR/% Input Offset Error Full ±2.6 ±3.5 % Power-Supply Rejection of Offset ∆ +VS = ±5% +25 °C 0.02 0.15 %FSR/% CONVERSION CHARACTERISTICS Sample Rate 10k 40M Sample/s Data Latency 6.5 Convert Cycle DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz t H = 13ns(3) +25°C ±0.6 ±1.0 LSB Full ±0.8 LSB f = 12MHz +25 °C ±0.4 ±1.0 LSB Full ±0.5 LSB No Missing Codes t H = 13ns(3) +25°C Tested LSB Integral Linearity Error at f = 500kHz Full ±1.9 LSB Spurious-Free Dynamic Range (SFDR) f = 500kHz (–1dBFS input) +25 °C 65 72 dBFS Full 60 66 dBFS f = 12MHz (–1dBFS input) +25 °C5 8 6 1 dBFS Full 55 61 dBFS SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY ADS800U SO-28 DW –40 °C to +85°C ADS800U ADS800U Rails, 28 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PACKAGE/ORDERING INFORMATION (1) NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.
SBAS035B www.ti.com ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ADS800U PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS (Cont.) 2-Tone Intermodulation Distortion (IMD)(4) f = 4.4MHz and 4.5MHz (–7dBFS each tone) +25 °C –63 dBc Full –62 dBc Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) +25 °C6 1 6 4 d B Full 57 63 dB f = 12MHz (–1dBFS input) +25 °C6 1 6 2 d B Full 56 62 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) +25 °C5 9 6 3 d B Full 54 64 dB f = 12MHz (–1dBFS input) +25 °C5 6 5 8 d B Full 51 57 dB Differential Gain Error NTSC or PAL +25 °C 0.5 % Differential Phase Error NTSC or PAL +25 °C 0.1 degrees Aperture Delay Time +25 °C2 n s Aperture Jitter +25 °C 7 ps rms Over-Voltage Recovery Time(5) 1.5x Full-Scale Input +25 °C2 n s OUTPUTS Logic Family TTL/HCT Compatible CMOS Logic Coding Logic Selectable SOB or BTC Logic Levels Logic “LO”, Full 0 0.4 V C L = 15pF max Logic “HI”, Full +2.5 +V S V C L = 15pF max 3-State Enable Time 20 40 ns 3-State Disable Time Full 2 10 ns POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Operating Full +4.75 +5.0 +5.25 V Supply Current: +IS Operating +25 °C7 8 9 3 m A Operating Full 78 97 mA Power Consumption Operating +25 °C 390 465 mW Operating Full 390 485 mW Thermal Resistance, θJA SO-28 75 °C/W NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.
SBAS035Bwww.ti.com PIN CONFIGURATION Top View SO PIN DESIGNATOR DESCRIPTION
1 GND Ground
2 B1 Bit 1, Most Significant Bit
3 B2 Bit 2
4 B3 Bit 3
5 B4 Bit 4
6 B5 Bit 5
7 B6 Bit 6
8 B7 Bit 7
9 B8 Bit 8
10 B9 Bit 9
11 B10 Bit 10
12 B11 Bit 11
13 B12 Bit 12, Least Significant Bit
14 GND Ground
16 CLK Convert Clock Input, 50% Duty Cycle
18 OE HI: High Impedance State. LO or Floating: Nor- mal Operation. Internal pull-down resistors.
19 MSBI Most Significant Bit Inversion, HI: MSB inverted
for complementary output. LO or Floating: Straight output. Internal pull-down resistors. 20 +V S +5V Power Supply 21 REFB Bottom Reference Bypass. For external bypass- ing of internal +1.25V reference. 22 CM Common-Mode Voltage. It is derived by (REFT + REFB)/2. 23 REFT Top Reference Bypass. For external bypassing of internal +3.25V reference. 24 +V S +5V Power Supply
25 GND Ground
26 IN Input
27 IN Complementary Input
28 GND Ground
S REFT CM REFB S MSBI OE S CLK S ADS800 TIMING DIAGRAM SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Convert Clock Period 25 100 µsn s tL Clock Pulse LOW 12 12.5 ns tH Clock Pulse HIGH 12 (2) 12.5 ns tD Aperture Delay 2 ns t1 Data Hold Time, CL = 0pF 3.9 ns t2 New Data Delay Time, CL = 15pF max 12.5 ns NOTES: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates. (2) tH must be 13ns minimum if no missing codes is desired only for the conditions of tCONV ≤ 28ns and fIN < 2MHz. Track Hold “N ” Hold “N + 1” Hold “N + 2” Hold “N + 3” Hold “N + 4” Hold “N + 5” Hold “N + 6”Track Data Valid N – 7 Data Valid N – 6 Internal Track-and-Hold Convert Clock Output Data tD DATA LATENCY (6.5 Clock Cycles) tCONV tL tH Track Track Track Track N – 3N – 5N – 4N – 2N – 1 N Track Track Data Valid N – 8 (1) Data Invalid
SBAS035B www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) 0 5 10 15 20 –20 –40 –60 –80 –100 –120 fIN = 500kHz SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) 0 5 10 15 20 –20 –40 –60 –80 –100 –120 fIN = 1MHz –20 –40 –60 –80 –100 –120 SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) 0 5 10 15 20 fIN = 5MHz SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) 0 5 10 15 20 –20 –40 –60 –80 –100 –120 fIN = 12MHz –20 –40 –60 –80 –100 –120 SPECTRAL PERFORMANCE Frequency (MHz) Amplitude (dB) 012345 fIN = 1MHz fS = 10MHz –20 –40 –60 –80 –100 –120 2-TONE INTERMODULATION Amplitude (dB) 0 5 10 15 20 Frequency (MHz) f1 = 12.5MHz f2 = 12.0MHz
SBAS035Bwww.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. 2.0 1.0 –1.0 –2.0 DIFFERENTIAL LINEARITY ERROR Code DLE (LSB) 0 1024 2048 3072 4096 fIN = 500kHz DIFFERENTIAL LINEARITY ERROR Code 0 1024 2048 3072 4096 fIN = 12MHz 2.0 1.0 –1.0 –2.0 DLE (LSB) DYNAMIC PERFORMANCE vs INPUT FREQUENCY Frequency (MHz) SFDR, SNR (dB) 0.1 1 10 100 SFDR SNR 100 Input Amplitude (dBm) SFDR (dBFS) SWEPT POWER SFDR fIN = 12MHz Input Amplitude (dBm) SWEPT POWER SNR SNR (dB) fIN = 12MHz 4.0 2.0 –2.0 –4.0 INTEGRAL LINEARITY ERROR ILE (LSB) 0 1024 2048 3072 4096 Code fIN = 500kHz
SBAS035B www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. DYNAMIC PERFORMANCE vs SINGLE-ENDED FULL-SCALE INPUT RANGE 45231 Single-Ended Full-Scale Range (Vp-p) Dynamic Range (dB) f IN = 12MHz SFDR SNR NOTE: REFT EXT varied, REFB is fixed at the internal value of +1.25V. DYNAMIC PERFORMANCE vs DIFFERENTIAL FULL-SCALE INPUT RANGE 2 3 4 Differential Full-Scale Input Range (Vp-p) Dynamic Range (dB) SNR (fIN = 12MHz) SFDR (fIN = 500kHz) SNR (fIN = 500kHz) SFDR (fIN = 12MHz) NOTE: REFT EXT varied, REFB is fixed at the internal value of +1.25V. SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE Temperature (°C) SFDR (dBFS) –25 0 25 50 75 fIN = 500kHz fIN = 12MHz SIGNAL-TO-NOISE RATIO vs TEMPERATURE Temperature (°C) SNR (dB) –25 0 25 50 75 fIN = 500kHz fIN = 12MHz SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE Temperature (°C) SINAD (dB) –25 0 25 50 75 fIN = 500kHz fIN = 12MHz SUPPLY CURRENT vs TEMPERATURE Temperature (°C) IQ (mA) –25 0 25 50 75
SBAS035Bwww.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. POWER DISSIPATION vs TEMPERATURE Temperature (°C) Power (mW) 425 400 375 350 –25 0 25 50 75 GAIN ERROR vs TEMPERATURE Temperature (°C) Gain (%FSR) 0.75 0.25 –0.25 –0.75 –1.25 –25 0 25 50 75 OFFSET ERROR vs TEMPERATURE Ambient Temperature (°C) Offset (%FSR) –2.25 –2.5 –2.75 –25 0 25 50 75 TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH Frequency (Hz) Track-Mode Input Response (dB) 10k 100k 1M 10M 100M 1G OUTPUT NOISE HISTOGRAM (NO SIGNAL) Counts 800k 600k 400k 200k 0.0 Code N – 1N – 2 N N + 1 N + 2
the external references are greater than or equal to 1.5V. FIGURE 9. ADS800 Interface Schematic with AC-Coupling and External Buffers. process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.
planes are particularly important for high-frequency circuits. ADS800 be connected directly to the analog ground plane. cause clipping on signal peaks.
- Signal-to-Noise-and-Distortion Ratio (SINAD):
- Signal-to-Noise Ratio (SNR):
- Intermodulation Distortion (IMD):
in dynamic signal processing applications. FIGURE 10. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp. NOTE: (1) Use parts alternatively for adjustment capability.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) ADS800E OBSOLETE SSOP DB 28 None Call TI Call TI ADS800E/1K OBSOLETE SSOP DB 28 None Call TI Call TI ADS800U ACTIVE SOIC DW 28 28 None CU SNPB Level-3-220C-168 HR ADS800U/1K ACTIVE SOIC DW 28 1000 None CU SNPB Level-3-220C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 14-Feb-2005 Addendum-Page 1
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