ADS6222IRGZT

ADS6225 TI | Alldatasheet

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www.ti.com DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE Pin Compatible 14-Bit Family (ADS624X SLAS542 Maximum Sample Rate: 125 MSPS Feature Compatible Quad Channel Family 12-Bit Resolution with No Missing Codes (ADS644X SLAS531 and ADS642X SLAS532 Simultaneous Sample and Hold 3.5 dB Coarse Gain and up to dB Programmable Fine Gain for SFDR/SNR Base-Station IF Receivers Trade-Off Diversity Receivers Serialized LVDS Outputs with Programmable Medical Imaging Internal Termination Option Test Equipment Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mV pp Table ADS62XX Dual Channel Family Internal Reference with External Reference 125 MSPS 105 MSPS MSPS MSPS Support ADS624X ADS6245 ADS6244 ADS6243 ADS6242 No External Decoupling Required for Bit References ADS622X ADS6225 ADS6224 ADS6223 ADS6222 Bit 3.3-V Analog and Digital Supply QFN Package mm mm) Table Performance Summary ADS6225 ADS6224 ADS6223 ADS6222 Fin 10MHz dB gain) SFDR, dBc Fin 170MHz (3.5 dB gain) Fin 10MHz dB gain) 70.7 70.8 71.3 71.3 SINAD, dBFS Fin 170MHz (3.5 dB gain) 67.4 68.1 68.2 68.7 Power per channel, mW 500 405 350 315 ADS6225/ADS6224/ADS6223/ADS6222 (ADS622X) is a family of high performance 12-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package mm mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in dB steps up to dB. The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than Gbps easing receiver design. The ADS622X also includes the traditional 1-wire interface that can be used at lower sampling frequencies. An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the ADC data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com (CONTINUED) Reference INA_P INA_M CLKP CLKM VCM SENPDNB SDA T APDNA SCLKCF RESE T CFG2CF CFG4 DCLKP DCLKM ADS622x SHA FCLKP FCLKM INB_P INB_M SHA RE FP REFM PLL BIT Clock FRAME Clock DA0_P DA1_P DA0_M DA1_M DB0_P DB1_P DB0_M DB1_M A VD D AGND LVDDCAP LGND Serial Interface Parallel Interface 12-Bit ADC 12-Bit ADC Digital Encoder and Serializer Digital Encoder and Serializer B0199-06 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The ADC channel outputs can be transmitted either as MSB or LSB first and complement or straight binary. ADS622X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range C to C). Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 PACKAGE/ORDERING INFORMATION (1) SPECIFIED TRANSPORT PACKAGE PACKAGE PRODUCT PACKAGE-LEAD TEMPERATURE ORDERING NUMBER MEDIA, DESIGNATOR MARKING RANGE QUANTITY ADS6225IRGZT 250, Tape/reel ADS6225 QFN-48 (2) RGZ C to C AZ6225 ADS6225IRGZR 2000, Tape/reel ADS6224IRGZT 250, Tape/reel ADS6224 QFN-48 (2) RGZ C to C AZ6224 ADS6224IRGZR 2000, Tape/reel ADS6223IRGZT 250, Tape/reel ADS6223 QFN-48 (2) RGZ C to C AZ6223 ADS6223IRGZR 2000, Tape/reel ADS6222IRGZT 250, Tape/reel ADS6222 QFN-48 (2) RGZ C to C AZ6222 ADS6222IRGZR 2000, Tape/reel (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com (2) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θ JA 23.17 C/W LFM air flow), θ JC 22.1 C/W when used with oz. copper trace and pad soldered directly to a JEDEC standard four layer in. x in. PCB. VALUE UNIT AVDD Supply voltage range 0.3 to 3.9 V LVDD Supply voltage range 0.3 to 3.9 V Voltage between AGND and DGND 0.3 to 0.3 V Voltage between AVDD to LVDD 0.3 to 3.3 V Voltage applied to external pin, VCM 0.3 to 2.0 V Voltage applied to analog input pins 0.3V to minimum 3.6, AVDD 0.3V) V T A Operating free-air temperature range to C T J Operating junction temperature range 125 C T stg Storage temperature range to 150 C Lead temperature 1,6 mm (1/16") from the case for seconds 220 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage 3.0 3.3 3.6 V LVDD LVDS Buffer supply voltage 3.0 3.3 3.6 V ANALOG INPUTS Differential input voltage range V pp 1.5 Input common-mode voltage V 0.1 Voltage applied on VCM in external reference mode 1.45 1.50 1.55 V CLOCK INPUT ADS6225 125 ADS6224 105 Input clock sample rate MSPS ADS6223 ADS6222 Sine wave, ac-coupled 0.4 1.5 LVPECL, ac-coupled 0.8 Input clock amplitude differential CLKP V CLKM V pp LVDS, ac-coupled 0.35 LVCMOS, ac-coupled 3.3 Input clock duty cycle 35% 50% 65% DIGITAL OUTPUTS Without internal termination Maximum external load capacitance from each output pin to C LOAD pF DGND With internal termination R LOAD Differential load resistance (external) between the LVDS output pairs 100 Ω T A Operating free-air temperature C Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 maximum rated sampling frequency, 50% clock duty cycle, 1dBFS differential analog input, internal reference mode (unless otherwise noted). ADS6225 ADS6224 ADS6223 ADS6222 F s 125 MSPS F s 105 MSPS F s MSPS F s MSPS PARAMETER UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX RESOLUTION Bits ANALOG INPUT Differential input voltage 2.0 2.0 2.0 2.0 V PP range Differential input pF capacitance Analog input bandwidth 500 500 500 500 MHz Analog input common mode 155 130 100 μ A current (per input pin of each ADC) REFERENCE VOLTAGES VREFB Internal reference bottom 1.0 1.0 1.0 1.0 V voltage VREFT Internal reference top 2.0 2.0 2.0 2.0 V voltage Δ V REF Internal reference error, mV (VREFT VREFB) VCM Common mode output 1.5 1.5 1.5 1.5 V voltage Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 maximum rated sampling frequency, 50% clock duty cycle, 1dBFS differential analog input, internal reference mode (unless otherwise noted). ADS6225 ADS6224 ADS6223 ADS6222 F s 125 MSPS F s 105 MSPS F s MSPS F s MSPS PARAMETER UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX VCM output current mA capability DC ACCURACY No missing codes Assured Assured Assured Assured E O Offset error, across devices mV and across channels within a device Offset error temperature 0.05 0.05 0.05 0.05 mV/ C coefficient, across devices and across channels within a device There are two sources of gain error internal reference inaccuracy and channel gain error E GREF Gain error due to internal 0.75 0.1 0.75 0.75 0.1 0.75 0.75 0.1 0.75 0.75 0.1 0.75 FS reference inaccuracy alone, Δ V REF /2.0)% Reference gain error 0.0125 0.0125 0.0125 0.0125 Δ C temperature coefficient E GCHAN Gain error of channel alone, 0.3 0.3 0.3 0.3 FS across devices and across channels within a device (1) Channel gain error 0.005 0.005 0.005 0.005 Δ C temperature coefficient, across devices and across channels within a device DNL Differential nonlinearity 0.95 0.5 2.0 0.95 0.5 2.0 0.9 0.4 1.8 0.9 0.4 1.8 LSB INL Integral nonlinearity -2.5 1.25 2.5 -2.2 1.25 2.2 -2.0 1.25 2.0 -2.0 1.0 2.0 LSB PSRR DC power supply rejection 0.5 0.5 0.5 0.5 mV/V ratio POWER SUPPLY I CC Total supply current 300 245 210 190 mA I AVDD Analog supply current 237 185 155 140 mA I LVDD LVDS supply current mA Total power 1.0 1.2 0.81 0.97 0.7 0.85 0.63 0.8 W Power down (with input 150 150 150 150 mW clock stopped) (1) This is specified by design and characterization; it is not tested in production. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ELECTRICAL CHARACTERISTICS ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 maximum rated sampling frequency, 50% clock duty cycle, 1dBFS differential analog input, internal reference mode (unless otherwise noted). ADS6225 ADS6224 ADS6223 ADS6222 F s 125 MSPS F s 105 MSPS F s MSPS F s MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX DYNAMIC AC CHARACTERISTICS Fin MHz 70.9 71.4 71.4 Fin MHz 67.5 70.5 70.8 71.1 71.2 Fin MHz 70.3 67.5 70.6 70.9 Fin 100 MHz 69.9 70.1 70.5 70.5 SNR dB Gain 68.5 68.8 69.1 Signal to dBFS Fin 170 noise ratio 3.5 dB 68.1 68.4 68.4 68.8 MHz Coarse gain dB Gain 67.4 67.8 66.9 68.1 Fin 230 3.5 dB 67.1 67.3 67.3 67.8 MHz Coarse gain Fin MHz 70.7 70.8 71.3 71.3 Fin MHz 69.8 67.5 70.9 Fin MHz 69.2 70.6 67.5 70.7 Fin 100 MHz 69.7 70.1 SINAD Signal to dB Gain 66.9 68.5 68.6 68.9 dBFS noise and Fin 170 3.5 dB 67.4 68.1 68.2 68.7 distortion ratio MHz Coarse gain dB Gain 66.8 66.5 67.3 Fin 230 3.5 dB 66.5 66.8 67.2 67.4 MHz Coarse gain Fin MHz Fin MHz Fin MHz Fin 100 MHz SFDR Spurious free dB Gain dBc dynamic Fin 170 3.5 dB range MHz Coarse gain dB Gain Fin 230 3.5 dB MHz Coarse gain Fin MHz Fin MHz Fin MHz Fin 100 MHz HD2 dB Gain Second dBc Fin 170 harmonic 3.5 dB MHz Coarse gain dB Gain Fin 230 3.5 dB MHz Coarse gain Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 maximum rated sampling frequency, 50% clock duty cycle, 1dBFS differential analog input, internal reference mode (unless otherwise noted). ADS6225 ADS6224 ADS6223 ADS6222 F s 125 MSPS F s 105 MSPS F s MSPS F s MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Fin MHz Fin MHz Fin MHz Fin 100 MHz HD3 dB Gain Third dBc Fin 170 harmonic 3.5 dB MHz Coarse gain dB Gain Fin 230 3.5 dB MHz Coarse gain Fin MHz Fin MHz Worst Fin MHz harmonic dBc (other than Fin 100 MHz HD2, HD3) Fin 170 MHz Fin 230 MHz Fin MHz 89.5 89.5 Fin MHz 78.5 85.5 THD Fin MHz Total dBc harmonic Fin 100 MHz 80.5 distortion Fin 170 MHz 77.5 78.5 Fin 230 MHz 75.5 76.5 ENOB Fin MHz 10.8 11.4 10.9 11.5 11.5 Effective Bits 10.9 Fin MHz 10.8 11.4 number of bits F1= 46.09 MHz, IMD 50.09 MHz 2-Tone dBFS intermodulatio F1= 185.09 MHz, n distortion 190.09 MHz Cross-talk signal Cross-talk 105 105 106 108 dBc frequency MHz Recovery to within (of final Input overload Clock value) for 6-dB overload with recovery cycles sine wave input AC PSRR Power Supply Up to 100 MHz, 100 mV PP on dBc Rejection AVDD Ratio Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com DIGITAL CHARACTERISTICS ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level or AVDD LVDD 3.3V, I O 3.5mA, R LOAD 100 Ω (1) All LVDS specifications are characterized, but not tested at production. ADS6225/ADS6224/AD S6223/ADS6222 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current μ A Low-level input current μ A Input capacitance pF DIGITAL OUTPUTS High-level output voltage 1375 mV Low-level output voltage 1025 mV OD Output differential voltage 250 350 450 mV V OS Output offset voltage Common-mode voltage of OUTP and OUTM 1200 mV Output capacitance Output capacitance inside the device, from either output to ground pF (1) I O refers to the LVDS buffer current setting, R LOAD is the external differential load resistance between the LVDS output pair. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com TIMING SPECIFICATIONS (1) ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP clock amplitude, C L pF (2) I O 3.5 mA, R L 100 Ω (3) no internal termination, unless otherwise noted. ADS6225 ADS6224 ADS6223 ADS6222 TEST PARAMETER UNIT CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX t J Aperture jitter Uncertainty in the 250 250 250 250 fs rms sampling instant Interface: 2-wire, DDR bit clock, 14x serialization From data Data setup t su cross-over to bit 0.35 0.55 0.45 0.65 0.65 0.85 0.8 1.1 ns time (4) (5) (6) clock cross-over From bit clock Data hold t h cross-over to data 0.35 0.58 0.5 0.7 0.7 0.9 0.8 1.1 ns time (4) (5) (6) cross-over Input clock rising Clock edge cross-over to t pd_clk propagation 3.4 4.4 5.4 3.4 4.4 5.4 3.4 4.4 5.4 3.4 4.4 5.4 ns frame clock rising delay (6) edge cross-over Bit clock cycle-cycle 350 350 350 350 ps pp jitter (5) Frame clock cycle-cycle ps pp jitter (5) Below specifications apply for MSPS Sampling freq 125 MSPS and all interface options Delay from input Aperture clock rising edge to t A ns delay the actual sampling instant Aperture Channel-channel delay within same device 250 250 250 250 250 250 250 250 ps variation Time for a sample ADC Latency to propagate to Clock (7) ADC outputs, see cycles Figure Time to valid data after coming out of 100 100 100 100 μ s global power down Time to valid data Wake up time after input clock is 100 100 100 100 μ s re-started Time to valid data clock after coming out of 200 200 200 200 cycles channel standby Data rise From 100 mV to ps t RISE 100 200 100 200 100 200 100 200 time +100 mV From +100 mV to t FALL Data fall time 100 200 100 200 100 200 100 200 ps 100 mV Bit clock and From 100 mV to t RISE Frame clock 100 200 100 200 100 200 100 200 ps +100 mV rise time (1) Timing parameters are ensured by design and characterization and not tested in production. (2) C L is the External single-ended load capacitance between each output pin and ground. (3) I o Refers to the LVDS buffer current setting; R L is the external differential load resistance between the LVDS output pair. (4) Timing parameters are measured at the end of a inch pcb trace (100- Ω characteristic impedance) terminated by R L and C L (5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options. (7) Note that the total latency ADC latency internal serializer latency. The serializer latency depends on the interface option selected as listed in Table Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com DCLKP DCLKM CLKM CLKP FCLKM FCLKP DOP DOM Sample N–1 tA tPD_CLK Sample N Sample N+1 1 Sample N+12 Sample N+13 Input Signal Input Clock Bit Clock Output Data Frame Clock D1 1 D1 1D7 D7D3 D3D9 D9D5 D5D1 D1D10 D10D6 D6D2 D2D8 D8D4 D4D0 D0 Latency 12 Clocks Sample N T0105-03 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 TIMING SPECIFICATIONS (continued) Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP clock amplitude, C L pF I O 3.5 mA, R L 100 Ω no internal termination, unless otherwise noted. ADS6225 ADS6224 ADS6223 ADS6222 TEST PARAMETER UNIT CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Bit clock and From +100 mV to t FALL Frame clock 100 200 100 200 100 200 100 200 ps 100 mV fall time LVDS Bit clock duty 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55% cycle LVDS Frame clock duty 47% 50% 53% 47% 50% 53% 47% 50% 53% 47% 50% 53% cycle Figure Latency Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com T0106-03 Bit□Clock DCLKP Output□Data DOP,□DOM tsu th th tsu DCLKM Dn+1 Dn ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure LVDS Timings Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com DEVICE PROGRAMMING MODES USING PARALLEL INTERFACE CONTROL ONLY USING SERIAL INTERFACE PROGRAMMING ONLY USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS622X offers flexibility with several programmable configured. The device can be configured independently using either parallel interface control or serial interface programming. In addition, the device supports a third configuration mode, where both the parallel interface and the serial control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority table Table If this additional level of flexibility is not required, the user can select either the serial interface programming or the parallel interface control. To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3, CFG4, PDNA, PDNB, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After power-up, the device will automatically get configured as per the parallel pin voltage settings Table to Table and no reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are controlled in this mode output data interface and format, power down modes, coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string as illustrated in Figure Table has a pins. Table Parallel Pin Definition PIN CONTROL FUNCTIONS SEN Coarse gain and internal/external reference. SCLK, SDATA Sync, deskew patterns and global power down. PDNA, PDNB Dedicated pins for individual channel ADC power down CFG1 1-Wire/2-wire and DDR/SDR bit clock CFG2 12x/14x Serialization and SDR bit clock capture edge CFG3 Reserved function. Tie CFG3 to Ground. CFG4 MSB/LSB First and data format. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high setting on the <RST bit (in register After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. Since the parallel pins (CFG1-4, PDNA and PDNB) are not used in this mode, they must be tied to ground. The register override bit <OVRD D10 in register 0x0D has to be set high to disable the control of parallel interface pins in this serial interface control ONLY mode. For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4, PDNA and PDNB) can also be used to configure the device. The parallel interface control pins CFG1-4, PDNA and PDNB are available. After power-up, the device will automatically get configured as per the parallel pin voltage settings Table to Table and no reset is required. A simple resistor string can be used as illustrated in Figure SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high setting on the <RST bit (in register After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. Since some functions are controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table Table Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com (3/8) AVDD (3/8) AVDD To□Parallel□Pin AVDD AVDDGND GND (5/8) AVDD (5/8) AVDD <OVRD bit is high If the <OVRD bit is CFG4 Table LOW, then the control voltage on these parallel pins determines the function as per Tables Bit of register 0x00 controls Power down global ONLY if PDN pin is LOW. If PDN is high PDN Global power down device is in global power down mode. Coarse Gain setting is controlled by bit of register 0x0D ONLY if the <OVRD bit is high Else, it is in default register setting of dB COARSE GAIN. SEN Serial Interface Enable Internal/external reference setting is determined by bit of register 0x00. D7, D6, Bits of register 0x0A control the sync and deskew output patterns. SCLK, Serial Interface Clock and SDATA Serial Interface Data pins Power down is determined by bit of 0x00 register. Figure Simple Scheme to Configure Parallel Pins Table SCLK, SDATA Control Pins SCLK SDATA conversion. SYNC ADC Outputs sync pattern on all channels. This pattern can be used by the receiver to align the LOW HIGH deserialized data to the frame boundary. See Capture Test Patterns for details. POWER DOWN Global power down, all channels of the ADC are powered down, including internal references, HIGH LOW PLL and output buffers. DESKEW ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure HIGH HIGH deserializer uses the right clock edge. See Capture Test Patterns for details. Table SEN Control Pin SEN (full-scale Vpp) (3/8)LVDD External reference and 3.5 dB coarse gain (full-scale 1.34 Vpp) (5/8)LVDD Internal reference and 3.5 dB coarse gain (full-scale 1.34 Vpp) LVDD Internal reference and dB coarse gain (full-scale Vpp) Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Independent of the programming mode used, after power-up the parallel pins PDNA,PDNB,CFG1 to CFG4 will automatically configure the device as per the voltage applied Table to Table Table PDNA Control Pin PDNA A ADC power down global Table PDNB Control Pin PDNB B ADC power down global Table CFG1 Control Pin CFG1 (3/8)LVDD Not used (5/8)LVDD SDR Bit clock and 2-wire interface LVDD DDR Bit clock and 2-wire interface Table 10. CFG2 Control Pin CFG2 (only in 2-wire SDR bit clock mode) (3/8)LVDD 14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode) (5/8)LVDD 14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode) LVDD 12x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode) Table 11. CFG3 Control Pin CFG3 RESERVED TIE TO GROUND Table 12. CFG4 Control Pin CFG4 (3/8)LVDD MSB First and offset binary (5/8)LVDD LSB First and offset binary LVDD LSB First and complement Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com SERIAL INTERFACE Register Reset T0109-03 t(SCLK) t(DSU) t(DH) t(SLOADS) D7A4 D3A0 D5A2 D1D9 D6A3 D2D10 D4A1 D0D8SDATA SCLK SEN RESET t(SLOADH) Register Address Register□Data ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The interface can work with SCLK frequency from MHz down to very low speeds (few hertz) and even with non-50% duty cycle SCLK. The first bits of the 16-bit word are the address of the register while the next bits are the register data. After power-up, the internal registers must be reset to their default values. This can be done in one of two ways: Either by applying a high-going pulse on RESET (of width greater than 10ns) OR By applying software reset. Using the serial interface, set the <RST bit in register 0x00 to high this resets the registers to their default values and then self-resets the <RST bit to LOW. When RESET pin is not used, it must be tied to LOW. Figure Serial Interface Timing Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com SERIAL INTERFACE TIMING CHARACTERISTICS RESET TIMING T0108-03 Power□Supply AVDD,□LVDD RESET SEN ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Typical values at min and max values across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 unless otherwise noted. PARAMETER MIN TYP MAX UNIT f SCLK SCLK Frequency, f SCLK 1/t SCLK DC MHz t SLOADS SEN to SCLK Setup time ns t SLOADH SCLK to SEN Hold time ns t DSU SDATA Setup time ns t DH SDATA Hold time ns Time taken for register write to take effect after 16th SCLK falling edge 100 ns Typical values at min and max values across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 unless otherwise noted. PARMATER CONDITIONS MIN TYP MAX UNIT t Power-on delay time Delay from power-up of AVDD and LVDD to RESET pulse active ms t Reset pulse width Pulse width of active RESET signal ns t Register write delay time Delay from RESET disable to SEN active ns t PO Power-up delay time Delay from power-up of AVDD and LVDD to output stable 6.5 ms Figure Reset Timing Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com SERIAL REGISTER MAP ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Table 13. Summary of Functions Supported By Serial Interface REGISTER REGISTER FUNCTIONS (1) (2) ADDRESS D10 <PDN <REF <PDN CHB <PDN CHA GLOBAL <RST INTERNAL POWER POWER GLOBAL S/W RESET OR DOWN CHB DOWN CH A POWER EXTERNAL DOWN <CLKIN GAIN INPUT CLOCK BUFFER GAIN CONTROL <DF DATA FORMAT <PATTERNS COMP OR TEST PATTERNS STRAIGHT BINARY <CUSTOM A CUSTOM PATTERN (LOWER BITS) <CUSTOM B <FINE GAIN CUSTOM FINE GAIN CONTROL (1dB to dB) PATTERN (MSB BIT) <COARSE FALLING OR <OVRD BYTE-WISE GAIN RISING BIT 12-BIT OR DDR OR 1-WIRE OR MSB OR OVERRIDE OR COURSE CLOCK 14-BIT SDR BIT 2-WIRE LSB FIRST BIT BIT-WISE GAIN CAPTURE SERIALIZE CLOCK INTERFACE ENABLE EDGE <TERM CLK <LVDS CURR <CURR DOUBLE LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS LVDS CURRENT SETTINGS LVDS CURRENT DOUBLE <TERM DATA WORD-WISE CONTROL LVDS INTERNAL TERMINATION DATA OUTPUTS (1) The unused bits in each register (shown by blank cells in above table) must be programmed as (2) Multiple functions in a register can be programmed in a single write operation. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

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1. REGISTER BITS ADDRESS D10 <REF <PDN <PDN CHB <PDN CHA <RST INTERNAL GLOBAL POWER POWER S/W RESET OR POWER DOWN CHB DOWN CH A EXTERNAL DOWN Power down modes <PDN GLOBAL Normal operation Global power down, including all channels ADCs, internal references, internal PLL and output buffers <PDN CHA CH A Powered up CH A ADC Powered down <PDN CHB CH B Powered up CH B ADC Powered down <REF Reference Internal reference enabled External reference enabled D10 <RST Software reset applied resets all internal registers and self-clears to Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Table 15. REGISTER BITS ADDRESS D10 <CLKIN GAIN INPUT CLOCK BUFFER GAIN CONTROL <CLKIN GAIN Input clock buffer gain control 11000 Gain minimum gain 00000 Gain 01100 Gain 01010 Gain 01001 Gain 01000 Gain maximum gain Table 16. REGISTER BITS ADDRESS D10 <DF DATA FORMAT <PATTERNS COMP TEST PATTERNS OR STRAIGHT BINARY <PATTERNS Capture test patterns 000 Normal ADC operation 001 Output all zeros 010 Output all ones 011 Output toggle pattern 100 Unused 101 Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C) 110 Output DESKEW pattern (serial stream of 1010..) 111 Output SYNC pattern <DF Data format selection Complement format Straight binary format Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Table 17. REGISTER BITS ADDRESS D10 <CUSTOM A CUSTOM PATTERN (LOWER BITS) D10 <CUSTOM A Lower bits of custom pattern <DATAOUT10 <DATAOUT0 Table 18. REGISTER BITS ADDRESS D10 <CUSTOM B <FINE GAIN CUSTOM FINE GAIN CONTROL dB to dB) PATTERN (MSB) <CUSTOM B MSB of 12-bit custom pattern <DATAOUT11 D10 <FINE GAIN Fine gain control 000 dB Gain (full-scale range 2.00 Vpp) 001 dB Gain (full-scale range 1.78 Vpp) 010 dB Gain (full-scale range 1.59 Vpp) 011 dB Gain (full-scale range 1.42 Vpp) 100 dB Gain (full-scale range 1.26 Vpp) 101 dB Gain (full-scale range 1.12 Vpp) 110 dB Gain (full-scale range 1.00 Vpp) Table 19. REGISTER BITS ADDRESS D10 <COARSE FALLING OR <OVRD BYTE-WISE GAIN RISING BIT 14-BIT OR DDR OR 1-WIRE OR MSB OR OVER-RIDE OR COURSE CLOCK 16-BIT SDR BIT 2-WIRE LSB FIRST BITE BIT-WISE GAIN CAPTURE SERIALIZE CLOCK INTERFACE ENABLE EDGE Interface selection Wire interface Wire interface Bit clock selection (only in 2-wire interface) DDR Bit clock SDR Bit clock Serialization selection 12x Serialization 14x Serialization Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Bit clock capture edge (only when SDR bit clock is selected, Capture data with falling edge of bit clock Capture data with rising edge of bit clock <COARSE GAIN Coarse gain control dB Coarse gain 3.5dB Coarse gain (Full-scale range 1.34 Vpp) MSB or LSB first selection MSB First LSB First Byte/bit wise outputs (only when 2-wire is selected) Byte wise Bit wise D10 <OVRD Over-ride bit. All the functions in register 0x0D can also be controlled using the parallel control pins. By setting bit <OVRD the

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pins. Disable over-ride Enable over-ride Table 20. REGISTER BITS ADDRESS D10 <TERM CLK <LVDS CURR <LVDS DOUBLE LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS LVDS CURRENT SETTINGS LVDS CURRENT DOUBLE <CURR DOUBLE LVDS current double for data outputs Nominal LVDS current, as set by <D5 Double the nominal value <CURR DOUBLE LVDS current double for bit and word clock outputs Nominal LVDS current, as set by <D5 Double the nominal value <LVDS CURR LVDS current setting for data outputs 3.5 mA mA 2.5 mA mA <LVDS CURR LVDS current setting for bit and word clock outputs 3.5 mA mA 2.5 mA mA Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 D10 <TERM CLK LVDS internal termination for bit and word clock outputs 00000 No internal termination 00001 166 Ω 00010 200 Ω 00100 250 Ω 01000 333 Ω 10000 500 Ω Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 100 Ω 00101 100 Ω Table 21. REGISTER BITS ADDRESS D10 <TERM DATA WORD-WISE CONTROL LVDS INTERNAL TERMINATION DATA OUTPUTS <TERM DATA LVDS internal termination for data outputs 00000 No internal termination 00001 166 Ω 00010 200 Ω 00100 250 Ω 01000 333 Ω 10000 500 Ω Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 100 Ω 00101 100 Ω D10 Only when 2-wire interface is selected Byte-wise or bit-wise output, frame clock Word-wise output enabled, 0.5x frame clock 01,10 Do not use Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com PIN CONFIGURATION (2-WIRE INTERFACE) P0023-07 ADS622x RGZ□PACKAGE (TOP VIEW) LGND A VDD L VDD NC CAP CFG4 RESET CM L VDD AGND AGND CLKP A VDD CLKM AGND AGND AGND CFG3 INA_M CFG2 INA_P CFG1 AGND A VDD 1 1 13 14 15 16 17 18 19 20 21 22 23 24 L VDD DA0_M LGND DA0_P SCLK DA1_M SDA T A DA1_P SEN DCLK_M PDNA DCLK_P PDNB FCLK_M AGND FCLK_P AGND DB0_M INB_M DB0_P INB_P DB1_M AGND DB1_P 48 47 46 45 44 43 42 41 40 39 38 37 P AD ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 PIN ASSIGNMENTS (2-WIRE INTERFACE) PINS NO. OF I/O NO. SUPPLY AND GROUND PINS AVDD 7,13,24 Analog power supply 6,8,9,12,17, AGND Analog ground 20,25,28,29 LVDD 2,5,36 Digital power supply LGND 1,35 Digital ground INPUT PINS CLKP, CLKM 18,19 I Differential input clock pair Differential input signal pair, channel If unused, the pins should be tied to VCM. Do not INA_P, INA_M 11,10 I float. Differential input signal pair, channel If unused, the pins should be tied to VCM. Do not INB_P, INB_M 26,27 I float. CAP I Connect 2-nF capacitor from pin to ground Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued) PINS NO. OF I/O NO. This pin functions as serial interface clock input when RESET is low. When RESET is high it controls DESKEW, SYNC and global POWER DOWN modes SCLK I (along with SDATA). See Table for description. This pin has an internal pull-down resistor. This pin functions as serial interface data input when RESET is low. When RESET is high it controls DESKEW, SYNC and global POWER DOWN modes SDATA I (along with SCLK). See Table for description. This pin has an internal pull-down resistor. This pin functions as serial interface enable input when RESET is low. When RESET is high it controls coarse gain and internal/external reference modes. See SEN I Table for description. This pin has an internal pull-up resistor. Serial interface reset input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset RESET I option. Refer to the Serial Interface section. In parallel interface mode, tie RESET permanently high (SCLK, SDATA and SEN function as parallel control pins in this mode). The pin has an internal pull-down resistor to ground. PDNA I Channel A ADC power down control pin. PDNB I Channel B ADC power down control pin. Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock CFG1 I selection. See Table for description. Tie to AVDD for 2-wire interface with DDR bit clock. Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. See CFG2 I Table for description. For 12x serialization with DDR bit clock, tie to ground or AVDD. CFG3 I RESERVED pin TIE to ground. Parallel input pin. It controls data format and MSB or LSB first modes. See Table for CFG4 I description. Internal reference mode common-mode voltage output VCM IO External reference mode reference input. The voltage forced on this pin sets the internal reference. OUTPUT PINS DA0_P,DA0_M 47,48 O Channel A differential LVDS data output pair, wire DA1_P,DA1_M 45,46 O Channel A differential LVDS data output pair, wire DB0_P,DB0_M 39,40 O Channel B differential LVDS data output pair, wire DB1_P,DB1_M 37,38 O Channel B differential LVDS data output pair, wire DCLKP,DCLKM 43,44 O Differential bit clock output pair FCLKP,FCLKM 41,42 O Differential frame clock output pair NC Do Not Connect Connect to ground plane using multiple vias. Refer to Board Design Considerations in PAD application section Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com PIN CONFIGURATION (1-WIRE INTERFACE) P0023-08 ADS622x RGZ□PACKAGE (TOP VIEW) LGND A VDD L VDD NC CAP CFG4 RESET CM L VDD AGND AGND CLKP A VDD CLKM AGND AGND AGND CFG3 INA_M CFG2 INA_P CFG1 AGND A VDD 1 1 13 14 15 16 17 18 19 20 21 22 23 24 L VDD UNUSED LGND UNUSED SCLK DA_M SDA T A DA_P SEN DCLK_M PDNA DCLK_P PDNB FCLK_M AGND FCLK_P AGND DB_M INB_M DB_P INB_P UNUSED AGND UNUSED 48 47 46 45 44 43 42 41 40 39 38 37 P AD ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 PIN ASSIGNMENTS (1-WIRE INTERFACE) PINS NO. I/O OF NO. PINS SUPPLY AND GROUND PINS AVDD 7,13,24 Analog power supply 6,8,9,12,1 AGND Analog ground 20,25,28,2 LVDD 2,5,36 Digital power supply LGND 1,35 Digital ground INPUT PINS CLKP, CLKM 18,19 I Differential input clock pair INA_P, INA_M 11,10 I Differential input signal pair, channel If unused, the pins should be tied to VCM. Do not float. IND_P, IND_M 26,27 I Differential input signal pair, channel If unused, the pins should be tied to VCM. Do not float. CAP I Connect 2-nF capacitance from pin to ground Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued) PINS NO. I/O OF NO. PINS This pin functions as serial interface clock input when RESET is low When RESET is high it controls DESKEW, SYNC and global POWER DOWN modes (along SCLK I with SDATA). See Table for description. This pin has an internal pull-down resistor. This pin functions as serial interface data input when RESET is low When RESET is high it controls DESKEW, SYNC and global POWER DOWN modes (along SDATA I with SCLK). See Table for description. This pin has an internal pull-down resistor. This pin functions as serial interface enable input when RESET is low When RESET is high it controls coarse gain and internal/external reference modes. See SEN I Table for description. This pin has an internal pull-up resistor. Serial interface reset input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset option. RESET I Refer to the Serial Interface section. In parallel interface mode, tie RESET permanently high (SCLK, SDATA and SEN function as parallel control pins in this mode). The pin has an internal pull-down resistor to ground. PDNA I Channel A ADC power down control pin. PDNB I Channel B ADC power down control pin. Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. See CFG1 I Table for description. Tie to ground for 1-wire interface with DDR bit clock. Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. See CFG2 I Table for description. For 12x serialization with DDR bit clock, tie to ground or AVDD. CFG3 I RESERVED pin TIE to ground Parallel input pin. It controls data format and MSB or LSB first modes. See Table for CFG4 I description. Internal reference mode common-mode voltage output VCM IO External reference mode reference input. The voltage forced on this pin sets the internal reference. OUTPUT PINS DA_P,DA_M 45,46 O Channel A differential LVDS data output pair DB_P,DB_M 39,40 O Channel B differential LVDS data output pair DCLKP,DCLKM 43,44 O Differential bit clock output pair FCLKP,FCLKM 41,42 O Differential frame clock output pair 37,38,47,4 UNUSED These pins are unused in the 1-wire interface. Do not connect NC Do not connect Connect to ground plane using multiple vias. Refer to Board Design Considerations in PAD application section Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com TYPICAL CHARACTERISTICS ADS6225 S 125 MSPS) f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 60 Amplitude − dB G001 SFDR = 91 dBc SINAD = 71.35 dBFS SNR = 71.41 dBFS THD = 89.5 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 60 Amplitude − dB G003 SFDR = 86.7 dBc SINAD = 69.9 dBFS SNR = 70.1 dBFS THD = 82.7 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 60 Amplitude − dB G005 SFDR = 79.2 dBc SINAD = 67.4 dBFS SNR = 68 dBFS THD = 77.9 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 60 Amplitude − dB G021 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –81 dBFS SFDR = –91 dBFS fIN − Input Frequency − MHz 0 50 100 150 200 250 SFDR − dBc G007 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 SNR − dBFS G008 Gain = 0 dB Gain = 3.5 dB ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 All plots are at AVDD LVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain (unless otherwise noted) FFT for MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL Figure Figure FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY Figure Figure SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 10. Figure 11. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com fIN − Input Frequency − MHz 10 30 50 70 90 110 130 150 170 190 210 230 SFDR − dBc G009 Input adjusted to get −1dBFS input 1 dB 6 dB 0 dB 2 dB 4 dB 5 dB 3 dB fIN − Input Frequency − MHz 20 40 60 80 100 120 140 160 180 200 220 SINAD − dBFS G010 4 dB 6 dB 2 dB 5 dB 0 dB 3 dB 3.5 dB 1 dB LVDD − Supply Voltage − V SFDR − dBc G012 SNR − dBFS fIN = 50.1 MHz AVDD = 3.3 V SNR SFDR AVDD − Supply Voltage − V SFDR − dBc G011 SNR − dBFS fIN = 50.1 MHz LVDD = 3.3 V SNR SFDR T − Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G013 SNR − dBFS fIN = 50.1 MHz SNR SFDR Input Amplitude − dBFS 100 110 fIN = 20 MHz SFDR − dBc, dBFS G014 SNR − dBFS SFDR (dBc) SFDR (dBFS) SNR (dBFS) ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6225 S 125 MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS Figure 12. Figure 13. PERFORMANCE vs AVDD PERFORMANCE vs LVDD Figure 14. Figure 15. PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE Figure 16. Figure 17. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com Input Clock Amplitude − VPP SFDR − dBc G015 SNR − dBFS SNR SFDR fIN = 50.1 MHz Input Clock Duty Cycle − % 35 40 45 50 55 60 65 SFDR − dBc G020 SNR − dBFS SNR SFDR fIN = 20.1 MHz fS − Sampling Frequency − MSPS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 25 50 75 100 125 PD − Power Dissipation − W G015 LVDD AVDD Output Code 2044 2045 2046 2047 2048 2049 2050 Occurence − % G017 RMS (LSB) = 0.407 f − Frequency − MHz −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 50 100 150 200 250 300 CMRR − Common-Mode Rejection Ratio − dBc G018 VVCM − VCM Voltage − V SFDR − dBc G018 SNR − dBFS fIN = 50.1 MHz External Reference Mode SNR SFDR ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6225 S 125 MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE Figure 18. Figure 19. OUTPUT NOISE HISTOGRAM WITH POWER DISSIPATION vs SAMPLING FREQUENCY INPUTS TIED TO COMMON-MODE Figure 20. Figure 21. PERFORMANCE IN EXTERNAL REFERENCE MODE CMRR vs FREQUENCY Figure 22. Figure 23. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6224 S 105 MSPS) f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 Amplitude − dB G001 SFDR = 91.7 dBc SINAD = 71.2 dBFS SNR = 71.2 dBFS THD = 89.8 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 Amplitude − dB G002 SFDR = 81.1 dBc SINAD = 69.7 dBFS SNR = 70.4 dBFS THD = 79.8 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 Amplitude − dB G003 SFDR = 80 dBc SINAD = 67.5 dBFS SNR = 67.8 dBFS THD = 79.5 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 Amplitude − dB G004 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –88 dBFS SFDR = –88 dBFS fIN − Input Frequency − MHz 0 50 100 150 200 250 SFDR − dBc G005 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 SNR − dBFS G006 Gain = 0 dB Gain = 3.5 dB ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 FFT for MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL Figure 24. Figure 25. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY Figure 26. Figure 27. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 28. Figure 29. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com fIN − Input Frequency − MHz 10 30 50 70 90 110 130 150 170 190 210 230 SFDR − dBc G007 Input adjusted to get −1dBFS input 1 dB 6 dB 0 dB 2 dB 4 dB 3 dB 5 dB fIN − Input Frequency − MHz 20 40 60 80 100 120 140 160 180 200 220 SINAD − dBFS G008 2 dB 5 dB 1 dB 0 dB 3 dB 3.5 dB 4 dB 6 dB SNR − dBFS AVDD − Supply Voltage − V SFDR − dBc G009 SNR SFDR fIN = 70.1 MHz LVDD = 3.3 V SNR − dBFS LVDD − Supply Voltage − V SFDR − dBc G010 fIN = 70.1 MHz AVDD = 3.3 V SNR SFDR Input Amplitude − dBFS 100 110 −40 −30 −20 −10 0 fIN = 20.1 MHz SFDR − dBc, dBFS G012 SNR − dBFS SFDR (dBc) SFDR (dBFS) SNR (dBFS) SNR − dBFS T − Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G011 fIN = 70.1 MHz SNR SFDR ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6224 S 105 MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS Figure 30. Figure 31. PERFORMANCE vs AVDD PERFORMANCE vs LVDD Figure 32. Figure 33. PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE Figure 34. Figure 35. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com SNR − dBFS SFDR − dBc Input Clock Amplitude − VPP G013 SNR SFDR fIN = 70.1 MHz SNR − dBFS Input Clock Duty Cycle − % 35 40 45 50 55 60 65 SFDR − dBc G014 SNR SFDR fIN = 20.1 MHz fS − Sampling Frequency − MSPS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 20 40 60 80 100 PD − Power Dissipation − W G033 LVDD AVDD SNR − dBFS VVCM − VCM Voltage − V fIN = 70.1 MHz External Reference Mode SFDR − dBc G017 SNR SFDR f − Frequency − MHz −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 50 100 150 200 250 300 CMRR − Common-Mode Rejection Ratio − dBc G018 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6224 S 105 MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE Figure 36. Figure 37. POWER DISSIPATION vs SAMPLING FREQUENCY PERFORMANCE IN EXTERNAL REFERENCE MODE Figure 38. Figure 39. CMRR vs FREQUENCY Figure 40. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6223 S MSPS) f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 Amplitude − dB G019 SFDR = 91.2 dBc SINAD = 71.2 dBFS SNR = 71.3 dBFS THD = 88.3 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 Amplitude − dB G020 SFDR = 85.8 dBc SINAD = 70.6 dBFS SNR = 70.9 dBFS THD = 83.9 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 Amplitude − dB G021 SFDR = 81 dBc SINAD = 68.3 dBFS SNR = 68.4 dBFS THD = 79.5 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 Amplitude − dB G022 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –92 dBFS SFDR = –93 dBFS fIN − Input Frequency − MHz 0 50 100 150 200 250 SFDR − dBc G023 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 SNR − dBFS G024 Gain = 0 dB Gain = 3.5 dB ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 FFT for MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL Figure 41. Figure 42. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY Figure 43. Figure 44. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 45. Figure 46. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com fIN − Input Frequency − MHz 10 30 50 70 90 110 130 150 170 190 210 230 SFDR − dBc G025 Input adjusted to get −1dBFS input 1 dB 6 dB 2 dB 4 dB 3 dB 5 dB 0 dB fIN − Input Frequency − MHz 20 40 60 80 100 120 140 160 180 200 220 SINAD − dBFS G026 2 dB 5 dB 1 dB 0 dB 3 dB 3.5 dB 4 dB 6 dB SNR − dBFS LVDD − Supply Voltage − V SFDR − dBc G028 fIN = 50.1 MHz AVDD = 3.3 V SNR SFDR SNR − dBFS AVDD − Supply Voltage − V SFDR − dBc G027 SNR SFDR fIN = 50.1 MHz LVDD = 3.3 V SNR − dBFS T − Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G029 fIN = 50.1 MHz SNR SFDR Input Amplitude − dBFS 100 110 −40 −30 −20 −10 0 fIN = 20.1 MHz SFDR − dBc, dBFS G030 SNR − dBFSSFDR (dBc) SFDR (dBFS) SNR (dBFS) ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6223 S MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS Figure 47. Figure 48. PERFORMANCE vs AVDD PERFORMANCE vs LVDD Figure 49. Figure 50. PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE Figure 51. Figure 52. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com SNR − dBFS SFDR − dBc Input Clock Amplitude − VPP G031 SNR SFDR fIN = 50.1 MHz SNR − dBFS Input Clock Duty Cycle − % 35 40 45 50 55 60 65 SFDR − dBc G032 SNR SFDR fIN = 20.1 MHz fS − Sampling Frequency − MSPS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 20 40 60 80 PD − Power Dissipation − W G051 LVDD AVDD SNR − dBFS VVCM − VCM Voltage − V fIN = 50.1 MHz External Reference Mode SFDR − dBc G035 SNR SFDR f − Frequency − MHz −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 50 100 150 200 250 300 CMRR − Common-Mode Rejection Ratio − dBc G018 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6223 S MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE Figure 53. Figure 54. POWER DISSIPATION vs SAMPLING FREQUENCY PERFORMANCE IN EXTERNAL REFERENCE MODE Figure 55. Figure 56. CMRR vs FREQUENCY Figure 57. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6222 S MSPS) f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 Amplitude − dB G037 SFDR = 92.5 dBc SINAD = 71.3 dBFS SNR = 71.4 dBFS THD = 90.1 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 Amplitude − dB G038 SFDR = 86.7 dBc SINAD = 71 dBFS SNR = 71.3 dBFS THD = 83.7 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 Amplitude − dB G039 SFDR = 81.5 dBc SINAD = 68.1 dBFS SNR = 68.4 dBFS THD = 80.3 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 Amplitude − dB G040 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –96 dBFS SFDR = –87 dBFS fIN − Input Frequency − MHz 0 50 100 150 200 250 SFDR − dBc G041 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 SNR − dBFS G042 Gain = 0 dB Gain = 3.5 dB ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 FFT for MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL Figure 58. Figure 59. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY Figure 60. Figure 61. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 62. Figure 63. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com fIN − Input Frequency − MHz 10 30 50 70 90 110 130 150 170 190 210 230 SFDR − dBc G043 Input adjusted to get −1dBFS input 6 dB 2 dB 4 dB 3 dB 5 dB 0 dB 1 dB fIN − Input Frequency − MHz 20 40 60 80 100 120 140 160 180 200 220 SINAD − dBFS G044 2 dB 5 dB 1 dB 0 dB3 dB 3.5 dB 4 dB 6 dB SNR − dBFS AVDD − Supply Voltage − V SFDR − dBc G045 SNR SFDR fIN = 50.1 MHz LVDD = 3.3 V SNR − dBFS LVDD − Supply Voltage − V SFDR − dBc G046 fIN = 50.1 MHz AVDD = 3.3 V SNR SFDR Input Amplitude − dBFS 100 110 −40 −30 −20 −10 0 fIN = 20.1 MHz SFDR − dBc, dBFS G048 SNR − dBFSSFDR (dBc) SFDR (dBFS) SNR (dBFS) SNR − dBFS T − Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G047 fIN = 50.1 MHz SNR SFDR ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6222 S MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS Figure 64. Figure 65. PERFORMANCE vs AVDD PERFORMANCE vs LVDD Figure 66. Figure 67. PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE Figure 68. Figure 69. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com SNR − dBFS SFDR − dBc Input Clock Amplitude − VPP G049 SNR SFDR fIN = 50.1 MHz SNR − dBFS Input Clock Duty Cycle − % 35 40 45 50 55 60 65 SFDR − dBc G050 SNR SFDR fIN = 20.1 MHz fS − Sampling Frequency − MSPS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 10 20 30 40 50 60 PD − Power Dissipation − W G069 LVDD AVDD SNR − dBFS VVCM − VCM Voltage − V fIN = 50.1 MHz External Reference Mode SFDR − dBc G053 SNR SFDR f − Frequency − MHz −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 50 100 150 200 250 300 CMRR − Common-Mode Rejection Ratio − dBc G018 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6222 S MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE Figure 70. Figure 71. POWER DISSIPATION vs SAMPLING FREQUENCY PERFORMANCE IN EXTERNAL REFERENCE MODE Figure 72. Figure 73. CMRR vs FREQUENCY Figure 74. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com Contour Plots Across Input and Sampling Frequencies 10 50 100 150 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPSS SFDR□-□dBc 200 250 300 400 450350 500 100 105 60 65 85 M0049-10 70 75 80 90 95 10 50 100 150 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPS S SFDR□-□dBc 200 250 300 400 450350 500 100 105 65 85 M0049-1 1 77 74 7780 70 75 80 90 95 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 75. SFDR Contour (no gain) Figure 76. SFDR Contour (3.5 dB coarse gain) Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com 10 50 100 150 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPSS SNR□-□dBFS 200 250 300 400 450350 500 100 105 60 62 7264 M0048-10 66 68 70 10 50 100 150 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPS S SNR□-□dBFS 200 250 300 400 450350 500 100 105 60 62 64 68 M0048-1 1 64 63 62 62 61 61 66 70 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Contour Plots Across Input and Sampling Frequencies (continued) Figure 77. SNR Contour (no gain) Figure 78. SNR Contour (3.5 dB coarse gain) Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com APPLICATION INFORMATION THEORY OF OPERATION ANALOG INPUT INP INM 25 /c87 25 /c87 RCR Filter 50 /c87 50 /c87 3.2 pF C 1□pF par2 C 1□pF par2 L 3□nH pkg L 3□nH pkg C 2□pF bond C 2□pF bond R 200 esr /c87 R 200 esr /c87 C 0.8 pF par1 Sampling Switch Sampling Switch Sampling Capacitor Sampling Capacitor R on /c87 R on /c87 R on /c87 C 4.0 pF samp C 4.0 pF samp S0237-01 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS6225/ADS6224/ADS6223/ADS6222 (ADS622X) is a family of dual channel, 12-bit pipeline ADCs based on switched capacitor architecture in CMOS technology. The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock. After the input signals are captured by the sample and hold circuit of each channel, the samples are sequentially converted by a series of low resolution stages. The stage outputs are combined in a digital correction logic block to form the final 12-bit word with a latency of clock cycles. The 12-bit word of each channel is serialized and output as LVDS levels. In addition to the data streams, a bit clock and frame clock are also output. The frame clock is aligned with the 12-bit word boundary. The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in Figure This differential topology results in very good AC performance even for high input frequencies. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 available on VCM pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM 0.5 V and VCM 0.5 resulting in a 2-V pp differential input swing. The maximum swing is determined by the internal reference voltages REFP (2.0V nominal) and REFM (1.0 nominal). The sampling circuit has a dB bandwidth that extends up to 500 MHz Figure shown by the transfer function from the analog input pins to the voltage across the sampling capacitors). Figure 79. Input Sampling Circuit Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com fIN − Input Frequency − MHz 0 100 200 300 400 500 600 700 Magnitude − dB G073 Drive Circuit Requirements ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 80. Analog Input Bandwidth For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. A Ω resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. It is also necessary to present low impedance Ω for the common mode switching currents. For example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM). In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance has to be taken into account. Figure shows that the impedance (Zin, looking into the ADC input pins) decreases at high input frequencies. The smith chart shows that the input impedance is capacitive and can be approximated by a series R-C up to 500 MHz. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com M0087-01 S(1,□1) Frequency□(100□kHz□to□500□MHz) F2 F1 Freq□=□50□MHz Impedance□=□62.211 – j421.739 Freq□=□400□MHz Impedance□=□58.132 – j29.510 100 200 300 400 500 600 700 800 900 1000 0 50 100 150 200 250 300 350 400 450 500 Magnitu de of Zin - -/c87 f - - Input Frequency - - MHzI Frequency = 50 MHz Mag(Zin1) = 426.302 Frequency = 400 MHz Mag(Zin1) = 65.193 Using RF-Transformer Based Drive Circuits ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 81. ADC Input Impedance, Zin For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. An example of input drive using RF transformers is shown in Figure The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer s leakage inductances. The termination is accomplished by two resistors connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the termination resistors (connected to common mode) has to be low 100 Ω to provide a low-impedance path for the ADC common-mode switching current. Figure shows a configuration using a single 1:1 turns ratio transformer (for example, WBC1-1) that can be used for low input frequencies up to 100 MHz. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com INP INM VCM 1:1 5 /c87 25 /c87 25 /c87 5 /c87

0.1 F/c109

TF_ADC S0256-01 ADS6xxx INP INM VCM 1:1 1:1 5 /c87 50 /c87 50 /c87 50 /c87 50 /c87 5 /c87

1. Single Transformer Drive Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. Figure shows an example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the shaded box in Figure may be required between the two transformers to improve the balance between the P and M sides. The center point of this termination must be connected to ground. Figure 83. Two Transformer Drive Circuit Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com Using Differential Amplifier Drive Circuits RG RF RF RFIL RFIL CFIL CFIL RG

10 F/c109

RS T||□R RT +VS CM INP INM ADS6xxx THS4509 VCM 500 /c87 200 /c87 200 /c87 5 /c87 5 /c87500 /c87 –V S S0259-01 INPUT COMMON MODE 155 /C0109AxFs

125 MSPS

(1) REFERENCE ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure shows a drive ciruit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential conversion, the amplifier also provides gain (10 dB in Figure As shown in the figure, R FIL helps to isolate the amplifier output from the switching inputs of the ADC. Together with C FIL it also forms a low-pass filter that bandlimits the noise (and signal) at the ADC input. As the amplifier outputs are ac-coupled, the common-mode of the ADC input pins is set using two resistors connected to VCM. The amplifier outputs can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC input pins can be biased to 1.5 Figure 84. Drive Circuit using THS4509 Refer to the EVM User Guide SLAU196 for more information. To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1- μ F low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 155 μ A at 125 MSPS (per input pin). Equation describes the dependency of the common-mode current and the sampling frequency. This equation helps to design the output capability and impedance of the CM driving circuit accordingly. The ADS622X has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the converter can be controlled in the external reference mode as explained below. The internal or external reference modes can be selected by programming the register bit <REF Table Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com S0165-04 VCM REFM REFP INTREF INTREF EXTREF 4□k/c87 1□k/c87 Internal Reference ADS6xxx Internal Reference External Reference Full−scale differential input pp/C0043(Voltage forced on VCM)/C00321.33 (2) COARSE GAIN AND PROGRAMMABLE FINE GAIN ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 85. Reference Section When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins. When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by Equation In this mode, the range of voltage applied on VCM should be 1.45 V to 1.55 The 1.5-V common-mode voltage to bias the input pins has to be generated externally. ADS622X includes gain settings that can be used to get improved SFDR performance (compared to dB gain mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from dB to dB. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The fine gain is programmable in dB steps from to dB. With fine gain also, SFDR improvement is achieved, but at the expense of SNR (there is about dB SNR degradation for every dB of fine gain). Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com CLOCK INPUT ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the register bits <COARSE GAIN Table and <FINE GAIN Table Note that the default gain after reset is dB. Table 22. Full-Scale Range Across Gains GAIN, dB TYPE FULL-SCALE, V pp Default (after reset) 3.5 Coarse setting (fixed) 1.34 1.78 1.59 1.42 Fine setting (programmable) 1.26 1.12 1.00 The ADS622X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-k Ω resistors as shown in Figure This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure and Figure Figure shows the impedance looking into the clock input pins. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com CLKP 5 k/c87 VCM 5 k/c87 6 pF 10 /c87 10 /c87 CLKM Clock Buffer Ceq Ceq Ceq 1 to 3 pF , equivalent input capacitance of clock buffer/c187 Lpkg 3 nH/c187 Lpkg 3 nH/c187 Cbond 1 pF/c187 Cbond 1 pF/c187 Resr 100/c187 /c87 Resr 100/c187 /c87 S0275-01 Clock Frequency − MHz 100 200 300 400 500 600 700 800 900 1000 0 25 50 75 100 125 Impedance (Magnitude) − Ω G082 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 86. Internal Clock Buffer Figure 87. Clock Buffer Input Impedance Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com S0167-05 CLKP CLKM Differential□Sine-Wave or□PECL or□LVDS□Clock□Input ADS6xxx REF_IN VCXO_INM CP_OU T CTRL OUTP OUTM Y0B ADS6xxx CLKM CLKP VCXO CDCM7005 VCXO_INP Reference Clock S0238-02 S0168-07 CLKP CLKM CMOS□Clock□Input ADS6xxx

1. Differential Clock Driving Circuit Figure shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance with this scheme is comparable with that of a low jitter sine wave clock source. Figure 89. PECL Clock Drive Using CDCM7005 Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a 0.1- μ F capacitor, as shown in Figure Figure 90. Single-Ended Clock Driving Circuit Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com CLOCK BUFFER GAIN POWER DOWN MODES Global Power Down Channel Standby Input Clock Stop ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is increased. Hence, it is recommended to use large clock amplitude. Use clock amplitude greater than Vpp to avoid performance degradation. In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock amplitude. The gain can be set by programming the register bits <CLKIN GAIN Table and increases monotonically from Gain to Gain settings. Table shows the minimum clock amplitude supported for each gain setting. Table 23. Minimum Clock Amplitude across gains CLOCK BUFFER GAIN MINIMUM CLOCK AMPLITUDE SUPPORTED, mVpp differential Gain (minimum gain) 800 Gain (default gain) 400 Gain 300 Gain 200 Gain (highest gain) 150 The ADS622X has three power down modes global power down, channel standby, and input clock stop. This is a global power down mode in which almost the entire chip is powered down, including the four ADCs, internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about mW typical (with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL Table The output data and clock buffers are in high impedance state. The wake-up time from this mode to data becoming valid in normal mode is 100 μ In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each of the four ADCs can be powered down independently using the register bits <PDN CH Table The output LVDS buffers remain powered up. The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles. The converter enters this mode: If the input clock frequency falls below MSPS or If the input clock amplitude is less than 400 mV (pp, differential with default clock buffer gain setting) at any sampling frequency. All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time from this mode to data becoming valid in normal mode is 100 μ Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com POWER SUPPLY SEQUENCING ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Table 24. Power Down Modes Summary (1) AVDD POWER LVDD POWER POWER DOWN MODE WAKE UP TIME (mW) (mW) In power-up 782 208 Global power down 100 μ s Channel in standby 208 200 Clocks Channels in standby 208 200 Clocks Input clock stop 100 μ s (1) Sampling frequency 125 MSPS. During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated inside the device. Externally, they can be driven from separate supplies or from a single supply. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com DIGITAL OUTPUT INTERFACE 1-WIRE INTERFACE AND SERIALIZATION WITH DDR BIT CLOCK ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS622X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of these options can be easily programmed using either parallel pins or the serial interface. The output interface options are: 1-Wire, frame clock, and serialization with DDR bit clock 2-Wire, frame clock, serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise 2-Wire, frame clock, serialization, with SDR bit clock, byte wise/bit wise/word wise 2-Wire, (0.5 frame clock, serialization, with DDR bit clock, byte wise/bit wise/word wise. The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface options selected (refer to Table 12). Table 25. Maximum Recommended Sampling Frequency for Different Output Interface Options MAXIMUM RECOMMENDED BIT CLOCK FRAME CLOCK SERIAL DATA RATE, INTERFACE OPTIONS SAMPLING FREQUENCY, FREQUENCY, MHZ Mbps FREQUENCY, MHZ MSPS Serialization 390 780 DDR Bit 1-Wire clock Serialization 455 910 Serialization 125 375 125 750 DDR Bit 2-Wire clock Serialization 125 437.5 62.5 875 Serialization 390 390 SDR Bit 2-Wire clock Serialization 455 455 Each interface option is described in detail below. Here the device outputs the data of each ADC serially on a single LVDS pair (1-wire). The data is available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data rate is sample frequency (12 serialization) and sample frequency (14 serialization). Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com (D0) D13 (D2) (D7) D10 (D3) (D10) (D6) (0) (D1) (D1) (D8) (D4) (D11) D11 (D2) (D9) (D5) (0) (D0) Data□Bit□in□LSB□First□Mode Data□Bit□in□MSB□First□Mode (1) In□14-Bit□serialization,□two□zero□bits□are□padded□to□the□12-bit ADC□data□on□the□MSB□side. Output□Data DA,□DB,□DC,□DD Data□Rate□=□14 Fs/c18014-Bit□Serialization (1) Input□Clock, CLK Freq□=□Fs Frame□Clock, FCLK Freq□=□1 Fs/c180 Bit□Clock, DCLK Freq□=□7 Fs/c180 T0225-01 D11 (D0) D11 (D0) (D6) (D3) (D9) D10 (D1) D10 (D1) (D7) (D4) (D10) (D2) (D8) (D5) (D11) Output□Data DA,□DB,□DC,□DD Data□Rate□=□12 Fs/c18012-Bit□Serialization Bit□Clock, DCLK Freq□=□6 Fs/c180 Sample□N Sample□N□+□1 2-WIRE INTERFACE SERIALIZATION WITH DDR/SDR BIT CLOCK ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 91. 1-Wire Interface The 2-wire interface is recommended for sampling frequencies above MSPS. The device outputs the data of each ADC serially on two LVDS pairs (2-wire). The data rate is Sample frequency since bits are sent on each wire every clock cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent over the wires as byte-wise or bit-wise or word-wise. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com White Cells – Sample N Grey Cells – Sample N + 1 D11 (D0) D11 (D0) (D0) (D7) (D7) (D3) (D3) (D10) (D10) (D6) (D6) D10 (D1) D10 (D1) (D8) (D8) (D4) (D4) (D11) (D11) (D2) (D2) (D9) (D9) (D5) (D5) Data□Bit□in□LSB□First□Mode Data□Bit□in□MSB□First□Mode Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1 In□Word-Wise□Mode D10 (D0) D11 (D1) (D2) (D3) (D6) (D7) (D9) D10 (D0) D11 (D1) (D2) (D3) (D4) (D5) (D8) (D8) (D9) (D10) (D4) (D5) (D6) (D7) (D10) (D11) (D11) Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1In□Bit-Wise□Mode (D0) (D0) D11 (D6) D11 (D6) (D3) (D3) (D9) (D9) (D1) (D1) D10 (D7) D10 (D7) (D4) (D4) (D10) (D10) (D2) (D2) (D8) (D8) (D5) (D5) (D11) (D11) Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1 In□Byte-Wise□Mode Data□Rate□=□6 Fs/c180 Input□Clock, CLK Freq□=□Fs Frame□Clock, FCLK Freq□=□1 Fs/c180 Bit□Clock – SDR, DCLK Freq□=□6 Fs/c180 Bit□Clock – DDR, DCLK Freq□=□3 Fs/c180 T0226-01 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 92. 2-Wire Interface Serialization Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com 2-WIRE INTERFACE SERIALIZATION ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 In serialization, two zero bits are padded to the 14-bit ADC data on the MSB side and the combined 14-bit data is serialized and output over two LVDS pairs. A frame clock at sample frequency is also available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5 sample frequency. The output data rate will be Sample frequency as data bits are output every clock cycle on each wire. Each ADC sample is sent over the wires as byte-wise or bit-wise or word-wise. Using the serialization makes it possible to upgrade to a 14-bit ADC in the 64xx family in the future seamlessly, without requiring any modification to the receiver capture logic design. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com White Cells – Sample N Grey Cells – Sample N + 1 (D0) (D0) (D7) (D0) (D7) D10 (D3) D10 (D3) (D10) (D10) (D6) (D6) (0) (0) (D1) (D1) (D1) (D1) (D8) (D8) (D4) (D4) (D11) (D11) D11 (D2) D11 (D2) (D9) (D9) (D5) (D5) (0) (0) (D0) (D0) Data□Bit□in□LSB□First□Mode Data□Bit□in□MSB□First□Mode Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1 In□W ord-Wise□Mode (D0) (D1) (D0) (D1) (D6) (D7) (D6) (D7) (0) (0) (0) (0) D10 (D2) D11 (D3) D10 (D2) D11 (D3) D10 (D2) D11 (D3) (D8) (D9) (D8) (D9) (D4) (D5) (D4) (D5) (D10) (D11) (D10) (D11) (D0) (D1) Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1In□Bit-Wise□Mode (D0) (D7) (D0) (D7) (D3) D10 (D10) (D3) D10 (D10) (D6) (0) (D6) (0) (D1) (D8) (D1) (D8) (D1) (D8) (D4) (D11) (D4) (D11) (D2) D11 (D9) (D2) D11 (D9) (D5) (0) (D5) (0) (D0) (D7) Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1 In□Byte-Wise□Mode Data□Rate□=□7 Fs/c180 Input□Clock, CLK Freq□=□Fs Frame□Clock, FCLK Freq□=□1 Fs/c180 Bit□Clock – SDR, DCLK Freq□=□7 Fs/c180 T0227-01 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 93. 2-Wire Interface Serialization SDR Bit Clock Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com White Cells – Sample N Grey Cells – Sample N + 1 (D0) (D0) (D7) (D0) (D7) D10 (D3) D10 (D3) (D10) (D10) (D6) (D6) (0) (0) (D1) (D1) (D1) (D1) (D8) (D8) (D4) (D4) (D11) (D11) D11 (D2) D11 (D2) (D9) (D9) (D5) (D5) (0) (0) (D0) (D0) Data□Bit□in□LSB□First□Mode Data□Bit□in□MSB□First□Mode Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1 In□W ord-Wise□Mode (D0) (D1) (D0) (D1) (D6) (D7) (D6) (D7) (0) (0) (0) (0) D10 (D2) D11 (D3) D10 (D2) D11 (D3) D10 (D2) D11 (D3) (D8) (D9) (D8) (D9) (D4) (D5) (D4) (D5) (D10) (D11) (D10) (D11) (D0) (D1) Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1In□Bit-Wise□Mode (D0) (D7) (D0) (D7) (D3) D10 (D10) (D3) D10 (D10) (D6) (0) (D6) (0) (D1) (D8) (D1) (D8) (D1) (D8) (D4) (D11) (D4) (D11) (D2) D11 (D9) (D2) D11 (D9) (D5) (0) (D5) (0) (D0) (D7) Output□Data DA0,□DB0,□DC0,□DD0 Output□Data DA1,□DB1,□DC1,□DD1 In□Byte-Wise□Mode Data□Rate□=□7 Fs/c180 Input□Clock, CLK Freq□=□Fs Frame□Clock, FCLK Freq□=□0.5 Fs/c180 Bit□Clock – DDR, DCLK Freq□=□3.5 Fs/c180 T0228-01 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 94. 2-Wire Interface Serialization DDR Bit Clock Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com OUTPUT BIT ORDER MSB/LSB FIRST OUTPUT DATA FORMATS LVDS CURRENT CONTROL LVDS INTERNAL TERMINATION ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 In the 2-wire interface, three types of bit order are supported byte-wise, bit-wise and word-wise. Byte-wise: Each sample is split across the wires. Wires DA0 and DB0 carry the LSB bits D5-D0 and wires DA1 and DB1 carry the MSB bits. Bit-wise: Each sample is split across the wires. Wires DA0 and DB0 carry the even bits (D0,D2,D4..) and wires DA1 and DB1 carry the odd bits (D1,D3,D5...). Word-wise: In this case, all bits of every sample are sent over a single wire. Successive samples are sent over the wires. For example sample N is sent on wires DA0 and DB0, while sample N+1 is sent over wires DA1 and DB1. The frame clock frequency is 0.5x sampling frequency, with the rising edge aligned with the start of each word. By default after reset, the ADC data is output serially with the MSB first The data can be output LSB first also by programming the register bit <MSB_LSB_First In the 2-wire mode, the bit order in each wire is flipped in the LSB first mode. Two output data formats are supported complement (default after reset) and offset binary. They can be selected using the serial interface register bit <DF In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 0xFFF in offset binary output format, and 0x7FF in complement output format. For a negative input overdrive, the output code is 0x000 in offset binary output format and 0x800 in complement output format. The default LVDS buffer current is 3.5 mA. With an external 100- Ω termination resistance, this develops 350-mV logic levels at the receiver. The LVDS buffer currents can also be programmed to 2.5 mA, 3.0 mA and 4.5 mA using the register bits <LVDS CURR In addition, there exists a current double mode, where the LVDS nominal current is doubled (register bits <CURR DOUBLE Table An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially terminated inside the device. Five termination resistances are available 166, 200, 250, 333, and 500 Ω (nominal with 20% variation). Any combination of these terminations can be programmed; the effective termination will be the parallel combination of the selected resistances. The terminations can be programmed separately for the clock and data buffers (bits <TERM CLK and <TERM DATA Table The internal termination helps to absorb any reflections from the receiver end, improving the signal integrity. This makes it possible to drive up to pF of load capacitance, compared to only pF without the internal termination. Figure and Figure show the eye diagram with pF and pF load capacitors (connected from each output pin to ground). With 100- Ω internal and 100- Ω external termination, the voltage swing at the receiver end will be halved (compared to no internal termination). The voltage swing can be restored by using the LVDS current double mode (bits <CURR DOUBLE Table Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com C001 C002 ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Figure 95. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination) Figure 96. LVDS Data Eye Diagram with 10-pF Load Capacitance (100 Ω Internal Termination) Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com CAPTURE TEST PATTERNS ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 ADS622X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures sufficient setup/hold times for a reliable capture by the receiver. The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface, the SYNC pattern is '1's followed by '0's (from MSB to LSB). This information can be used by the receiver logic to shift the deserialized data till it matches the SYNC pattern. In addition to DESKEW and SYNC, the ADS622X includes other test patterns to verify correctness of the capture by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization and bit order. Table 26. Test Patterns PATTERN low. All ones Outputs logic high. Toggle Outputs toggle pattern <D11-D0 alternates between 101010101010 and 010101010101 every clock cycle. Outputs a 12-bit custom pattern. The 12-bit custom pattern can be specified into two serial interface registers. In the 2-wire Custom interface, each code is sent over the wires depending on the serialization and bit order. Sync Outputs a sync pattern. Deskew Outputs deskew pattern. Either <D11 101010101010 OR <D11 010101010101 every clock cycle. Table 27. SYNC Pattern INTERFACE OPTION SERIALIZATION SYNC PATTERN ON EACH WIRE 12x MSB -111111000000- LSB 1-Wire 14x MSB -11111110000000- LSB 12x MSB -111000- LSB 2-Wire 14x MSB -1111000- LSB Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output interface in the tables below. Table to Table Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD LVDD 3.3 C L pF I O 3.5 mA, R L 100 Ω no internal termination, unless otherwise noted. Timing parameters are ensured by design and characterization and not tested in production. Ts Sampling frequency 1/Fs Table 28. Clock Propagation Delay and Serializer Latency for Different Interface Options SERIALIZER LATENCY (1) INTERFACE SERIALIZATION CLOCK PROPAGATION DELAY, t pd_clk clock cycles 12x t pd_clk 0.5xT s t delay 1-Wire with DDR bit clock 14x t pd_clk 0.428xT s t delay 2-Wire with DDR bit clock t pd_clk t delay 12x 2-Wire with SDR bit clock t pd_clk 0.5xT s t delay (when t pd_clk T s 2-Wire with DDR bit clock t pd_clk 0.857xT s t delay 14X (when t pd_clk T s 2-Wire with SDR bit clock t pd_clk 0.428xT s t delay (1) Note that the total latency ADC latency serializer latency. The ADC latency is clocks Table 29. Timings for 1-Wire Interface DATA SETUP TIME, t su DATA HOLD TIME, t h t delay SAMPLING FREQUENCY ns ns ns SERIALIZATION MSPS MIN TYP MAX MIN TYP MAX MIN TYP MAX 0.4 0.6 0.5 0.7 F s MSPS 0.8 1.0 0.9 1.1 1.6 2.0 1.8 2.2 F s MSPS 3.5 4.0 3.5 4.2 4.5 0.3 0.5 0.4 0.6 F s MSPS 0.65 0.85 0.7 0.9 1.3 1.65 1.6 1.9 F s MSPS 3.2 3.5 3.2 3.6 4.5 Table 30. Timings for 2-Wire Interface, DDR Bit Clock DATA SETUP TIME, t su DATA HOLD TIME, t h t delay SAMPLING FREQUENCY ns ns ns SERIALIZATION MSPS MIN TYP MAX MIN TYP MAX MIN TYP MAX 105 0.55 0.75 0.6 0.8 F s MSPS 0.65 0.85 0.7 0.9 3.4 4.4 5.4 0.8 1.0 0.8 1.05 0.9 1.2 1.0 1.3 F s MSPS 1.7 2.0 1.1 2.1 3.7 5.2 6.7 105 0.45 0.65 0.6 0.7 F s MSPS 0.55 0.75 0.7 0.8 0.65 0.85 0.8 0.9 0.8 1.1 1.0 1.1 F s MSPS 1.4 1.7 1.1 1.9 4.5 Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Table 31. Timings for 2-Wire Interface, SDR Bit Clock DATA SETUP TIME, t su DATA HOLD TIME, t h t delay SAMPLING FREQUENCY ns ns ns SERIALIZATION MSPS MIN TYP MAX MIN TYP MAX MIN TYP MAX 1.0 1.2 1.1 1.3 F s MSPS 1.8 2.0 1.9 2.1 3.4 4.4 5.4 3.9 4.1 3.8 4.1 F s MSPS 8.2 8.4 7.8 8.2 3.7 5.2 6.7 0.8 1.0 1.0 1.2 F s MSPS 1.5 1.7 1.6 1.8 3.4 4.4 5.4 3.4 3.6 3.3 3.5 F s MSPS 6.9 7.2 6.6 6.9 3.7 5.2 6.7 Table 32. Output Jitter (applies to all interface options) BIT CLOCK JITTER, CYCLE-CYCLE FRAME CLOCK JITTER, CYCLE-CYCLE SAMPLING FREQUENCY ps, peak-peak ps, peak-peak MSPS MIN TYP MAX MIN TYP MAX 350 Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com BOARD DESIGN CONSIDERATIONS Grounding Supply Decoupling Exposed Thermal Pad ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 A single ground plane is sufficient to give optimum performance, provided the analog, digital and clock sections of the board are cleanly partitioned. Refer to the EVM User Guide SLAU196 for more layout details. As the ADS622X already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that the decoupling capacitors can help to filter external power supply noise, so the optimum number of decoupling capacitors would depend on actual application. It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching noise from sensitive analog circuitry. In case only a single 3.3 V supply is available, it should be routed first to AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed to LVDD. It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal performance. For detailed information, see application notes QFN Layout Guidelines SLOA122 and QFN/SON PCB Attachment SLUA271 A). Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com DEFINITION OF SPECIFICATIONS SNR /C004310Log10 P S P N (3) SINAD /C004310Log10 P S PN /C0041PD (4) ENOB /C0043SINAD /C00421.76 6.02 (5) THD /C004310Log10 P S PD (6) ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by dB with respect to the low frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) The INL is the deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Offset Error The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from T MIN to T MAX It is calculated by dividing the maximum deviation of the parameter across the T MIN to T MAX range by the difference T MAX T MIN Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first nine harmonics. SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter s full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental S to the power of all the other spectral components including noise N and distortion D but excluding dc. SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Effective Number of Bits (ENOB) The ENOB is a measure of a converter s performance as compared to the theoretical limit based on quantization noise. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental S to the power of the first nine harmonics (PD). THD is typically given in units of dBc (dB to carrier). Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

www.ti.com PSRR /C004320Log10 /C0068Vout /C0068Vsup , expressed in dBc (7) CMRR /C004320Log10 /C0068Vout /C0068Vcm_in , expressed in dBc (8) ADS6225 ADS6224 ADS6223 ADS6222 SLAS543A MAY 2007 REVISED SEPTEMBER 2007 Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies and f2) to the power of the worst spectral component at either frequency 2f1 or 2f2 f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter s full-scale range. DC Power Supply Rejection Ratio (DC PSRR) The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. AC Power Supply Rejection Ratio (AC PSRR) AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If Δ Vsup is the change in supply voltage and Δ Vout is the resultant change of the ADC output code (referred to the input), then Voltage Overload Recovery The number of clock cycles taken to recover to less than error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from their expected values) is noted. Common Mode Rejection Ratio (CMRR) CMRR is the measure of rejection of variations in the analog input common-mode by the ADC. If Δ Vcm_in is the change in the common-mode voltage of the input pins and Δ Vout is the resultant change of the ADC output code (referred to the input), then Cross-Talk (only for multi-channel ADC) This is a measure of the internal coupling of a signal from adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighbouring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) ADS6222IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6222IRGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6222IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6222IRGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6223IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6223IRGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6223IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6223IRGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6224IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6224IRGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6224IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6224IRGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6225IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6225IRGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6225IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6225IRGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2007 Addendum-Page 1

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2007 Addendum-Page 2

TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant ADS6222IRGZR RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 ADS6222IRGZT RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 ADS6223IRGZR RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 ADS6223IRGZT RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 ADS6224IRGZR RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 ADS6224IRGZT RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 ADS6225IRGZR RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 ADS6225IRGZT RGZ 48 SITE 60 330 16 7.3 7.3 1.5 12 16 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 12-Jan-2008 Pack Materials-Page 1

Device Package Pins Site Length (mm) Width (mm) Height (mm) ADS6222IRGZR RGZ 48 SITE 60 342.9 345.9 28.58 ADS6222IRGZT RGZ 48 SITE 60 342.9 345.9 28.58 ADS6223IRGZR RGZ 48 SITE 60 342.9 345.9 28.58 ADS6223IRGZT RGZ 48 SITE 60 342.9 345.9 28.58 ADS6224IRGZR RGZ 48 SITE 60 342.9 345.9 28.58 ADS6224IRGZT RGZ 48 SITE 60 342.9 345.9 28.58 ADS6225IRGZR RGZ 48 SITE 60 342.9 345.9 28.58 ADS6225IRGZT RGZ 48 SITE 60 342.9 345.9 28.58 PACKAGE MATERIALS INFORMATION www.ti.com 12-Jan-2008 Pack Materials-Page 2

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