ADS61B29IRGZT

ADS61B29 TI | Alldatasheet

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www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 14-/12-Bit, 250-MSPS ADCs With Integrated Analog Buffer Integrated High Impedance Analog Input Buffer The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It Maximum Sample Rate: 250 MSPS combines high dynamic performance and low power 14-Bit Resolution ADS61B49 consumption in a compact 48-QFN package. An 12-Bit Resolution ADS61B29 integrated analog buffer makes it well-suited for 790 mW Total Power Dissipation at 250 MSPS multi-carrier, wide bandwidth communications applications. The buffer maintains constant Double Data Rate (DDR) LVDS and Parallel performance and input impedance across a wide CMOS Output Options frequency range. Programmable Fine Gain up to dB for The ADS61B49 (ADS61B29) has fine gain options SNR/SFDR Trade-Off and 1-V pp Full-Scale that can be used to improve SFDR performance at Operation lower full-scale input ranges. It includes a dc offset DC Offset Correction correction loop that can be used to cancel the ADC Supports Input Clock Amplitude Down to 400 offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. mV PP Differential At lower sampling rates, the ADC automatically 48-QFN Package (7mm 7mm) operates at scaled down power with no loss in Pin Compatible with ADS6149 Family performance. It includes internal references while the traditional reference pins and associated decoupling capacitors Multicarrier, Wide Bandwidth Communications have been eliminated. The device is specified over Wireless Multi-Carrier Communications the industrial temperature range C to C). Infrastructure ANALOG 250 MSPS 210 MSPS Software Defined Radio BUFFER Power Amplifier Linearization Feedback ADC ADS614X NO ADS6149 ADS6148 14-Bit Family 802.16d/e YES ADS61B49 Test and Measurement Instrumentation ADS612X NO ADS6129 ADS6128 12-Bit Family High Definition Video YES ADS61B29 Medical Imaging Radar Systems Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

D0_D1_P D0_D1_M D2_D3_P D4_D5_P D6_D7_P D8_D9_P D10_D1 1_P D12_D13_P D2_D3_M D4_D5_M D6_D7_M D8_D9_M D10_D1 1_M D12_D13_M OVR_SDOUT ADS61B49 RESET SCLK SEN SDA T A DFS MODE L VDS Interface A VDD AGND DRVDD DRGND Sample and Hold Analog Buffer CLOCKGEN ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

D0_D1_P D0_D1_M D2_D3_P D4_D5_P D6_D7_P D8_D9_P D10_D1 1_P D2_D3_M D4_D5_M D6_D7_M D8_D9_M D10_D1 1_M OVR_SDOUT ADS61B29 RESET SCLK SEN SDA T A DFS MODE L VDS Interface A VDD AGND DRVDD DRGND Sample and Hold Analog Buffer CLOCKGEN ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

(1) RECOMMENDED OPERATING CONDITIONS ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com PACKAGE/ORDERING INFORMATION (1) (2) SPECIFIED PACKAGE- PACKAGE LEAD/BALL PACKAGE ORDERING TRANSPORT MEDIA, PRODUCT TEMPERATURE LEAD DESIGNATOR FINISH MARKING NUMBER QUANTITY RANGE ADS61B49IRGZR ADS61B49 QFN-48 RGZ C to C Cu NiPdAu AZ61B49 Tape and reel ADS61B49IRGZT ADS61B29IRGZR ADS61B29 QFN-48 RGZ C to C Cu NiPdAu AZ61B29 Tape and reel ADS61B29IRGZT (1) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θ JA 25.41 C/W (0LFM air flow), θ JC 16.5 C/W when used with 2oz. copper trace and pad soldered directly to a JEDEC standard four layer in x in (7.62 cm x 7.62 cm) PCB. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. over operating free-air temperature range (unless otherwise noted) VALUE UNIT Supply Voltage, AVDD -0.3 to 3.9 V Supply Voltage, DRVDD -0.3 to 2.2 V Voltage between AGND and DRGND -0.3 to 0.3 V Voltage between AVDD to DRVDD (when AVDD leads DRVDD) to 3.3 V Voltage between DRVDD to AVDD (when DRVDD leads AVDD) -1.5 to 1.8 V Voltage applied to analog input pins INP, INM -0.3 to minimum (3.6, AVDD 0.3) V Voltage applied to input pins CLKP, CLKM (2) RESET, SCLK, -0.3 to (AVDD 0.3) V SDATA, SEN, DFS and MODE T A Operating free-air temperature range -40 to C T J Max Operating junction temperature 125 C T stg Storage temperature range -65 to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is 0.3V.) This prevents the ESD protection diodes at the clock input pins from turning on. over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage 3.3 3.6 V DRVDD Digital supply voltage 1.7 1.8 1.9 V ANALOG INPUTS Differential input voltage range V pp Input common-mode voltage (different than ADS6149 family) 2.3 0.1 V Maximum analog input frequency with 2Vpp input amplitude (1) 500 MHz Maximum analog input frequency with 1Vpp input amplitude (1) 800 MHz CLOCK INPUT Input clock sample rate 250 MSPS Sine wave, ac-coupled 0.3 1.5 LVPECL, ac-coupled 1.6 V pp Input clock amplitude differential CLKP V CLKM LVDS, ac-coupled 0.7 LVCMOS, single-ended, ac-coupled 3.3 V (1) See the Theory of Operations in the section. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Input clock duty cycle 40% 50% 60% DIGITAL OUTPUTS C L Maximum external load capacitance from each output pin to DRGND pF R L Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω T A Operating free-air temperature C Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com Typical values are at AVDD 3.3 DRVDD 1.8 50% clock duty cycle, dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range T MIN C to T MAX AVDD 3.3 DRVDD 1.8 V ADS61B49/ADS61B29 250 MSPS PARAMETER UNIT MIN TYP MAX ANALOG INPUT Differential input voltage range V PP Differential input resistance (at dc), See Figure k Ω Differential input capacitance, See Figure pF Analog input bandwidth 750 MHz Analog Input common-mode current (per input pin) µ A VCM common-mode output voltage (different than ADS6149 family) 2.3 V VCM output current capability mA DC ACCURACY Offset error -15 +15 mV Temperature coefficient of offset error 0.005 mV/ C Variation of offset error with supply 0.3 mV/V E GREF Gain error due to internal reference inaccuracy alone -2.5 0.2 +2.5 %FS E GCHAN Gain error of channel alone 0.2 %FS Temperature coefficient of EGCHAN .001 Δ C POWER SUPPLY I AVDD Analog supply current 200 mA Output buffer supply current, LVDS interface with 100- Ω external termination mA I DRVDD Output buffer supply current, CMOS interface F in MHz, mA 10-pF external load capacitance Analog power 660 730 mW Digital power LVDS interface 130 160 mW Digital power CMOS interface, F in MHz, 10-pF external load capacitance 101 mW Global power down mW Standby 120 mW Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Typical values are at AVDD 3.3 DRVDD 1.8 50% clock duty cycle, dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range T MIN C to T MAX AVDD 3.3 DRVDD 1.8 V ADS61B49 ADS61B29 250 MSPS 250 MSPS PARAMETER UNIT MIN TYP MAX MIN TYP MAX F in MHz 72.3 70.1 F in MHz 69.8 SNR F in 100 MHz 71.6 69.6 dBFS Signal-to-noise ratio, LVDS F in 170 MHz 68.5 70.7 66.5 F in 300 MHz 67.8 F in MHz 72.5 70.3 F in MHz 71.8 69.7 SINAD F in 100 MHz 71.6 69.5 dBFS Signal-to-noise and distortion ratio, LVDS F in 170 MHz 67.5 65.7 68.4 F in 300 MHz 67.1 66.3 ENOB F in 170 MHz (using SINAD in dBFS) 11.3 11.1 LSB Effective number of bits DNL -0.95 0.4 -0.5 0.2 LSB Differential non-linearity INL -2.5 2.5 LSB Integrated non-linearity Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com Typical values are at AVDD 3.3 DRVDD 1.8 50% clock duty cycle, dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range T MIN C to T MAX AVDD 3.3 DRVDD 1.8 V ADS61B49/ADS61B29 250 MSPS PARAMETER UNIT MIN TYP MAX F in MHz F in MHz F in 100 MHz SFDR dBc Spurious free dynamic range F in 170 MHz (all spurs/harmonics) F in 170 MHz (excluding 2nd harmonic) F in 300 MHz F in MHz F in MHz THD F in 100 MHz dBc Total harmonic distortion F in 170 MHz F in 300 MHz F in MHz F in MHz HD2 F in 100 MHz dBc Second harmonic distortion F in 170 MHz F in 300 MHz F in MHz F in MHz HD3 F in 100 MHz dBc Third harmonic distortion F in 170 MHz F in 300 MHz F in MHz F in MHz Worst Spur F in 100 MHz dBc Other than second, third harmonics F in 170 MHz F in 300 MHz MHz, MHz, Each tone at dBFS IMD dBFS 2-tone inter-modulation distortion 185 MHz, 190 MHz, Each tone at dBFS Recovery to within (of final value) for 6-dB Clock Input overload recovery overload with sine wave input Cycles PSRR For 100-mV pp signal on AVDD supply dB AC power supply rejection ratio Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

Dn_Dn+1_PDn_Dn+1_P Dn_Dn+1_MDn_Dn+1_M GNDGND VOCMVOCM Logic□0 V = –350□mVODL (1) Logic□1 V =□350□mVODH (1) T0399-01 ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level or AVDD 3.3 DRVDD 1.8 V ADS61B49/ADS61B29 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX DIGITAL INPUTS RESET, SCLK, SDATA, SEN (1) High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS 1.3 V logic levels Low-level input voltage 0.4 V SDATA, SCLK (2) V High 3.3 V High-level input current µ A SEN (3) V High 3.3 V SDATA, SCLK V Low V Low-level input current µ A SEN V Low V Input capacitance pF DIGITAL OUTPUTS CMOS INTERFACE (Pins to D13 and OVR_SDOUT) DRVDD High-level output voltage with I OH 1mA DRVDD V -0.1 Low-level output voltage with I OL 1mA 0.1 V Output capacitance (internal to device) pF DIGITAL OUTPUTS LVDS INTERFACE (Pins D0_D1_P/M to D12_D13_P/M) (4) V ODH High-level output voltage (5) 275 350 425 mV V ODL Low-level output voltage (5) 425 350 275 mV Capacitance inside the device, from either output V OCM Common-mode output voltage 1.2 1.3 V to ground Output capacitance pF (1) SCLK, SDATA, SEN function as digital input pins in serial configuration mode. (2) SDATA, SCLK have internal 200-k Ω pull-down resistor. (3) SEN has internal 100-k Ω pull-up resistor to AVDD. (4) OVR_SDOUT has CMOS output logic levels, determined by DRVDD voltage. (5) With external 100- Ω termination Figure LVDS Voltage Levels Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

(1) ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Typical values are at AVDD 3.3 DRVDD 1.8 sampling frequency 250 MSPS, sine wave input clock, C LOAD pF (2) R LOAD 100 Ω (3) Low Speed mode disabled, unless otherwise noted. Min and max values are across the full temperature range T MIN C to T MAX AVDD 3.3 DRVDD 1.7 V to 1.9 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t a Aperture delay 0.7 1.2 1.7 ns t j Aperture jitter 170 fs rms Time to valid data after coming out of STANDBY mode 0.3 µ s Time to valid data after coming out of PDN GLOBAL mode 100 Wake-up time Clock Time to valid data after stopping and restarting the input clock Cycles Clock ADC Latency (4) Default, after reset Cycles DDR LVDS MODE (5) t su Data setup time Data valid (6) to zero-crossing of CLKOUTP 0.8 1.2 ns t h Data hold time Zero-crossing of CLKOUT to data becoming invalid (6) 0.25 0.6 ns t PDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 0.2 t s t delay ns 100 MSPS Sampling frequency 250 MSPS t delay 6.2 7.5 ns Duty cycle of differential clock, (CLKOUTP CLKOUTM) LVDS bit clock duty cycle 52% 100 MSPS Sampling frequency 250 MSPS Rise time measured from 100 mV to 100 mV t RISE Data rise time, Fall time measured from 100 mV to 100 mV 0.08 0.14 0.2 ns t FALL Data fall time MSPS Sampling frequency 250 MSPS Rise time measured from 100 mV to 100 mV t CLKRISE Output clock rise time, Fall time measured from 100 mV to 100 mV 0.08 0.14 0.2 ns t CLKFALL Output clock fall time MSPS Sampling frequency 250 MSPS t OE Output enable (OE) to data delay Time to valid data after OE becomes active ns PARALLEL CMOS MODE (7) t START Input clock to data delay Input clock rising edge cross-over to start of data valid (8) 3.2 ns t DV Data valid time Time interval of valid data (8) 0.7 1.5 ns t PDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 0.78 t s t delay ns 100 MSPS Sampling frequency 150 MSPS t delay 6.5 ns Duty cycle of differential clock, (CLKOUT) Output clock duty cycle 50% 100 MSPS Sampling frequency 150 MSPS Rise time measured from 20% to 80% of DRVDD, t RISE Data rise time, Fall time measured from 80% to 20% of DRVDD, 0.7 1.2 ns t FALL Data fall time MSPS Sampling frequency 250 MSPS Rise time measured from 20% to 80% of DRVDD, t CLKRISE Output clock rise time, Fall time measured from 80% to 20% of DRVDD, 0.5 1.5 ns t CLKFALL Output clock fall time MSPS Sampling frequency 150 MSPS t OE Output enable (OE) to data delay Time to valid data after OE becomes active ns (1) Timing parameters are specified by design and characterization and not tested in production. (2) C LOAD is the effective external single-ended load capacitance between each output pin and ground (3) R LOAD is the differential load resistance between the LVDS output pair. (4) At higher frequencies, t PDI is greater than one clock period and overall latency ADC latency (5) Measurements are done with a transmission line of 100- Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to logic high of +100 mV and logic low of 100 mV. (7) For F s 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). (8) Data valid refers to logic high of 1.26 V and logic low of 0.54 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 LVDS Timings at Lower Sampling Frequencies SETUP TIME, ns HOLD TIME, ns SAMPLING FREQUENCY, MSPS MIN TYP MAX MIN TYP MAX 210 1.0 1.4 0.4 0.8 190 1.1 1.5 0.5 0.9 170 1.3 1.7 0.7 1.1 150 1.6 1.9 0.9 1.2 125 1.9 2.2 1.1 1.4 100 2.5 2.0 Enable low speed mode t PDI ns MIN TYP MAX F s 100, 8.2 Enable low speed mode CMOS Timings at Lower Sampling Frequencies TIMINGS SPECIFIED WITH RESPECT TO INPUT CLOCK SAMPLING FREQUENCY, MSPS t START ns DATA VALID TIME, ns MIN TYP MAX MIN TYP MAX 210 1.7 1.6 2.4 190 0.4 2.2 3.0 170 5.1 2.4 3.6 150 4.8 3.0 4.3 TIMINGS SPECIFIED WITH RESPECT TO CLKOUT SAMPLING FREQUENCY, MSPS SETUP TIME, ns HOLD TIME, ns MIN TYP MAX MIN TYP MAX 150 2.0 3.2 1.5 2.2 125 2.9 2.2 2.7 100 5.0 3.8 Enable low speed mode t PDI ns MIN TYP MAX F s 100 Enable low speed mode Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

18□Clock□Cycles* T0105-10 E E E E E E E E E EO O O O O O O O O O Input Clock CLKOUTM CLKOUTP Output□Data DXP,□DXM DDR LVDS N–18 N–17 N–16 N–15 N–14 N–1 N N+1 N+2 N–18 N–17 N–16 N–15 N N+2 18□Clock□Cycles* CLKOUT Output□Data Parallel CMOS Input Signal Sample N N+1 N+2 N+3 N+4 th tPDI ta tsu th tPDI CLKP CLKM N+18 N+19 N+20 tsu E – Even Bits D0,D2,D4,... O – Odd Bits D1,D3,D5, ... N+1 * This□is□the ADC□latency. At□higher□sampling□frequencies,□t >□1□clock□cycle. Then,□overall□latency□= ADC□latency□+□1. PDI ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Figure Latency Diagram Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

Data□Pair CLKP CLKOUTP Dn_Dn+1_P, Dn_Dn+1_M CLKM tPDI tsu th th tsu CLKOUTM (1) Dn – Bits□D0,□D2,□D4,... (2) Dn+1 – Bits□D1,□D3,□D5,□... Dn (1) Dn+1 (2) T0107-05 Output Data Dn tSTART Dn* Input Clock CLKM CLKP Input Clock Output Clock Output Data CLKM Dn CLKP tsu th CLKOUT Dn* tPDI tDV ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Figure LVDS Mode Timing Figure CMOS Mode Timing Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com The ADS61B49/29 can be configured independently using either parallel interface control or serial interface programming. To put the device in parallel configuration mode, keep RESET tied to high (DRVDD). Now, pins DFS, MODE, SEN, and SDATA can be used to directly control certain modes of the ADC. The device can be easily configured by connecting the parallel pins to the correct voltage levels (as described in Table to Table There is no need to apply reset. In this mode, SEN and SDATA function as parallel interface control pins. Frequently used functions can be controlled in this mode standby, selection between LVDS/CMOS output formats, complement/straight binary output format, and position of the output clock edge. Table briefly describes the modes controlled by the parallel pins. Table Parallel Pin Functions TYPE OF PIN CONTROL MODES CONTROL DFS Analog Data format and LVDS/CMOS output interface. In the ADS61B49/B29, external reference is not supported. Prior use of the MODE pin in the ADS6149/29 family is therefore not the same in the ADS61B49/B29 family. In the next generation pin-compatible MODE Analog ADC family, MODE is converted to a digital control pin for certain reserved functions. The MODE pin can be routed to a digital controller for possible future migration to a next generation ADC. SEN Analog CLKOUT edge programmability. Global power down (ADC, internal references and output buffers are SDATA Digital powered down) To exercise this mode, first the serial registers have to be reset to their default values and the RESET pin has to be kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by setting the RESET bit (D7 in register 0x00) high. The serial interface section describes register programming and register reset in more detail. Since the parallel pin DFS is not to be used in this mode, it has to be tied to ground. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 For increased flexibility, an additional configuration mode is supported wherein a combination of serial interface registers and parallel pin control (DFS) can be used to configure the device. To exercise this mode, the serial registers have to be reset to their default values and the RESET pin has to be kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the internal registers of ADC. The registers can be reset either by applying a pulse on the RESET pin or by setting the RESET bit (D7 in register 0x00) high. The serial interface section describes register programming and register reset in more detail. The parallel interface control pin DFS can be used and its function is determined by the appropriate voltage levels as described in Table The voltage levels can be easily derived, by using a resistor string as illustrated with an example as shown in Figure Since some functions can be controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table as listed in Table Table Priority Between Parallel Pins and Serial Registers FUNCTION PRIORITY MODE is not used in this device (legacy from the ADS6149 and future family this pin could be Int/ext reference not used redefined) DFS pin controls this selection ONLY if the register bits DATA FORMAT 00, otherwise DATA Data format selection FORMAT controls the selection DFS pin controls this selection ONLY if the register bits LVDS CMOS 00, otherwise LVDS LVDS or CMOS interface selection CMOS controls the selection Table SDATA DIGITAL CONTROL PIN SDATA (default) AVDD Global power down. ADC, internal references and the output buffers are powered down. Table SEN ANALOG CONTROL PIN SEN (1) LVDS: Data and output clock transitions are aligned CMOS: Setup time increases by (6xT s /26), hold time reduces by (6xT s /26) LVDS: Setup time decreases by (4xT s /26), hold time increases by (4xT s /26) (3/8)AVDD CMOS: Setup time increases by (9xT s /26), hold time reduces by (9xT s /26) LVDS: Setup time increases by (4xT s /26), hold time reduces by (4xT s /26) (5/8)AVDD CMOS Setup time increases by (3xT s /26), hold time reduces by (3xT s /26) Default output clock position (setup/hold timings of output data with respect to this clock position is specified in the AVDD timing characteristics table). (1) T s sampling frequency Table DFS ANALOG CONTROL PIN DFS (3/8)AVDD complement data and parallel CMOS output (5/8)AVDD Offset binary data and parallel CMOS output AVDD Offset binary data and DDR LVDS output Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

To□Parallel□Pin GND GND AVDD AVDD (5/8) AVDD (5/8) AVDD (3/8) AVDD (3/8) AVDD S0321-01 SERIAL INTERFACE Register Initialization ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Table MODE ANALOG CONTROL PIN MODE ADS61B49/B29, external reference is not supported. The prior use of the MODE pin in ADS6149/29 family is therefore not the same in the ADS61B49/B29 family. In the next generation pin-compatible ADC family, MODE Not used could be converted to a digital control pin for certain reserved functions. The MODE pin can be routed to a digital controller for possible future migration to a next generation ADC. Figure Simple Scheme to Configure Parallel Pins SEN and SCLK The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first bits form the register address, and the remaining bits are the register data. The interface can work with a SCLK frequency from MHz down to very low speeds (few hertz) and also with a non-50% SCLK duty cycle. After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two ways: Either through hardware reset by applying a high-going pulse on the RESET pin (of width greater than ns) as shown in Figure OR By applying a software reset. Using the serial interface, set the RESET bit (D7 in register 0x00) to high. This initializes the internal registers to their default values and then self-resets the RESET bit to low. In this case the RESET pin is kept low. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

Register Address Register□Data t(SCLK) t(DSU) t(DH) t(SLOADS) D7A7 D3A3 D5A5 D1A1 D6A6 D2A2 D4A4 D0A0SDATA SCLK SEN RESET t(SLOADH) SERIAL INTERFACE TIMING CHARACTERISTICS SERIAL REGISTER READOUT ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Figure Serial Interface Timing Typical values at min and max values across the full temperature range T MIN C to T MAX AVDD 3.3 DRVDD 1.8 unless otherwise noted. PARAMETER MIN TYP MAX UNIT f SCLK SCLK frequency t SCLK dc MHz t SLOADS SEN to SCLK setup time ns t SLOADH SCLK to SEN hold time ns t DS SDATA setup time ns t DH SDATA hold time ns The device includes an option where the

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back. This may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. First, set register bit SERIAL READOUT This also disables any further writes into the registers (EXCEPT register bit SERIAL READOUT itself). Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read. The device outputs the (D7-D0) of the selected register on the OVR_SDOUT pin. The external controller can latch the SCLK. To enable register writes, reset register bit SERIAL READOUT Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

OVR_SDOUT Register Address□(A7:A0)□=□0x3F Register□Data□(D7:D0)□=□XX□(Don't□Care) B)□Read□contents□of□register□0x3F. This□register□has□been□initialized□with□0x04□(device□is□put□in□global□power□down□mode) Pin□OVR_SDOUT functions□as□serial□readout□(<SERIAL READOUT>□=□1) D70 D30 D50 D10 D60 D20 D40 D00SDATA SCLK SEN OVR_SDOUT Register Address□(A7:A0)□=□0x00 Register□Data□(D7:D0)□=□0x01 A)□Enable□serial□readout□(<SERIAL READOUT>□=□1) Pin□OVR_SDOUT functions□as□OVR□(<SERIAL READOUT>□=□0) ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Figure Serial Readout Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

Power□Supply AVDD,□DRVDD RESET SEN SERIAL REGISTER MAP ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Typical values at min and max values across the full temperature range T MIN C to T MAX unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t Power-on delay time Delay from power-up of AVDD and DRVDD to RESET pulse active ms ns t Reset pulse width Pulse width of active RESET signal that resets the serial registers µ s t Delay time Delay from RESET disable to SEN active 100 ns Figure Reset Timing Diagram Table Summary of Functions Supported by Serial Interface (1) REGISTER ADDRESS REGISTER FUNCTIONS IN HEX RESET SERIAL Software READOUT Reset ENABLE LOW SPEED MODE PDN PDN REF (RESERVED) STANDBY GLOBAL OBUF LVDS CMOS Output interface CLKOUT POSN Output clock position control DATA FORMAT complement or offset binary CUSTOM PATTERN LOW CUSTOM PATTERN HIGH ENABLE OFFSET CORR OFFSET CORR TIME CONSTANT FINE GAIN Offset correction time constant TEST PATTERNS PROGRAM OFFSET PEDESTAL (1) Multiple functions in a register can be programmed in a single write operation. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com IN HEX RESET SERIAL READOUT Software Reset RESET Software reset applied resets all internal registers and self-clears to SERIAL READOUT Serial readout disabled Serial readout enabled, pin OVR_SDOUT functions as serial data readout. IN HEX ENABLE LOW SPEED MODE ENABLE LOW SPEED MODE Low speed mode disabled. Use for sampling frequency 100 MSPS Enable low speed mode for sampling frequencies 100 MSPS. IN HEX PDN PDN REF (RESERVED) STANDBY GLOBAL OBUF D6,D5 REF RESERVED (Not used) In the ADS61B49/61B29, external reference mode is not supported. See ADS6149/6129 non-buffered ADCs if an external reference is required. This register controls the reference mode in those devices. PDN GLOBAL Normal operation Total power down ADC, internal references and output buffers are powered down. Slow wake-up time. STANDBY Normal operation ADC alone powered down. Internal references, output buffers are active. Quick wake-up time PDN OBUF Power down output buffer Output buffer enabled Output buffer powered down IN HEX LVDS CMOS D7,D6 LVDS CMOS DFS pin controls LVDS or CMOS interface selection DDR LVDS interface Parallel CMOS interface IN HEX CLKOUT POSN Output clock position control Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 LVDS Interface D7-D5 CLKOUT POSN Output clock rising edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Rising edge shifted by (4/26)T s 110 Rising edge aligned with data transition 111 Rising edge shifted by (4/26)T s D4-D2 CLKOUT POSN Output clock falling edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Falling edge shifted by (4/26)T s 110 Falling edge aligned with data transition 111 Falling edge shifted by (4/26)T s CMOS Interface D7-D5 CLKOUT POSN Output clock rising edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Rising edge shifted by (4/26)T s 110 Rising edge shifted by (6/26)T s 111 Rising edge aligned with data transition D4-D2 CLKOUT POSN Output clock falling edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Falling edge shifted by (4/26)T s 110 Falling edge shifted by (6/26)T s 111 Falling edge aligned with data transition IN HEX DATA FORMAT complement or offset binary D2,D1 DATA FORMAT DFS pin controls data format selection complement Offset binary IN HEX Custom LOW Custom HIGH CUSTOM LOW lower bits of custom pattern available at the output instead of ADC data. CUSTOM HIGH upper bits of custom pattern available at the output instead of ADC data Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com IN HEX ENABLE OFFSET CORR Offset correction enable ENABLE OFFSET CORR Offset correction disabled Offset correction enabled IN HEX FINE GAIN OFFSET CORR TC Offset correction time constant FINE GAIN Gain programmability in 0.5-dB steps 0000 0-dB gain, default after reset 0001 0.5-dB gain 0010 1.0-dB gain 0011 1.5-dB gain 0100 2.0-dB gain 0101 2.5-dB gain 0110 3.0-dB gain 0111 3.5-dB gain 1000 4.0-dB gain 1001 4.5-dB gain 1010 5.0-dB gain 1011 5.5-dB gain 1100 6.0-dB gain OFFSET CORR TC Time constant of correction loop in number of clock cycles. See Offset Correction in application section. 0000 256 k 0001 512 k 0010 M 0011 M 0100 M 0101 M 0110 M 0111 M 1000 M 1001 128 M 1010 256 M 1011 512 M 1100 to 1111 Reserved Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 IN HEX TEST PATTERNS TEST PATTERNS Test patterns to verify data capture 000 Normal operation 001 Outputs all zeros 010 Outputs all ones 011 Outputs toggle pattern 100 Outputs digital ramp 101 Outputs custom pattern 110 Unused 111 Unused IN HEX OFFSET PEDESTAL OFFSET PEDESTAL When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. For example, See Offset Correction in application section. 011111 Mid-code LSB 011110 Mid-code LSB 011101 Mid-code LSB .... 000000 Mid-code 111111 Mid-code LSB 111110 Mid-code LSB .... 100000 Mid-code LSB Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

M DRVDD AGND OVR_SDOUT IN P CLKOUTM IN M CLKOUTP AGND DFS AVDD OE AG ND AVDD AVDD AGND NC CLKP AVD D CLKM M ODE AGND AVDD 13 14 15 16 17 18 19 20 21 22 23 24 DRGND D12_ D13_P DRVDD D12_D13 D0_D1_P D10 _D11_P D0_D1_M D10_D1 1_M NC _D9_P NC D8_D9_M RESET D6_ D7_P SCLK D6_D7_ M SDA T A _D5_P SEN D4_D5 A VDD D2_D3 AGND _D3_M 48 47 46 45 44 43 42 41 40 39 38 37 Thermal□Pad Pad□is□connected□to□DRGND P0023-13 DRGND VC M DRVDD AGND OVR_SDOUT IN P CLKOUTM IN M CLKOUTP AGND DFS AVDD OE AG ND AVDD AVDD AGND NC CLKP AVD D CLKM M ODE AGND AVDD 13 14 15 16 17 18 19 20 21 22 23 24 DRGND D10_ D11_P DRVDD D10_D11 NC D8_ D9_P NC D8_D9_ M NC _D7_P NC D6_D7_M RESET D4_ D5_P SCLK D4_D5_ M SDA T A _D3_P SEN D2_D3 A VDD D0_D1 AGND _D1_M 48 47 46 45 44 43 42 41 40 39 38 37 Thermal□Pad Pad□is□connected□to□DRGND ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Figure PIN CONFIGURATION (LVDS MODE) ADS61B49 Figure 10. PIN CONFIGURATION (LVDS MODE) ADS61B29 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Table PIN ASSIGNMENTS (LVDS MODE) ADS61B49 and ADS61B29 PIN NO. I/O of NO. PINS 18, 20, AVDD I 3.3-V analog power supply 22, 24, 12, 14, AGND I Analog ground 17, 19, CLKP, CLKM 10, I Differential clock input INP, INM 15, I Differential analog input Internal reference mode Common-mode voltage output. VCM IO External reference mode Reference input. The voltage forced on this pin sets the internal references. Serial interface RESET input. When using serial interface mode, the user MUST initialize the internal registers through a hardware RESET by applying a high-going pulse on this pin or by using the software reset option. Refer to the SERIAL INTERFACE section. RESET I In parallel interface mode, the user has to tie the RESET pin permanently high. (SDATA and SEN are used as parallel pin controls in this mode.) The pin has an internal 100-k Ω pull-down resistor. SCLK I Serial interface clock input. The pin has an internal 100-k Ω pull-down resistor. This pin functions as the serial interface data input when RESET is low. It functions as the power-down control pin when RESET is tied high. SDATA I See Table for detailed information. The pin has an internal 100-k Ω pull-down resistor. This pin functions as the serial interface enable input when RESET is low. It functions as the output clock edge control when RESET is tied high. See Table for detailed SEN I information. The pin has an internal 100-k Ω pull-up resistor to AVDD. OE I Output buffer enable input, active high. The pin has an internal 100-k Ω pull-up resistor to DRVDD Data format select input. This pin sets the data format (2s complement or offset binary) and the LVDS/CMOS output interface type. DFS I See Table for detailed information. MODE (1) I Not used. See Table and note below for detailed information. CLKOUTP O Differential output clock, true CLKOUTM O Differential output clock, complement D0_D1_P O Differential output data and multiplexed, true D0_D1_M O Differential output data and multiplexed, complement D2_D3_P O Differential output data and multiplexed, true D2_D3_M O Differential output data and multiplexed, complement D4_D5_P O Differential output data and multiplexed, true D4_D5_M O Differential output data and multiplexed, complement See D6_D7_P O Differential output data and multiplexed, true Figure and D6_D7_M O Differential output data and multiplexed, complement Figure D8_D9_P O Differential output data and multiplexed, true D8_D9_M O Differential output data and multiplexed, complement D10_D11_P O Differential output data D10 and D11 multiplexed, true D10_D11_M O Differential output data D10 and D11 multiplexed, complement D12_D13_P O Differential output data D12 and D13 multiplexed, true D12_D13_M O Differential output data D12 and D13 multiplexed, complement It is a CMOS output with logic levels determined by the DRVDD supply. It functions as an out-of-range indicator OVR_SDOUT O after a reset and when register bit SERIAL READOUT It functions as the serial register readout pin when register bit SERIAL READOUT DRVDD I 1.8-V digital and output buffer supply DRGND 36, PAD I Digital and output buffer ground (1) In the next generation pin-compatible ADC family, MODE is converted to a digital control pin for certain reserved functions. So, the selection of the internal or external reference and low speed functions are supported using MODE. In a system board using the ADS61x9/x8, the MODE pin can be routed to a digital controller. This avoids board modification if migrating to the next generation ADC. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com Table PIN ASSIGNMENTS (LVDS MODE) ADS61B49 and ADS61B29 (continued) PIN NO. I/O of NO. PINS See Figure NC Do not connect and Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

M DRVDD AGND OVR_SDOUT IN P UNUSED IN M CLKOUT AGND DFS AVDD OE AG ND AVDD AVDD AGND NC CLKP AVD D CLKM M ODE AGND AVDD 13 14 15 16 17 18 19 20 21 22 23 24 DRGND D13 DRVDD D12 D11 D10 NC NC RESET SCLK SDA T A SEN A VDD AGND 48 47 46 45 44 43 42 41 40 39 38 37 Thermal□Pad Pad□is□connected□to□DRGND P0023-15 DRGND VC M DRVDD AGND OVR_SDOUT IN P UNUSED IN M CLKOUT AGND DFS AVDD OE AG ND AVDD AVDD AGND NC CLKP AVD D CLKM M ODE AGND AVDD 13 14 15 16 17 18 19 20 21 22 23 24 DRGND D11 DRVDD D10 NC NC NC NC RESET SCLK SDA T A SEN A VDD AGND 48 47 46 45 44 43 42 41 40 39 38 37 Thermal□Pad Pad□is□connected□to□DRGND ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Figure 11. PIN CONFIGURATION (CMOS MODE) ADS61B49 Figure 12. PIN CONFIGURATION (CMOS MODE) ADS61B29 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com PIN ASSIGNMENTS (CMOS MODE) ADS61B49 and ADS61B29 PIN NO. of I/O NO. 18, 20, AVDD I 3.3-V analog power supply 22, 24, 12, 14, AGND I Analog ground 17, 19, CLKP, CLKM 10, I Differential clock input INP, INM 15, I Differential analog input Internal reference mode Common-mode voltage output. VCM IO External reference mode Reference input. The voltage forced on this pin sets the internal references. Serial interface RESET input. When using serial interface mode, the user MUST initialize the internal registers through a hardware RESET by applying a high-going pulse on this pin or by using the software reset option. Refer to the SERIAL INTERFACE section. RESET I In parallel interface mode, the user has to tie the RESET pin permanently high. (SDATA and SEN are used as parallel pin controls in this mode.) The pin has an internal 100-k Ω pull-down resistor. SCLK I Serial interface clock input. The pin has an internal 100-k Ω pull-down resistor. This pin functions as the serial interface data input when RESET is low. It functions as the power-down control pin when RESET is tied high. SDATA I See Table for detailed information. The pin has an internal 100-k Ω pull-down resistor. This pin functions as the serial interface enable input when RESET is low. It functions as the output clock edge control when RESET is tied high. See Table for detailed SEN I information. The pin has an internal 100-k Ω pull-up resistor to DVDD. Data format select input. This pin sets the data format (2s complement or offset binary) and the LVDS/CMOS output interface type. DFS I See Table for detailed information. MODE (1) I Not used. See Table and note below for detailed information. CLKOUT O CMOS output clock Output buffer enable input, active high. The pin has an internal 100-k Ω pull-up resistor to OE I DRVDD See Figure D13 O 14-bit/12-bit CMOS output data and Figure It is a CMOS output with logic levels determined by the DRVDD supply. It functions as an OVR_SDOUT O out-of-range indicator after a reset and when register bit SERIAL READOUT It functions as the serial register readout pin when SERIAL READOUT DRVDD I 1.8-V digital and output buffer supply DRGND 36, PAD I Digital and output buffer ground UNUSED Unused pin in CMOS mode See Figure NC Do not connect and Figure (1) In the next generation pin-compatible ADC family, MODE is converted to a digital control pin for certain reserved functions. So, the selection of the internal or external reference and low speed functions are supported using MODE. In a system board using the ADS61x9/x8, the MODE pin can be routed to a digital controller. This avoids board modification while migrating to the next generation ADC. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G001 SFDR = 91.5 dBc SINAD = 72.5 dBFS SNR = 72.6 dBFS THD = 86.8 dBc f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G002 SFDR = 88.9 dBc SINAD = 72.1 dBFS SNR = 72.2 dBFS THD = 84.9 dBc f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G003 SFDR = 80.3 dBc SINAD = 70.2 dBFS SNR = 70.7 dBFS THD = 79.2 dBc f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G004 SFDR = 75.7 dBc SINAD = 67.2 dBFS SNR = 68.4 dBFS THD = 72.4 dBc f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G005 fIN1 = 190 MHz, –7 dBFS fIN2 = 185 MHz, –7 dBFS 2-Tone IMD = –90 dBFS SFDR = –95 dBFS f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G006 fIN1 = 190.1 MHz, –36 dBFS fIN2 = 185.1 MHz, –36 dBFS 2-Tone IMD = –112 dBFS SFDR = –99 dBFS ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) FFT for MHz INPUT SIGNAL FFT for MHz INPUT SIGNAL Figure 13. Figure 14. FFT for 170 MHz INPUT SIGNAL FFT for 300 MHz INPUT SIGNAL Figure 15. Figure 16. FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD) Figure 17. Figure 18. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G007 Gain = 0 dB fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G008 Gain = 0 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G009 Input adjusted to get −1dBFS input 1 dB0 dB 6 dB 2 dB 3 dB 4 dB 5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SINAD − dBFS G010 5 dB 1 dB 4 dB 6 dB Input adjusted to get −1dBFS input 2 dB 3 dB 0 dB ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS ADS61B49 (continued) All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) SFDR SNR vs vs INPUT FREQUENCY INPUT FREQUENCY Figure 19. Figure 20. SFDR SINAD vs vs INPUT FREQUENCY and INTERNAL GAIN INPUT FREQUENCY and INTERNAL GAIN Figure 21. Figure 22. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

SNR − dBFS VCM − Common-Mode Voltage − V fIN = 65 MHz External Reference Mode SFDR − dBc G012 SNR SFDR SNR − dBFS Input Amplitude − dBFS 100 120 SFDR − dBc, dBFS G011 SFDR (dBc) SFDR (dBFS) SNR (dBFS) fIN = 65 MHz TA − Free-Air Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G013 AVDD = 3 V AVDD = 3.2 V AVDD = 3.4 V AVDD = 3.6 V AVDD = 3.5 V DRV DD = 1.8 V fIN = 65 MHz AVDD = 3.1 V AVDD = 3.3 V TA − Free-Air Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G014 AVDD = 3.3 V fIN = 65 MHz DRV DD = 1.9 V DRV DD = 1.7 V DRV DD = 2 V DRV DD = 1.8 V ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS ADS61B49 (continued) All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE PERFORMANCE vs vs INPUT AMPLITUDE INPUT COMMON-MODE VOLTAGE Figure 23. Figure 24. SFDR SFDR vs vs TEMPERATURE and AVDD TEMPERATURE and DRVDD Figure 25. Figure 26. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

TA − Free-Air Temperature − °C 71.0 71.5 72.0 72.5 73.0 −40 −20 0 20 40 60 80 SNR − dBFS G015 AVDD = 3 V AVDD = 3.2 V, AVDD = 3.4 V DRV DD = 1.8 V fIN = 65 MHz AVDD = 3.1 V AVDD = 3.3 V, AVDD = 3.5 V AVDD = 3.6 V TA − Free-Air Temperature − °C 71.0 71.5 72.0 72.5 73.0 73.5 74.0 −40 −20 0 20 40 60 80 SNR − dBFS G016 AVDD = 3.3 V fIN = 65 MHz DRV DD = 1.9 V, DRV DD = 2 V DRV DD = 1.7 V DRV DD = 1.8 V SNR − dBFS Input Clock Duty Cycle − % G018 35 40 45 50 55 60 65 SFDR − dBc SNR SFDR fIN = 65 MHz SNR − dBFS SFDR − dBc Input Clock Amplitude − VPP G017 SNR SFDR fIN = 65 MHz Output Code 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 Occurence − % G019 RMS (LSB) = 1.179 ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS ADS61B49 (continued) All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) SNR SNR vs vs TEMPERATURE and AVDD TEMPERATURE and DRVDD Figure 27. Figure 28. PERFORMANCE PERFORMANCE vs vs INPUT CLOCK AMPLITUDE INPUT CLOCK DUTY CYCLE Figure 29. Figure 30. OUTPUT NOISE HISTOGRAM Figure 31. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G020 SFDR = 91.9 dBc SINAD = 70.3 dBFS SNR = 70.3 dBFS THD = 86.9 dBc f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G021 SFDR = 88.7 dBc SINAD = 70 dBFS SNR = 70.1 dBFS THD = 84.8 dBc f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G022 SFDR = 80.1 dBc SINAD = 68.8 dBFS SNR = 69.1 dBFS THD = 79 dBc f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G023 SFDR = 75.7 dBc SINAD = 66.4 dBFS SNR = 67.4 dBFS THD = 72.3 dBc f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G024 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.1 MHz, –7 dBFS 2-Tone IMD = –89.7 dBFS SFDR = –96 dBFS f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G025 fIN1 = 190.1 MHz, –36 dBFS fIN2 = 185.1 MHz, –36 dBFS 2-Tone IMD = –110 dBFS SFDR = –99 dBFS ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) FFT for MHz INPUT SIGNAL FFT for MHz INPUT SIGNAL Figure 32. Figure 33. FFT for 170 MHz INPUT SIGNAL FFT for 300 MHz INPUT SIGNAL Figure 34. Figure 35. FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD) Figure 36. Figure 37. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G026 Gain = 0 dB fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G027 Gain = 0 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G028 Input adjusted to get −1dBFS input 1 dB 0 dB 6 dB 2 dB 4 dB 5 dB 3 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SINAD − dBFS G029 5 dB 1 dB 4 dB 6 dB Input adjusted to get −1dBFS input 2 dB 3 dB 0 dB ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS ADS61B29 (continued) All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) SFDR SNR vs vs INPUT FREQUENCY INPUT FREQUENCY Figure 38. Figure 39. SFDR SINAD vs vs INPUT FREQUENCY and INTERNAL GAIN INPUT FREQUENCY and INTERNAL GAIN Figure 40. Figure 41. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

SNR − dBFS Input Amplitude − dBFS 100 120 SFDR − dBc, dBFS G030 SFDR (dBc) SFDR (dBFS) SNR (dBFS) fIN = 65 MHz SNR − dBFS VCM − Common-Mode Voltage − V fIN = 65 MHz External Reference Mode SFDR − dBc G031 SNR SFDR TA − Free-Air Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G032 AVDD = 3.2 V AVDD = 3.4 VAVDD = 3.5 V DRV DD = 1.8 V fIN = 65 MHz AVDD = 3.1 V AVDD = 3.3 V AVDD = 3 V AVDD = 3.6 V TA − Free-Air Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G033 AVDD = 3.3 V fIN = 65 MHz DRV DD = 1.9 V DRV DD = 1.7 V DRV DD = 2 V DRV DD = 1.8 V ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS ADS61B29 (continued) All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE PERFORMANCE vs vs INPUT AMPLITUDE INPUT COMMON-MODE VOLTAGE Figure 42. Figure 43. SFDR SFDR vs vs TEMPERATURE and AVDD TEMPERATURE and DRVDD Figure 44. Figure 45. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

TA − Free-Air Temperature − °C 69.0 69.5 70.0 70.5 71.0 −40 −20 0 20 40 60 80 SNR − dBFS G034 AVDD = 3 V DRV DD = 1.8 V fIN = 65 MHz AVDD = 3.2 V AVDD = 3.1 V, AVDD = 3.3 V, AVDD = 3.4 V, AVDD = 3.5 V, AVDD = 3.6 V TA − Free-Air Temperature − °C 69.0 69.5 70.0 70.5 71.0 −40 −20 0 20 40 60 80 SNR − dBFS G035 AVDD = 3.3 V fIN = 65 MHz DRV DD = 1.7 V, DRV DD = 1.9 V DRV DD = 1.8 V DRV DD = 2 V SNR − dBFS SFDR − dBc Input Clock Amplitude − VPP G036 SNR SFDR fIN = 65 MHz SNR − dBFS Input Clock Duty Cycle − % G037 35 40 45 50 55 60 65 SFDR − dBc SNR SFDR fIN = 65 MHz Output Code 100 2051 2052 2053 2054 2055 2056 2057 2058 2059 Occurence − % G038 RMS (LSB) = 0.3 ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS ADS61B29 (continued) All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) SNR SNR vs vs TEMPERATURE and AVDD TEMPERATURE and DRVDD Figure 46. Figure 47. PERFORMANCE PERFORMANCE vs vs INPUT CLOCK AMPLITUDE INPUT CLOCK DUTY CYCLE Figure 48. Figure 49. OUTPUT NOISE HISTOGRAM Figure 50. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

(Both ADS61B49/61B29) f − Frequency − MHz −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 Amplitude − dB G042 SINAD = 67.8 dBFS THD = 82 dBc Amp (fCM ) = 86.5 dBFS Amp (fIN + fCM ) = 74.5 dBFS Amp (fIN − fCM ) = 72.3 dBFS fIN = 65 MHz fCM = 40 MHz, 140 mVpp HD3 = 86 dBc SNR = 68.1 dBFS fCM HD3 fIN + fCM fIN − fCM fIN − Input Frequency − Hz −80 −70 −60 −50 −40 −30 −20 −10 0 50 100 150 200 250 300 CMRR − dB G039 fS − Sampling Frequency − MSPS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 50 100 150 200 250 P − Total Power − W G040 LVDS CMOS C L = 10 pF CMOS C L = 0 pF fS − Sampling Frequency − MSPS 100 0 50 100 150 200 250 IDRVDD − DRVDD Current − mA G041 fIN = 3 MHz LVDS CMOS C L = 10 pF CMOS C L = 0 pF ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 All plots are at AVDD 3.3 DRVDD 1.8 maximum rated sampling frequency, sine wave input clock. 1.5-V PP differential clock amplitude, 50% clock duty cycle, DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) CMRR vs INPUT FREQUENCY FFT SHOWING EFFECTS OF COMMON-MODE SIGNAL Figure 51. Figure 52. TOTAL POWER DRVDD CURRENT vs vs SAMPLING FREQUENCY SAMPLING FREQUENCY Figure 53. Figure 54. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPS S SFDR□-□dBc 250 350 500 100 200 120 140 160 180 220 240 250 70 75 M0049-22 80 85 100 300 450400 20 50 150 200 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPSS SFDR□-□dBc 250 350 500 100 200 120 140 160 180 220 240 250 M0049-23 80 85 100 300 450400 ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Plots are at AVDD 3.3 DRVDD 1.8 sine wave input clock, 1.5-V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) Figure 55. SFDR Contour Plot (0-dB gain) Figure 56. SFDR Contour Plot (6-dB gain) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPS S SNR□-□dBFS 250 350 500 100 200 120 140 160 180 220 240 250 64 66 68 M0048-22 6566 100 300 450400 20 50 150 200 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPSS SNR□-□dBFS 250 350 500 100 200 120 140 160 180 220 240 250 63 64 65 M0048-23 66 65.5 65.5 65.5 64.5 64.5 64.5 66.5 66.5 66.5 100 300 450400 ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Plots are at AVDD 3.3 DRVDD 1.8 sine wave input clock, 1.5-V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) Figure 57. SNR Contour Plot (0-dB gain) Figure 58. SNR Contour Plot (6-dB gain) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPSS SNR□-□dBFS 250 350 500 100 200 120 140 160 180 220 240 250 65 66 68 M0048-24 68.5 68.5 67.5 66.5 66.5 66.5 65.5 65.5 65.5 64.5 64.5 67.5 67.568.5 69 67 66 69.5 69.5 69.5 70.5 70.5 100 300 450400 7067 20 50 150 200 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPSS SNR□-□dBFS 250 350 500 100 200 120 140 160 180 220 240 250 63 65 M0048-25 66.5 66.5 65.5 65.5 65.5 64.5 64.5 63.5 63.5 64.5 100 300 450400 6664 ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Plots are at AVDD 3.3 DRVDD 1.8 sine wave input clock, 1.5-V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) Figure 59. SNR Contour Plot (0-dB gain) Figure 60. SNR Contour Plot (6-dB gain) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

2.3□V Req Buf Req Buf Ceq Buf Ceq Buf Cbond 1 pF/c187 Cbond 1 pF/c187 Resr 100/c187 /c87 Resr 100/c187 /c87 Sample and Hold Ceq□Buf□(Equivalent□Input□Capacitance□of□the□Buffer)□=□3□pF Req□Buf 10 No Capacitance□Shown□for□Soldered-Down□Package, Typically□1□pF–2□pF□to□Ground /c187 /c87 ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 The ADS61B49/29 are high performance, low power 14-bit and 12-bit A/D converters with maximum sampling rates up to 250 MSPS. The primary difference from the ADS6149/29 is the addition of an integrated analog buffer (hence B in the device name). The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline resulting in a data latency of clock cycles. The output is available as 14-bit/12-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary complement format. The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with 2-Vpp amplitude) and about 800MHz (with 1-Vpp amplitude) before the performance becomes ill-behaved. This is separate from the full power analog bandwidth of 750MHz, which is only an indicator of signal amplitude versus frequency. The analog input consists of an integrated input buffer followed by a switched-capacitor based differential sample and hold architecture. The addition of a buffer provides isolation from the non-linear impedance and switching transients of the switched-capacitor circuit. With a constant input impedance, the ADC is easier to drive and to reproduce data sheet measurements. For wide-band applications, like power amplifier linearization, the signal gain across frequency is more consistent. Spectral performance variance across frequency is also reduced. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 2.3 available on the VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM+ 0.5 V and VCM 0.5 resulting in a 2-V pp differential input swing. Figure 61. Analog Input Equivalent Circuit The input sampling circuit has a high 3-dB bandwidth that extends up to 750 MHz (measured from the input pins to the sampled voltage). Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

0 100 200 300 400 500 600 700 800 900 1000 f − Frequency − MHz R IN − Input Resistance − kΩ 0.01 100 0.1 G081 ADS61B49 ADS6149 f − Frequency − MHz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 100 200 300 400 500 600 700 800 900 1000 C IN − Input Capacitance − pF G082 ADS6149 ADS61B49 ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even-order harmonic rejection. A Ω resistor in series with each input pin is recommended to dampen out ringing caused by package parasitics. Due to the integrated high impedance buffer in the ADS61B49/29 family, the filtering of the glitches with an external R-C-R filter suggested for the ADS6149/29 family is not required. The drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Figure and Figure show the impedance IN R IN C IN looking into the ADC input pins. These figures compare the buffered ADS61B49 to the non-buffered ADS6149. Figure 62. ADC Analog Input Resistance Across Frequency Figure 63. ADC Analog Input Capacitance Across Frequency Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

1:1 5 /c87 25 /c87 25 /c87 5 /c87

0.1 F/c109

1:1 1:1 50 /c87 50 /c87 INP INM 5 /c87 50 /c87 50 /c87 5 /c87 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Two example driving circuit configurations are shown in Figure and Figure one optimized for low input frequencies and the other for high input frequencies. Notice in both cases that the board circuitry is simplified compared to the non-buffered ADS6149. In Figure a single transformer is used and is suited for low input frequencies and works for some high frequency well. To optimize even-harmonic performance at high input frequencies 2nd Nyquist), the use of back-to-back transformers is recommended (see Figure Note that both drive circuits have been terminated by 50- Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. Figure 64. Drive Circuit for Low Frequencies The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high frequency input signals. An additional termination resistor pair may be required between the two transformers as shown in the figures. The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side have to be chosen to achieve an effective Ω (in the case of 50- Ω source impedance). Figure 65. Drive Circuit for High Frequencies To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1- µ F low-inductance capacitor connected to ground. The input common-mode voltage is nominally 2.3 which is 1.5 V for the ADS6149. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com The ADS61B49/29 have built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling. External reference mode is not supported. The reference generates the VCM output (2.3 V). Figure 66. Reference Section The ADS61B49/29 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS) with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-k Ω resistors. This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

Ceq 1 to 3 pF , Equivalent Input Capacitance of Clock Buffer/c187 Lpkg 2 nH/c187 Lpkg 2 nH/c187 Cbond 1 pF/c187 Cbond 1 pF/c187 Resr 100/c187 /c87 Resr 100/c187 /c87 S0275-04 S0168-16 CLKP CLKM CMOS□Clock□Input 1.5□V S0167-10 CLKP CLKM Differential□Sine-Wave or□PECL or□LVDS□Clock□Input www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Figure 67. Internal Clock Buffer A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1- µ F capacitor, as shown in Figure For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 68. Differential Clock Driving Circuit Figure 69. Single-Ended Clock Driving Circuit Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com The ADS61B49/29 include gain settings that can be used to get improved SFDR performance (compared to no gain) or to reduce the required full-scale input voltage. The gain is programmable from dB to dB (in 0.5-dB steps). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades about 0.5 dB. The SNR degradation is less at high input frequencies. As a result, the fine gain is useful at high input frequencies as the SFDR improvement is significant with marginal degradation in SNR. So, the fine gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is dB. Table Full-Scale Range Across Gains GAIN, dB TYPE FULL-SCALE, V PP Default after reset V 1.78 1.59 1.42 Fine, programmable 1.26 1.12 1.00 The ADS61B49/29 have an internal offset correction algorithm that estimates and corrects the dc offset up to mV. The correction can be enabled using the serial register bit ENABLE OFFSET CORR Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using register bits OFFSET CORR TIME CONSTANT as described in Table After the offset is estimated, the correction can be locked in by setting OFFSET CORR TIME CONSTANT Once locked, the last estimated value is used for offset correction every clock cycle. Note that offset correction is disabled by default after a reset. Figure shows the time response of the offset correction algorithm, after it is enabled. Table 10. Time Constant of Offset Correction Algorithm TIME CONSTANT CCLK NUMBER OF OFFSET CORR TIME CONSTANT D3-D0 TIME CONSTANT, sec CCLK x 1/F s (1) CLOCK CYCLES 0000 256 k ms 0001 512 k ms 0010 M ms 0011 M ms 0100 M ms 0101 M ms 0110 M ms 0111 M 134 ms 1000 M 268 ms 1001 128 M 536 ms 1010 256 M 1.1 s 1011 512 M 2.2 s 1100 Reserved 1101 Reserved 1110 Reserved (1) Sampling frequency, F s 250 MSPS Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

t − Time − µs 8148 8152 8156 8160 8164 8168 8172 8176 8180 8184 8188 8192 8196 8200 8204 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 Code − LSB G080 Offset Correction DisabledOffset Correction Enabled Output Data With

36 LSB Offset

www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Table 10. Time Constant of Offset Correction Algorithm (continued) TIME CONSTANT CCLK NUMBER OF OFFSET CORR TIME CONSTANT D3-D0 TIME CONSTANT, sec CCLK x 1/F s (1) CLOCK CYCLES 1111 Reserved Figure 70. Output Code Time Response with Offset Correction Enabled The ADS61B49/29 have three power-down modes power-down global, standby, and output buffer disable. In this mode, the entire chip including the A/D converter, the internal reference, and the output buffers are powered down resulting in reduced total power dissipation of about mW. The output buffers are in a high impedance state. The wake-up time from global power down to data becoming valid in normal mode is typically µ This can be controlled using register bit PDN GLOBAL or using the SDATA pin (in parallel configuration mode). Here, only the A/D converter is powered down and the internal references are active, resulting in a fast wake-up time of 300 ns. The total power dissipation in standby is about 120 mW. This can be controlled using register bit STANDBY The output buffers can be disabled and put in a high impedance state wakeup time from this mode is fast, about ns. This can be controlled using register bit PDN OBUF In addition to the above, the converter enters a low-power mode when the input clock frequency falls below MSPS. The power dissipation is about 120 mW. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M Output□Clock Data□bits□D0, D1 Data□bits□D2, D3 Data□bits□D4, D5 Data□bits□D6, D7 Data□bits□D8, D9 Data□bits□D10, D11 ADS612X Pins 12□bit ADC□data LVDS□Buf fers CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M Output□Clock Data□bits□D0, D1 Data□bits□D2, D3 Data□bits□D4, D5 Data□bits□D6, D7 Data□bits□D8, D9 Data□bits□D10,D11 ADS 614X Pins D12_D13_P D12_D13_M Data□bits□D12,D13 14□bit ADC□data LVDS□Buffers ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the device. The ADS61B49/29 provide 14-bit/12-bit data and an output clock synchronized with the data. Two output interface options are available double data rate (DDR) LVDS and parallel CMOS. They can be selected using the serial interface register bit ODI or using the DFS pin in parallel configuration mode. In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair. Figure 71. 14-Bit ADC LVDS Outputs Figure 72. 12-Bit ADC LVDS Outputs Even data bits D0, D2, are output at the falling edge of CLKOUTP, and the odd data bits D1, D3, are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to capture all of the data bits (see Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

D0_D1_P, D0_D1_M D2_D3_P, D2_D3_M D4_D5_P, D4_D5_M D6_D7_P, D6_D7_M D8_D9_P, D8_D9_M D10_D11_P, D10_D11_M D12_D13_P, D12_D13_M D10 D12 Sample□N+1Sample□N D10 D12 D11 D13 D11 D13 CLKOUTM LVDS Buffer ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Figure 73. DDR LVDS Interface The equivalent circuit of each LVDS output buffer is shown in Figure The buffer is designed to present an output impedance of 100 Ω (Rout). The differential outputs can be terminated at the receive end by a 100- Ω termination. The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and its value cannot be changed. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

h Low Low Rout –0.35□V1.2□V 0.35□V External 100- Load/c87 Switch□impedance□is nominally□50 ( 10%)/c87 /c177 When□the□High□switches□are□closed,□OUTP =□1.375□V,□OUTM□=□1.025□V When□the□Low□switches□are□closed,□OUTP =□1.025□V,□OUTM□=□1.375□V When□the□High□(or□Low)□switches□are□closed,□Rout□=□100 /c87 S0374-02 Parallel CMOS Interface ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Figure 74. LVDS Buffer Equivalent Circuit In CMOS mode, each data bit is output on a separate pin as a CMOS voltage level, every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver (for sampling frequencies up to approximately 150 MSPS) Up to 150 MSPS, the setup and hold timings of the output data with respect to CLKOUT are specified. It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them. For sampling frequencies 150 MSPS in CMOS mode, it is recommended to use an external clock to capture data. The input clock to output data delay and data valid times are specified for the higher sampling frequencies. These timings can be used to delay the input clock appropriately and use it to capture the data (see Figure It is recommended to consider using the LVDS output mode at high sample rates due to device and board noise generated by the CMOS mode. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

14-Bit ADC□Data CMOS Output□Buffers CLKOUT OVR_SDOUT Output Buffer Strength Programmability CMOS Interface Power Dissipation Output Data Format ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Figure 75. CMOS Output Interface Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this, the CMOS output buffers are designed with a controlled drive strength to achieve the best SNR. The default drive strength also ensures a wide data stable window for load capacitances up to pF. With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between and every clock cycle. In an actual application, the DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital current due to CMOS output switching C L DRVDD F AVG where C L load capacitance, N x F AVG average number of output bits switching. Figure shows the current across the sampling frequencies with a 3-MHz analog input frequency. Two output data formats are supported complement and offset binary. They can be selected using the serial interface register bit DATA FORMAT or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output format, and 0x1FFF in complement output format. For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in complement output format. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

www.ti.com A single ground plane is sufficient to achieve good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide for details on layout and grounding. As the ADS61B49/29 already include internal decoupling, minimal external decoupling can be used without a loss in performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. In addition to providing a path for heat dissipation, the pad is also electrically connected to digital ground internally. So, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see the application notes for QFN Layout Guidelines SLOA122 and QFN/SON PCB Attachment SLUA271 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

N PSNR = 10Log P (1) 10 S N D PSINAD = 10Log P + P (2) ADS61B29 ADS61B49 www.ti.com SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by dB with respect to the low frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay will be different across channels. The maximum variation is specified as aperture delay variation (channel-channel). Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error due to reference inaccuracy and error due to the channel. Both these errors are specified independently as E GREF and E GCHAN To a first order approximation, the total gain error is E TOTAL E GREF E GCHAN For example, if E TOTAL 0.5%, the full-scale input varies from (1-0.5/100) x FS ideal to 0.5/100) x FS ideal Offset Error The offset error is the difference, given in number of LSBs, between the actual average idle channel output code and the ideal average idle channel output code of the ADC. This quantity is often mapped into mV. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from T MIN to T MAX It is calculated by dividing the maximum deviation of the parameter across the T MIN to T MAX range by the difference T MAX T MIN Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental S to the noise floor power N excluding the power at DC and the first nine harmonics. SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental S to the power of all the other spectral components including noise N and distortion D but excluding dc. SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. Effective Number of Bits (ENOB) The ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS61B29 ADS61B49

SINAD 1.76ENOB = 6.02 /c45 (3) 10 S N PTHD = 10Log P (4) (Expressed□in□dBc)/c68VSUP /c68VOUT10PSRR□□=□20Log (5) (Expressed□in□dBc)/c68VCM /c68VOUT10CMRR□□=□20Log (6) ADS61B29 ADS61B49 SLWS214A OCTOBER 2008 REVISED DECEMBER 2008 www.ti.com Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental S to the power of the first nine harmonics (PD). THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies and f2) to the power of the worst spectral component at either frequency 2f1 or 2f2 f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter s full-scale range. DC Power Supply Rejection Ratio (DC PSRR) The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. AC Power Supply Rejection Ratio (AC PSRR) AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If Δ V SUP is the change in supply voltage and Δ V OUT is the resultant change of the ADC output code (referred to the input), then Voltage Overload Recovery The number of clock cycles taken to recover to less than error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from their expected values) is noted. Common Mode Rejection Ratio (CMRR) CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If Δ V CM_IN is the change in the common-mode voltage of the input pins and Δ V OUT is the resultant change of the ADC output code (referred to the input), then Cross-Talk (only for multi-channel ADC) This is a measure of the internal coupling of a signal from adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) ADS61B29IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS61B29IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS61B49IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS61B49IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS61B29IRGZR QFN RGZ 48 2500 333.2 345.9 28.6 ADS61B29IRGZT QFN RGZ 48 250 333.2 345.9 28.6 ADS61B49IRGZR QFN RGZ 48 2500 333.2 345.9 28.6 ADS61B49IRGZT QFN RGZ 48 250 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2008 Pack Materials-Page 2

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