ADS6125IRHBT

ADS6122 TI1 | Alldatasheet

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ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 www.ti.com 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Maximum Sample Rate: 125 MSPS 12-Bit Resolution with No Missing Codes ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling 3.5 dB Coarse Gain and up to dB frequencies up to 125 MSPS. It combines high Programmable Fine Gain for SNR/SFDR performance and low power consumption in a Trade-Off compact QFN package. Using an internal high Parallel CMOS and Double Data Rate (DDR) bandwidth sample and hold and a low jitter clock LVDS Output Options buffer helps to achieve high SNR and high SFDR even at high input frequencies. Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mV PP It ranges. Internal Reference with Support for External Reference The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several strength, Programmable Output Clock Position and and LVDS current and internal termination Drive Strength to Ease Data Capture programmability. 3.3 V Analog and 1.8 V to 3.3 V Digital Supply The output interface type, gain, and other functions 32-QFN Package mm mm) are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured Pin Compatible 12-Bit Family (ADS612X) using dedicated parallel pins so that the device comes up in the desired state after power-up. Wireless Communications Infrastructure ADS612X includes internal references, while eliminating the traditional reference pins and Software Defined Radio associated external decoupling. External reference Power Amplifier Linearization mode is also supported. 802.16d/e The devices are specified over the industrial Test and Measurement Instrumentation temperature range C to C). High Definition Video Medical Imaging Radar Systems ADS612X Performance Summary ADS6125 ADS6124 ADS6123 ADS6122 F in MHz dB gain) SFDR, dBc F in 170 MHz (3.5 dB gain) F in MHz dB gain) 71.1 71.3 71.5 71.6 SINAD, dBFS F in 170 MHz (3.5 dB gain) 67.6 69.1 69.2 69.8 Power, mW 417 374 318 285 Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2007 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com SHA 12-Bit ADC CLOCK GEN Reference Digital Encoder and Serializer Control Interface INP INM CLKP CLKM VCM CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D4_D5_P D6_D7_P D8_D9_P D10_D11_P D2_D3_M D4_D5_M D6_D7_M D8_D9_M D10_D11_M ADS612X SCLK SEN SDATA RESET LVDS□MODE AVDD AGND DRVDD DRGND PDN ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ADS61XX FAMILY 125 MSPS 105 MSPS MSPS MSPS ADS614X ADS6145 ADS6144 ADS6143 ADS6142 Bits ADS612X ADS6125 ADS6124 ADS6123 ADS6122 Bits Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 PACKAGE/ORDERING INFORMATION (1) SPECIFIED PACKAGE- PACKAGE PACKAGE ORDERING PRODUCT TEMPERATURE TRANSPORT MEDIA LEAD DESIGNATOR MARKING NUMBER RANGE ADS6125IRHBT Tape and Reel, small ADS6125 QFN-32 (2) RHB C to C AZ6125 ADS6125IRHBR Tape and Reel, large ADS6124IRHBT Tape and Reel, small ADS6124 QFN-32 (2) RHB C to C AZ6124 ADS6124IRHBR Tape and Reel, large ADS6123IRHBT Tape and Reel, small ADS6123 QFN-32 (2) RHB C to C AZ6123 ADS6123IRHBR Tape and Reel, large ADS6122IRHBT Tape and Reel, small ADS6122 QFN-32 (2) RHB C to C AZ6122 ADS6122IRHBR Tape and Reel, large (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com (2) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θ JA C/W LFM air flow), θ JC C/W when used with oz. copper trace and pad soldered directly to a JEDEC standard four layer in in (7.62 cm 7.62 cm) PCB. VALUE UNIT Supply voltage range, AVDD 0.3 to 3.9 V V I Supply voltage range, DRVDD 0.3 to 3.9 V Voltage between AGND and DRGND 0.3 to 0.3 V Voltage between AVDD to DRVDD 0.3 to 3.3 V Voltage applied to VCM pin (in external reference mode) 0.3 to V Voltage applied to analog input pins, INP and INM 0.3 to minimum 3.6, AVDD 0.3) V Voltage applied to analog input pins, CLKP and CLKM 0.3 to (AVDD 0.3) V T A Operating free-air temperature range to C T J Operating junction temperature range 125 C T stg Storage temperature range to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com RECOMMENDED OPERATING CONDITIONS ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage 3.3 3.6 V CMOS Interface 1.65 1.8 to 3.3 3.6 V DRVDD Output buffer supply voltage (1) LVDS Interface 3.3 3.6 V ANALOG INPUTS Differential input voltage range V pp V IC Input common-mode voltage 1.5 0.1 V Voltage applied on VCM in external reference mode 1.45 1.5 1.55 V CLOCK INPUT ADS6125 125 ADS6124 105 F S Input clock sample rate MSPS ADS6123 ADS6122 Sine wave, ac-Coupled 0.4 1.5 LVPECL, ac-Coupled 0.8 Input clock amplitude differential V pp CLKP V CLKM LVDS, ac-Coupled 0.35 LVCMOS, ac-Coupled 3.3 Input Clock duty cycle 35% 50% 65% DIGITAL OUTPUTS For C LOAD pF and DRVDD 2.2 DEFAULT V strength For C LOAD pF and DRVDD 2.2 MAXIMUM Output buffer drive strength (2) V strength MAXIMUM For DRVDD 2.2 V strength CMOS Interface, maximum buffer strength Maximum external load capacitance from each LVDS Interface, without internal C LOAD pF output pin to DRGND termination LVDS Interface, with internal termination R LOAD Differential load resistance (external) between the LVDS output pairs 100 Ω T A Operating free-air temperature -40 C (1) For easy migration to next generation, higher sampling speed devices 125 MSPS), use 1.8V DRVDD supply. (2) See Output Buffer Strength Programmability in application section Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ELECTRICAL CHARACTERISTICS ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD DRVDD 3.3 maximum rated sampling frequency, 50% clock duty cycle, dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. ADS6125 ADS6124 ADS6123 ADS6122 F S 125 MSPS F S 105 MSPS F S MSPS F S MSPS PARAMETER UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX RESOLUTION Bits ANALOG INPUT Differential input voltage range V PP Differential input resistance (at dc) M Ω see Figure Differential input capacitance pF see Figure Analog input bandwidth 450 450 450 450 MHz Analog input common mode current 180 151 114 µ A (per input pin of each ADC) REFERENCE VOLTAGES VREFB Internal reference bottom voltage V VREFT Internal reference top voltage V Δ V REF Internal reference error -20 -20 -20 -20 mV (VREFT VREFB) V CM Common mode output voltage 1.5 1.5 1.5 1.5 V DC ACCURACY No missing codes Specified Specified Specified Specified E O Offset error -10 -10 -10 -10 mV Offset error temperature coefficient 0.05 0.05 0.05 0.05 mV/ C There are two sources of gain error internal reference inaccuracy and channel gain error E GREF Gain error due to internal reference 0.25 0.25 0.25 0.25 FS inaccuracy alone, Δ V REF /2) E GCHAN Gain error of channel alone (1) 0.3 0.3 0.3 0.3 FS Channel gain error temperature 0.005 0.005 0.005 0.005 Δ C coefficient DNL Differential nonlinearity -0.75 0.6 -0.75 0.6 -0.75 0.5 -0.75 0.5 LSB INL Integral nonlinearity LSB POWER SUPPLY I AVDD Analog supply current 123 110 mA Digital supply current, CMOS interface I DRVDD 6.1 5.4 4.5 4.0 mA DRVDD 1.8 V No load capacitance, F IN MHZ (2) Digital supply current, LVDS interface I DRVDD DRVDD 3.3 V mA With 100 Ω external termination Total power, CMOS 417 625 374 525 318 440 285 400 mW Global power down mW (1) This is specified by design and characterization; it is not tested in production. (2) In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on output pins (see Figure Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ELECTRICAL CHARACTERISTICS ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD DRVDD 3.3 maximum rated sampling frequency, 50% clock duty cycle, dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. ADS6125 ADS6124 ADS6123 ADS6122 F S 125 MSPS F S 105 MSPS F S MSPS F S MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX DYNAMIC AC CHARACTERISTICS Fin MHz 71.3 71.4 71.6 71.7 Fin MHz 68.5 71.1 71.1 71.4 71.5 Fin MHz 70.9 68.5 71.3 71.5 SNR dB Gain 69.5 70.3 70.6 Fin 170 Signal to noise dBFS 3.5 dB Coarse MHz ratio, CMOS 68.7 69.4 69.7 69.9 gain dB Gain 68.6 69.2 69.6 69.9 Fin 230 3.5 dB Coarse MHz 67.9 68.6 69.1 69.4 gain Fin MHz 71.5 71.5 71.8 71.8 Fin MHz 68.5 71.4 71.3 71.5 71.6 Fin MHz 71.3 68.5 71.3 71.5 71.6 SNR dB Gain 70.3 70.3 70.6 70.7 Fin 170 Signal to noise dBFS 3.5 dB Coarse MHz ratio, LVDS 69.8 69.8 70.1 70.1 gain dB Gain 69.6 69.6 70.1 Fin 230 3.5 dB Coarse MHz 69.5 69.6 gain Fin MHz 71.1 71.3 71.5 71.6 Fin MHz 70.3 70.7 68.5 71.3 71.4 Fin MHz 70.4 70.9 70.9 68.5 71.4 SINAD Signal to noise dB Gain 67.7 69.5 69.6 70.2 Fin 170 and distortion dBFS 3.5 dB Coarse MHz ratio 67.6 69.1 69.2 69.8 gain CMOS dB Gain 66.6 68.9 69.1 Fin 230 3.5 dB Coarse MHz 66.3 68.6 gain Fin MHz 71.5 71.5 71.7 71.7 Fin MHz 70.6 70.7 71.4 71.5 Fin MHz 71.1 71.5 SINAD Signal to noise dB Gain 69.1 69.7 70.1 70.3 Fin 170 and distortion dBFS 3.5 dB Coarse MHz ratio 69.3 69.5 69.9 gain LVDS dB Gain 68.2 68.1 69.4 69.1 Fin 230 3.5 dB Coarse MHz 68.3 68.3 69.2 69.1 gain ENOB Fin MHz 11.4 11.55 Effective Bits Fin MHz 11.5 11.56 number of bits Fin MHz Fin MHz Fin MHz SFDR dB Gain Fin 170 Spurious free dBc 3.5 dB Coarse MHz dynamic range gain dB Gain Fin 230 3.5 dB Coarse MHz gain Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD DRVDD 3.3 maximum rated sampling frequency, 50% clock duty cycle, dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. ADS6125 ADS6124 ADS6123 ADS6122 F S 125 MSPS F S 105 MSPS F S MSPS F S MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Fin MHz 88.5 91.5 Fin MHz 79.5 82.5 Fin MHz THD dB Gain 73.5 Fin 170 Total harmonic dBc 3.5 dB Coarse MHz distortion gain dB Gain 71.5 75.5 Fin 230 3.5 dB Coarse MHz 72.5 77.5 78.5 gain Fin MHz Fin MHz Fin MHz HD2 dB Gain Second Fin 170 dBc harmonic 3.5 dB Coarse MHz distortion gain dB Gain Fin 230 3.5 dB Coarse MHz gain Fin MHz Fin MHz Fin MHz HD3 dB Gain Fin 170 Third harmonic dBc 3.5 dB Coarse MHz distortion gain dB Gain Fin 230 3.5 dB Coarse MHz gain Fin MHz Fin MHz Worst spur Fin MHz (Other than dBc Fin 170 HD2, HD3) MHz Fin 230 MHz IMD 2-Tone 185 MHz, 190 MHz dBFS intermodulation Each tone at dBFS distortion Recovery to within (of final Input overload clock value) for 6-dB overload with sine recovery cycles wave input PSRR AC Power For 100 mVpp signal on AVDD dBc supply rejection supply ratio Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com DIGITAL CHARACTERISTICS (1) ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level or AVDD 3.3 V ADS6125/ADS6124 PARAMETER TEST CONDITIONS ADS6123/ADS6122 MIN TYP MAX UNIT DIGITAL INPUTS PDN, SCLK, SEN SDATA (2) High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current µ A Low-level input current µ A Input capacitance pF DIGITAL OUTPUTS CMOS INTERFACE, DRVDD 1.8 to 3.3 V High-level output voltage DRVDD V Low-level output voltage V Output capacitance inside the device, from Output capacitance pF each output to ground DIGITAL OUTPUTS LVDS INTERFACE, DRVDD 3.3 I O 3.5 mA, R L 100 Ω (3) High-level output voltage 1375 mV Low-level output voltage 1025 mV Output differential voltage, OD 225 350 mV V OS Output offset voltage, single-ended Common-mode voltage of OUTP, OUTM 1200 mV Output capacitance inside the device, from Output capacitance pF either output to ground (1) All LVDS and CMOS specifications are characterized, but not tested at production. (2) SCLK SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins, analog voltage needs to be applied as per Table Table (3) I O Refers to the LVDS buffer current setting, R L is the differential load resistance between the LVDS output pair. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com TIMING CHARACTERISTICS LVDS AND CMOS MODES (1) ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Typical values are at min and max values are across the full temperature range T MIN C to T MAX AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP clock amplitude, C L pF (2) I O 3.5 mA, R L 100 Ω (3) no internal termination, unless otherwise noted. For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data sheet. ADS6125 ADS6124 ADS6123 ADS6122 F S 125 MSPS F S 105 MSPS F S MSPS F S MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Aperture t a 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns delay Aperture t j 150 150 150 150 fs rms jitter From global power µ s down Wake-up time From standby µ s (to valid From output CMOS 100 200 100 200 100 200 100 200 ns data) buffer LVDS 200 500 200 500 200 500 200 500 ns disable clock Latency cycles DDR LVDS MODE (4) DRVDD 3.3 V Data valid (6) to Data setup t su zero-cross of 1.7 2.3 2.5 3.1 3.9 4.5 5.4 6.0 ns time (5) CLKOUTP Zero-cross of Data hold t h CLKOUTP to data 0.7 1.7 0.7 1.7 0.7 1.7 0.7 1.7 ns time (5) becoming invalid (6) Input clock rising edge Clock zero-cross to output t PDI propagation 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 ns clock rising edge delay zero-cross Duty cycle of LVDS bit differential clock, clock duty (CLKOUTP- 40% 47% 55% 40% 47% 55% 40% 47% 55% 40% 47% 55% cycle CLKOUTM) Fs 125 MSPS Rise time measured Data rise from mV to mV t r time, Fall time measured 100 170 100 170 100 170 100 170 ps t f Data fall from mV to mV time Fs 125 MSPS Rise time measured t CLKRI Output clock from mV to mV SE rise time, Fall time measured 100 170 100 170 100 170 100 170 ps t CLKFA Output clock from mV to mV LL fall time Fs 125 MSPS PARALLEL CMOS MODE, DRVDD 2.5 V to 3.3 default output buffer drive strength (7) Data setup Data valid (8) to 50% of t su 2.9 4.4 3.6 5.1 5.1 6.6 6.5 8.0 ns time (5) CLKOUT rising edge 50% of CLKOUT Data hold t h Rising edge to data 1.3 2.7 2.1 3.5 3.6 5.0 5.1 6.5 ns time (5) becoming invalid (8) Clock Input clock rising edge t PDI propagation zero-cross to 50% of 6.5 7.9 6.5 7.9 6.5 7.9 6.5 7.9 ns delay CLKOUT rising edge (1) Timing parameters are specified by design and characterization and not tested in production. (2) C L is the Effective external single-ended load capacitance between each output pin and ground. (3) I O Refers to the LVDS buffer current setting; R L is the differential load resistance between the LVDS output pair. (4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. (5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to logic high of +100 mV and logic low of 100 mV. (7) For DRVDD 2.2V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See Parallel CMOS interface in application section. (8) Data valid refers to logic high of (1.7V) and logic low of 0.8 V (0.7V) for DRVDD 3.3V (2.5V). Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TIMING CHARACTERISTICS LVDS AND CMOS MODES (continued) For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data sheet. ADS6125 ADS6124 ADS6123 ADS6122 F S 125 MSPS F S 105 MSPS F S MSPS F S MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Duty cycle of output Output clock clock (CLKOUT) 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55% duty cycle Fs 125 MSPS Rise time measured from 20% to 80% of Data rise DRVDD t r time, Fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns t f Data fall from 80% to 20% of time DRVDD Fs 125 MSPS Rise time measured from 20% to 80% of t CLKRI Output clock DRVDD SE rise time, Fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns t CLKFA Output clock from 80% to 20% of LL fall time DRVDD Fs 125 MSPS Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com O O O O O O O O O OE E E E E E E E E E Input Clock CLKOUTM CLKOUTP Output□Data DXP,□DXM DDR LVDS N–9 N–8 N–7 N–6 N–5 N–1 N N+1 N+2 N–9 N–8 N–7 N–6 N–5 N N+2 9□Clock□Cycles 9□Clock□Cycles CLKOUT Output□Data D0–D11 Parallel CMOS Input Signal Sample N N+1 N+2 N+3 N+4 th tPDI ta tsu th tPDI CLKP CLKM N+9 N+10 N+11 N+12 tsu E – Even□Bits□D0,D2,D4,D6,D8,D10 O – Odd□Bits□D1,D3,D5,D7,D9,D11 N+1N–1 Input Clock Output Clock Output Data CLKM Dn CLKP tPDI tsu th CLKOUT (1) Dn – Bits□D0–D11 Dn (1) Input Clock Output Clock Output Data□Pair CLKM CLKOUTP Dn_Dn+1_P, Dn_Dn+1_M CLKP tPDI tsu th th tsu CLKOUTM (1) (2) Dn+1 – Bits□D1,□D3,□D5,□D7,□D9,□D11 Dn (1) Dn+1 (2) ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure Latency Figure CMOS Mode Timing Figure LVDS Mode Timing Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com DEVICE PROGRAMMING MODES USING SERIAL INTERFACE PROGRAMMING ONLY USING PARALLEL INTERFACE CONTROL ONLY (3/8) AVDD (3/8) AVDD To□Parallel□Pin (SCLK,□SDATA,□SEN) AVDD AVDDGND (5/8) AVDD (5/8) AVDD GND ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 ADS612X has several programming. To program using the serial interface, the internal registers must first be reset to their default values, and the RESET pin must be kept low In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET pin, or by a high setting on the <RST bit (D4 in register 0x00). The Serial Interface section describes register programming and register reset in more detail. To control the device using parallel interface, keep RESET tied to high (AVDD). Now, SEN, SCLK, SDATA and PDN function as parallel interface control pins. These pins can be used to directly control certain modes of the ADC by connecting them to the correct voltage levels (as described in Table to Table There is no need to apply a reset pulse. Frequently used functions are controlled in this mode standby, selection between LVDS/CMOS output format, internal/external reference and complement/straight binary output format. Table Table and Table describe the modes controlled by the parallel pins. Figure Simple Scheme to Configure Parallel Pins (Full-scale V PP (3/8) AVDD External reference and dB gain (Full-scale V PP (5/8) AVDD External reference and 3.5 dB coarse gain (Full-scale 1.34 V PP AVDD Internal reference and 3.5 dB coarse gain (Full-scale 1.34 V PP Table SEN Control Pin SEN (3/8) AVDD Straight binary format and DDR LVDS interface (5/8) AVDD Straight binary and parallel CMOS interface AVDD Complement format and parallel CMOS interface Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com SERIAL INTERFACE SCLK SEN A 4 A3 A 2 A 1 A 0 D 10 D9 D 8 D 7 D 6 D5 D 4 D3 D 2 D 1 D0 REGISTER ADDRESS REGISTER□DATA SDATA RESET tSCLK tDSU tDH tSLOADS tSLOADH REGISTER INITIALIZATION ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Table SDATA, PDN Control Pins SDATA PDN (AVDD) Standby only the ADC is powered down High (AVDD) Low Output buffers are powered down, fast wake-up time High (AVDD) High (AVDD) Global power down. ADC, internal reference and output buffers are powered down, slow wake-up time The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET (of width greater than ns). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. If the word length exceeds a multiple of bits, the excess bits are ignored. Data is loaded in multiples of 16-bit words within a single active SEN pulse. The first bits form the register address and the remaining bits form the register data. The interface can work with SCLK frequency from MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty cycle. Figure Serial Interface Timing Diagram After power-up, the internal registers must be reset to their default values. This is done in one of two ways: Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than ns) as shown in Figure OR By applying software reset. Using the serial interface, set the <RST bit (D4 in register 0x00) to high This initializes the internal registers to their default values and then self-resets the <RST bit to low In this case the RESET pin is kept low Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com SERIAL INTERFACE TIMING RESET TIMING Power□Supply AVDD,□DRVDD RESET SEN ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Typical values at min and max values across the full temperature range T MIN C to T MAX AVDD DRVDD 3.3 V (unless otherwise noted) MIN TYP MAX UNIT f SCLK SCLK Frequency 1/t SCLK DC MHz t SLOADS SEN to SCLK Setup time ns t SLOADH SCLK to SEN Hold time ns t DSU SDATA Setup time ns t DH SDATA Hold time ns Typical values at min and max values across the full temperature range T MIN C to T MAX AVDD DRVDD 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active ms t Reset pulse width Pulse width of active RESET signal ns t Register write delay Delay from RESET disable to SEN active ns t PO Power-up time Delay from power-up of AVDD and DRVDD to output stable 6.5 ms NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure Reset Timing Diagram Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com SERIAL REGISTER MAP ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Table provides a summary of all the modes that can be programmed through the serial interface. Table Summary of Functions Supported by Serial Interface (1) (2) REGISTER ADDRESS REGISTER FUNCTIONS IN HEX D10 <PDN <PDN <LVDS OBUF <REF CLKOUT <COARSE CMOS <RST <STBY Output Internal or Output GAIN LVDS or Software ADC Power buffers external clock buffer Coarse gain CMOS output Reset down powered Reference powered interface down down <DATAOUT <CLKOUT <CLKOUT POSN EDGE POSN Output data Output Output Clock position Clock edge position control control control Bit-wise or Byte-wise control <DATA FORMAT <TEST PATTERNS complement or straight binary <CUSTOM LOW Custom Pattern lower 7bits <FINE GAIN <CUSTOM HIGH Fine Gain to 6dB Custom Pattern upper bits <CURRENT LVDS Termination <LVDS CURRENT DOUBLE LVDS Internal Termination control for output data and clock LVDS Current control LVDS current double <DRIVE STRENGTH CMOS output buffer drive strength control (1) The unused bits in each register (shown by blank cells in above table) must be programmed as (2) Multiple functions in a register can be programmed in a single write operation. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Each register function is explained in detail below. Table D10 (hex) <PDN OBUF <COARSE <LVDS CMOS <REF <RST <PDN CLKOUT <STBY Output buffers GAIN LVDS or CMOS Internal or Software Output clock ADC Power powered down Coarse gain output interface external Reset buffer powered down reference down <STBY Power down modes Normal operation Device enters standby mode where only ADC is powered down. <PDN CLKOUT Power down modes Output clock is active (on CLKOUT) pin Output clock buffer is powered down and becomes tri-stated. Data outputs are unaffected. <RST Software reset applied resets all internal registers and the bit self-clears to <REF Reference selection Internal reference enabled External reference enabled <LVDS CMOS Output Interface selection Parallel CMOS interface DDR LVDS interface <COARSE GAIN Gain programming dB Coarse gain 3.5 dB Coarse gain D10 <PDN OBUF Power down modes Output data and clock buffers enabled Output data and clock buffers disabled Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Table D10 (hex) <DATAOUT POSN <CLKOUT EDGE <CLKOUT POSN Output data position Output Clock edge Output Clock control control position control <CLKOUT POSN Output clock position control Default output clock position after reset. The setup/hold timings for this clock position are specified in the timing specifications table. Output clock shifted (delayed) by 400 ps <CLKOUT EDGE Use rising edge to capture data Use falling edge to capture data D10 <DATAOUT_POSN Default position (after reset) Data transition delayed by half clock cycle with respect to default position Table D10 (hex) Bit-wise or Byte-wise control D10 Bit-wise or byte-wise selection (DDR LVDS mode only) Bit-wise sequence Even data bits (D0, D2, D4..D12) are output at rising edge of CLKOUTP and odd data bits (D1, D3, D5..D13) at falling edge of CLKOUTP Byte-wise sequence Lower data bits (D0-D7) are output at rising edge of CLKOUTP and upper data bits (D8-D13) at falling edge of CLKOUTP Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Table D10 (hex) <DF <TEST PATTERNS complement or straight binary D7-D5 Test Patterns 000 Normal operation <D13:D0 ADC output 001 All zeros <D13:D0 0x0000 010 All ones <D13:D0 0x3FFF 011 Toggle pattern <D13:D0 toggles between 0x2AAA and 0x1555 100 Digital ramp <D13:D0 increments from 0x0000 to 0x3FFF by one code every cycle 101 Custom pattern <D13:D0

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<DATA FORMAT Complement Straight binary Table D10 (hex) <CUSTOM LOW Lower 7bits of custom pattern Table 10. D10 (hex) <FINE GAIN <CUSTOM HIGH Fine Gain to 6dB Upper bits of custom pattern Reg <CUSTOM LOW Specifies lower bits of custom pattern D10-D4 Reg <CUSTOM HIGH Specifies upper bits of custom pattern D4-D0 D10-D8 <FINE GAIN Gain programming 000 dB Gain 001 dB Gain 010 dB Gain 011 dB Gain 100 dB Gain 101 dB Gain 110 dB Gain 111 Unused Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Table 11. D10 (hex) <LVDS TERMINATION <LVDS <CURRENT LVDS Internal Termination control for output data and clock CURRENT DOUBLE LVDS Current LVDS current control double D1-D0 <CURRENT DOUBLE LVDS current programming LVDS Data buffer current control Default current, set by <LVDS_CURR LVDS Current set by <LVDS_CURR LVDS Clock buffer current control Default current, set by <LVDS_CURR LVDS Current set by <LVDS_CURR D3-D2 <LVDS CURRENT LVDS current programming 3.5 mA 2.5 mA 4.5 mA 1.75 mA D9-D4 LVDS internal termination D9-D7 <DATA TERM Internal termination for LVDS output data bits 000 No internal termination 001 300 Ω 010 185 Ω 011 115 Ω 100 150 Ω 101 100 Ω 110 Ω 111 Ω D6-D4 <CLKOUT TERM Internal termination for LVDS output clock 000 No internal termination 001 300 Ω 010 185 Ω 011 115 Ω 100 150 Ω 101 100 Ω 110 Ω 111 Ω Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Table 12. D10 (hex) <DRIVE STRENGTH CMOS output buffer drive strength control D7-D4 <DRIVE STRENGTH Output buffer drive strength controls 0101 WEAKER than default drive 0000 DEFAULT drive strength 1111 STRONGER than default drive strength (recommended for load capacitances pF) 1010 MAXIMUM drive strength (recommended for load capacitances pF) Other Do not use combinations Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com PIN CONFIGURATION (CMOS MODE) PDN DRVDD AGND INP OVR INM CLKOUT AGNDAVDD AVDD AGND CLKP CLKM 9 10 11 12 13 14 15 16 D11D10 NC NC D8 D7 D6 RESET SCLK SDATA SEN 31 30 29 28 27 26 25 Bottom□Pad□Connected To□DRGND VCM ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 RHB PACKAGE (TOP VIEW) Figure CMOS Mode Pinout Table 13. Pin Assignments CMOS Mode PIN PIN NUMBER PIN NAME I 13, AGND Analog ground I CLKP, CLKM Differential clock input I INP, INM Differential analog input I 10, Internal reference mode common-mode voltage output. VCM External reference mode reference input. The voltage forced on this pin sets the I/O internal references. Serial interface RESET input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin, or by using RESET the software reset option. See the SERIAL INTERFACE section. I In parallel interface mode, the user has to tie the RESET pin permanently HIGH. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100-k Ω pull-down resistor. This pin functions as serial interface clock input when RESET is low. When RESET is tied high, it controls the coarse gain and internal/external reference SCLK selection. Tie SCLK to low for internal reference and dB gain and high for I internal reference and 3.5 dB gain. See Table The pin has an internal 100-k Ω pull-down resistor. This pin functions as serial interface data input when RESET is low It controls various power down modes along with PDN pin when RESET is tied high SDATA I See Table for detailed information. The pin has an internal 100 k Ω pull-down resistor. This pin functions as serial interface enable input when RESET is low When RESET is high, it controls output interface type and data formats. See Table for SEN I detailed information. The pin has an internal 100-k Ω pull-up resistor to DRVDD. PDN Global power down control pin I Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Table 13. Pin Assignments CMOS Mode (continued) PIN PIN NUMBER PIN NAME O CMOS Output data O CMOS Output data O CMOS Output data O CMOS Output data O CMOS Output data O CMOS Output data O CMOS Output data O CMOS Output data O CMOS Output data O CMOS Output data O D10 CMOS Output data D10 O D11 CMOS Output data D11 O Indicates over-voltage on analog inputs (for differential input greater than full-scale), O OVR CMOS level DRVDD Digital supply I Digital ground. I PAD DRGND Connect the pad to the ground plane. See Board Design Considerations in application information section. NC Do not connect 17,18 Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com PIN CONFIGURATION (LVDS MODE) PDN DRVDD AGND INP CLKOUTM INM CLKOUTP AGNDAVDD AVDD AGND CLKP CLKM 9 10 11 12 13 14 15 16 D10_D1 1_P D10_D11_M NC D8_D9_P NC RESET D4_D5_P SCLK D4_D5_M SDATA D2_D3_P SEN D2_D3_M D0_D1_P D0_D1_M 31 30 29 28 27 26 25 Bottom□Pad□Connected To□DRGND VCM ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 RHB PACKAGE (TOP VIEW) Figure LVDS Mode Pinout Table 14. Pin Assignments LVDS Mode PIN PIN NUMBER PIN NAME I 13, AGND Analog ground I CLKP, CLKM Differential clock input I INP, INM Differential analog input I 10, Internal reference mode common-mode voltage output. VCM External reference mode reference input. The voltage forced on this pin sets the I/O internal references. Serial interface RESET input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin, or by using the RESET software reset option. See the SERIAL INTERFACE section. I In parallel interface mode, the user has to tie the RESET pin permanently HIGH. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100-k Ω pull-down resistor. This pin functions as serial interface clock input when RESET is low. When RESET is tied high, it controls the coarse gain and internal/external reference SCLK selection. Tie SCLK to low for internal reference and dB gain and high for internal I reference and 3.5 dB gain. See Table The pin has an internal 100-k Ω pull-down resistor. This pin functions as serial interface data input when RESET is low It controls various power down modes along with PDN pin when RESET is tied high SDATA I See Table for detailed information. The pin has an internal 100 k Ω pull-down resistor. This pin functions as serial interface enable input when RESET is low When RESET SEN is high, it controls output interface type and data formats. See Table for detailed I information. The pin has an internal 100-k Ω pull-up resistor to DRVDD. PDN Global power down control pin I Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Table 14. Pin Assignments LVDS Mode (continued) PIN PIN NUMBER PIN NAME clock, true O CLKOUTM Differential output clock, complement O D0_D1_P Differential output data and multiplexed, true O D0_D1_M Differential output data and multiplexed, complement. O D2_D3_P Differential output data and multiplexed, true O D2_D3_M Differential output data and multiplexed, complement O D4_D5_P Differential output data and multiplexed, true O D4_D5_M Differential output data and multiplexed, complement O D6_D7_P Differential output data and multiplexed, true O D6_D7_M Differential output data and multiplexed, complement O D8_D9_P Differential output data and multiplexed, true O D8_D9_M Differential output data and multiplexed, complement O D10_D11_P Differential output data D10 and D11 multiplexed, true O D10_D11_M Differential output data D10 and D11 multiplexed, complement O DRVDD Digital supply I Digital ground. I PAD DRGND Connect the pad to the ground plane. See Board Design Considerations in application information section. NC Do not connect 17,18 Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com TYPICAL CHARACTERISTICS ADS6125 S 125 MSPS) f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 60 Amplitude − dB G001 SFDR = 92 dBc SINAD = 71.3 dBFS SNR = 71.5 dBFS THD = 87.9 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 60 Amplitude − dB G002 SFDR = 84.2 dBc SINAD = 70.6 dBFS SNR = 71 dBFS THD = 82.7 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 60 Amplitude − dB G003 SFDR = 74.1 dBc SINAD = 66.5 dBFS SNR = 68.6 dBFS THD = 71.4 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 60 Amplitude − dB G004 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –83.6 dBFS SFDR = –81.3 dBFS fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G005 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G006 Gain = 0 dB Gain = 3.5 dB ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) FFT for MHz INPUT SIGNAL FFT for MHz INPUT SIGNAL Figure Figure 10. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY Figure 11. Figure 12. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 13. Figure 14. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G007 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G008 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 100 200 300 400 500 SFDR − dBc G009 Input adjusted to get −1dBFS input 1 dB 0 dB 5 dB 6 dB 2 dB 3 dB 4 dB fIN − Input Frequency − MHz 0 100 200 300 400 500 SINAD − dBFS G010 5 dB 1 dB 0 dB 6 dB Input adjusted to get −1dBFS input 3 dB 4 dB 2 dB SNR − dBFS DRV DD − Supply Voltage − V SFDR − dBc G012 fIN = 10.1 MHz AVDD = 3.3 V SNR SFDR AVDD − Supply Voltage − V SFDR − dBc G011 fIN = 70.1 MHz DRV DD = 3.3 V SNR − dBFS SNR SFDR ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TYPICAL CHARACTERISTICS ADS6125 S 125 MSPS) (continued) All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SNR vs INPUT FREQUENCY (LVDS interface) Figure 15. Figure 16. SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS Figure 17. Figure 18. PERFORMANCE vs AVDD PERFORMANCE vs DRVDD Figure 19. Figure 20. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com T − Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G013 SNR − dBFS fIN = 10.1 MHz SNR SFDR Input Amplitude − dBFS fIN = 10.1 MHz SFDR − dBc, dBFS G014 SNR − dBFS SFDR (dBFS) SNR (dBFS) SFDR (dBc) 100 110 SFDR − dBc Input Clock Amplitude − VPP G015 fIN = 20.1 MHz SNR − dBFS 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 SNR SFDR Input Clock Duty Cycle − % 30 35 40 45 50 55 60 65 70 SFDR − dBc G016 fIN = 10.1 MHz SNR − dBFS 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 SNR SFDR VVCM − VCM Voltage − V fIN = 20.1 MHz External Reference Mode SFDR − dBc G018 SNR − dBFS SNR SFDR Output Code 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 Occurence − % G017 RMS (LSB) = 0.497 ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TYPICAL CHARACTERISTICS ADS6125 S 125 MSPS) (continued) All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE Figure 21. Figure 22. PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs INPUT CLOCK DUTY CYCLE Figure 23. Figure 24. OUTPUT NOISE HISTOGRAM (INPUTS TIED TO COMMON-MODE) PERFORMANCE IN EXTERNAL REFERENCE MODE Figure 25. Figure 26. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com TYPICAL CHARACTERISTICS ADS6124 S 105 MSPS) f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 Amplitude − dB G019 SFDR = 88.2 dBc SINAD = 71.3 dBFS SNR = 71.5 dBFS THD = 87.1 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 Amplitude − dB G020 SFDR = 84.8 dBc SINAD = 70.8 dBFS SNR = 71.1 dBFS THD = 82.9 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 Amplitude − dB G021 SFDR = 74.9 dBc SINAD = 65.8 dBFS SNR = 67.1 dBFS THD = 73.3 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 50 Amplitude − dB G022 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –82.4 dBFS SFDR = –87.8 dBFS fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G023 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G024 Gain = 0 dB Gain = 3.5 dB ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) FFT for MHz INPUT SIGNAL FFT for MHz INPUT SIGNAL Figure 27. Figure 28. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY Figure 29. Figure 30. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 31. Figure 32. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G025 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G026 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 100 200 300 400 500 SFDR − dBc G027 Input adjusted to get −1dBFS input 1 dB 0 dB 5 dB6 dB 2 dB 4 dB 3 dB fIN − Input Frequency − MHz 0 100 200 300 400 500 SINAD − dBFS G028 1 dB0 dB 3 dB 4 dB 2 dB Input adjusted to get −1dBFS input 5 dB 6 dB AVDD − Supply Voltage − V G029 fIN = 70.1 MHz DRV DD = 3.3 V SFDR − dBc SNR − dBFS SNR SFDR SNR − dBFS DRV DD − Supply Voltage − V SFDR − dBc G030 fIN = 10.1 MHz AVDD = 3.3 V SNR SFDR ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TYPICAL CHARACTERISTICS ADS6124 S 105 MSPS) (continued) All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SNR vs INPUT FREQUENCY (LVDS interface) Figure 33. Figure 34. SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS Figure 35. Figure 36. PERFORMANCE vs AVDD PERFORMANCE vs DRVDD Figure 37. Figure 38. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com SNR − dBFS Input Amplitude − dBFS SFDR − dBc, dBFS G032 fIN = 20.1 MHz SFDR (dBc) SFDR (dBFS) SNR (dBFS) 100 110 T − Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G031 SNR − dBFS fIN = 10.1 MHz SNR SFDR SFDR − dBc Input Clock Amplitude − VPP G033 SNR − dBFS 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 SNR fIN = 20.1 MHz SFDR SNR − dBFS 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 Input Clock Duty Cycle − % G034 SNR SFDR fIN = 10.1 MHz 30 35 40 45 50 55 60 65 70 SFDR − dBc VVCM − VCM Voltage − V fIN = 20.1 MHz External Reference Mode SFDR − dBc G036 SNR − dBFS SNR SFDR ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TYPICAL CHARACTERISTICS ADS6124 S 105 MSPS) (continued) All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE Figure 39. Figure 40. PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs INPUT CLOCK DUTY CYCLE Figure 41. Figure 42. PERFORMANCE IN EXTERNAL REFERENCE MODE Figure 43. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com TYPICAL CHARACTERISTICS ADS6123 S MSPS) f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 Amplitude − dB G037 SFDR = 89.34 dBc SINAD = 71.57 dBFS SNR = 71.74 dBFS THD = 86.63 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 Amplitude − dB G038 SFDR = 83.43 dBc SINAD = 71.03 dBFS SNR = 71.49 dBFS THD = 82.65 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 Amplitude − dB G039 SFDR = 81.4 dBc SINAD = 69 dBFS SNR = 69.7 dBFS THD = 78 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 40 Amplitude − dB G040 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –84.1 dBFS SFDR = –89.5 dBFS fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G041 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G042 Gain = 0 dB Gain = 3.5 dB ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) FFT for MHz INPUT SIGNAL FFT for MHz INPUT SIGNAL Figure 44. Figure 45. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY Figure 46. Figure 47. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 48. Figure 49. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G043 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G044 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 100 200 300 400 500 SFDR − dBc G045 Input adjusted to get −1dBFS input 1 dB 0 dB 5 dB 6 dB2 dB 3 dB 4 dB fIN − Input Frequency − MHz 0 100 200 300 400 500 SINAD − dBFS G046 2 dB 5 dB 1 dB 0 dB 3 dB 4 dB Input adjusted to get −1dBFS input 6 dB SNR − dBFS DRV DD − Supply Voltage − V 100 102 SFDR − dBc G048 fIN = 10.1 MHz AVDD = 3.3 V SNR SFDR AVDD − Supply Voltage − V SFDR − dBc G047 fIN = 70.1 MHz DRV DD = 3.3 V SNR − dBFS SNR SFDR ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TYPICAL CHARACTERISTICS ADS6123 S MSPS) (continued) All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SNR vs INPUT FREQUENCY (LVDS interface) Figure 50. Figure 51. SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS Figure 52. Figure 53. PERFORMANCE vs AVDD PERFORMANCE vs DRVDD Figure 54. Figure 55. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com T − Temperature − °C −40 −20 0 20 40 60 80 SFDR − dBc G049 SNR − dBFS fIN = 10.1 MHz SFDR SNR SNR − dBFS Input Amplitude − dBFS G050 fIN = 20 MHz SFDR (dBc) SFDR (dBFS) SNR (dBFS) 100 110 SFDR − dBc, dBFS SNR − dBFS 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 Input Clock Duty Cycle − % G052 SNR SFDR fIN = 10.1 MHz 30 35 40 45 50 55 60 65 70 SFDR − dBc SFDR − dBc Input Clock Amplitude − VPP G051 SNR − dBFS 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 fIN = 20.1 MHz SNR SFDR VVCM − VCM Voltage − V fIN = 20.1 MHz External Reference Mode SFDR − dBc G054 SNR − dBFS SNR SFDR ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TYPICAL CHARACTERISTICS ADS6123 S MSPS) (continued) All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE Figure 56. Figure 57. PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs INPUT CLOCK DUTY CYCLE Figure 58. Figure 59. PERFORMANCE IN EXTERNAL REFERENCE MODE Figure 60. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com TYPICAL CHARACTERISTICS ADS6122 S MSPS) f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 Amplitude − dB G055 SFDR = 91.8 dBc SINAD = 71.1 dBFS SNR = 71.8 dBFS THD = 89.8 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 Amplitude − dB G056 SFDR = 83 dBc SINAD = 71.1 dBFS SNR = 71.6 dBFS THD = 82.3 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 Amplitude − dB G057 SFDR = 82.8 dBc SINAD = 69.5 dBFS SNR = 70.1 dBFS THD = 79.6 dBc f − Frequency − MHz −160 −140 −120 −100 −80 −60 −40 −20 0 10 20 30 Amplitude − dB G058 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –88.5 dBFS SFDR = –91.9 dBFS fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G059 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G060 Gain = 0 dB Gain = 3.5 dB ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) FFT for MHz INPUT SIGNAL FFT for MHz INPUT SIGNAL Figure 61. Figure 62. FFT for 230 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY Figure 63. Figure 64. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 65. Figure 66. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G061 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G062 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 100 200 300 400 500 SFDR − dBc G063 Input adjusted to get −1dBFS input 1 dB 0 dB 5 dB 2 dB 3 dB 4 dB 6 dB fIN − Input Frequency − MHz 0 100 200 300 400 500 SINAD − dBFS G064 2 dB 5 dB 1 dB 0 dB 4 dB 3 dB Input adjusted to get −1dBFS input 6 dB AVDD − Supply Voltage − V SFDR − dBc G065 fIN = 70.1 MHz DRV DD = 3.3 V SNR − dBFS SNR SFDR SNR − dBFS DRV DD − Supply Voltage − V 100 102 104 106 SFDR − dBc G066 fIN = 10.1 MHz AVDD = 3.3 V SNR SFDR ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TYPICAL CHARACTERISTICS ADS6122 S MSPS) (continued) All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SNR vs INPUT FREQUENCY (LVDS interface) Figure 67. Figure 68. SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS Figure 69. Figure 70. PERFORMANCE vs AVDD PERFORMANCE vs DRVDD Figure 71. Figure 72. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com Input Amplitude − dBFS fIN = 20.1 MHz G068 SFDR (dBc) SNR − dBFS SFDR (dBFS) SNR (dBFS) 100 110 SFDR − dBc, dBFS SNR − dBFS T − Temperature − °C G067 SNR SFDR −40 −20 0 20 40 60 80 SFDR − dBc fIN = 10.1 MHz SFDR − dBc Input Clock Amplitude − VPP G069 SNR − dBFS 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 fIN = 20.1 MHz SNR SFDR SNR − dBFS 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 Input Clock Duty Cycle − % G070 fIN = 10.1 MHz SNR SFDR 30 35 40 45 50 55 60 65 70 SFDR − dBc SNR − dBFS VVCM − VCM Voltage − V G072 fIN = 20.1 MHz External Reference Mode SNR SFDR SFDR − dBc ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 TYPICAL CHARACTERISTICS ADS6122 S MSPS) (continued) All plots are at AVDD DRVDD 3.3 maximum rated sampling frequency, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT AMPLITUDE Figure 73. Figure 74. PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs INPUT CLOCK DUTY CYCLE Figure 75. Figure 76. PERFORMANCE IN EXTERNAL REFERENCE MODE Figure 77. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com TYPICAL CHARACTERISTICS LOW SAMPLING FREQUENCIES F S MSPS fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G073 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G074 Gain = 0 dB Gain = 3.5 dB F S MSPS fIN − Input Frequency − MHz 100 0 50 100 150 200 250 300 350 400 450 500 SFDR − dBc G075 Gain = 0 dB Gain = 3.5 dB fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 SNR − dBFS G076 Gain = 0 dB Gain = 3.5 dB ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 All plots are at AVDD DRVDD 3.3 sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 78. Figure 79. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 80. Figure 81. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com COMMON PLOTS f − Frequency − MHz −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 50 100 150 200 250 300 CMRR − dBc G077 fS − Sampling Frequency − MSPS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 25 50 75 100 125 PD − Power Dissipation − W G078 LVDS CMOS fIN = 2.5 MHz C L = 5 pF fS − Sampling Frequency − MSPS 0 25 50 75 100 125 DRV DD Current − mA G079

1.8 V, 5 pF

3.3 V, 5 pF

3.3 V, 10 pF

1.8 V, No Load

3.3 V, No Load

ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 All plots are at AVDD DRVDD 3.3 sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, dBFS differential analog input, internal reference mode, dB gain, CMOS output interface (unless otherwise noted) POWER DISSIPATION vs COMMON-MODE REJECTION RATIO vs FREQUENCY SAMPLING FREQUENCY (DDR LVDS and CMOS) Figure 82. Figure 83. DRVDD current vs SAMPLING FREQUENCY across load capacitance (CMOS) Figure 84. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com Contour Plots Across Input and Sampling Frequencies 10 50 100 150 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPSS SFDR□-□dBc 200 250 300 400 450350 500 100 110 120 125 60 65 75 M0049-15 87 87 84 84 8484 78 80 8570 90 95 81 78 6063 10 50 100 150 f -□Input□Frequency□-□MHzIN f -□Sampling□Frequency□-□MSPSS SFDR□-□dBc 200 250 300 400 450350 500 100 110 120 125 60 65 75 M0049-16 87 8787 80 8570 90 95 ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure 85. SFDR Contour (No gain, F S V PP Figure 86. SFDR Contour (with 3.5 dB Coarse gain, F S 1.34 V PP Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Contour Plots Across Input and Sampling Frequencies (continued) Figure 87. SNR Contour (No gain, F S V PP Figure 88. SNR Contour (with 3.5 dB Coarse gain, F S 1.34 V PP Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com APPLICATION INFORMATION THEORY OF OPERATION ANALOG INPUT Resr 200 /c87 Lpkg nH/c1871 25 /c87 Sampling Capacitor Csamp 4.0□pF INP INM Cbond pF/c1871 50 /c87 Cpar1 0.8□pF Cpar2 1□pF Ron 15 /c87 Ron 10 /c87 Ron 15 /c87 Cpar2 1□pF 50 /c87 3.2□pF Lpkg 1□nH/c187 25 /c87Cbond pF/c1871 Resr 200 /c87 Csamp 4.0□pF Sampling Capacitor Sampling Switch Sampling Switch RCR□Filter ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 ADS612X is a family of low power 12-bit pipeline ADC in a CMOS process up to 125 MSPS sampling frequency. It is based on switched capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold, the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary complement format. The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in Figure This differential topology results in good ac-performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM 0.5 V and VCM 0.5 resulting in a 2-V PP differential input swing. The maximum swing is determined by the internal reference voltages REFP (2.5 V nominal) and REFM (0.5 nominal). Figure 89. Input Stage The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins to the voltage across the sampling capacitors). Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com fIN − Input Frequency − MHz 0 100 200 300 400 500 600 Magnitude − dB G080 Drive Circuit Requirements f − Frequency − MHz 0 100 200 300 400 500 600 R − Resistance − kΩ 100 0.1 0.01 G083 ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure 90. ADC Analog Input Bandwidth For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. A Ω resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. It is also necessary to present low impedance Ω for the common mode switching currents. For example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM). In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Over a wide frequency range, the input impedance can be approximated by a parallel combination of Rin and Cin (Zin Rin Cin). Figure 91. ADC Input Resistance, Rin Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com f − Frequency − MHz 0 100 200 300 400 500 600 C − Capacitance − pF G084 Using RF-Transformer Based Drive Circuits INP INM VCM 1 : 1 5 /c87 0.1 /c109F 0.1 /c109F 25 /c87 TF _ADC 25 /c87 5 /c87 ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure 92. ADC Input Capacitance, Cin Figure shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that can be used for low input frequencies (about 100 MHz). The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer s leakage inductances. The termination is accomplished by two resistors connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the termination resistors (connected to common mode) has to be low 100 Ω to provide a low-impedance path for the ADC common-mode switching current. Figure 93. Single Transformer Drive Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. Figure shows an example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the shaded box in Figure may be required between the two transformers to improve the balance between the P and M sides. The center point of this termination must be connected to ground. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com INP INM VCM 1 :1 5 /c870 .1/c109F 1 :1 50 /c87 50 /c87 0 .1/c109F 50 /c87 50 /c87 5 /c87 Using Differential Amplifier Drive Circuits RG RF RF RFIL RFIL CFIL CFIL RG

0.1 F/c109

10 F/c109

RS T||□R RT +VS CM INP INM ADS612x THS4509 VCM 500 /c87 200 /c87 200 /c87 5 /c87 5 /c87500 /c87 –V S ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure 94. Two Transformer Drive Circuit Figure shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interface to the ADC analog input pins. In addition to the single-ended to differential conversion, the amplifier also provides gain (10 dB in Figure R FIL helps to isolate the amplifier outputs from the switching input of the ADC. Together with C FIL it also forms a low-pass filter that band-limits the noise (and signal) at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC input pins is set using two 200 Ω resistors connected to VCM. The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC input pins can be biased to 1.5 In this case, use V and V supplies for the THS4509 so that its output common-mode voltage (1.5 is at mid-supply. Figure 95. Drive Circuit Using the THS4509 See the EVM User Guide SLWU028 for more information. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com Input Common-Mode Fs180 A x 125 MSPS/c109 (1) REFERENCE VCM REFM REFP INTREF INTREF EXTREF INTERNAL REFERENCE 1□k/c87 4□k/c87 Internal Reference External Reference Full−scale differential input pp/C0043(Voltage forced on VCM)/C00321.33 (2) ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1- µ F low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 180 µ A (at 125 MSPS). Equation describes the dependency of the common-mode current and the sampling frequency. Equation helps to design the output capability and impedance of the CM driving circuit. ADS612X has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the integration of the requisite reference capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the converter is controlled in the external reference mode as explained below. The internal or external reference modes can be selected by programming the serial interface register bit <REF (see Table Figure 96. Reference Section When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins. When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by Equation In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no change in performance compared to internal reference mode. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com COARSE GAIN and PROGRAMMABLE FINE GAIN ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 ADS612X includes gain settings that can be used to get improved SFDR performance (compared to dB gain mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from dB to dB. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as seen in Figure and Figure The fine gain is programmable in dB steps from to dB. With fine gain also, SFDR improvement is achieved, but at the expense of SNR (there is about dB SNR degradation for every dB of fine gain). So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the register bits <COARSE GAIN (see Table and <FINE GAIN (see Table Note that the default gain after reset is dB. Table 15. Full-Scale Range Across Gains GAIN, dB TYPE FULL-SCALE RANGE, V PP Default after reset 2.00 3.5 Coarse setting (fixed) 1.34 1.78 1.59 1.42 Fine gain (programmable) 1.26 1.12 1.00 Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com CLOCK INPUT CLKP 5 k/c87 VCM 5 k/c87 6 pF 10 /c87 10 /c87 CLKM Clock Buffer Ceq Ceq Ceq 1 to 3 pF , equivalent input capacitance of clock buffer/c187 Lpkg 1 nH/c187 Lpkg 1 nH/c187 Cbond 1 pF/c187 Cbond 1 pF/c187 Resr 100/c187 /c87 Resr 100/c187 /c87 ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 The clock inputs of the ADS612X can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between configurations. The common-mode voltage of the clock inputs is set to VCM using internal 5-k Ω resistors as shown in Figure This allows the use of transformer-coupled drive circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources Figure and Figure 100 For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.1- µ F capacitors, as shown in Figure A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1- µ F capacitor, as shown in Figure 100 For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure shows the performance of the ADC versus clock duty cycle. Figure 97. Internal Clock Buffer Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com Clock Frequency − MHz 100 200 300 400 500 600 700 800 900 1000 0 25 50 75 100 125 Impedance (Magnitude) − Ω G082 CLKP CLKM Differential□Sine-Wave or□PECL or□LVDS Clock□Input ADS612x CMOS□Clock□Input ADS612x ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure 98. Clock Buffer Input Impedance Figure 99. Differential Clock Driving Circuit Figure 100. Single-Ended Clock Driving Circuit Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com POWER DOWN MODES Global Powerdown Standby Output Buffer Disable Input Clock Stop Power Supply Sequence ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 ADS612X has four power-down modes global power down, standby, output buffer disable and input clock stopped. These modes can be set using the serial interface or using the parallel interface (pins SDATA and PDN). Table 16. Power Down Modes POWER DOWN PARALLEL INTERFACE SERIAL INTERFACE TOTAL POWER, WAKE-UP TIME MODES REGISTER BIT mW (to valid data) SDATA PDN Table Normal operation Low Low <PDN OBUF and 417 <STBY Standby Low High <PDN OBUF and Slow (50 µ <STBY Output buffer disable High Low <PDN OBUF and 408 Fast (200 ns) <STBY Global power down High High <PDN OBUF and Slow (50 µ <STBY In this mode, the A/D converter, internal references and the output buffers are powered down and the total power dissipation reduces to about mW. The output buffers are in high impedance state. The wake-up time from the global power down to output data becoming valid in the normal mode is maximum µ Note that after coming out of global power down, optimum performance will be achieved after the internal reference voltages have stabilized (about ms). Here, only the A/D converter is powered down and the total power dissipation is about mW. The wake-up time from standby to output data becoming valid is maximum µ The data output buffers can be disabled, reducing the total power to about 408 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time from this mode to data becoming valid in normal mode is maximum 500 ns in LVDS mode and 200 ns in CMOS mode. The converter enters this mode when the input clock frequency falls below MSPS. The power dissipation is about 120 mW, and the wake-up time from this mode to data becoming valid in normal mode is maximum µ During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated inside the device. Externally, they can be driven from separate supplies or from a single supply. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com DIGITAL OUTPUT INTERFACE Parallel CMOS Interface ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 ADS612X outputs data bits together with an output clock. The output interface are either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit <LVDS CMOS or parallel pin SEN. In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V (typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle. For DRVDD 2.2 it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed (125 MSPS). It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them. For DRVDD 2.2 it is recommended to use external clock (for example, input clock delayed to get desired setup/hold times). Output Clock Position Programmability There exists an option to shift (delay) the output clock position so that the setup time increases by 400 ps (typical, with respect to the default timings specified). This may be useful if the receiver needs more setup time, especially at high sampling frequencies. This can be programmed using the serial interface register bit <CLKOUT_POSN (see Table Output Buffer Strength Programmability Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this, the ADS612X CMOS output buffers are designed with controlled drive strength to get best SNR. The default drive strength also ensures wide data stable window for load capacitances upto pF and DRVDD supply voltage 2.2 To ensure wide data stable window for load capacitance pF, there is an option to increase the drive strength using the serial interface <DRIVE STRENGTH see Table Note that for DRVDD supply voltage 2.2 it is recommended to use maximum drive strength (for any value of load capacitance). CMOS Mode Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between and every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital current due to CMOS output switching C L DRVDD x x F AVG where C L load capacitance, N F AVG average number of output bits switching Figure shows the current with various load capacitances across sampling frequencies at MHz analog input frequency. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com D10 D11 ADS612X Pins CLKOUT 12□bit ADC□data OVR CMOS Output□Buffers ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure 101. CMOS Output buffers Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com DDR LVDS Interface CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D1 1_P D10_D1 1_M Output Clock Data bits D0, D1 Data bits D2, D3 Data bits D4, D5 Data bits D6, D7 Data bits D8, D9 Data bits D10, D1 1 ADS612x Pins 12-Bit ADC Data L VDS B uffers ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 The LVDS interface works only with 3.3 V DRVDD supply. In this mode, the data bits and the output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output on each LVDS differential pair every clock cycle (DDR Double Data Rate, see Figure 102 So, there are LVDS output pairs for the data bits and LVDS output pair for the output clock. LVDS Buffer Current Programmability The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω this results in a 350-mV single-ended voltage swing (700-mV PP differential swing). The LVDS buffer currents can also be programmed to 2.5 mA, 4.5 mA, and 1.75 mA (register bits <LVDS CURRENT see Table In addition, there is a current double mode, where this current is doubled for the data and output clock buffers (register bits <CURRENT DOUBLE see Table Figure 102. DDR LVDS Outputs Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the rising edge of CLKOUTP and the odd data bits D1, D3, D5, D7, D9, D11, and D13 are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all the data bits (see Figure 103 Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com CLKOUTP D0_D1_P, D0_D1_M D2_D3_P, D2_D3_M D4_D5_P, D4_D5_M D6_D7_P, D6_D7_M D8_D9_P, D8_D9_M D10_D11_P, D10_D11_M D10 Sample□N+1Sample□N D10 D11 D11 CLKOUTM ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure 103. DDR LVDS Interface LVDS Buffer Internal Termination An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially terminated inside the device. The termination resistances available are 300 Ω 185 Ω and 150 Ω (nominal with 20% variation). Any combination of these three terminations can be programmed; the effective termination is the parallel combination of the selected resistances. This results in eight effective terminations from open (no termination) to Ω The internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end is halved (compared to no internal termination). The voltage swing can be restored by using the LVDS current double mode. Figure 104 and Figure 105 compare the LVDS eye diagrams without and with internal termination (100 Ω With internal termination, the eye looks clean even with pF load capacitance (from each outpin to ground). The terminations is programmed using register bits <DATA TERM and <CLKOUT TERM (see Table Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com Output Data Format Output Timings ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 Figure 104. LVDS Eye Diagram No Internal Termination Figure 105. LVDS Eye Diagram with 100- Ω Internal 5-pF Load Capacitance Termination Blue Trace Output Clock (CLKOUT) 10-pF Load Capacitance Pink Trace Output Data Blue Trace Output Clock (CLKOUT) Pink Trace Output Data Two output data formats are supported complement and offset binary. They can be selected using the parallel control pin SEN or the serial interface register bit <DATA FORMAT (see Table The following table lists the timings at lower sampling frequencies. Table 17. Timing Characteristics at Lower Sampling Frequencies (1) (2) t su DATA SETUP TIME, ns t h DATA HOLD TIME, ns t PDI CLOCK PROPAGATION DELAY, ns Fs, MSPS MIN TYP MAX MIN TYP MAX MIN TYP MAX CMOS INTERFACE, DRVDD 2.5 V to 3.3 V 11.3 12.8 11.2 6.5 7.9 DDR LVDS INTERFACE, DRVDD 3.3 V 10.2 10.8 0.7 1.7 4.3 5.8 7.3 0.7 1.7 4.5 6.5 8.5 0.7 1.7 4.5 6.5 8.5 (1) Timing parameters are specified by design and characterization and not tested in production. (2) Timings are specified with default output buffer drive strength and C L pF Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com BOARD DESIGN CONSIDERATIONS Grounding Supply Decoupling Exposed Thermal Pad ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of the board are cleanly partitioned. See the EVM User Guide SLWU028 for details on layout and grounding. As ADS612X already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum number of capacitors would depend on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed to DRVDD. It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal performance. For detailed information, see application notes QFN Layout Guidelines SLOA122 and QFN/SON PCB Attachment SLUA271 Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth Aperture Delay Aperture Uncertainty (Jitter) Clock Pulse Width/Duty Cycle Maximum Conversion Rate Minimum Conversion Rate Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Gain Error Offset Error Temperature Drift ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 The analog input frequency at which the power of the fundamental is reduced by dB with respect to the low frequency value. The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. The sample-to-sample variation in aperture delay. The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. The minimum sampling rate at which the ADC functions. An ideal ADC exhibits code transitions at analog input values spaced exactly LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs The INL is the deviation of the ADC s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. The gain error is the deviation of the ADC s actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. The offset error is the difference, given in number of LSBs, between the ADC s actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from T MIN to T MAX It is calculated by dividing the maximum deviation of the parameter across the T MIN to T MAX range by the difference T MAX T MIN Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com Signal-to-Noise Ratio SNR /C004310Log10 P s P N (4) Signal-to-Noise and Distortion (SINAD) SINAD /C004310Log10 P s P N /C0041P D (5) Effective Number of Bits (ENOB) ENOB /C0043SINAD /C00421.76 6.02 (6) Total Harmonic Distortion (THD) THD /C004310Log10 P s P N (7) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion DC Power Supply Rejection Ratio (DC PSRR) ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 SNR is the ratio of the power of the fundamental S to the noise floor power N excluding the power at dc and the first nine harmonics. SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter s full-scale range. SINAD is the ratio of the power of the fundamental S to the power of all the other spectral components including noise N and distortion D but excluding dc. SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter s full-scale range. The ENOB is a measure of a converter s performance as compared to the theoretical limit based on quantization noise. THD is the ratio of the power of the fundamental S to the power of the first nine harmonics D THD is typically given in units of dBc (dB to carrier). The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). IMD3 is the ratio of the power of the fundamental (at frequencies and f2) to the power of the worst spectral component at either frequency 2f1 or 2f2 f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter s full-scale range. The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com AC Power Supply Rejection Ratio (AC PSRR) (Expressed□in□dBc)/c68VSUP /c68VOUT10PSRR□□=□20Log (8) Common Mode Rejection Ratio (CMRR) (Expressed□in□dBc)/c68VCM /c68VOUT10CMRR□□=□20Log (9) Voltage Overload Recovery ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If Δ V SUP is the change in the supply voltage and Δ V OUT is the resultant change in the ADC output code (referred to the input), then CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If Δ Vcm is the change in the input common-mode voltage and Δ V OUT is the resultant change in the ADC output code (referred to the input), then The number of clock cycles taken to recover to less than error for a 6-dB overload on the analog inputs. A 6-dBFS sine wave at Nyquist frequency is used as the test stimulus. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A OCTOBER 2007 REVISED MARCH 2008 REVISION HISTORY Changes from Original (October 2007) to Revision A Page Changed DDR LVDS output data sequence in Figure Changed pin configuration (CMOS mode) information Changed pin configuration (LVDS mode) information Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) ADS6122IRHB25 ACTIVE QFN RHB 32 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6122IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6122IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6122IRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6122IRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6123IRHB25 ACTIVE QFN RHB 32 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6123IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6123IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6123IRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6123IRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6124IRHB25 ACTIVE QFN RHB 32 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6124IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6124IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6124IRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6124IRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6125IRHB25 ACTIVE QFN RHB 32 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6125IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6125IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6125IRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6125IRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2010 Addendum-Page 1

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2010 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS6122IRHBR QFN RHB 32 3000 338.1 338.1 20.6 ADS6122IRHBT QFN RHB 32 250 338.1 338.1 20.6 ADS6123IRHBR QFN RHB 32 3000 338.1 338.1 20.6 ADS6123IRHBT QFN RHB 32 250 338.1 338.1 20.6 ADS6124IRHBR QFN RHB 32 3000 338.1 338.1 20.6 ADS6124IRHBT QFN RHB 32 250 338.1 338.1 20.6 ADS6125IRHBR QFN RHB 32 3000 338.1 338.1 20.6 ADS6125IRHBT QFN RHB 32 250 338.1 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 2

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