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GC5330IZEV TI | Alldatasheet

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I/Q□Mod I/Q□Mod I/Q□Mod I/Q□Mod PA PA PA PA SW Baseband Data DAC3484 ADS61B49 TRF3703/3720 Complex TX Subsampled Feedback Mixer/BPF Mixer/BPF Mixer/BPF Mixer/BPF Mixer/BPF LNA LNA LNA LNA ADS62P49 ADS62P49 RX FB I/Q I/Q RX RX RX Real RX Real RX B0441-01 ADC ADC ADC ADC ADC GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 WidebandTransmit-ReceiveDigitalSignalProcessors Check forSamples: GC5330 ,GC5337 1FEATURES APPLICATIONS

• Multi-StandardBase Stations• IntegratedTransmitand Receive DigitalIF Solution • 3GPP (LTE,W-CDMA, TDS-CDMA)
• MC-GSM• Up to4 TX, 8 RX, Plus DPD Feedback
• WiMAX and WiBro (OFDMA)• TX-TransmitIncludesDUC, CFR, DPD, TX
• Multi-CarrierPower Amplifiers(MCPAs)Equalizer,and Bulk Upconverter
• WirelessInfrastructureRepeaters• 62-MHz TX SignalBandwidth With Fifth-Order DPD Correction • Up to4 × 4 MIMO
• CFR: 6-dB PAR forWCDMA, 7-db LTE Signals DESCRIPTIONWith EVM Meeting 3GPP Specs; Configurable forAllMajor WirelessInfrastructureStandards The GC533x is a wideband transmitand receive signalprocessorthatincludesdigitaldownconverter/• DPD: Memory Compensation, TypicalACLR upconverter(DDUC), transmit,receive,and captureImprovement of20 dB or More bufferblocks.The transmitpathincludescrestfactor• RX-Receive IncludesDC-OffsetCancellation, reduction(CFR), digitalpredistortion(DPD) andFront-Endand Back-End AGC, Bulk associatedfeedbackpath,complex equalization,andDownconverter,RX Equalizer,I/QImbalance bulkupconversion.Correction,DDC The receivepathincludeswideband and narrowband• 4 DDUCs, 1–12 Channels per DDUC, Each automaticgaincontrol(AGC), bulkdownconversion,DDUC Can Be Programmed toTX or RX, ata complexequalization,and I/Qimbalancecorrection.Common Resampler Rate – Multimode The DDUC sectionconsistsof fouridenticalDDUCSupport blocks,each supportingup to 12 channels.Each• Seamless InterfacetoTIHigh-Speed Data channel has independentfractionalresamplersandConverters NCOs to enable flexiblecarrierconfigurations.
• 4 TX Aggregate Output toDACs up to Multi-mode/multi-standardoperation can be supportedby configuringtheindividualDDUC blocks930 MSPS Complex todifferentfilteringand oversamplingscenarios.• 8 RX Aggregate InputFrom ADCs up to 1.24GSPS Real
• Supports Envelope TrackingTechniques
• 16-Tap (Complex) RX Equalizers
• Two 4K Complex Word Capture Buffersfor SignalAnalysis,AdaptiveFiltering,and DPD Algorithms
• TMS320C6748 DPD OptimizationSoftware
• 1.1-VCore,3.3-VI/OCMOS, 1.8-VI/OLVDS
• Power Consumption, 3.5W Typical
• 484-BallTE-PBGA Package, 23 mm × 23 mm Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. © 2010–2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. DESCRIPTION (Continued) The CFR blockreducesthepeak-to-averageratio(PAR) ofthedigitaltransmitsignals,such as thoseused in third-generation(3G) code divisionmultipleaccess (CDMA) and orthogonalfrequency-divisionmultiple-access (OFDMA) applications. The DPD pathwitha 310-MHz DPD clockcan be configuredtosupportone antennaat62 MHz, two antennasat 62 MHz each,or fourantennasat 31 MHz each,allwithan associated5× DPD expansionbandwidth.The GC533x DPD processorreduces power amplifier(PA) nonlinearity,e.g.,as measured by adjacent-channel leakageratio(ACLR), by over 20 dB. By reducingthe PAR of the digitalsignaland the PA nonlinearity,the operationalefficiencyoffollow-onpower amplifierscan be substantiallyimproved. A higherDPD bandwidth is possiblewith reduced DPD performance.Severalarchitecturesthatprovide performanceand costoptimizationarelistedinTable1 Table1.Sample ConfigurationsforGC5330 {GC5337} Figure TX Antenna DPD Bandwidth ET Support Feedback RX Antenna Other 2 typicalat250 Lower-cost2-antennaFigure1 2-62{74}MHz 310 {370}MHz Subsampled real Msps, up to4 at solution250 Msps 2 at250Msps, 4Full-raterealup to 2-antennasolutionwithFigure2 2-62{74}MHz 310 {370}MHz withlower-rateRX1Gsps full-raterealfeedbackADC 2 at250Msps, 4 2-antennasolutionwithSubsampledFigure3 2-62{74}MHz 310 {370}MHz withlower-rateRX complexfeedback,lowercomplex ADC subsamplingratio 2 at250Msps, 4 2-antennasolution,with2-envelope Full-raterealup toFigure4 2-62{74}MHz 310 {370}MHz withlower-rateRX envelopetrackingwithtracking 1Gsps ADC full-raterealfeedback 4 at250Msps, 8 Lower-cost4 antennaFigure5 4-31{37}MHz 155 {185}MHz Subsampled real withlower-rateRX solutionADC

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I/Q□Mod I/Q□Mod PA PA SW Baseband Data DAC3283/3482 ADS41B49 TRF3703/3720 Complex TX Subsampled Feedback Mixer/BPF Mixer/BPF Mixer/BPF LNA LNA ADS62P49 RX FB I/Q I/Q RX Real RX B0442-01 ADC ADC ADC DAC DAC C6748 DSP GC533x DUC-CFR DPD DDC I/Q□Mod I/Q□Mod PA PA SW Baseband Data DAC3283/3482 ADS5474 Complex TX Real Feedback Mixer/BPF Mixer/BPF Mixer/BPF LNA LNA ADS62P49 RX RX I/Q I/Q RX Real RX B0443-01 ADC ADC ADC DAC DAC TRF3703/3720 GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 ANTENNA MODE EXAMPLE DIAGRAMS Figure1. Two-Antenna-Mode Subsampled-Feedback Diagram Figure2. Two-Antenna-Mode Full-RateReal-FeedbackDiagram © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):GC5330 GC5337

I/Q□Mod I/Q□Mod PA PA SW Baseband Data DAC3283/3482 TRF3703/3720 Complex TX Complex Feedback Mixer/BPF Mixer/BPF LNA LNA ADS62P49 ADS62P49 RX I/Q RX I/Q RX RX Real RX B0435-01 ADC ADC DAC ADC DAC ADC I/Q□Demod C6748 DSP GC533x DUC-CFR DPD DDC I/Q□Mod I/Q□Mod Env.□Mod Env.□Mod PA PA SW Baseband Data DAC3484 ADS5474 TRF3703/3720 ET TX Real Feedback Mixer/BPF Mixer/BPF Mixer/BPF LNA LNA ADS62P49 RX RX I/Q RX Real RX B0444-01 ADC ADC ADC DAC DAC GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Figure3. Two-Antenna-Mode Complex-Feedback Diagram Figure4. Two-Antenna-Mode, Envelope-Tracking,Full-RateReal-FeedbackDiagram

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I/Q□Mod I/Q□Mod I/Q□Mod I/Q□Mod PA PA PA PA SW Baseband Data DAC3484 ADS61B49 TRF3703/3720 Complex TX Subsampled Feedback Mixer/BPF Mixer/BPF Mixer/BPF Mixer/BPF Mixer/BPF LNA LNA LNA LNA ADS62P49 ADS62P49 RX FB I/Q I/Q RX RX RX Real RX Real RX B0441-01 ADC ADC ADC ADC ADC GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Figure5. Four-Antenna-Mode Subsampled Real-FeedbackExample Diagram GENERAL DESCRIPTION The GC533x isa widebandtransmitand receivesignalprocessorthatincludesdigitaldownconverter/upconverter (DDUC), transmit,receive,and capturebufferblocks.The transmitpath includescrestfactorreduction(CFR), digitalpredistortion(DPD) and associatedfeedbackpath,complex equalization,and bulkupconversion.The receivepathincludeswideband and narrowbandautomaticgaincontrol(AGC), bulkdownconversion,complex equalization,and I/Qimbalancecorrection.The GC5337 isa higher-speedversionoftheGC5330 thathas the same package, but with interfacesthatcan providemore processingperformance for higher-bandwidth applications.Inthedescriptions,theGC5337 differencesareshown with{}values. The architecturesupportsdifferentRX, TX, and feedback modes of operation.This providesfor many configurationstooptimizeperformanceand cost.

• RX – realorcomplexinput
• TX – real,complex,complexwithenvelopetracking
• Feedback – subsampledreal,full-ratereal,full-ratecomplex © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com The RX pathcan be configuredforone ortwo multichannelADC inputports.The RX blockprovideseach ADC channel with a front-endAGC, IQ demodulationcorrection,real-to-complexconversion,complex mixing, decimation,and complex equalization.The RX blockoutputisinputtotheDDUC block.The outputoftheDDUC blockgoes throughgainand back-endAGC and isformattedforthebaseband output. There arefourDDUC blocks.Each can be used fortheRX DDC downconversionorTX DUC upconversion,one ata time.The DDUC has a complex mixer,cascade integratorcomb filter,resampler,and a programmableFIR filter.Each DDUC can support1 to12 channels. The TX path can be configuredforone, two,or fourantenna streams.In addition,withone or two antenna streams,an envelopemodulatoroutputisavailable.The DAC and envelopemodulatorsharethesame output ports.The TX inputisfromthebaseband input,throughtheDDUC tocreatecomplexantennastreams.The CFR blockprovidesforgainadjustment,peak reduction,and peak limiting.The CFR blockpeak power reductionand follow-oncircularlimiterprovidetheheadroom toapplytheDPD correction,and tolowerthepeak power results formore power amplifierefficiency.Additionalinterpolationstages afterCFR expand the antenna stream bandwidthtotheDPD bandwidth. The DPD has both high-performance(more correction)and high-bandwidth(more bandwidth)modes. The high-bandwidthmode supports62 MHz {74MHz} forone ortwo antennastreams,and 31 MHz {37MHz} forfour antennastreamswithfifth-orderexpansionbandwidth.The high-performancemode supportsone antennaat62 MHz {74MHz}, two antennaeat31 MHz {37MHz}, orfourantennaeat15.5MHz {18.5MHz}. The GC533x DPD processorprovidesphase correction,gaincorrection,and nonlinearfeedforwardcorrectionforeach TX stream. The spectralemissionorACP performanceisimprovedby 20 dB ormore. SpecializedcapturelogiccollectstheRX input,feedbackinput,RX output,DPD input,and DPD outputforthe DSP processorto perform the adaptionalgorithm.The capturelogiccan also be used forperformance monitoringand power measurement. AVAILABLE OPTIONS PART NUMBER TC PACKAGE THERMAL PROPERTIES GC5330IZEV –40°C to85°C 484 ball23-mm × 23-mm PBGA Heat transferthroughpackage top GC5337IZEV –40°C to85°C 484 ball23-mm × 23-mm PBGA Heat transferthroughpackage top

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40 LVDS (1.8V) 40 LVDS (1.8V)TX Format and DAC Interface Control and Sync CMOS (3.3 V) JTAG CMOS (3.3 V) 228 416 uP addr 24 LVDS (1.8V) (1.8V) 1–4 TX Streams Up to 8 DACs (2 40-Pin Ports) GC5330, GC5337 TESTMOD, RESET uP data 60 LVDS (1.8V) 60 LVDS (1.8V) Up to 8 ADCs (2 30-Pin Ports)

1 ADC

(1 16-Pin Port) High- Speed Sync, Clocks 16 CMOS (3.3V)

2 LVDS

4 LVDSSync A, B in

24 LVDS

(port AB) ADC inter- face (port C) uP ctrl INT B0445-01 SPI en, SPI clk SPIDIO LVDS showing the number of pins; each signal is a diff pairSPIDO (SPARE) Mux and Sum (TX) or Dist (RX) Baseband Interface Power Meter, per Channel beAGC per Channel TX Complex Gain per Channel FIR 1 , /c180 /c180 Farrow 10241– /c180 1–12 Channel DDUC Block (config as TX or RX, showing TX) CIC 1–3 /c180 X NCO DPD and TX Eq UC 1/2/c180CFR TX 1–2 Streams Includes interp before or after CFR, 80% BW, 90 dB stop 1/2/3/4 80% BW, 90 dB stop; 90% BW, 80 dB stop /c18040% BW, 90 dB stop 2/c180 ET BUC Eq (16 Taps) BDC RX 1/2/4 Streams 1/2/4/8/16/c180 I/Q Imbal Correction When I/Q correction enabled, IF NCO is disabled Interval Based Power Meter IF NCO Switch R2C fe- AGC DC Offset Cancel DVGA Format/ GPIO Running Avg Power Meter TX IF Mux and SumIF NCO X JTAG GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 NOTE: UC1 and UC2 areforCFR interpolation;UC2 can onlybe used ifUC1 isalsoused. Figure6. GC533x Block Diagram GC533x Introduction The GC533x isa flexibletransmitand receivedigitalsignalprocessorthatincludesreceiverand transmitter blocks,digitaldownconverter/upconverter(DDUC) blocks,crestfactorreduction(CFR) and digitalpredistortion (DPD) engines,flexibleLVDS dataconverterand baseband interfaces,and capturebuffersforDPD and adaptive filteringalgorithms. Each ofthefourDDUC blockscan be configuredas eithera digitaldownconverter(DDC) ora digitalupconverter (DUC). Typically,a system can be implementedas both TX and RX, withboth DDC and DUC functions.The DDUC blocksprovideprogrammableFIR filterswithflexiblenumbers oftaps,dependingon signalbandwidthand number of channels,as wellas fractionalresamplers,CIC filters,and complex mixers.The DDUC complex mixerssupportstaticorhoppingtuningfunctions. beAGC aftertheDDC ispartofthebaseband interface.StaticgainisappliedintheBB blockforboththeDDC outputand DUC input. The receiverblockprovidesdc offsetcorrection,front-endAGC, real-to-complexconversion,complex mixing, decimatingfilters,a complexequalizer,and a blindRX IQ imbalancecorrectionfunction. The CFR blockreducesthepeak-to-averageratio(PAR) ofcomplex,arbitraryTX signals.ReducingthePAR of the TX signalallowswireless-infrastructure(WI) base stationsand repeatersto use smallerand lower-cost multi-carrierpower amplifiers(MCPAs). The DPD blockcan processone ortwo TX streamsat62 MHz {74MHz} orfourTX streamsat31 MHz {37MHz} each,withfifth-ordernonlinearcorrection.The DPD engineuses a companion TIDSP TMS320C6748 tocollect thereferenceand feedbackdata,calculatethefeedforwardcorrection,and updatetheGC533x registers. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com InWI applications,theGC533x meets multi-carrier3G and 4G performancestandards(PCDE, compositeEVM, and ACLR) atPAR levelsdown to6 dB forWCDMA and 7 dB forLTE, and improvestheACLR by over20 dB at thePA output.The GC533x integrateseasilyintothetransmit/receivesignalchainbetween Texas Instruments’ high-performancedata convertersand baseband processorssuch as the TI TMS320C64xx family.In wireless repeaterapplications,theGC533x can provideseamlessinterfacestoTIdataconverters,alongwithreceiveand transmitfiltering,DDC, and DUC functions. The GC533x is extremelyflexibleand can be used in system architectureswithdifferentsignaltypes and TX-by-RX antennaconfigurationssuch as 2×2,2×4,4×4,and 4×8. The GC533x EVM system providesan example sectortransmit-receivesignalchain solution,from the multi-carrierbaseband totheRF antenna. ABSOLUTE MAXIMUM RATINGS overrecommended operatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT VDD Core supplyvoltage –0.3 1.32 V VDDA PLL analogvoltage –0.3 2 V VDDS DigitalsupplyvoltageforTX –0.3 2 V VDDSHV Digitalsupplyvoltage –0.3 3.6 V VIN Inputvoltage(under/overshoot) –0.5 VDDSHV + 0.5 V Clamp currentforan input/output –20 20 mA Tstg Storagetemperature –65 140 °C ESD classification Class2 (2.5kV HBM, 500 V CDM, 150 V MM) Moisturesensitivity MoisturesensitivityClass3 (1week floorlifeat30°C /60% H) (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderRecommended Operating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT VDDA AnalogsupplyforPLLs 60 mA max. (each)(2) 1.71 1.8 1.89 VDDS DigitalsupplyvoltageforLVDS I/O 700 mA max.(2) 1.71 1.8 1.89 V VDDSHV DigitalsupplyvoltageCMOS I/O PC boarddesigndependent 3.15 3.3 3.45 V TC Case temperature –40 30 90 °C TJ Junctiontemperature i(4) 105 °C (1) Productiontestedhotusingchecksum at310 MHz and maximum supplies.Power scaleslinearlywithfrequencywitha dc consumption around350 mA typical,700 mA worstcase. (2) Chipspecificationsareproductiontestedto90°C case temperature.QA testsareperformedat85°C. (3) Power consumptionisa strongfunctionoftheconfiguration.A calculatorisavailabletoestimatepower fora specificconfiguration. (4) Reliabilitycalculationspresume junctiontemperature105°C orbelow.Operationabove 105°C junctiontemperaturereducesproduct lifetime.

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 THERMAL INFORMATION GC5330 THERMAL METRIC ZEV UNIT

484 PINS

θJA Junction-to-ambientthermalresistance(1) 15.4 °C/W θJCtop Junction-to-case(top)thermalresistance(2) 2.1 °C/W θJB Junction-to-boardthermalresistance(3) 7.6 °C/W ψJT Junction-to-topcharacterizationparameter(4) 0.5 °C/W ψJB Junction-to-boardcharacterizationparameter(5) 7.5 °C/W θJCbot Junction-to-case(bottom)thermalresistance(6) N/A °C/W (1) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (2) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specific JEDEC-standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (3) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8. (4) The junction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA,usinga proceduredescribedinJESD51-2a (sections6 and 7). (5) The junction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA ,usinga proceduredescribedinJESD51-2a (sections6 and 7). (6) The junction-to-case(bottom)thermalresistanceisobtainedby simulatinga coldplateteston theexposed (power)pad.No specific JEDEC standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):GC5330 GC5337

= 1.1 V = 1.8 V, 3.3 V = GND BB AA CC DD EE FF GG HH JJ KK LL MM NN PP RR TT UU VV WW YY AAAA NC BBIN5P BBIN4P BBIN3P BBIN1P SPIDENB SPICLK CEB UPA5 UPA2 UPD15 UPD12 UPD8 UPD5 UPD1 VSSA2 SYNCBN SYNC OUTN SYNC OUTP TXA1N TXA2P NC BBIN7N BBIN7P BBIN5N BBIN4N BBIN3N BBIN1N SPIDIO INTERRPT UPA6 UPA3 WEB UPD13 UPD9 UPD6 UPD2 UPD0 VDDA2 SYNCBP TXA0N TXA1P TXA2N TXA5N BBIN8N BBIN8P BBIN6P BBIN6N VSSA1 BBIN2P BBIN0P EMIFENA UPA7 UPA4 UPA0 UPD14 UPD10 UPD7 UPD3 SYNCAPDPDCLKP TXA0P TXA3P TXA4P TXA4N TXA5P NC BBIN9N BBIN9P NC VDDA1 BBIN2N BBIN0N VSS OEB VSS UPA1 VSS UPD11 VSS UPD4 SYNCAN DPDCLKN TXA3N TXA6N TXA7N TXA8N TXA9P BBOUT0P BBIN10P BBIN10N BBIN11P BBIN11N VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD NC NC TXA6P TXA7P TXA8P TXA9N BBOUT0N BBOUT2N BBOUT2P BBOUT1N BBOUT1P NC VDDS2 VDDSHV1 VDD VDDSHV1 VDD VDDSHV1 VDD VDDSHV1 VDD VDDS1 NC VDD TXA11N TXA11P TXA10N TXA10P BBOUT4N BBOUT4P BBOUT3N BBOUT3P VDDS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD TXA13P TXA13N TXA12P TXA12N BBOUT6N BBOUT6P BBOUT5N BBOUT5P VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDS1 TXA15P TXA15N TXA14N TXA14P BBOUT8N BBOUT8P BBOUT7N BBOUT7P VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD TXA17P TXA17N TXA16N TXA16P BBOUT10N BBOUT10P BBOUT9N BBOUT9P VDDS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDS1 TXA19N TXA19P TXA18N TXA18P RXA13P RXA14N RXA14P BBOUT1 1P BBOUT1 1N VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD TXB1P TXB1N TXB0P TXB0N RXA13N RXA12P RXA11N RXA11P VDDS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDS1 TXB3P TXB3N TXB2P TXB2N RXA12N RXA10P RXA9N RXA9P VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD TXB5P TXB5N TXB4P TXB4N RXA10N RXA8N RXA8P RXA7N RXA7P VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD TXB7P TXB7N TXB6P TXB6N RXA6N RXA6P RXA5N RXA5P VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDS1 TXB9P TXB9N TXB8P TXB8N RXA4N RXA3N RXA3P RXA2N RXA2P VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD TXB11P TXB11N TXB10P TXB10N RXA4P RXA1P RXA0N RXA0P VDD NC VDDS2 VDD VDDSHV2 VDD VDDSHV2 VDD VDDSHV2 VDD VDD VDDS1 NC VDD TXB13P TXB13N TXB12P TXB12N RXA1N RXB14N RXB10N RXB10P NC NC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD NC NC TXB15P TXB15N TXB14N TXB14P RXB14P RXB13P NC RXB6P RXB6N RXB4P RXB2P VPP VSS VPP VSS DVGA6 VSS TDO TMS RXC6N RXC4N NC TXB17P TXB17N TXB16P TXB16N RXB13N RXB12N RXB8N RXB8P RXB5P RXB4N RXB2N VDDMON RESETB DVGA13 DVGA10 DVGA7 DVGA3 DVGA0 TDI RXC6P RXC5N RXC4P TXB19N TXB19P TXB18N TXB18P RXB12P RXB11P RXB9P RXB7N RXB5N RXB3P RXB1N VSSMON SPIDO (SPARE) DVGA14 DVGA11 DVGA8 DVGA4 DVGA1 TRSTB RXC7N RXC5P RXC3P RXC2N RXC2P RXC0N NC NC RXB11N RXB9N RXB7P NC RXB3N RXB1P RXB0P RXB0N TESTMOD DVGA15 DVGA12 DVGA9 DVGA5 DVGA2 TCK RXC7P RXC3N RXC1N RXC1P RXC0P NC ABAB P0131-01 GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Pin Assignment and Descriptions(Top View) Figure7. GC533x Pinout(Top View)

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Pin Functions NAME NUMBER TYPE DESCRIPTION POWER AND BIASING VDD E6,E7,E8,E9,E10,E11,E12,E13,E14,E15,E16,F9, PWR 1.1-Vpower supply F11,F13,F15,F18,G18, H5, J5,J18,L18,N5, N18, P18, R5, T18,U5, U8, U10, U12, U14, U15, U18, V7,V8,V9, V10,V11,V12,V13,V14,V15,V16 VDDSHV2 U9, U11, U13 PWR 3.3-Vpower supplyforCMOS I/O VDDSHV1 F8,F10,F12,F14 PWR 3.3-Vpower supplyforCMOS I/O VDDS1 F16,H18, K18,M18, R18, U16, PWR 1.8-Vpower supplyforLVDS I/O VDDS2 F7,G5, K5,M5, U7 PWR 1.8-Vpower supplyforLVDS I/O VPP W8, W10 PWR 1.1-VE-fusesupply,connecttoVDD VDDMON Y8 NC Do notconnect,internalmonitorpoint VSSMON AA8 NC Do notconnect,internalmonitorpoint VDDA2 B17 PWR 1.8-Vpower forPLL (requiresfiltering) VDDA1 D5 PWR 1.8-Vpower forPLL (requiresfiltering) VSSA2 A16 PWR Ground forPLL (requiresfiltering) VSSA1 C5 PWR Ground forPLL (requiresfiltering) VSS D8, D10, D12, D14, G6, G7. G8, G9, G10, G11, G12, G13, PWR Ground G14, G15, G16, G17, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, J6,J7,J8,J9,J10,J11,J12,J13,J14, J15,J16,J17,K6,K7,K8,K9,K10,K11,K12,K13,K14, K15,K16,K17,L6,L7,L8,L9,L10,L11,L12,L13,L14, L15,L16,L17,M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, P6,P7,P8,P9,P10,P11,P12,P13,P14, P15,P16,P17,R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, T6,T7,T8,T9,T10,T11,T12,T13,T14, T15,T16,T17,W9, W11, W13 NC E17,E18,F6,F17,U6, U17, V5,V6,V17,V18 NC No connection.Recommend connectingtoground NC A1,A22,D1, D4, W3, W18, AA22, AB1, AB5, AB22, NC No connection BASEBAND INPUT/OUTPUT BBIN[11:0]P E4,E2,D3, C2, B2,C3, A2,A3,A4,C6, A5,C7 I Baseband input– LVDS positive BBIN[11:0]N E5,E3,D2, C1, B1,C4, B3,B4,B5,D6, B6,D7 I Baseband input– LVDS negative BBOUT[11:0]P L4,K2,K4,J2,J4,H2, H4, G2, G4, F3,F5,E1 O Baseband output– LVDS positive BBOUT[11:0]N L5,K1,K3,J1,J3,H1, H3, G1, G3, F2,F4,F1 O Baseband output– LVDS negative TX DAC INTERFACE TXA[19:0]P K20,K22,J19,J22,H19, H22, G19, G21, F20,F22,D22, O DAC TX portA – LVDS positive E21,E20,E19,C22, C20, C19, A21,B20,C18 TXA[19:0]N K19,K21,J20,J21,H20, H21, G20, G22, F19,F21,E22, O DAC TX portA – LVDS negative D21, D20, D19, B22,C21, D18, B21,A20,B19 TXB[19:0]P Y20,Y22,W19, W21, V19,V22,U19, U21, T19,T21,R19, O DAC TX portB – LVDS positive R21, P19,P21,N19, N21, M19, M21, L19,L21 TXB[19:0]N Y19,Y21,W20, W22, V20,V21,U20, U22, T20,T22,R20, O DAC TX portB – LVDS negative R22, P20,P22,N20, N22, M20, M22, L20,L22 RX and FB ADC INTERFACE RXA[14:0]P L3,L1,M2, M4, N2, N4, P3,P5,R2, R4, U1, T3,T5,U2, U4 I ADC receiveportA – LVDS positive RXA[14:0]N L2,M1, N1, M3, P1,N3, P2,P4,R1, R3, T1,T2,T4,V1,U3 I ADC receiveportA – LVDS negative RXB[14:0]P W1, W2, AA1, AA2, V4,AA3, Y4,AB4, W4, Y5,W6, AA6, I ADC receiveportB – LVDS positive W7, AB7, AB8 RXB[14:0]N V2,Y1,Y2,AB2, V3,AB3, Y3,AA4, W5, AA5, Y6,AB6, Y7, I ADC receiveportB – LVDS negative AA7, AB9 RXC[7:0]P AB17, Y16,AA17, Y18,AA18, AA20, AB20, AB21 I ADC receiveportC – LVDS positive RXC[7:0]N AA16, W16, Y17,W17, AB18, AA19, AB19, AA21 I ADC receiveportC – LVDS negative © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):GC5330 GC5337

1.8V GND R□=□0 Ω R□=□0 Ω 50 Ω 50 Ω C□=□0.01 FμC□=□0.1 Fμ VDDA1□or□VDDA2 VSSA1□or□VSSA2 Ferrite□Bead Ferrite□Bead S0510-01 GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Pin Functions(continued) NAME NUMBER TYPE DESCRIPTION DVGA INTERFACE DVGA[15:0] AB11, AA10, Y10,AB12, AA11, Y11,AB13, AA12, Y12, O W12, AB14, AA13, Y13,AB15, AA14, Y14 MPU INTERFACE UPD[15:0] A11,C12, B12,A12,D13, C13, B13,A13,C14, B14,A14, I/O D15, C15, B15,A15,B16 UPA[7:0] C9, B9,A9,C10, B10,A10,D11, C11 I WEB B11 I Writeenable,active-low EMIFENA C8 I EMIFENA switchesbetween address/dataµP accessand SPI access.Itsvaluemay be changed atany time,butbothaddress/dataaccessand SPI accessmust be idleduringthechange.Logic1 = EMIF, logic0 = SPI pinhas internalpullup. OEB D9 I Read and outputenable,active-low CEB A8 I Chipenable,active-low JTAG INTERFACE TRSTB AA15 I JTAG reset(active-low);pulldown ifJTAG isnot used. TMS W15 I JTAG mode select TDO W14 O JTAG dataout TDI Y15 I JTAG datain TCK AB16 I JTAG clock SPI INTERFACE SPIDENB A6 I Serialinterfaceenable SPICLK A7 I Serialinterfaceclock SPIDIO B7 I/O Serialinterfacedata SPIDO(SPARE) AA9 O Serialinterfacedataoutinfour-wireSPI mode MISCELLANEOUS TESTMOD AB10 I Testmode forGC533x, typicallygrounded RESETB Y9 I Chipreset– required– active-low INTERRPT B8 O Outputinterrupt DPDCLKP C17 I DPD CLK input– LVDS positive DPDCLKN D17 I DPD CLK input– LVDS negative SYNCOUTP A19 O Sync output– LVDS positive SYNCOUTN A18 O Sync output– LVDS negative SYNCAP C16 I Sync inputA – LVDS positive SYNCAN D16 I Sync inputA – LVDS negative SYNCBP B18 I Sync inputB – LVDS positive SYNCBN A17 I Sync inputB – LVDS negative NOTE: 0-Ω R0603 resistorisused toaccommodate seriesresistorifneeded. Figure8. GC533x PLL Filtering

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1□to□4 Tx Streams BUC TX□Block Envelope Tracking Block TX□BB TX□BB□Input□Formatter DAC□Output□Formatter IF NCO FIR 1x,□2x Farrow 1024x1– 1–12 Channel□DUC□Block CIC 1–3x X NCO UC 1/2x UC 1/2/4xCFR DPD 1–2□Streams 80%□BW, 90□dBstop 1/2/3/4x 80%□BW, 90□dBstop; 90%□BW, 80%□dB□stop 40%□BW, 90□dBstop Includes 16-tap□Eq IF Sum B0446-01 R2C; Format; feAGC; DC Offset Correction 1 to 9 ADC Inputs 1/2/4 Streams IF Mux DVGA Outputs When I/Q correction enabled, IF NCO is disabled RX Block RX Equalizer

16 Taps

1 , 2x/c180 Farrow 10241– /c180 1–12 Channel DDC Block CIC 1–3 /c180 X NCO IF NCO IF NCO X X B0447-01 GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 The two GC533x PLLs requirea filteredpower supply.The supplycan be generatedby filteringthedigitalsupply (VDDS1, VSSA1, VDDS2, and VSSA2). A representativefilterisshown inFigure8.The two PLLs shouldhave separatefiltersthatare locatedas closeas is reasonableto theirrespectivepins (especiallythe bypass capacitors).The ferritebeads shouldbe series50R (similartoMurataP/N:BLM31P500SPT, Description:IND FB BLM31P500SPT 50R 1206). Sub-Chip Descriptions Figure9 shows theTX functionalblockdiagram,and Figure10 shows theRX functionalblockdiagram.Note that each figureshows up tofourDUC or DDC blocksintheTX or RX paths,and thereare a totaloffourDDUC blocksthatmay be configuredas eitherDUC orDDC each. Figure9. TX FunctionalBlock Diagram Figure10. RX FunctionalBlock Diagram TX Baseband InputFormatter The TX baseband (BB)input-formatterblockacceptsTX baseband inputsfromtheFPGA orbaseband processor and formatsthem fortheDUC blocks.There are 12 unidirectionalLVDS pairsfortheTX inputformatter,and theirfunctiondepends on the operationalmode. There are threeoperationalmodes forthe TX BB input formatter:bytemode (B,8 or 9 bits),nibblemode (N,4 bits),and serialmode (S,2 bits)toallowmultipleBB inputrates.The GC533x can acceptup tothreedifferentBB inputdatarates.Table2 and Table3 summarize each mode and the pinassignments.In Table 3, BBIN[X]isthe BBIN differentialpair(assumed positiveand negativeconnections),and BB0, BB1, and BB2 representthreedifferentTX baseband portsatarbitraryrates. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Table2.TX BB FormatterModes Maximum Complex InterfaceRate per ChannelMODE DESCRIPTION TotalNumber ofInterfacePins N isthenumber ofchannels. 1B Bytemode, 1 interfacerate 10 or11 = 8 or9 data+ 1 clk+ 1 (Clk× 4/4)/N;maximum 192.31MSPS total(forall sync channels) 1N Nibblemode, 1 interfacerate 6 = 4 data+ 1 clk+ 1 sync (Clk× 4/8)/N;maximum 125 (Nibble0),96.15(Nibble 1)MSPS total 1S Serialmode, 1 interfacerate 4 = 2 data+ 1 clk+ 1 sync (Clk× 4/16)/N;maximum 48.07MSPS total 2N Nibblemode, 2 interfacerates 12 = 4 data+ 1 clk+ 1 sync+ 4 (Clk× 4/8)/N× 2;maximum 221.15MSPS total data+ 1 clk+ 1 sync 2N ’(1) Nibble+ bytemode, 2 interface 16 = 4 data+ 1 clk+ 1 sync+ 8 Nibbleport:(Clk× 4/8)/N;maximum 125 MSPS total rates, data+ 1 clk+ 1 sync Byteport:(Clk× 2/4)/N;maximum 125,250 MSPS RX-ADC inputpinsused for total byte-modeport. 2S Serialmode, 2 interfacerates 8 = 2 data+ 1 clk+ 1 sync+ 2 data (Clk× 4/16)/N;maximum 96.15MSPS total + 1 clk+ 1 sync 3S Serialmode, 3 interfacerates 12 = 2 data+ 1 clk+1sync+ 2 data (Clk× 4/16)/N;maximum 144.23MSPS total + 1 clk+ 1 sync+ 2 data+ 1 clk+ 1 sync (1) 2N ’ istheonlyconfigurationthatallowsa specialmode tore-useRX inputportA as baseband TX inputs Table3.TX BB Pin Assignments LVDS PAIR BBI[11:0] BYTE MODE NIBBLE MODE SERIAL MODE BBIN[0]pos.and neg. BB0_DATA_0 BB0_DATA_0 BB0_DATA_0 BBIN[1]pos.and neg. BB0_DATA_1 BB0_DATA_1 BB0_DATA_1 BBIN[2]pos.and neg. BB0_DATA_2 BB0_SYNC BB0_SYNC BBIN[3]pos.and neg. Spare BB0_CLOCK BB0_CLOCK BBIN[4]pos.and neg. BB0_DATA_3 BB0_DATA_2 BB1_DATA_0 BBIN[5]pos.and neg. BB0_DATA_4 BB0_DATA_3 BB1_DATA_1 BBIN[6]pos.and neg. BB0_SYNC BB1_SYNC BB1_SYNC BBIN[7]pos.and neg. BB0_CLOCK BB1_CLOCK BB1_CLOCK BBIN[8]pos.and neg. BB0_DATA_5 BB1_DATA_0 BB2_DATA_0 BBIN[9]pos.and neg. BB0_DATA_6 BB1_DATA_1 BB2_DATA_1 BBIN[10]pos.and neg. BB0_DATA_7 BB1_DATA_2 BB2_SYNC BBIN[11]pos.and neg. BB0_DATA_8 BB1_DATA_3 BB2_CLOCK Number ofBBdata streams 1 2 3 Number ofDDR clockstotransfer1 complexsample 2 4 8 The actualdatatransferrateinnibblemode is2 timeshigherthanthebytemode forthesame totalthroughput.If two portsarerequired(e.g.,tosupporttwo differentsample rates),and a lowerspeed on theinterfaceisdesired, theGC533x can re-usetheRX ADC inputportA as a baseband TX inputbus.RX ADC portA has 15 pairsof LVDS inputpinsand supportsone setof baseband inputdata inbytemode. When RX portA isused as a baseband TX input,itcannotbe alsoused as an RX inputport. The baseband interfacesupportsa full-clockorgated-clockformat.These formatsareshown inFigure11 The mapping fortheRX portA pinswhen inBB TX inputmode is:

• RXA14: clock
• RXA13: sync
• RXA12 –5:BB0_DATA7 –0

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Q0-EQn-E 00 I0-EIn-EQ1-EQ0-E I1-EI0-E Q0-OQn-O I0-OIn-OQ1-OQ0-O I1-OI0-O In-D Qn-A 00Qn-CIn-BQ0-DI0-D Q0-BI0-B Qn-D I0-AIn-C Qn-BIn-AQ0-CI0-C Q0-AI0-A ‘n’ can be up to 47, ‘A’ is 4 MSBs, ‘B’ is next 4 bits, ‘C’ is next 4 bits and ‘D’ is 4 LSBs BBIN Data 0 BBIN Data 0 BBIN Data 1 BBIN C k 0l BBIN Clk 0 BBIN Clk 1 BBIN Sync 0 BBIN Sync 0 BBIN Sync 1 Mode 1B T0504-01 Mode 1N (1 Rate) Mode 2N (2 Rates) In-D Qn-A 00Qn-CIn-BQ0-DI0-D Q0-BI0-B Qn-D I0-AIn-C Qn-BIn-AQ0-CI0-C Q0-AI0-A Qn-D Qn-E 00Qn-GQn-BI0-HI0-D I0-FI0-B Qn-H I0-AQn-C Qn-FQn-AI0-GI0-C I0-EI0-A ‘n’ can be up to 47, ‘A’ is 2 MSBs, ‘B’ is next 2 bits, ‘C’ is next 2 bits, ... and ‘H’ is 2 LSBs BBIN Data 0 BBIN Data 1 BBIN Data 2 BBIN Clk 0 BBIN Clk 1 BBIN Clk 2 BBIN Sync 0 BBIN Sync 1 BBIN Sync 2 Mode 1S (1 Rate) Mode 2S (2 Rates) Mode 3S (3 Rates) Qn-D Qn-D Qn-E Qn-E Qn-G Qn-G Qn-B Qn-B I0-H I0-H I0-D I0-D I0-F I0-F I0-B I0-B Qn-H Qn-H I0-A I0-A Qn-C Qn-C Qn-F Qn-F Qn-A Qn-A I0-G I0-G I0-C I0-C I0-E I0-E I0-A I0-A GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Figure11. TX BB Formats The TX formatterblockincludesa per-channelTX gainadjustviaa 16-bitcomplex digitalword whichcan be set tohave gainbetween –∞ and 9 dB. DigitalDown- and Upconverters(DDUCs) The GC533x has fouridenticaland independentDDUC blocksthatcan be configuredas eitherDDC or DUC. Each DDUC can supportup to12 channelswithscalablebandwidth. The onlydifferencebetween theDUC and DDC configurationsistheinterpolate(DUC) versusdecimate(DDC) functionsand thedatapathdirectionas shown inFigure12.Both DDC and DUC are describedinthissection. Note thateach DDUC block must be configuredstaticallyas a DUC or DDC and cannot switchmodes dynamicallyinTDD applications. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):GC5330 GC5337

1 , 2/c180 /c180 FIR 1 , 2/c180 /c180 Farrow 10241– /c180 Farrow 10241– /c180 1–12 Channel DUC Block 1–12 Channel DDC Block DUC Configuration DDC Configuration All 3 Blocks Interpolate All 3 Blocks Decimate CIC 1–3 /c180 CIC 1–3 /c180 X X NCO NCO B0448-01 Mixer Mixer GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Figure12. DUC and DDC FunctionalBlock Diagram Incombinationwiththefollow-onmux and sum block,theDUC blockinterpolates,filters,mixes each carrier,and combines multiplechannelsintoone tofourwideband,compositeTX signalstreams.Any inputchannelcan be mapped toany TX streaminthemux and sum block. The DDC configurationacceptsan RX streamfromthedistributorblockand providesmixing,decimationfiltering, fractionalresampling,and filteringtoRX channels.The RX blockoutputsare mapped tothemixerCIC stream viathedistributorblock. Each DDUC block containsa finiteimpulse response (FIR)filter,a fractionalresampler(Farrow filter),a cascadedintegrator-comb(CIC)filter,a complexmixerand NCO forchannelplacementinthecompositestream, and a programmablefrequencyhopper(seeFigure12). The number oftapsavailableintheFIR filterdepends on variousparameterssuch as theBBclk rate(derived from DPDCLK) , inputsample rate,interpolateand decimatesettings,and number of channels.Differenttap valuesmay be used foreach channel(however,thatreducesthenumber offiltertapsavailable). Note thattheinputsample rateistheinputfrom theTX BB inputformatterfortheDUC configurationand the inputfrom the distributorblockforDDC configuration.The number of tapsforvariouswirelessstandardsand configurationsisshown inTable4. The Farrowfiltersupportsone realchannelor1–12 complex channelsand can be configuredforany resampling ratiofrom1 to1024 with32-bitresolution.A differentdelayvalueforeach channelissupported.The Farrowfilter isused toresampledifferentTX BB inputsample ratestoa common CFR and DPD sample rate,and itprovides 95-dB rejectionat±0.25outputfS (samplerate),83-dB rejectionat±0.375outputfS,and 56-dB rejectionat±0.4 outputfS. The CIC interpolatesordecimatesby a factorof1,2,or3.Ifeach DDUC must supportmore thaneightcarriers, theCIC must interpolate/decimateby 3.Ifeach DDUC must supportbetween fourand eightcarriers,theCIC can interpolate/decimateby 2 or3.Ifeach DDUC must supportfewerthanfourcarriers,theCIC can interpolateby 1, 2,or3.

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 The NCO containsa 48-bitfrequencyword and 48-bitaccumulator,and operatesattheDUC outputsample rate. The minimum resolutionistheDUC outputsample rateor DDC inputsample ratedividedby 248,or about0.2 μHz fora 61.44-MSPS DUC outputrate.The mixer and NCO can be used forfrequencyplanningor fine frequencycontrol. Per-channelphase can be adjustedin the mixer/NCO blockwitha 16-bitphase word, whileper channel fractionaldelaycan be adjustedintheFarrowblock. Table4.Number ofFIR FilterTaps forExample SignalTypes Input DUC Mode DDC ModeBBclk Sample FilterType Interp. Decim. No. ofRateName Max. TapsChannels Sym orMHz MSPS 1 or 2 1 or 2Un-Sym lte20_1 245.76 30.72 S 1 1 1 159 lte20_2 245.76 30.72 S 1 1 2 79 lte10_2 245.76 15.36 S 1 1 2 159 lte10_3 245.76 15.36 S 1 1 3 99 lte10_4 245.76 15.36 S 1 1 4 79 lte5_4 245.76 7.68 S 1 1 4 159 lte5_8 245.76 7.68 S 1 1 8 79 wimax20_r3 246.4 44.8 S 1 2 3 59 wimax20_t3 246.4 22.4 S 2 1 3 39 wimax20_r2 246.4 44.8 S 1 2 2 99 wimax20_t2 246.4 22.4 S 2 1 2 79 wimax20_r1 246.4 44.8 S 1 2 1 219 wimax20_t1 246.4 22.4 S 2 1 1 199 wimax10_r2 246.4 22.4 S 1 2 2 219 wimax10_t2 246.4 11.2 S 2 1 2 199 wimax10_r3 246.4 22.4 S 1 2 3 139 wimax10_t3 246.4 11.2 S 2 1 3 119 wimax10_r4 246.4 22.4 S 1 2 4 99 wimax10_t4 246.4 11.2 S 2 1 4 79 wimax5_r4 246.4 11.2 S 1 2 4 219 wimax5_t4 246.4 5.6 S 2 1 4 199 wimax5_r8 246.4 11.2 S 1 2 8 99 wimax5_t8 246.4 5.6 S 2 1 8 79 wbcdma_r4 245.76 7.68 S 1 1 4 159 wbcdma_t4 245.76 3.84 S 2 1 4 319 wbcdma_r8 245.76 7.68 S 1 1 8 79 wbcdma_t8 245.76 3.84 S 2 1 8 159 cdma_r12 245.76 2.4576 S 1 1 12 99 cdma_t12 245.76 1.2288 U 2 1 12 100 tdscdma_r12 245.76 2.56 S 1 1 12 99 tdscdma_t12 245.76 1.28 S 2 1 12 199 gsm_12 243.8 0.5417 S 1 1 12 99 eedge_12 243.8 1.625 S 1 1 12 99 wideband_60MHz_r 250 75 S 1 1 1 59 wideband_60MHz_t 250 75 S 2 1 1 39 © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com MUX and SUM (TX Direction) The MUX and SUM blockmaps any channel from the DUC to any TX stream forsubsequent per-stream processing. CrestFactorReduction (CFR) The CFR blocksincludetheCFR functionand two interpolate-by-2filters(referredtohere as UC1 and UC2). The two CFR blockstogethercan support1, 2, or 4 TX streams.The CFR functionselectivelyreducesthe peak-to-averageratio(PAR) ofwideband digitalsignalsprovidedinquadrature(Iand Q) format,such as those used in3G and 4G wirelessapplications.For example,theCFR functioncan reducethePAR ofWCDMA Test Model 1 signalsto5.7dB, whilestillmeetingall3GPP requirementsforACLR, compositeEVM, and peak code domain error(PCDE). The CFR blockscan be configuredinelevendifferentmodes, dependingon thenumber ofTX streams,theDPD mode, and the signalsample rates.Relativeto previousTI CFR products,the GC533x CFR has enhanced featuressuch as:

• ConstantPAR mode
• Constantinput-to-outputpower mode
• Dynamic PAR targetlevelsfordifferentportionsofthetime-domainsignal
• Up to25% lesslatencyforcertainconfigurations
• Enhanced CFR performancefornarrowbandsignals
• Automatic(i.e.,no hostinteractionrequired)CFR coefficientgenerationforfrequency-hoppingsignals The UC1 and UC2 blockscan be setto1× or2× interpolationand may be used toprovideoptimum selectionof signaloversamplingratioatCFR. UC1 may be positionedbeforeoraftertheCFR function,whileUC2 isalways at the outputof CFR. Since UC2 has onlya 40% bandwidthimage rejection(90 dB) filter,itisonlyused if precededby UC1, whichhas an 80% bandwidthimage-rejection(90dB) filter. DigitalPredistortion(DPD) The DPD blocksincludethe DPD function,TX equalization,and the envelope tracking(ET) function.The GC533x supportstwo modes ofoperation,dependingon signalbandwidthand desiredDPD correctioncapability: high-performance(HP) mode and high-bandwidth(HB) mode. For 5× DPD expansionbandwidth(fifth-orderDPD correction),thefollowingsignalbandwidthsand number ofstreamscan be supported. High-performanceDPD mode

1 TX streamat62 {74}MHz

2 TX streamsat31 {37}MHz each

4 TX streamsat15.5{18.5}MHz each This mode providesmore extensivenonlinearcorrectionor longerDPD memory and is suitableforthe most-difficultand high-performanceDPD requirements. High-bandwidthDPD mode

2 TX streamsat62 {74}MHz each

4 TX streamsat31 {37}MHz each

Thismode providesexcellentDPD correctionformost DPD requirements. The TX equalizerisa complex equalizerand isconfigurablefrom17 to34 taps,dependingon theDPD mode of operation.InHP modes, thenumber oftapsmay be up to34.InHB modes, thenumber oftapsmay be up to17. ContacttheTIfactoryforadditionaldetails. The predistortioncorrectiontermsare computed by an externalprocessor(e.g.,TI TMS320C6748 DSP) based on reference-inputand PA-feedbackdatacapturedintheGC533x capturebuffers.The externalprocessorreads the captureddata buffersfrom the GC533x and writesback the newly computed DPD correctionterms on a continuousbasis.

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 DPD – Envelope Tracking(ET)Mode The ET blockprovidesa 10-,12-,or14-bitrealdigitalword,ata rateup to155 MSPS, thatisproportionaltothe peak envelopesignalofthecompositeTX streameitherbeforeoraftertheDPD function.The ET blockincludes fixedand fractionaldelayadjustmentsand a LUT toprovidenonlinearshapingtotheET waveform.The GC533x can provideone or two ET outputsalongwiththecorrespondingone or two TX signalstreamoutputs.The ET outputsuse one oftheLVDS DAC portsand have two interfaceformatmodes: a. One or two antenna streams.One antenna stream per port,withinterleavedMSB half-wordand LSB half-word.The portcan be configuredas 7-,6-,or5-bitDDR data(seeTable14 and Figure18),plusclock (maximum clockrateof155 MHz inthismode).Inallthreecases,the16-bitinternaldataisroundedtothe specified14,12,or10 bits.Formaton theDDR dataportforthethreecasesis: 14-bit:[13:7],then[6:0] 12-bit:[11:6],then[5:0] 10-bit:[9:5],then[4:0] b. One antennastreamonly.One antennastreamper port.The portcan be configuredas 14-,12-,or 10-bit SDR data(seeFigure18),plusclock(maximum clockrateof155 MHz inthismode).Inallthreecases,the 16-bitinternaldataisroundedtothespecified14,12,or10 bits. Note thatclockoutmay have a few hundredps ofjitterand isnotsuitablefordirectlydrivingtheET modulator DAC. The clockfortheET modulatorDAC shouldcome directlyfroma TICDC clockchip,whichisalreadyon theboardtoprovideclocksources. TX IFSub-Chip The TX IF sub-chipincludesa bulkupconverter(BUC), fourIF mixer/NCO blocks,and TX stream MUX and SUM. The BUC blockhas interpolationsof 1×, 1.5×, 2×, 3×, and 4×. In the DPD high-bandwidthmode, the 2× interpolationfromtheBUC isroutedtotheDPD input.Inthehigh-bandwidthmode, BUC interpolationisnotused afterDPD. IntheDPD high-performancemode, BUC interpolationisdependenton theconfiguration. There arefourparallelNCO/MIX blockstoallowfrequencytranslationofeach compositeTX stream.The NCO is 48 bitsand isreferencedto the TX outputrate.The NCO/MIX blockcan be used ineitherHP or HB modes; however,usingthemixerreducestheDPD expansionbandwidthby theamount offrequencytranslation. The TX streamMUX and SUM blockallowssumming ofTX streamstocreatecompositeTX streams. TX DAC Formatter The DAC outputconsistsof two 20-pairLVDS blocksthatcan be configuredby the DAC formatterblockfor severalTI DACs and system configurations.The formattercan supportup to 8 DACs for4 TX streams in complex mode. The DAC formatterblocksupportstheTI DAC5682, DAC328x, and DAC348x families.Table5 illustratesthepinconnectionsthedifferentDAC and envelope[ET]modulatortypes. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Table5.GC533x DAC InterfacePin Map GC533x 328x (ET) 3482 Byte 5682 3484 3482 Word TXA0 P1-d7 P1-d7 P1-sync P1-sync P1-sync TXA1 P1-d6 P1-d6 P1-d15 P1-d15 P1-d15 TXA2 P1-d5 P1-d5 P1-d14 P1-d14 P1-d14 TXA3 P1-d4 P1-d4 P1-d13 P1-d13 P1-d13 TXA4 P1-dataclk P1-dataclk P1-d12 P1-d12 P1-d12 TXA5 P1-frame P1-frame P1-d11 P1-d11 P1-d11 TXA6 P1-d3 P1-d3 P1-d10 P1-d10 P1-d10 TXA7 P1-d2 P1-d2 P1-d9 P1-d9 P1-d9 TXA8 P1-d1 P1-d1 P1-d8 P1-d8 P1-d8 TXA9 P1-d0 P1-d0 P1-dataclk P1-dataclk P1-dataclk TXA10 P2-d7 P2-d7 NA P1-frame NA TXA11 P2-d6 P2-d6 P1-d7 P1-d7 P1-d7 TXA12 P2-d5 P2-d5 P1-d6 P1-d6 P1-d6 TXA13 P2-d4 P2-d4 P1-d5 P1-d5 P1-d5 TXA14 P2-dataclk P2-dataclk P1-d4 P1-d4 P1-d4 TXA15 P2-frame P2-frame P1-d3 P1-d3 P1-d3 TXA16 P2-d3 P2-d3 P1-d2 P1-d2 P1-d2 TXA17 P2-d2 P2-d2 P1-d1 P1-d1 P1-d1 TXA18 P2-d1 P2-d1 P1-d0 P1-d0 P1-d0 TXA19 P2-d0 P2-d0 NA P1-parity P1-parity TXB0 P3-d7 P3-d7 P2- sync P2-sync P2-sync TXB1 P3-d6 P3-d6 P2-d15 P2-d15 P2-d15 TXB2 P3-d5 P3-d5 P2-d14 P2-d14 P2-d14 TXB3 P3-d4 P3-d4 P2-d13 P2-d13 P2-d13 TXB4 P3-dataclk P3-dataclk P2-d12 P2-d12 P2-d12 TXB5 P3-frame P3-frame P2-d11 P2-d11 P2-d11 TXB6 P3-d3 P3-d3 P2-d10 P2-d10 P2-d10 TXB7 P3-d2 P3-d2 P2-d9 P2-d9 P2-d9 TXB8 P3-d1 P3-d1 P2-d8 P2-d8 P2-d8 TXB9 P3-d0 P3-d0 P2-dataclk P2-dataclk P2-dataclk TXB10 P4-d7 P4-d7 NA P2-frame NA TXB11 P4-d6 P4-d6 P2-d7 P2-d7 P2-d7 TXB12 P4-d5 P4-d5 P2-d6 P2-d6 P2-d6 TXB13 P4-d4 P4-d4 P2-d5 P2-d5 P2-d5 TXB14 P4-dataclk P4-dataclk P2-d4 P2-d4 P2-d4 TXB15 P4-frame P4-frame P2-d3 P2-d3 P2-d3 TXB16 P4-d3 P4-d3 P2-d2 P2-d2 P2-d2 TXB17 P4-d2 P4-d2 P2-d1 P2-d1 P2-d1 TXB18 P4-d1 P4-d1 P2-d0 P2-d0 P2-d0 TXB19 P4-d0 P4-d0 NA P2-parity P2-parity Note:P1,P2,P3,and P4 areused toidentifya specificDAC port.Differentportshave differenttiming.

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 RX ADC Formatter There are threeADC inputports:two 15-pairLVDS ports(referredtoas portsA and B) and one 8-pairLVDS port(referredto as portC and typicallyused forthe DPD feedbackpath).Depending on the ADCs selected, thesethreeportscan accommodate up to17 ADCs (e.g.,usingtwo octalsand a single).The formatterblockcan routeany porttoeitherthecapturebufferblockortheRX signalprocessingblocks.The pinconnectionsforthe ADCs areshown inTable6. The GC533x worksseamlesslywiththefollowingTIADCs. Single:5400,12-bit,1 GSPS, may need specialroutingon thePCB. 5463,12-bit,500 MSPS, may need clock-to-data-skewspecialroutingon thePCB. 54RF63, 12-bit,550 MSPS, may need clock-to-data-skewspecialroutingon thePCB. 5474,14-bit,400 MSPS, may need clockclock-to-data-skewspecialroutingon thePCB. 5493,16-bit,130 MSPS 548x,16-bit,80-200MSPS 612x,12-bit,65–250 MSPS 614x,14-bit,65-250MSPS 58B18,11-bit,200 MSPS 414x,14-bit,160–250 MSPS 412x,12-bit,160–250 MSPS 552x,12-bit,170–210 MSPS 554x,14-bit,170–210 MSPS 5517,11-bit,200 MSPS Dual: 62c15,11-bit,125 MSPS 62c17,11-bit,200 MSPS 58c28,11-bit,200 MSPS 62p4x,14-bit,65-250MSPS 62p2x,12-bit,65-250MSPS 624x,14-bit,65-125MSPS 622x,12-bit,65-125MSPS Quad: 642x,12-bit,65–125 MSPS 644x,14-bit,65–125 MSPS Octal: 527x,12-bit,65 MSPS 528x,12-bit,65 MSPS © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Table6.GC533x ADC InterfacePin Map 58c48 42x958b18 5517GC533x 64p4x 5463 54444149 61B49 548x 6145 5400L 5400R 642x 644x 527x 528x Two 624xPin Name 62p4x 54745547 62c15 RXA0 0 0 0 12 syncout [istrobe] RXA1 2 2 1 11 0 RXA2 4 4 2 10 1 d1 b1 RXA3 6 0 6 3 9 2 d0 b0 RXA4 8 2 8 4 8 3 c1 f RXA5 10 4 10 5 7 4 c0 c0 a1 RXA6 12 6 12 6 6 5 frame c1 a0 RXA7 clk clk clk 7 clk clk clk clk clk RXA8 [14] 8 0 8 5 6 b1 c2 RXA9 10 2 9 4 7 b0 c3 b1 RXA10 12 4 10 3 8 a1 c4 b0 RXA11 14 6 11 2 9 a0 c5 f RXA12 8 12 1 10 c6 a1 RXA13 10 13 0 11 c7 a0 RXA14 [istrobe] [istrobe] 12 clk syncout [12] fr clk RXB0 0 0 0 [12] syncout RXB1 2 2 1 11 0 RXB2 4 4 2 10 1 RXB3 6 0 6 3 9 2 RXB4 8 2 8 4 8 3 RXB5 10 4 10 5 7 4 RXB6 12 6 12 6 6 5 RXB7 clk clk clk 7 clk clk RXB8 [14] 8 0 8 5 6 RXB9 10 2 9 4 7 RXB10 12 4 10 3 8 RXB11 14 6 11 2 9 RXB12 8 12 1 10 RXB13 10 13 0 11 RXB14 [istrobe] [istrobe] 12 clk syncout [12] RXC0 0 RXC1 2 RXC2 4 RXC3 6 RXC4 8 RXC5 10 RXC6 12 RXC7 clk (1) []indicatesassignmentifpinsavailable Feedback Processing The feedbackpathisinputtoRXC as a realADC. Thisiscapturedinthecapturebufferand senttotheDSP. In cases where a higher-raterealADC (>250 Msps) or a complex feedbackpath isdesired,forbetterfeedback performance,one oftheRX ADC inputscan be used forthefeedbackpath,and one RX ADC inputisused for theRX path.Note:bothRX downconverterscan stillbe used fortheRX path,orone can be used forfeedback.

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 The widest-bandfeedbackisseen directlyfromtheADC interfacetothecapturebuffer.FurtherRX processingto getthecomplexdatatothecapturebufferrequiresthatthecomplexrateisone-halftheDPD clockrateorlower. RX Sub-Chips Each of two RX sub-chipsconsistsof the followingblocks(each blockmay be optionallybypassed),which operateon a per-streambasis:

• DC offsetcancellation
• Front-endautomaticgaincontrol(feAGC)
• Real-to-Complex(R2C) conversion
• Switchforreplicatingormoving streamsacrossthefourpaths(persub-chip)
• IFNCO forcomplexmixing(frequencytranslation)
• Bulkdownconverter(BDC)
• Equalizer
• IQ imbalancecorrection DC offsetcancellation The dc offsetcancellercan be programmed tointegratea number ofinputsamples automatically,divideby a power of 2, and subtractthe mean offsetor a programmed offsetfrom the input.The inputcan be realor complex.Each inputADC has a separatecancellationforeach RX blockchannel. Front-endAGC The feAGC blockisused tocontroltheRX ADC inputlevelby controllingan externalDVGA. The feAGC has multiplechannelsineach RX block:
• 1 realstreamup to4 × DPD clockrate(onlyuse one block)
• 2 real(usingbothblocks)or1 complexstream(onlyuse one block)up to2 × DPD clockrateeach
• 4 realor2 complexstreamsup toDPD clockrateeach (usesbothblocks)
• 8 realor4 complexstreamsup to1/2DPD clockrateeach (usesbothblocks) The feAGC has both thresholdcomparisonand an integratedpower measurement. The feAGC has an error accumulation.The erroraccumulationcan be mapped to a specificADC desiredoperatingpoint.The integral controlleroutputstheDVGA valuetocontroltheADC input.DVGA controlsare mapped tothespecificDVGA outputs,supportingmultipleDVGA types.Multipliersinthe data path can be used to compensate forexternal DVGA gainchanges (fromthefeAGC outputcontrolword).A delayblockalignsthegainvalueappliedtothe internalmultiplierwiththepointintimeon thedatasamples where theexternalgainchange was applied.Use of thismultiplierminimizesgain stepsthatwould cause transientsin the downstream digitalfiltersand allows relativepower measurements on thedigitalsignals. The AGC operationmay be suspended duringcertainconditions.The internalcontrolled-delayAGC updateand specialclockgatingcan be used tosuspend theAGC operation. The controlword outputsfrom thefeAGC blocksare appliedtoexternalDVGA partsviatheDVGA pins.There are16 DVGA pins(3.3-VCMOS) whichmay be individuallyconfiguredas DVGA outputsignalsorGPIO (inputor output)signals.When used as DVGA controlsignals,therearetwo modes:
• Transparentmode – paralleloutputwords are connecteddirectlytoDVGAs thatare beingused ina mode withouta clockorlatchsignaltoclock-inthegainword.Thisistheminimum latencymode. There can be two portsof8 bitseach,threeportsof5 bitseach,fourportsof4 bitseach,orfiveportsof3 bitseach.
• Clocked mode – eightlatchenable(LE)signalsand one 8-bitoutputword.Thismode allowsup to eight controlsignals,up to8 bitseach,butwithincreasedlatency.The LE signalmay be a positiveor negative pulse,withprogrammablewidth. R2C Inthereal-to-complexconversionblock,realsignalinputsareup-ordownconvertedby fS/4,filteredtoisolatethe selectedsideband,and decimatedby a factorof2.Real-to-complexconversionisbypassedforcomplexinputs. The rejectionoftheR2C decimationfilteris:
• For90% bandwidthsignal,–68 dB,stopband
• For80% bandwidthsignal,–106 dB,stopband © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Switch Any oftheup toeightcomplex RX antenna/signalinputsacrossbothsub-chipsmay be switchedtoone ormore oftheup to4 outputstreamsofeach sub-chip. IFNCO The NCO/mixer blockgeneratesin-phaseand quadraturesinusoidalsignals(cos/sin)and mixes them withthe switchedantennastreamstofrequency-translatetheRX signals.The NCO containsa 48-bitfrequencyword and 48-bitaccumulator. BDC The BDC supportsthefollowingmodes and sample ratesatitsinput(acrossbothsub-chips):

• Single– 4 × DPD clockratereal,2× DPD clockratecomplex
• Dual– 2 × DPD clockratereal,DPD clockratecomplex
• Quad – DPD clockratereal,1/2DPD clockratecomplex
• Octal– 1/2DPD clockratereal Totaldecimationfactorsmay be 1,2,4,8,or 16.The decimationfilteringisachievedwiththecascade ofthe real-to-complexfilter(R2C),a fixedfilterF1,and a fixedfilterF2.The rejectionoftheF1 and F2 filtersis:
• FilterF1 (decimateby 1 or2) – Ifused,alwaysfollowedby filterF2,so relaxedrequirements – 45% bandwidth,–107 dB stopband
• FilterF2 – Recirculated1–3 timestoprovide2,4,or8× decimationfactor – 90% bandwidth,–75 dB,stopband – 80% bandwidth,–106 dB,stopband Equalizer The receiveequalizerisfull-complex16-tapfilterthatperformsthefollowingsignal-processingfunctions:
• Programmable spectralinversionattheinput
• Equalizationofanalogsignalpaths
• Channelequalizationforrepeaterapplications
• Gain/phase/fractionaldelayadjust(MIMO/smartantennasupport)
• Fixeddc offsetcompensationattheoutput Independentcomplex coefficientsfor realand imaginarysignaldata allow fullflexibilityfor independent equalizationofthedirect-and cross-IQsignalcomponents,as wellas frequency-dependentIQ gainand phase imbalancecompensation.The programmable16-bitcoefficientsets(i.e.,C ii,C qq,C iqand C qi,foreach tap)can be updatedon thefly. IQ imbalance correction AutomaticcorrectionofIQ imbalanceisprovidedwitha 1-tapblindadaptivealgorithm.The correctioncoefficients alsomay be programmed to fixedvalues.Thisblocksupportsprogrammable integrationintervalsand flexible gatingofloopoperation. RX Distributor The outputsfromtheRX sub-chipsareroutedtotheRX distributorblock,whichenablesarbitraryassignmentof RX streamstoDDC channelsand blocks. RX Baseband Output Formatter The RX baseband (BB)outputformatterblockacceptsdatafromtheDDC and formatsthedataforoutputon the BB LVDS pins.A back-endAGC (beAGC) functionisincludedthatoptionallyadjuststhegainofeach channel and providesmultipleformatoptions.Thereare12 unidirectionalLVDS pairsfortheRX BB interface.

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Back-end AGC The beAGC functionisavailableforreceivechannelsfromDDUC3 and DDUC2 (DDUC1 and DDUC0 may also be used forreceive—withthe formatsas describedfollowing—but withoutthe beAGC function).When the floating-pointformatisselected(describedfollowing),the beAGC isnot used.For the fixed-pointformats,the beAGC may be on or off.There are separatebeAGC blocksassociatedwithDDUC3 and DDUC2, and each blockcan processup to 12 channels.Withina block,thereare two setsof controlparameters.Thisprovides support for two differentsignaltypes sharing the same DDUC block.Each channel may have a programmable-gainstartingpointor a fixedgain,and thereisa per-channelflexiblegatingsignalto control freeze/operateintervalsforTDD signaltypes.The beAGC has approximatelya 100 dB dynamic range.The beAGC algorithmadjuststhegaintodrivethemedian magnitudeofgain-loopoutputdatatoa targetthreshold value.There are fourstep-sizesused (twoforabove and two forbelow thethreshold),dependingon distance fromthethresholdvalue. Output formatter Therearethreeoperationalmodes fortheRX BB outputformatter:bytemode (B,9 bits),nibblemode (N,4 bits), and serialmode (S,2 bits).The nibbleand serialmodes allowmultipleBB outputratesand theuse offewerpins on the interface.The GC533x can provideup to threedifferentBB outputdata rates.Table 7 and Table 8 summarize thedifferentmodes and pinassignmentsforthebyte,nibble,and serialmodes. As can be seen in Table8,therearetwo dataformatssupported:

• Floatingpoint(indicatedwithan F inthemode label;14-or16-bitmantissa,4-bitexponent)
• Fixedpointwithoutgainword (16-or18-bitoptions) In Table 8, BBOUT[X] isthe BBOUT differentialpair(assumed positiveand negativeconnections),and BB0, BB1, and BB2 representthreedifferentRX differentialbaseband inputsignalsthatcan be atarbitraryrates. Figure13 shows the BB outputformats.The maximum-data-rateconfigurationshave the DDR clockout transitioningsynchronouslywiththedata(referredtoas DDR Mode 0 inthetable).At halfthemaximum possible datarate(referredtoas DDR Mode 1 inthetable)and a quarterofthemaximum possibledatarate(referredto as DDR Mode 2 inthetable),theDDR clockouttransitionsinthemiddleofthedata-steadytime. Table7.RX BB FormatterModes TotalNumber ofInterface Maximum Complex InterfaceRate per ChannelMODE Description Pins N isthenumber ofchannels 1B 1 interfacerate(upto18 bits) 11 = 9 data+ 1 clk+ 1 sync (Clk4/4)/N/2;maximum 125 MSPS total(forallchannels) 1BF 1 interfacerate(upto16 bits)+ exponent(4 10 = 8 data+ 1 clk+ 1 sync (Clk4/4)/N/2;maximum 125 MSPS total(forallchannels) bits) 1N 1 interfacerate(16bits) 6 = 4 data+ 1 clk+ 1 sync (Clk4/8)/N;maximum 96.15(Nibble0),125 (Nibble1)MSPS total 1NF 1 interfacerate(14bits)+ exponent(4bits) 6 = 4 data+ 1 clk+ 1 sync (Clk4/8)/N;maximum 96.15(Nibble0),125 (Nibble1)MSPS total 1S 1 interfacerate(16bits) 4 = 2 data+ 1 clk+ 1 sync (Clk4/16)/N;maximum 48.07MSPS total 1SF 1 interfacerate(14bits)+ exponent(4bits) 4 = 2 data+ 1 clk+ 1 sync (Clk4/16)/N;maximum 48.07MSPS total 2N 2 interfacerates(16bits) 12 = 4 data+ 1 clk+ 1 sync+ (Clk4/8)/N;maximum 221.15MSPS total 4 data+ 1 clk+ 1 sync 2NF 2 interfacerates(14bits)+ exponent(4bits) 12 = 4 data+ 1 clk+ 1 sync+ (Clk4/8)/N;maximum 221.15MSPS total 4 data+ 1 clk+ 1 sync 2S 2 interfacerates(16bits) 8 = 2 data+ 1 clk+ 1 sync+ (Clk4/16)/N;maximum 96.15MSPS total 2 data+ 1 clk+ 1 sync 2SF 2 interfacerates(14bits)+exponent(4bits) 8 = 2 data+ 1 clk+ 1 sync+ (Clk4/16)/N;maximum 96.15MSPS total 2 data+ 1 clk+ 1 sync 3S 3 interfacerates(16bits) 12 = 2 data+ 1 clk+ 1 sync+ (Clk4/16)/N;maximum 144.23MSPS total 2 data+ 1 clk+ 1 sync+ 2 data+ 1 clk+ 1 sync 3SF 3 interfacerates(14bits)+exponent(4bits) 12 = 2 data+ 1 clk+ 1 sync+ (Clk4/16)/N;maximum 144.23MSPS total 2 data+ 1 clk+ 1 sync+ 2 data+ 1 clk+ 1sync © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):GC5330 GC5337

‘n’ can be up to 47, ‘A’ is 4 MSBs, ‘B’ is next 4 bits, ‘C’ is next 4 bits and ‘D’ is 4 LSBs BB Data 0OUT BB Data 0OUT BB Data 0OUT BBOUT Clk 0 (if DDR Mode 0) BB Clk 0 (if DDR Mode 0) OUT BBOUT Clk 0 (if DDR Mode 0) OUT BB Clk 0 (if DDR Mode 1 or 2) OUT BB Clk 0 (if DDR Mode 1 or 2) OUT BB Clk 0 (if DDR Mode 1 or 2) OUT BB Sync 0OUT BB Sync 0OUT BB Sync 0OUT T0505-01 Mode 1B 18 bit I/Q Data 9I, 9I, 9Q, 9Q Mode 1BF 16 bit I/Q Data + 4 bits gain 8I +1G, 8I + 1G, 8Q + 1G, 8Q + 1G Modes 1N, 2N 16 bit I/Q Data 4I, 4I, 4I, 4I, 4Q, 4Q, 4Q, 4Q Modes 1NF, 2NF 14 bit I/Q Data + 4 bits gain 4I, 4I, 4I, 2I +2Q, 4Q, 4Q, 4Q, 4G Modes 1S, 2S, 3S 16 bit I/Q Data 4I, 4I, 4I, 4I, 4Q, 4Q, 4Q, 4Q Modes 1SF, 2SF, 3SF 14 bit I/Q Data + 4 bits gain 4I, 4I, 4I, 2I +2Q, 4Q, 4Q, 4Q, 4G ‘n’ can be up to 47, ‘A’ is 2 MSBs, ‘B’ is next 2 bits, ‘C’ is next 2 bits, ... and ‘H’ is 2 LSBs Qn-D Qn-H Qn-H In-D Qn-D Qn-D Qn-B Qn-F Qn-F In-B Qn-B Qn-B Q0-D I0-H I0-H I0-D I0-D I0-D Q0-B I0-F I0-F I0-B I0-B I0-B Qn-C Qn-G Qn-G In-C Qn-C Qn-C Qn-A Qn-E Qn-E In-A Qn-A Qn-A Q0-C I0-G I0-G I0-C I0-C I0-C Q0-A I0-E I0-E I0-A I0-A I0-A BB Data 1OUT BB Data 1OUT BB Data 2OUT BBOUT Clk 1 (if DDR Mode 0) BB Clk 1 (if DDR Mode 0) OUT BBOUT Clk 2 (if DDR Mode 0) BB Clk 1 (if DDR Mode 1 or 2) OUT BB Clk 1 (if DDR Mode 1 or 2) OUT BB Clk 2 (if DDR Mode 1 or 2) OUT BB Sync 1OUT BB Sync 1OUT BB Sync 2OUT GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Table8.RX BB Pin Assignments LVDS PairBBI[11:0] Byte Mode NibbleMode SerialMode BBOUT[0] pos.and neg. BB0_DATA_0 BB0_DATA_0 BB0_DATA_0 BBOUT[1] pos.and neg. BB0_DATA_1 BB0_DATA_1 BB0_DATA_1 BBOUT[2] pos.and neg. BB0_DATA_2 BB0_SYNC BB0_SYNC BBOUT[3] pos.and neg. Spare BB0_CLOCK BB0_CLOCK BBOUT[4] pos.and neg. BB0_DATA_3 BB0_DATA_2 BB1_DATA_0 BBOUT[5] pos.and neg. BB0_DATA_4 BB0_DATA_3 BB1_DATA_1 BBOUT[6] pos.and neg. BB0_SYNC BB1_SYNC BB1_SYNC BBOUT[7] pos.and neg. BB0_CLOCK BB1_CLOCK BB1_CLOCK BBOUT[8] pos.and neg. BB0_DATA_5 BB1_DATA_0 BB2_DATA_0 BBOUT[9] pos.and neg. BB0_DATA_6 BB1_DATA_1 BB2_DATA_1 BBOUT[10] pos.and neg. BB0_DATA_7 BB1_DATA_2 BB2_SYNC BBOUT[11] pos.and neg. BB0_DATA_8 BB1_DATA_3 BB2_CLOCK Number ofBBdata streams 1 2 3 Number ofDDR clockstotransfer1 complexsample 2 4 8 Figure13. RX BB Formats

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Capture Buffers The GC533x has two capturebuffers,each 4096 complex words (18-bitsI,18-bitsQ) deep, which are periodicallyreadby theexternalcoefficientupdatecontroller(DSP) inordertooptimizetheDPD coefficients.The capturebufferscan be configuredtosample datasignalsatthefollowingpointsintheGC533x:

• DPD HP mode input (Referredtoas node A)
• DPD HP mode output (Node B)
• DPD HB mode input (Node C)
• DPD HB mode output (Node D)
• RX AB input (Node E)
• RX path0/1output (Node F)
• RX C (feedback)input (Node G)
• Testbus The capturebufferscan be triggeredvia an externalsync signal,througha softwaretrigger,or when the monitoredsignalexceeds theuser-configurablethresholds.The capturebufferscan be programmed tomonitor the signalstatisticscontinuouslyand only capturedata when certainrequirementsare met, as wellas to generatean interruptwhen a qualifiedbufferiscaptured.Thishelpsinselectingan optimum setofdataforthe DSP to use in optimizingthe DPD coefficients.The capturebufferscan be read by the DSP viathe MPU interface. The capturebuffersalsoallowsynchronizedmulti-chipdata capture.For a multipleantenna system thatuses more thanone GC533x, a feedbacksignaltouse inadaptingDPD coefficientsinmultipleGC533x chipscan be connectedtojustone oftheGC533x chips.The SYNCOUT signalcan be used todaisy-chain(e.g.,connecting toSYNCA on thenextchip)acrosstheGC533x chipsinthesystem.The SYNCOUT signalindicatestheend of thedatacaptureand can be used as a capturetriggerinallchips. Microprocessor(MPU) Interface The MPU interfaceisdesignedtointerfacewithexternalmemory interface(EMIF)portson TIDSPs operatingin asynchronousmode. Itconsistsofa 16-bitbidirectionaldatabus,an 8-bitaddressbus,and WEB, OEB, CEB, and EMIFENA controlsignals.The interfacesupportsthe TI ‘C6748 as an EMIF asynchronousinterface.The MPU interfacehas two addressspaces:a paged addressspace and an auto-incrementaddressspace. To enabletheEMIF interface,pinEMIFENA must be settologichigh. In an MPU writecycle,a GC533x internalMPUCLK signalis generatedby NORing CEB and WEB. The MPUCLK signalgoes highwhen bothCEB and WEB areassertedand goes low as soon as eitherCEB orWEB isde-asserted.The MPU data islatchedon the risingedge of the MPUCLK signal.For the auto-increment addressspaces,theauto-incrementaddressincrementson thefallingedge oftheMPUCLK signal. Inan MPU readcycle,a GC533x internalMPUCLK signalisgeneratedby NORing CEB and OEB. The MPUCLK signalgoes high when both CEB and OEB are assertedand goes low as soon as eitherCEB or OEB is de-asserted.The MPU readbackdata isavailablesoon afterthe risingedge of the MPUCLK signal.For the auto-incrementaddress spaces,the auto-incrementaddress incrementson the failingedge of the MPUCLK signal. Figure14 shows the MPU interfacetimingdiagram.The timingspecificationsare providedin Table 26 and Table27. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):GC5330 GC5337

Read□Cycle T0506-01 Write□Cycle GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Figure14. MPU InterfaceFormat SerialPeripheralInterface(SPI) The MPU and SPI interfacescan be onlyenabledone ata time.EMIFENA must be settologiclow toenablethe SPI interface.A three-orfour-wireSPI interfaceissupportedintheGC533x. ItconsistsofSPIDENB, SPICLK , SPIDIO,and SPIDO-(SPARE) (outputinfour-wiremode) signals.See Table25 and Figure25. JTAG Interface The GC533x includesa five-pinJTAG interfacethatsupportsboundary scan forallCMOS pads inthe chip, asidefromtheTESTMOD pin.The BBIN, BBOUT, RX, TX, and SYNC pinsareallLVDS and do notgetJTAG boundary scan.IMPORTANT NOTE: ifnot usingJTAG, the TRSTB signalshouldbe grounded (orpulledto groundthroughR ≤ 1 kΩ);otherwise,theJTAG portmay takecontrolofthepins.See Table24 and Figure24. A BSDL fileisavailableon theGC533x Web page. Inputand Output Syncs The GC533x featurestwo LVDS inputsyncs (SYNCA and SYNCB) and one LVDS output(SYNCOUT) user-programmablesync.These are typicallyused as trigger/synchronizationmechanisms to activatefeatures withinthedevice.The inputsyncscan be used totriggereventssuch as:

• Power measurements
• DUC channeldelay,mixerphase and dither
• Initializing/loadingfiltercoefficients
• Capturingand sourcingofdatainthecapturebuffers
• ControllinggatingintervalsforAGC and otheradaptiveloops
• FrequencyNCO changes,orhoppingsynchronization The SYNCA signalis used for device startup.The SYNCB signalcan be used for shared feedback synchronizationbetween multipleGC533x devices.The sync signalisactive-high.The width(number ofpositive edges of the DPD clock)of the sync signaldepends on the configuration.See the GC533x sync and MPU applicationnote to determinethe propersync duration.A typicalsync-pulsedurationisfourDPD clocks.The syncmust be periodic,and usuallystartsatthebeginningoftheTX frame. The outputsync can be programmed toreflecttriggeringofspecificeventswithintheGC533x, and isprimarily used tooutputthecapture-buffersyncoutsignal.

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Programmable Power Meters Interval-BasedPower Meter There are three interval-basedpower meters which compute magnitude-squaredsample values during programmabletimeintervalsand providethefollowingresults:

• Integratedmagnitude-squaredpower
• Peak power
• Number ofmagnitude-squaredvaluesabove a firstthreshold
• Number ofmagnitude-squaredvaluesabove a second threshold An interruptbitis set when new measurement resultsare available.For itsinput,each power meter can independentlyselectfromthesame setofinternalnode sourcesas thecapturebuffers. Running-Average Power Meter forPA Protection The running-averagepower metermonitorsup tofoursignalstreamson a singlenode,whichisselectablefrom thesame setofinternalsourcesas thecapturebuffers.For each signalstream,itmeasures running-average power and countsinstantaneouspower valuesabove a threshold(referredto as peaks).Itcan be used in conjunctionwithhardwarealarmsformonitoringpower levelsforPA protection. The running-averagepower meterhas thefollowingfeatures:
• Runningaveragemode, withprogrammableforgettingfactorexponent,u (0< u < 15) AAA y(k+1)= (1– 2-u)× y(k)+ 2-u × |x(k)|2, AAA where x(k)isthesignalsample and y(k)isthepower meteroutput. AAA Typically,one must setu = 11 toget0.5-dBaccuracy,u = 14 toget0.1-dBaccuracy.
• Peak countmode: countsthe number of power values,|x(k)|2, above a thresholdina specifiednumber of samples(window).The number ofpower values,threshold,and window areallprogrammable.
• Flexiblegatingoftheoperationinterval Alarms The output,y(k),fromtherunning-averagepower metercan be compared on an ongoingbasistoprogrammable highand low thresholds(alwayspositive).There aretwo alarms,alarm0and alarm1.Each alarmistriggered(ifit isenabled)based on theprogrammed mode: (0) Disabled (1) Averagepower alarm.The alarmistriggeredbased on thefollowingconditions: Ifalarmpolarity= 0 (seethealm_polarityregister),y(k)> high_threshold Ifalarmpolarity= 1,y(k)< low_threshold Ifalarmpolarity= 2,y(k)> high_thresholdory(k)< low_threshold (2) Peak power alarm.The alarmistriggeredbased on thefollowingconditions: Ifthecountofpower values|x(k)|2 > peak_thresholdexceedstheprogrammed number of samples,peak_samples,ina programmed window,peak_window (3) The alarmistriggeredifeither(1)or(2)occurs. Alarm checks are computed on a per-antenna-streambasis.Each antenna stream y(k)resultiscompared to per-streamprogrammablethresholds. Once an alarmhas been triggered,theoutputINTERRPT pinisassertedand theappropriate(alarm0oralarm1) alarminterruptbitissetand,foralarm1,a programmable actiontakesplace.The programmable actionisthe same forallantennastreams,butthealarmtriggeringisindependentforeach antennastream. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Programmable triggeractionsforalarm1: (0) No action (1) Reduce gainofDPD outputby programmablescalefactor(programmed with stream[n].gain_reduce),onlyifalarmcaused by y(k)> high_thresholdand alm_polarit= 0 or2. The gainreductionisappliedattheCFR input.A controlsignalfromthecapturebufferblockis used toselecttheprogrammed gainvalueforthemultiplierattheCFR input.When thehost resetsthisalarmby writingtotheappropriateregister,thecontrolsignalreturnsto0 (statethatis notselectingtheprogrammed gainvalue). GENERAL SPECIFICATIONS GeneralElectricalCharacteristics This sectiondescribesthe electricalcharacteristicsfor the CMOS interfaces(DVGA, MPU, JTAG, SPI, TESTMOD, RESETB and INTERRPT) and LVDS interfaces(BBIN,BBOUT, TXA, TXB, RXA, RXB, RXC, SYNC, DPDCLK) overrecommended operatingconditions(unlessotherwisenoted). Table9.GeneralElectricalCharacteristics,CMOS Interface PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VIL Voltageinputlow See (1) 0.8 V VIH Voltageinputhigh See (1) 2 VDDSHV V VOL Voltageoutputlow IOL = 2 mA (1) 0.5 V VOH Voltageoutputhigh IOH = –2 mA) (1) 2.4 VDDSHV V |IPU | Pullupcurrent VIN = 0 V (1) 30 100 250 µA |IPD | Pulldowncurrent VIN = VDDSHV (1) 30 100 250 µA |IIN| Leakage current VIN = 0 orVDDSHV (1)(2) 20 µA (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Forinputswithno pulluporpulldown,inputswithpullupand VIN = VDDSHV ,inputswithpulldownand VIN = 0,and bidirectionalsininput mode ineitherstate. Table10.GeneralElectricalCharacteristics,LVDS Interfaces PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VICM Inputcommon mode voltage(VP – VN )/2 See (1) 700 1500 mV |VP – VN | Inputdifferentialvoltage See (1) 150 700 mV R IN Inputdifferentialimpedance See (1) 80 92 120 Ω VCOM Outputcommon-mode voltage See (2) 1125 1200 1275 mV VOD Ouput differentialvoltage See (1) 250 500 mV (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Characteristicsaredeterminedby design. GeneralSwitchingCharacteristics The baseband interfaceTX has a singleDDR interfaceinputmode. The customerlogicand traceroutingmust meet thelistedtsu and th inputtiming.

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BBIN Data, BBIN Sync BBIN Clk tsu tsuth th T0507-01 GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Table11.GeneralSwitchingCharacteristics,TX BB LVDS Input PARAMETER TEST CONDITIONS MIN NOM MAX UNIT BASEBAND INTERFACE DDR LVDS fCLK(BB-Serial) 384 500(Nibble0)fCLK(BB-Nibble) Baseband inputclockfrequency See (1) MHz384(Nibble1) fCLK(BB-Byte) 384 fCLK(RXA) Baseband inputclockfrequency,usingRXA See (1) 250 MHz tsu(BBS0) BBIN3 Clk,BBIN1:0Data,BBIN2 Sync See (1)(2) 250 ps thi(BBS0) BBIN3 Clk,BBIN1:0Data,BBIN2 Sync See (1)(2) 200 ps tsu(BBS1) BBIN7 Clk,BBIN5:4Data,BBIN6 Sync See (1)(2) 210 ps thi(BBS1) BBIN7 Clk,BBIN5:4Data,BBIN6 Sync See (1)(2) 250 ps tsu(BBS2) BBIN11 Clk,BBIN9:8Data,BBIN10 Sync See (1)(2) 240 ps thi(BBS2) BBIN11 Clk,BBIN9:8Data,BBIN10 Sync See (1)(2) 190 ps tsu(BBN0) BBIN3 Clk,BBIN5,4,1,0Data,BBIN2 Sync See (1)(2) 250 ps th(BBN0) BBIN3 Clk,BBIN5,4,1,0Data,BBIN2 Sync See (1)(2) 220 ps tsu(BBN1) BBIN7 Clk,BBIN11:8Data,BBIN6 Sync See (1)(2) 250 ps th(BBN1) BBIN7 Clk,BBIN11:8Data,BBIN6 Sync See (1)(2) 220 ps tsu(BB) BBIN7 Clk,BBIN11:8,5:4,2:0Data,BBIN6 Sync See (1)(2) 280 ps th(BB) BBIN7 Clk,BBIN11:8,5:4,2:0Data,BBIN6 Sync See (1)(2) 250 ps (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Setupand holdtimesaremeasured fromdifferentialdatacrossingzerotodifferentialclockcrossingzero. Figure15. TX Baseband LVDS InputTiming Specifications The BB LVDS RX outputshave threedifferentoutputtimingmodes, DDR0, DDR1 and DDR2. DDR1 and DDR2 modes outputdata,and the BBclk outputiscenteredover the data.In DDR0 mode, the data and clockare edge-aligned.DifferentBBOUT pinsareused forclock,frame,and datapinsdependingon thebyte,nibble,and serialmodes. The DDR1 and DDR2 modes areshown inTable12 and Figure16.The DDR0 mode isshown in Table 13 and Figure17. Table 12 and Figure16. DDR1 mode isused upto a BBclk frequencyof 310 MHz. DDR2 mode isused uptoa BBclk frequencyof155 MHz. When thedatarateishigherthan500 MHz, BBclk above 250 MHz, theoperatingmode isDDR0. Inthismode, theclockisalignedwiththeoutputdatatransition.In DDR0 mode, thecustomermust delaytheclocktomeet thetsu and thi targetforthebaseband input.The tskw timeismeasured as therelativeskew forthedataand frametotheclockoutput.Thisisshown inFigure13 and Table17. In receive(uplink)mode, the GC5330 outputsdata usingthe LVDS pinsBBOUT. The BBOUT portmay be operatedinthreemodes, DDR0, DDR1, and DDR2. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com The lowest-rateoutputsuse DDR2 mode, where the outputclockchanges on one risingedge of the internal clockand theoutputdatachanges on thesubsequentrisingedge.InDDR2 mode, theoutputbitrate(perLVDS pair)ishalfoftheinternalclock.Middle-rateoutputsuse DDR1 mode, where theoutputclockchanges on the fallingedge of the internalclockand the outputdata changes on the risingedge of the internalclock,which resultsinan outputbitrateequaltotheinternalclockrate.Both DDR1 and DDR2 resultintheoutputclockedge occurringinthe middleof outputdata-stabletime.The DDR1 and DDR2 modes are shown inTable 12 and Figure16. The highest-rateoutputsuse DDR0 mode, where boththeoutputclockand outputdatachange withboththe risingand fallingedges of the internalclock.The DDR0 outputbitrateistwicethe internalclockrate.DDR0 resultsintheclockand datachangingatthesame time,and typicallyrequiresextratracelengthon thePC board forthe clockoutsignalto providethe requiredsetuptimeforthe receivingchip.The DDR0 mode isshown in Table13 and Figure17. Table12.GeneralSwitchingCharacteristics,RX BB LVDS Output – DDR1, DDR2 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT BASEBAND INTERFACE DDR LVDS fCLK(BB-DDR2) See (1).AppliestoBBOUT byte, 155 Baseband outputclockfrequency MHznibble,orserialfCLK(BB-DDR1) 310 tskmin(BB)Serial0 BBOUT3 Clk,BBOUT1:0 Data,BBOUT2 Sync See (2)(3) –20 ps tskmax (BB)Serial0 BBOUT3 Clk,BBOUT1:0 Data,BBOUT2 Sync See (2)(3) 350 ps tskmin(BB)Serial1 BBOUT7 Clk,BBOUT5:4 Data,BBOUT6 Sync See (2)(3) 15 ps tskmax (BB)Serial1 BBOUT7 Clk,BBOUT5:4 Data,BBOUT6 Sync See (2)(3) 310 ps tskmin(BB)Serial2 BBOUT11 Clk,BBOUT9:8 Data,BBOUT10 Sync See (2)(3) 60 ps tskmin(BB)Serial2 BBOUT11 Clk,BBOUT9:8 Data,BBOUT10 Sync See (2)(3) 300 ps tskmax(BB)Nibble0 BBOUT3 Clk,BBOUT5,4,1,0Data,BBOUT2 Sync See (2)(3) 170 ps tskmax(BB)Nibble0 BBOUT3 Clk,BBOUT5,4,1,0Data,BBOUT2 Sync See (2)(3) 340 ps tskmin(BB)Nibble1 BBOUT7 Clk,BBOUT11:8 Data,BBOUT6 Sync See (2)(3) 55 ps tskmax(BB)Nibble1 BBOUT7 Clk,BBOUT11:8 Data,BBOUT6 Sync See (2)(3) 305 ps BBOUT7 Clk,BBOUT11:8,5:4,2:0Data,BBOUT6tskmin(BB)Byte See (2)(3) 250 psSync BBOUT7 Clk,BBOUT11:8,5:4,2:0Data,BBOUT6tskmax(BB)Byte See (2)(3) 255 psSync (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Skew measured forRX BBOUT dataand framesignals,relativetotheBBclksignalatzerocrossing.BBclkismeasured atthreshold crossing.Lab measurement +signal→ 50 Ω → Vcommon → 50 Ω → –signal.Vcommon has a 0.01-µF filtercapacitortoGND. Differentialprobeused formeasurement. (3) tsu calculation:1/4BBclkperiod– tskmin;th calculation:1/4BBclkperiod– tskmax Figure16. RX Baseband LVDS DDR1, DDR2 Output Timing Specifications

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Table13.GeneralSwitchingCharacteristics,RX BB LVDS Output – DDR0 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT BASEBAND INTERFACE DDR LVDS fCLK(Byte) Baseband outputclockfrequency See (1) 384 MHz fCLK(Nibble0) 384 MHz fCLK(Nibble1) 500 MHz fCLK(Serial) 384 MHz tskmax(BB)Serial0 BBOUT3 Clk,BBOUT1:0 Data,BBOUT2 See (2)(3) –60 ps Sync tskmin(BB)Serial0 BBOUT3 Clk,BBOUT1:0 Data,BBOUT2 See (2)(3)(4) 400 ps Sync tskmax(BB)Serial1 BBOUT3 Ck,BBOUT1:0 Data,BBOUT2 See (2)(3) –130 ps Sync tskmin(BB)Serial1 BBOUT3 Clk,BBOUT1:0 Data,BBOUT2 See (2)(3)(4) 500 ps Sync tskmax(BB)Serial2 BBOUT7 Clk,BBOUT5:4 Data,BBOUT6 See (5)(6) –45 ps Sync tskmin(BB)Serial2 BBOUT7 Clk,BBOUT5:4 Data,BBOUT6 See (5)(6)(7) 425 ps Sync tskmax(BB)Nibble0 BBOUT3 Clk,BBOUT5,4,1,0Data,BBOUT2 See (5)(6) 0 ps Sync tskmin(BB)Nibble0 BBOUT3 Clk,BBOUT5,4,1,0Data,BBOUT2 See (5)(6)(7) 400 ps Sync tskmax(BB)Nibble1 BBOUT7 Clk,BBOUT11:8 Data,BBOUT6 See (5)(6) 10 ps Sync tskmin(BB)Nibble1 BBOUT7 Clk,BBOUT11:8 Data,BBOUT6 See (5)(6)(7) 460 ps Sync tskmax(BB)Byte BBOUT7 Clk,BBOUT11:8,5:4,2:0Data, See (5)(6) 0 ps BBOUT6 Sync tskmin(BB)Byte BBOUT7 Clk,BBOUT11:8,5:4,2:0Data, See (5)(6)(7) 480 ps BBOUT6 Sync (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Skew measured forRX BBOUT dataand framesignals,relativetotheBBclksignalatzerocrossing.BBclkismeasured atthreshold crossing.Lab measurement +signal→ 50 Ω → Vcommon → 50 Ω → –signal.Vcommon has a 0.01-µF filtercapacitortoGND. Differentialprobeused formeasurement. (3) The customerinterfacedesignmodifiesthetracelengthsbased on thedesiredreceivertimingand clockdelays. (4) tsu = –tskmax;thold= 1/4BBclkperiod– tskmin. (5) Skew measured forRX BBOUT dataand framesignals,relativetotheBBclksignalatzerocrossing.BBclkismeasured atthreshold crossing.Lab measurement +signal→ 50 Ω → Vcommon → 50 Ω → –signal.Vcommon has a 0.01-µF filtercapacitortoGND. Differentialprobeused formeasurement. (6) The customerinterfacedesignmodifiesthetracelengthsbased on thedesiredreceivertimingand clockdelays. (7) tsu = –tskmax;thold= 1/4BBclkperiod– tskmin. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):GC5330 GC5337

BBOUT Data, BBOUT Sync tskmin tskmax tskmaxtskmin T0509-01 GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Figure17. RX Baseband LVDS DDR0 Output Timing Specifications The DAC TX interfacehas a 40-signaloutputbus.The DAC TX bus can provide4-byte-wideor 2-word-wide interfaces.Table5 shows thedifferentDAC devicesthatcan be connectedtotheTX outputports.The DAC TX interfacehas two stylesofclockoutput,one where theDDR clockiscenteredovertheoutputdata-stabletime, and one where the clocktransitionisalignedwiththe data transition.Ifthe outputclockrateisgreaterthan 500 MHz, theGC533x must be configuredforclocktransitionalignedwiththedatatransition.Depending on the DAC type selected,the clock,frame,and data forthe DAC may requirea traceroutingdelay forproper alignment.See Table14,Table15,and Table16. Table14.TX DAC and Envelope ModulatorCharacteristics DAC or Envelope Modulator Timing Model DAC Data Rate TableNumber FigureNumberType DAC3282, 3283 byte-envelope Clockcenteredoverdata <1000 Mbyte/s Table15 Figure18modulator DAC3282, 3283 byte-envelope ClockalignedwithdataatGC533x, routing ≥1000 Mbyted/s Table16 Figure19modulator providestimingskew forclockcenteredoverdata DAC3484, 3482 word Clockcenteredoverdata <1000 Mword/s Table15 Figure18 ClockalignedwithdataatGC533x, routingDAC3484, 3482 word ≥1000 Mword/s Table16 Figure19providestimingskew forclockcenteredoverdata ClockalignedwithdataatGC533x. PC board DAC5682 routingmay be requiredtoprovidesome timing All Table16 Figure19 skew foroptimum performance.

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DAC Data, DAC Frame T0510-01 Ideal Data Placement GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Table15.TX DAC Clock Centered Over Data SwitchingCharacteristics(See Table5 forConnections) PARAMETER TEST CONDITIONS MIN MAX UNIT DDR LVDS fCLK(DAC) DAC outputclockfrequency See (1) 620 MHz MIN MAXCLOCK DATA TEST CONDITIONS UNITSKEW SKEW TXA4 TXA9:5,3:0 See (2)(3) –190 139 ps TXA14 TXA19:15,13:10 See (2)(3) –241 205 ps TXA9 TXA19:10,8:0 See (2)(3) –200 155 ps TXB4 TXB9:5,3:0 See (2)(3) –169 238 ps TXB14 TXB19:15,13:10 See (2)(3) –198 146 ps TXB9 TXB19:10,8:0 See (2)(3) –145 235 ps (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Skew measured fromDAC DATA desiredP/N crossingtoDATA P/N crossing.A negativeskew iswhen thedataarrivespriortothe clock. (3) tsu = 1/4DAC clockperiod– Max. Skew, th = 1/4DAC clockperiod+ Min.Skew Table16.TX DAC Clock AlignedWith Data SwitchingCharacteristics(See Table5 forConnections) PARAMETER TEST CONDITIONS MIN MAX UNIT DDR LVDS fCLK(DAC) DAC outputclockfrequency See (1) 620 MHz MIN MAXCLOCK DATA TEST CONDITIONS UNITSKEW SKEW TXA4 TXA9:5,3:0 See (2) –190 139 ps TXA14 TXA19:15,13:10 See (2) –241 205 ps TXA9 TXA19:10,8:0 See (2) –200 155 ps TXB4 TXB9:5,3:0 See (2) –169 238 ps TXB14 TXB19:15,13:10 See (2) –198 146 ps TXB9 TXB19:10,8:0 See (2) –145 235 ps (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Skew measured fromDAC DATA desiredP/N crossingtoDATA P/N crossing.A negativeskew iswhen thedataarrivespriortothe clock. Figure18. TX LVDS Timing Specifications(TXA and TXB) (DACCLK Centered Over Data) © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):GC5330 GC5337

DAC□Data□Clock Ideal Data Placement Ideal Data Placement DAC□Data,□DAC□Frame T0511-01 Min Skew Min Skew Max Skew Max Skew GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Figure19. TX LVDS Timing Specifications(TXA and TXB) (DACCLK AlignedWith Data) The envelopemodulatorinterfaceuses thesame pinsas theDAC interface.The ET connectionsare shown in Table5.The ET modulatortimingislistedinTable15. Data is outputmost-significantbyte (half-word)firstwiththe risingedge of the clockoutin the middle of data-stabletime,thenleast-significantbyte(half-word)withthefallingedge oftheclockoutinthemiddleofthe data-stabletime. The ADC outputinterfacehas two types of timing,based on the clockcenteredover the data,or clock edge-alignedwiththe data.The GC533x only processesclockcenteredover the data.Each ADC type is characterizedby thedataand clockalignment,inTable17,fromwhichthepropertableand timingdiagramcan be determinedas follows:ADC W7 inTable18 and Figure20;ADC W14 inTable19 and Figure21;and ADC B7 in Table 20 and Figure20. Note:The generalADC routingisto alignthe clockand data traceswitha common routingdelay.For theADS5463 and ADS5474 theclocktracemust be adjustedinlengthtomeet the systemtimingdesign. Note:when RXA isused as a baseband interface,thespecificationisshown intableTable17.The tableshows a samplingofADCs releasedatpublicationtime.Iftheclockisnotcentered,thepc board may requireadded routingdelaytotheclockouttosatisfythesetuptimerequirements.See (*)inTable17. W7 – word-wideADC interface,clockon bit7 W14 – word-wideADC interface,clockon bit14 B7 – byte-wideADC interface,clockon bit7 B14 – byte-wideADC interface,clockon bit14

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Table17.GeneralLVDS ADC InterfaceTable ClockADC Type Bitsper Rail ADC Format ADC InputTiming Table ADC FigureCentered ADS5400 1 Yes W7 Table18 Figure20 ADS54RF63 (*) 1 No W14 Table19 Figure20 ADS5463 (*) 1 No W14 Table19 Figure20 ADS5474 (*) 1 No W14 Table19 Figure20 RXA as baseband 2 Yes Baseband format– W14 Table21 Figure20TX input ADS61xx, ADS41xx, 2 Yes B7 Table20 Figure20ADS62pxx ADS55xx 2 Yes B7,W7 Table20Table18 Figure20 ADS58B18 2 Yes B7,W7 Table20Table18 Figure20 ADS58B28, 2 Yes B7,W7 Table20Table18 Figure20ADS62c1x ADS64xx 6 or7 Yes W7 Table18 Figure21 ADS52xx 12 or14 Yes W7 Table18 Figure21 Table18.RX ADC-W7 SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fCLK(ADC) RX inputclockfrequency,ADCA7 Clk See (1) 620 MHz Inputdatasetuptimeon portA beforeADCA7tsu(ADC,A) See (1)(2) 260 psClktransition Inputdataholdtimeon portA afterADCA7 Clkth(ADC,A) See (1)(2) 170 pstransition Inputdatasetuptimeon portB beforeADCB7tsu(ADC,B) See (1)(2) 260 psClktransition Inputdataholdtimeon portB afterADCB7 Clkth(ADC,B) See (1)(2) 140 pstransition (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Setupand holdtimesapplytodataand appropriateADC Clk,respectively.Timingismeasured fromADC Clkthresholdcrossing. Figure20. RX ADC LVDS Timing Specifications(RXA and RXB) © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Table19.RX ADC-W14 SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT RX inputclockfrequencyADCA14 Clk,fCLK(ADC) See (1) 620 MHzADCB14 Clk tsu(ADC,A) Inputdatasetuptimeon portA before See (1)(2) 160 ps ADCA14 Clktransition th(ADC,A) Inputdataholdtimeon portA after See (1)(2) 200 ps ADCA14 Clktransition tsu(ADC,B) Inputdatasetuptimeon portB before See (1)(2) 180 ps ADCB14 Clktransition th(ADC,B) Inputdataholdtimeon portB after See (1)(2) 220 ps ADCB14 Clktransition (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Setupand holdtimesapplytodataand appropriateADC Clk,respectively.Timingismeasured fromADC Clkthresholdcrossing. Table20.RX ADC-B7, B14 SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fCLK(ADC-AB) RX inputclockfrequency,ADCA7 Clk, See (1) 620 MHz ADCB7 Clk fCLK(ADC-C) RX inputclockfrequency,ADCC7 Clk See (1) 620 MHz Inputdatasetuptimeon portA beforetsu(ADC,A) See (1)(2) 260 psADCA7 Clktransition Inputdataholdtimeon portA afterth(ADC,A) See (1)(2) 160 psADCA7 Clktransition Inputdatasetuptimeon portB beforetsu(ADC,B) See (1)(2) 170 psADCB7 Clktransition Inputdataholdtimeon portB afterth(ADC,B) See (1)(2) 140 psADCB7 Clktransition Inputdatasetuptimeon portC beforetsu(ADC,C) See (1)(2) 290 psADCC7 Clktransition Inputdataholdtimeon portC afterth(ADC,C) See (1)(2) 150 psADCC7 Clktransition Inputdatasetuptimeon portA beforetsu(ADC,A) See (1)(2) 130 psADCA14 Clktransition Inputdataholdtimeon portA afterth(ADC,A) See (1)(2) 200 psADCA14 Clktransition Inputdatasetuptimeon portB beforetsu(ADC,B) See (1)(2) 170 psADCB14 Clktransition Inputdataholdtimeon portB afterth(ADC,B) See (1)(2) 240 psADCB14 Clktransition (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Setupand holdtimesapplytodataand appropriateADC Clk,respectively.Timingismeasured fromADC Clkthresholdcrossing.

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Figure21. RX ADC LVDS Timing Specifications(RXA and RXB) Table21.RXA-BB SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fCLK(BB-A) RX inputclockfrequency See (1) 250 MHz Inputdatasetuptimeon portA beforetsu(BB-A) See (1)(2) 160 psADCA Clktransition Inputdataholdtimeon portA afterth(BB-A) See (1)(2) 200 psADCA Clktransition (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Setupand holdtimesapplytodataand appropriateADC Clk,respectively.Timingismeasured fromADC Clkthresholdcrossing. Table22.DPD Clock and Sync A,B SwitchingCharacteristics(1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fCLK(DPD) 310 MHzDPD inputclockfrequency See (2) {370} 250fCLK(BB) BB internalclockfrequency See (1) MHz{290} tDUTY-CYCLE DPD inputclockdutycycle See (3) 40% 60% fCLK (JITTERRMS-DPD) DPD clockinputjitter See (3) 2.5% tsu(SYNCA) InputdatasetuptimebeforefCLK ↑ See (2) 0.25 ns th(SYNCA) InputdataholdtimeafterfCLK ↑ See (2) 0.1 ns tsu(SYNCB) InputdatasetuptimebeforefCLK ↑ See (2) 0.35 ns th(SYNCB) InputdataholdtimeafterfCLK ↑ See (2) 0.05 ns (1) The PLL outputrangesare400–1000 MHz. These areconfigurationdependentbutrelatedtotheDPDCLK frequency.The cmd5330 softwareautomaticallycheckstheselimitswhen compilinga configuration. (2) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (3) SpecificationisfromthePLL specificationand isnotproductiontested. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):GC5330 GC5337

SYNCA, SYNCB DPD Clock tsu th T0514-014 cycles, min. DPD□Clock Sync□Out tHO T0515-01 td GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Figure22. SYNCA, SYNCB Timing toDPD Clock Table23.DPD Clock and Sync Out SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT td(SYNCOut) Data validafterDPD clock See (1) 0.95 ns tHO(SYNCOut) Data heldvalidafternextDPD clock See (1) 0.3 ns (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. Figure23. Sync Out Timing toDPD Clock The JTAG testconnectionsare used withthe CMOS signalsforboard interconnectiontests.The TRSTB pin must be toggledlow,or low initially.IfJTAG isnot used,the TRSTB signalshouldbe GROUNDed or tiedto GND through< 1 kΩ resistance.TRSTB shouldbe 0 fornormaloperation. Table24.JTAG SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN MAX UNIT fTCK JTAG clockfrequency 50 MHz tTCKL JTAG clocklowperiod See (1) 10 ns tTCKH JTAG clockhighperiod See (1) 10 ns tsu(TDI,TMS) InputdatasetuptimebeforefTCK ↑ See (1) 7 ns tH(TDI,TMS) InputdataholdtimeafterfTCK ↑ See (1) 1.5 td OutputdatadelayfromfTCK ↓ See (1) 10 ns tOHD(TDO) PreviousdatavalidfromfTCK ↓ See (1) 2 ns (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C.

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t tOH tSU tH td T0289-02 T0516-01 SPI Clock SPIDIO-In SPIENB SPIDO(SPARE) tsu(DENB) tsu(DI) th(DI) th(DO)td(DO1) GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Figure24. JTAG Timing Specifications The SPI programminginterfaceisactiveonlywhen EMIFENA is0.There areboththree-wireand four-wireSPI interfaces;theSPIDO(SPARE) isthefourthwireforSPI dataoutput. Table25.SPI SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tsu(DENB) EnablesetuptimebeforeSPI CLK ↑ ValidforSPIDENB, see(1) 5 ns tsu(DI) Data setuptimebeforeSPI CLK ↑ ValidforSPIDIO,see(1) 5 ns th(DI) InputdataholdtimeafterCLK ↑ ValidforSPIDIO,see(1) 0.6 ns td(DO) OutputdatadelayfromfTCK ↓ ValidforSPIDIO,see(2) 8 ns td(DO1) OutputdatadelayfromfTCK ↓ ValidforSPIDO(SPARE), see(2) 8 ns fclkSPI SPI clockfrequency See (1) 50 MHz (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) The SPI dataoutputinthree-wiremode comes fromSPIDIO;infour-wiremode theoutputisfromSPIDO(SPARE). Figure25. SPI Timing Specifications © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):GC5330 GC5337

tsu(RD) tsu(RD) tdly(RD) th(RD) th(RD) toh(RD) tz(RD) GC5330 GC5337 SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com Table26.MPU SwitchingCharacteristics(READ) PARAMETER TEST CONDITIONS MIN MAX UNIT tsu(RD) CEB and ADDR setuptimeto↓OEB See (1) 1.5 ns tdly(RD) Data validtimeafter↓OEB See (1) 15 ns th(RD) CEB and ADDR holdtimeto↑OEB See (1) 2.5 ns tHIGH(RD) Time OEB must remainHIGH between READs See (1) 6 ns tz(RD) Data goes tohigh-impedancestateafter↑OEB or↑CEB See (2) 5 ns tcycle(RD) Time between READs See (1) 21 ns toh(RD) Time afterOEB ↑ thatdataisvalid See (2) TBD ns (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C. (2) Bench testedforoutputstartchangingafterreleasingstrobewitha 50-Ω loadon theoutput Figure26. MPU READ Timing Specifications Table27.MPU SwitchingCharacteristics(WRITE) PARAMETER TEST CONDITIONS MIN MAX UNIT tsu(WR) CEB, DATA, and ADDR setuptimeto↓WEB See (1) 1.4 ns th(WR) CEB, DATA, and ADDR holdtimeafter↑WEB See (1) 3 ns tlow(WR) Time WEB and CEB must remainsimultaneouslyLOW See (1) 4 ns thigh(WR) Time CEB orWRB must remainHIGH between WRITEs See (1) 7 ns tcycle(WR) Time between WRITEs See (1) 11 ns (1) Chipspecificationsareproductiontestedat90°C case temperatureforthegivenspecification.Earlyproductionlotsaresample tested at–40°C.

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tsu(WR) tsu(WR) tsu(WR) th(WR) th(WR) th(WR) thigh(WR)tlow(WR) GC5330 GC5337 www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 Figure27. MPU WRITE Timing Specifications Power Sequencing Guideline TI ASIC I/Odesignallowseitherthe core supply(VDD) or the I/Osupply(VDDS) to be powered up(2) foran indefiniteperiodoftimewhiletheotherpower supplyisnotpowered up,ifalloftheseconstraintsaremet:

• Chipiswithinallmaximum ratingsand recommended operatingconditions.
• Have followedallwarningsabout exposure to maximum ratedand recommended conditions,particularly junctiontemperature.These applytopower transitionsas wellas normaloperation.
• Bus contentionwhileVDDS ispowered up must be limitedto 100 hours over the projectedlifetimeof the device.
• Bus contentionwhileVDDS ispowered down may violatetheabsolutemaximum ratings. However,itisgenerallygood practicetopower up VDD, VDDSHV, and VDDS allwithin1 second ofeach other. ApplicationInformation The GC533x referencedesignincludesthefollowingadditionaltransmit/receivesignalchaincomponents:
• TMS320C6748 digitalsignalprocessor(DSP) and DPD adaptationsoftware
• DAC3283 16-bit800-MSPS, dac348X,orDAC5682 16-bit,1-GSPS DAC (transmitpath)
• CDCE72010 clockgenerator
• TRF3720 300-MHz to4.8-GHzquadraturemodulatorwithintegratedwidebandPLL/VCO
• TRF370317 0.4-GHzto4-GHz quadraturemodulator
• ADS41B49 14-bit,250-MSPS ADC (andotheroptions;feedbackpath)
• AMC7823 analogmonitoringand controlcircuitwithGPIO and SPI
• PGA870 widebandprogrammablegainamplifier
• ADS42b49 14-bitdual250-MSPS receiveorcomplexfeedbackADC (andotheroptions;RX path) MPU InterfaceGuidelines The followingsectiondescribesthe hardware interfacebetween the recommended microprocessorand the GC533x. The GC533x interfaceisan EMIF asynchronousinterface. (2) A supplybus ispowered up when thevoltageiswithintherecommended operatingrange.Itispowered down when itisbelowthat range,eitherstableorintransition. © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com The TMS320C674x/OMAP-L1x ProcessorPeripheralsOverview referencdeguide (SPRUFK9 ) illustratesthe connectionsto the TMS320C6748 peripherals.The TMS320C674x/OMAP-L1x ProcessorExternalMemory InterfaceA (EMIFA)user's guide(SPRUFL6 )illustratestheconnectionstotheEMIF A interface,and DSP timing. Itisrecommended thatifmore thanone EMIF-A loadisconnectedtotheDSP, bufferingisused forthecontrol bus WE, RD, addressbus,and databus. RelatedMaterialand Documents The followingdocuments areavailablethroughyourTIFieldApplicationEngineerFAE:

• GC5330 EVM schematicdiagram
• GC5330 EVM layoutdiagram
• GC533x Baseband ApplicationNote
• GC533x Baseband beAGC ApplicationNote
• GC533x DDUC ApplicationNote
• GC533x CFR ApplicationNote
• GC533x DPD ApplicationNote
• GC533x TX (BUC, DAC Interface)ApplicationNote
• GC533x RX ApplicationNote
• GC533x feAGC ApplicationNote
• GC533x Sync,MPU ApplicationNote
• GC533x SoftwareApplicationGuide

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www.ti.com SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 APPENDIX GlossaryofTerms 3G Thirdgeneration(referstonext-generationwidebandcellularsystemsthatuse CDMA) 3GPP ThirdGenerationPartnershipProject(W-CDMA specification,www.3gpp.org) 3GPP2 ThirdGenerationPartnershipProject2 (cdma2000 specification,www.3gpp2.org) ACLR Adjacent-channelleakageratio(measureofout-of-bandenergyfromone CDMA carrier) ACPR Adjacent-channelpower ratio ADC Analog-to-digitalconverter BBclk Clock-to-basebandsectionofGC533x BW Bandwidth CCDF Complementarycumulativedistributionfunction CDMA Code divisionmultipleaccess(spreadspectrum) CEVM Compositeerrorvectormagnitude CFR Crestfactorreduction DPD_CLK Clock-to-DPDsectionofGC533x CIC Cascaded integratorcomb (typeofdigitalfilter) CMOS Complementarymetal-oxidesemiconductor DAC Digital-to-analogconverter dB Decibels dBm Decibelsrelativeto1 mW (30dBm = 1 W) DDR Dualdatarate(ADC outputformat) DPD Digitalpre-distortion DSP Digitalsignalprocessingordigitalsignalprocessor DUC Digitalupconverter(usuallyprovidestheGC533x input) EVM Errorvectormagnitude FIR Finiteimpulseresponse(typeofdigitalfilter) HP-DPD High-performanceDPD mode oftheGC533x HS-DPD High-speedDPD mode oftheGC533x I/Q In-phaseand quadrature(signalrepresentation) IF Intermediatefrequency IIR Infiniteimpulseresponse(typeofdigitalfilter) JTAG JointTestActionGroup (chipdebug and teststandard1149.1) LO Localoscillator LSB Least-significantbit MSB Most-significantbit MSPS Megasamples persecond (1× 106 samples/s) PA Power amplifier PAR Peak-to-averageratio PCDE Peak code domain error PDC Peak detectionand cancellation(stage) PDF Probabilitydensityfunction RF Radiofrequency RMS Root-mean-square(methodtoquantifyerror) SDR Singledatarate(ADC outputformat) SEM Spectrumemissionmask SNR Signal-to-noiseratio(usuallymeasured indB ordBm) UMTS Universalmobiletelephoneservice W-CDMA Wideband code divisionmultipleaccess(synonymouswith3GPP) © 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):GC5330 GC5337

SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011 www.ti.com WiBro WirelessBroadband (KoreaninitiativeIEEE 802.16e) WiMAX WorldwideInteroperabilityofMicrowaveAccess (IEEE802.16e) AA AA AA

REVISION HISTORY

Changes from RevisionA (December 2010)toRevisionB Page

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www.ti.com 9-Jul-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) GC5330IZEV ACTIVE BGA ZEV 484 60 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR GC5337IZEV ACTIVE BGA ZEV 484 60 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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