ADS5102

ADS5102 TI | Alldatasheet

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SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE 1www.ti.com

FEATURES

/C0068ADS5102 (65 MSPS) ADS5103 (40 MSPS) /C0068Differential Input /C00681.8 V Analog/Digital Supply /C0068Digital Outputs Compatible With 1.8 V or 3.3 V Logic /C0068Signal-to-Noise: 58 dB at 20 MHz (ADS5103) /C0068Spurious Free Dynamic Range: 71 dB at

20 MHz (ADS5102)

/C0068105-mW Power Dissipation (ADS5103) /C0068336 µW Power-Down Mode

APPLICATIONS

/C0068Ultrasound /C0068Digital Cameras /C0068Imaging /C0068Communications /C0068Baseband Digitization

DESCRIPTION

The ADS5102/3 are low-power CMOS, 10-bit, analog- to-digital converters (ADC) that operate from a single 1.8-V supply. The internal reference can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. A 10-bit parallel output data bus is provided with 3-state outputs. For power sensitive systems, a standby mode is provided which reduces power consumption to 336 µW. Also, if using external voltage reference, then the internal VREF circuit can be powered down. The analog input is differential, which provides excellent common-mode noise rejection as well as superior performance from the ADS5102/3. FUNCTIONAL BLOCK DIAGRAM Timing Circuitry CM AGND BG PDREF REFT REFB CML DRGND DGND CLK AIN+ AIN– NC RBIAS NC AV DD STBY DRV DD DV DD D[0–9] OE Sample and Hold

10 Bit

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2001, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 2 www.ti.com DRV DD NC DV DD DGND CLK STBY OE PDREF NC NC RBIAS NC DRGND NC DV DD DGND AV DD AGND AIN– AIN+ AGND AV DD NC NC 567 8 35 34 33 32 3136 30 NC NC NC NC NC AGND REFB CML BG NC AGND 28 27 2629 9 10 11 12 DD NC REFT PFB PACKAGE (TOP VIEW) AV NC – No internal connection

ORDERING INFORMATION

48-TQFP (PFB) Tape and Reel 48-TQFP (PFB) Tray 48-TQFP (PFB) Tape and Reel 48-TQFP (PFB) TrayTA

40 MSPS 40 MSPS 65 MSPS 65 MSPS

0°C to 70°C ADS5103CPFBR ADS5103CPFB ADS5102CPFBR ADS5102CPFB –40°C to 85°C ADS5103IPFBR ADS5103IPFB ADS5102IPFBR ADS5102IPFB Evaluation module ADS5103EVM ADS5103EVM ADS5102EVM ADS5102EVM

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 3www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AV DD 2, 41, 46 I Analog supply, 1.8V ±5% AGND 3, 9, 42, 45 I Analog ground REFT 4 I/O Reference top REFB 5 I/O Reference bottom CML 6 O Common mode level output— nominally 1.0 V BG 7 O Band-gap decoupling— decouple with 1 µF to GND and 100 kΩ to AVDD (refer to Figure 30) PDREF 17 I Powerdown reference when using external voltage reference 0 = internal VREF, 1 = external VREF. In external VREF mode, connect pins BG and REFT together. RBIAS 14 O Connect a resistor between this pin and AGND. This resistor value is determined by speed grade selected and is used to set amplifier internal bias currents. (see Table 2) OE 18 I 1 = 3-state the data outputs , 0 = data bus enable STBY 19 I 0 = power down mode, 1 = normal operation mode CLK 20 I Clock Input DGND 21, 40 I Digital ground DV DD 22, 39 I Digital supply— 1.8 V nominally DRV DD 24 I Driver digital supply— 1.8 V or 3.3 V nominally D9 25 O Digital Bit 9 (MSB) D8 26 O Digital Bit 8 D7 27 O Digital Bit 7 D6 28 O Digital Bit 6 D5 29 O Digital Bit 5 D4 30 O Digital Bit 4 D3 31 O Digital Bit 3 D2 32 O Digital Bit 2 D1 33 O Digital Bit 1 D0 34 O Digital Bit 0 (LSB) DRGND 37 I Driver digital ground AIN+ 44 I Positive analog input AIN– 43 I Negative analog input NC 1,8,10,11,12, 13,15,16,23,35, 36, 38,47,48 NA No internal connection on this pin

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 4 www.ti.com absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN TYP MAX UNIT Analog Inputs Analog input voltage (AIN+, AIN–) REFB REFT V Input voltage, differential full scale 1 Vpp Input common-mode voltage, (REFT+REFB)/2 0.8 1.1 V Input capacitance (Ci), measured to ground 5 pF Overvoltage recovery time, 1.8-V input voltage 10 ns Analog input bandwidth 950 MHz Input impedance (switch capacitor) ADS5102 38.5 kΩInput impedance (switch capacitor)ADS5103 62.5 kΩ Supplies and References Operating free-air temperature, TA –40 85 °C Analog supply voltage, AVDD 1.65 1.80 2.00 V Digital supply voltage, DVDD 1.65 1.80 2.00 V Digital driver supply voltage, DRVDD 1.65 1.80 3.6 V Reference top voltage, VREFT 1.30 1.34 1.39 V Reference bottom voltage, VREFB 0.78 0.81 0.84 V Common-mode voltage, VCML 0.85 1.05 1.15 V Bandgap voltage, VBG 1.22 1.27 1.32 V Clock Inputs CLK Sampling rate ADS5102 1 65 MSPSSampling rate ADS5103 1 40 MSPS

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 5www.ti.com electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V, DRV DD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted) internal reference voltages PARAMETER MIN TYP MAX UNIT VREFT Reference top voltage 1.30 1.34 1.39 V VREFB Reference bottom voltage 0.78 0.81 0.84 V VCML Common-mode voltage 0.85 1.05 1.15 V VBG Bandgap voltage 1.22 1.27 1.32 V external reference voltages PARAMETER MIN TYP MAX UNIT REFT Reference input voltage (top) 1.15 1.25 1.35 V REFB Reference input voltage (bottom) 0.70 0.75 0.85 V REFT –REFB Differential input 0.45 0.50 0.55 V Input resistance 200 Ω digital outputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V High level output voltage I5 0 A DRV DD = 1.8 V DRV DD – 0.1 VVOH High-level output voltage I OH = 50 µA DRV DD = 3.3 V DRV DD – 0.2 V V Low level output voltage I5 0 A DRV DD = 1.8 V 0.1 VVOL Low-level output voltage I OL = 50 µA DRV DD = 3.3 V 0.2 V C L External load capacitance 15 pF digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V High level input voltage DRV DD = 1.8 V 0.8 × DRV DD VVIH High-level input voltage DRV DD = 3.3 V 0.8 × DRV DD V V Low level input voltage DRV DD = 1.8 V 0.2 × DRV DD VVIL Low-level input voltage DRV DD = 3.3 V 0.2 × DRV DD V IIH High-level input current VIH = DRVDD ±5 µA IIL Low-level input current VIL = 0 V ±5 µA dc accuracy PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (INL) Integral nonlinearity ADS5102 ±1 ±2.5 LSB (INL) Integral nonlinearity ADS5103 ±0.5 ±1.5 LSB (DNL) Differential nonlinearity ADS5102 ±0.5 ±1 LSB (DNL) Differential nonlinearity ADS5103 ±0.4 ±0.8 LSB Missing code No missing code assured Offset error REFT = 1.25 V, REFB = 0.75 V ±0.4 ±1.5 %FSR Gain error REFT = 1.25 V, REFB = 0.75 V ±1.4 ±2 %FSR

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 6 www.ti.com electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V, DRV DD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted) (continued) dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADS5102 f = 3.5 MHz 8.7 9.2 Bits ENOB Effective number of bits ADS5102 f = 20 MHz 9 Bits ENOB Effective number of bits ADS5103 f = 3.5 MHz 9.0 9.3 BitsADS5103 f = 20 MHz 9.2 Bits ADS5102 f = 3.5 MHz 58 73 dBc SFDR Spurious free dynamic range ADS5102 f = 20 MHz 71 dBc SFDR Spurious free dynamic range ADS5103 f = 3.5 MHz 64 69 dBcADS5103 f = 20 MHz 66 dBc ADS5102 f = 3.5 MHz –71 –55 dBc THD Total harmonic distortion ADS5102 f = 20 MHz –71 dBc THD Total harmonic distortion ADS5103 f = 3.5 MHz –65 –62 dBcADS5103 f = 20 MHz –68 dBc ADS5102 f = 3.5 MHz 56 58 dBc SNR Signal to noise ratio ADS5102 f = 20 MHz 57 dBc SNR Signal-to-noise ratio ADS5103 f = 3.5 MHz 57 59 dBcADS5103 f = 20 MHz 58 dBc ADS5102 f = 3.5 MHz 54 58 dBc SINAD Signal to noise and distortion ADS5102 f = 20 MHz 57 dBc SINAD Signal-to-noise and distortion ADS5103 f = 3.5 MHz 56 58 dBcADS5103 f = 20 MHz 57 dBc power supply† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AV DD 1.65 1.8 2 Operating voltage DV DD 1.65 1.8 2 VO erating voltage DRV DD 1.65 1.8 3.6 V I(AVDD ) Analog supply current ADS5102 AV DD =D VDD =18V D R V DD =33V 70 80 mAI(AVDD ) Analog supply current ADS5103 AV DD = DVDD = 1.8 V, DRV DD = 3.3 V 45 53 mA I(DVDD ) Digital supply current ADS5102 AV DD =D VDD =18V D R V DD =33V 8 9 mAI(DVDD ) Digital supply current ADS5103 AV DD = DVDD = 1.8 V, DRV DD = 3.3 V 5 7 mA I(DRVDD ) Output driver supply current ADS5102 AV DD =D VDD =18V D R V DD =33V 6.5 8 mAI(DRVDD ) Output driver supply currentADS5103 AV DD = DVDD = 1.8 V, DRV DD = 3.3 V 4.8 5.5 mA I(TOTAL) Total current consumption ADS5102 AV DD =D VDD =18V D R V DD =33V 84 97 mAI(TOTAL) Total current consumption ADS5103 AV DD = DVDD = 1.8 V, DRV DD = 3.3 V 54 66 mA PD Power dissipation ADS5102 AV DD =D VDD =18V D R V DD =33V 160 188 mWPD Power dissipation ADS5103 AV DD = DVDD = 1.8 V, DRV DD = 3.3 V 105 126 mW Standby power CLK running 336 390 µW Power supply rejection 0.25 %FS † Sinewave input, fi = 3.5 MHz, –1 dBFS input span

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 7www.ti.com electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V, DRV DD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted) (continued) timing characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Clock duty cycle 50 ±10 % td(o) Output propagation delay 9 12 ns t(en) OE ↓ to outputs enabled time 6 ns tdis OE ↑ rising to outputs 3-state disable time 10 ns td(latency) Pipeline latency 5.5 cyc td(ap) Aperture delay 1 ns Aperture uncertainty 2 ps rms timing diagram S2 S3 S1 S2 S3 123456789 10 td(latency) t(en) td(o) tdis Analog CLK OE D[0–9] S1

approaching 200 MHz in under sampling applications. Figure 29. Simplified Functional Block Diagram to Figure 30 for correct configuration).

Figure 30. BG Reference Configuration recommended to apply a common-mode voltage to the input of 1 V. of clock and aperture can be considered to add in quadrature, i.e.

differential input signal applied. There is a 5.5 clock latency from the sampling to valid data output on D0–D9. capacitance is typically made up of two sources, next stage input capacitance and PWB etch run capacitance. generally 22 Ω is a good value. Again this depends on the load capacitance. The digital output of these devices is offset binary and follows the following format. Table 1. Output Coding

• • 511 0 1 1 1 1 1 1 1 1 1 REFB REFT 0 0 0 0 0 0 0 0 0 0 0 † Where there is either an internal voltage reference or an external voltage reference applied to the REFT and REFB pins. driving the analog input Since many real world signals are single ended and most modern high speed ADC’s employ differential inputs, it is necessary in many cases to perform single ended to differential conversion prior to the ADC. Also, the ADC performs optimally if a differential signal is applied to the inputs. In some cases, signal conditioning is required in the form of the amplification or filtering. The two preferred techniques for driving the ADC input are: 1) With an active amplifier specifically designed to drive ADC’s; 2) With an RF transformer. driving the analog input with a differential amplifier Texas Instruments has developed a family of high quality operational amplifiers that have been designed specifically for driving the input stage of modern ADC’s. These devices allow for amplification and filtering prior to the ADC. This stage can be used to set the maximum signal voltage to match the full scale input of the ADC. The best solution for driving the ADS5102/3 ADC’s is the THS4501 amplifier. Figure 31 shows how to use this device with a gain of 2. The ADC common mode output voltage can be directly connected to the op amp to provide the proper levels. The THS4501 provides optimum matching of op amp output to the input of the ADS5102/3. This configuration provides signal amplification, filtering, and single-ended to differential conversion. It is recommended to provide de-coupling capacitors of 0.1 µF and 0.001 µF on the CML output. This filters out any high frequency noise prior the ADC input.

Figure 33. Driving the Analog Inputs only dissipates less than 1 mW of power. The resistor accuracy of 1% is adequate. Table 2. Resistor Value

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 21www.ti.com DEFINITION OF SPECIFICATIONS Analog Input Bandwidth— The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay— The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainity (Jitter)— The sample-to-sample variation in aperture delay. Differential Nonlinearity (DNL)— The maximum deviation of any single LSB transition at the digital output from an ideal 1 LSB step at the analog input. Ideally, each transition step is 1 LSB wide. DNL is the measured error from theoretical in step size. A DNL of less than –1 LSB implies no missing codes. Integral Nonlinearity (INL)— is the summation of the differential nonlinearity errors and indicates the worst case deviation from an best fit straight line that is drawn from 1/2 LSB of the first transition to 1/2 LSB above the last transition. The best fit is determined using the least squares curve fitting method. Duty Cycle— is the ratio of the clock time high over the full clock period (time high plus time low) and then also the time low over the total clock period. At a given clock rate, these specs define the acceptable duty cycle allowed on the clock. Sampling Rate (Fs)— The rate at which the converter tested to ensure conversion of analog signals to digital. The maximum rate specified is the rate and which the device is production tested to ensure performance specs are met. Expressed in mega samples per second (MSPS). Output Propagation Delay— The delay between the 50% point of the falling edge of clock signal and the time when all output data bits are within valid logic levels. Offset Error— In an ideal ADC the first transition from 0000000000 should occur at 1/2 LSB above REFB. Offset Error is defined as the difference between this ideal first transition and the voltage level where the first transition actually occurs. Expressed in % full scale range (%FSR) but may also be expressed in volts. This can be thought of as shifting the transfer function either left or right along the X-axis. Overvoltage Recovery Time— The amount of time required for the converter to recover to 0.2% accuracy after an analog input signal 150% of full scale is reduced to midscale. Power Supply Rejection Ratio— The ratio of a change in input offset voltage to a change in power supply voltage. Total Harmonic Distortion (THD)— The ratio of the peak signal amplitude to the summation of the harmonic components. This is expressed in – dB. THD = 20 Log [input amplitude/(summation of harmonic bins)]. For calculation purposes, the first 7 harmonics are included in the calculations. Signal To Noise Distortion (SINAD)— The ratio of the rms signal amplitude (set 1 dB below full scale) to rms value of the sum of all other spectral noise and harmonic components, but excluding dc. Signal to Noise Ratio (SNR)— The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the the sum of all other spectral components, excluding the first five harmonics and dc. Reported in dB. Spurious Free Dynamic Range (SFDR)— The difference between the peak amplitude of a fundamental input sine wave and the largest peak spurious component that appears, excluding dc and the input. The peak spurious component may or may not be a harmonic frequency. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale).

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 22 www.ti.com MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–/C02577° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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