ADS1014LIYCJR

ADS1014L_V01 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 44

Technical content

ADS101xL Ultra-Small, Low-Power, 12-Bit, 3.3-kSPS ADCs With PGA, Comparator and 1.8-V I2C Bus Voltage Support

1 Features

• Noise-free resolution: 12 bits
• Supply voltage range: 2.0 V to 3.6 V
• Low current consumption: – 150 μA (continuous-conversion mode)
• Programmable data rate: 128 SPS to 3.3 kSPS
• Single-cycle settling
• Internal low-drift voltage reference
• Internal oscillator
• Digital comparator with ALERT output pin
• I2C interface: – Four pin-selectable address – Compatible with 1.8-V I2C bus voltages
• Operating temperature range: – –40°C to +125°C

2 Applications

• General system monitoring: – Supply-voltage monitoring – Current measurement – Temperature measurement
• Wearables and personal electronics Device Information PART NUMBER INPUT CHANNELS FEATURES(1) ADS1014L 1 DE (1 SE) PGA, comparator ADS1015L 2 DE (4 SE) PGA, comparator (1) See the Device Comparison Table for details.

3 Description

The ADS1014L and ADS1015L (ADS101xL) are precision, low-power, 12-bit, I 2C-compatible, analog- to-digital converters (ADCs) offered in ultra-small, 12-pin DSBGA and a 10-pin VSSOP packages. The ADS101xL incorporate a low-drift voltage reference and an oscillator. The ADS101xL also incorporate a programmable gain amplifier (PGA) and a digital comparator. These features, along with the device wide operating supply range, are useful for power- and space-constrained, sensor measurement applications. The ADS101xL perform conversions at data rates up to 3300 samples per second (SPS). The PGA offers input ranges from ±256 mV to ±6.144 V, allowing precise large- and small-signal measurements. The ADS1015L features an input multiplexer (MUX) that allows two differential or four single-ended input measurements. Use the digital comparator in the ADS101xL for under- and overvoltage detection.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) ADS101xL YCJ (DSBGA, 12) 1.47 mm × 1.03 mm DGS (VSSOP, 10) 3.00 mm × 4.9 mm (1) For all available packages, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. 1.8 V 3.3 V ADS1015L AIN0 AIN1 AIN3 Mux PGA 12-Bit ΔƩ ADC Voltage Reference GND VDD I2C Interface SDA ADDR SCL AIN2 3.3 V I2C Bus Analog Output Temperature Sensor IC Current Sense Amplifier RSHUNT Power Supply Monitoring 3.3 V ALERT/ RDY RBias Thermistor Comparator Oscillator System-Monitoring Application Example ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10.1 Receiving Notification of Documentation Updates..33

12 Mechanical, Packaging, and Orderable

ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

4 Device Comparison Table

(Bits) MAXIMUM SAMPLE RATE (SPS) INPUT CHANNELS Differential (Single-Ended) INTERFACE DIGITAL INPUT LEVELS ADS1014L 12 3300 1 (1) I2C Independent of VDD ADS1015L 12 3300 2 (4) I2C Independent of VDD ADS1114L 16 860 1 (1) I2C Independent of VDD ADS1115L 16 860 2 (4) I2C Independent of VDD ADS1014 12 3300 1 (1) I2C Ratiometric to VDD ADS1015 12 3300 2 (4) I2C Ratiometric to VDD ADS1114 16 860 1(1) I2C Ratiometric to VDD ADS1115 16 860 2 (4) I2C Ratiometric to VDD

5 Pin Configuration and Functions

Figure 5-1. DGS Package, 10-Pin VSSOP (Top View) Table 5-1. Pin Functions: DGS Package PIN TYPE DESCRIPTION(1)NAME ADS1014L ADS1015L ADDR 1 1 Digital input I2C target address select pin. See the I2C Address Selection section for details. AIN0 4 4 Analog input Analog input 0 AIN1 5 5 Analog input Analog input 1 AIN2 — 6 Analog input Analog input 2 (ADS1015L only) AIN3 — 7 Analog input Analog input 3 (ADS1015L only) ALERT/RDY 2 2 Digital output Comparator output or conversion ready. Open-drain output. Connect to VDD using a pullup resistor. GND 3 3 Analog Ground NC 6, 7 — — No connect. Leave pin floating or connect to GND. SCL 10 10 Digital input Serial clock input. Connect to VDD using a pullup resistor. SDA 9 9 Digital I/O Serial data input and output. Connect to VDD using a pullup resistor. VDD 8 8 Analog Power supply. Connect a 0.1-μF, power-supply decoupling capacitor to GND. (1) See the Unused Inputs and Outputs section for unused pin connections. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: ADS1014L ADS1015L

A B C D Not to scale AIN1 AIN2 AIN3 AIN0 GND GND VDD VDD SDA ALERT/RDY ADDR SCL Figure 5-2. YCJ Package, 12-Pin DSBGA (Top View) Table 5-2. Pin Functions: YCJ Package PIN TYPE DESCRIPTION(1) ADS1014L ADS1015L NAME D2 D2 ADDR Digital input I2C target address select pin. See the I2C Address Selection section for details. B1 B1 AIN0 Analog input Analog input 0 A1 A1 AIN1 Analog input Analog input 1 — A2 AIN2 Analog input Analog input 2 (ADS1015L only) — A3 AIN3 Analog input Analog input 3 (ADS1015L only) D1 D1 ALERT/RDY Digital output Comparator output or conversion ready. Open-drain output. Connect to VDD using a pullup resistor. B2, B3 B2, B3 GND Analog Ground A2, A3 — NC — No connect. Leave pin floating or connect to GND. D3 D3 SCL Digital input Serial clock input. Connect to VDD using a pullup resistor. C3 C3 SDA Digital I/O Serial data input and output. Connect to VDD using a pullup resistor. C1, C2 C1, C2 VDD Analog Power supply. Connect a 0.1-μF, power-supply decoupling capacitor to GND. (1) See the Unused Inputs and Outputs section for unused pin connections. ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted) (1) MIN MAX UNIT Power-supply voltage VDD to GND –0.3 5.5 V Analog input voltage AIN0, AIN1, AIN2, AIN3 GND – 0.3 VDD + 0.3 V Digital input voltage SCL, SDA, ADDR, ALERT/RDY GND – 0.3 5.5 V Input current Continuous, any pin except power-supply pins –10 10 mA Temperature Junction, TJ 150 Storage, Tstg –60 150 (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY Power supply VDD to GND 2 3.6 V ANALOG INPUTS(1) VAINx Absolute input voltage GND VDD V FSR Full-scale input voltage range(2) VIN = VAINP – VAINN ±0.256 ±6.144 V DIGITAL INPUTS Input voltage GND 3.6 V TEMPERATURE RANGE TA Operating ambient temperature –40 125 °C (1) AINP and AINN denote the selected positive and negative inputs of the ADC. AINx denotes one of the two (ADS1014L) or four (ADS1015L) available analog inputs. (2) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 3.6 V (whichever is smaller) must be applied to this device. See Table 7-1 for more information. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: ADS1014L ADS1015L

6.4 Thermal Information

THERMAL METRIC(1) DGS (VSSOP) YCJ (DSBGA) UNIT

10 PINS 12 PINS

RθJA Junction-to-ambient thermal resistance 182.7 101.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 67.2 0.7 °C/W RθJB Junction-to-board thermal resistance 103.8 25.9 °C/W ψJT Junction-to-top characterization parameter 10.2 0.4 °C/W ψJB Junction-to-board characterization parameter 102.1 25.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

6.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at VDD = 3.3 V, data rate = 128 SPS, and full-scale input range (FSR) = ±2.048 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Common-mode input impedance FSR = ±6.144 V(1) 10 MΩ FSR = ±1.024 V 3 FSR = ±0.512 V, FSR = ±0.256 V 100 Differential input impedance FSR = ±6.144 V(1) 22 MΩ FSR = ±4.096 V(1) 15 FSR = ±2.048 V 4.9 FSR = ±1.024 V 2.4 FSR = ±0.512 V, FSR = ±0.256 V 710 kΩ SYSTEM PERFORMANCE Resolution (no missing codes) 12 Bits DR Data rate 128, 250, 490, 920, 1600, 2400, 3300 SPS Data rate variation All data rates –10% 10% INL Integral nonlinearity (best fit) DR = 128 SPS, FSR = ±2.048 V 0.5 LSB Offset error (input referred) FSR = ±2.048 V, differential inputs –0.5 0 0.5 LSB FSR = ±2.048 V, single-ended inputs ±0.25 LSB Offset drift FSR = ±2.048 V 0.005 LSB/°C Offset error match Between any two inputs 0.25 LSB Gain error TA = 25°C, FSR = ±2.048 V ±0.05% 0.25% Gain drift(2) FSR = ±0.256 V 7 ppm/°CFSR = ±2.048 V 5 40 FSR = ±6.144 V 5 Gain error match Between any two gain settings –0.1% ±0.02% 0.1% Between any two inputs –0.1% ±0.05% 0.1% DIGITAL INPUTS/OUTPUTS VIL Logic input level, low GND 0.25 V VIH Logic input level, high 1 3.6 V VOL Logic output level, low IOL = 3 mA GND 0.3 V IOL Low-level output current VOL = 0.6 V 6 mA Input current GND ≤ VDigital Input ≤ VDD –10 10 µA Ci Capacitance Each pin 10 pF ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

6.5 Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at VDD = 3.3 V, data rate = 128 SPS, and full-scale input range (FSR) = ±2.048 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT AND POWER DISSIPATION IVDD Supply current Power-down 1.2 5 µA Operating 150 300 PD Power dissipation VDD = 3.3 V 0.5 mW VDD = 2.0 V 0.3 (1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 3.6 V (whichever is smaller) must be applied to this device. See Table 7-1 for more information. (2) Includes all errors from onboard PGA, ADC, and voltage reference.

6.6 I2C Timing Requirements

over operating ambient temperature range, VDD = 2 V to 3.6 V, bus capacitance ≤ 400 pF, and pullup resistor = 1 kΩ (unless otherwise noted) MIN MAX UNIT STANDARD MODE fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 4.0 µs tLOW Pulse duration, SCL low 4.7 µs tHIGH Pulse duration, SCL high 4.0 µs tSU;STA Setup time, repeated START condition 4.7 µs tHD;DAT Hold time, data 0 µs tSU;DAT Setup time, data 0.25 µs tr Rise time, SCL, SDA 1 µs tf Fall time, SCL, SDA 0.3 µs tSU;STO Setup time, STOP condition 4.0 µs tBUF Bus free time, between STOP and START conditions 4.7 µs tVD;DAT Valid time, data 3.45 µs tVD;ACK Valid time, acknowledge 3.45 µs FAST MODE fSCL SCL clock frequency 0 400 kHz tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 600 ns tLOW Pulse duration, SCL low 1300 ns tHIGH Pulse duration, SCL high 600 ns tSU;STA Setup time, repeated START condition 600 ns tHD;DAT Hold time, data 0 ns tSU;DAT Setup time, data 100 ns tr Rise time, SCL, SDA 20 300 ns tf Fall time, SCL, SDA 20 × (VDD / 5.5 V) 300 ns tSU;STO Setup time, STOP condition 600 ns tBUF Bus free time, between STOP and START conditions 1300 ns tVD;DAT Valid time, data 900 ns tVD;ACK Valid time, acknowledge 900 ns tSP Pulse duration of spikes that must be suppressed by the input filter 0 50 ns www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: ADS1014L ADS1015L

6.7 Timing Diagram

tSU;STA tHD;STA Sr 9th clock tVD;ACK 70% 30% tSU;STO P S 70% 30% 9th clocktHD;STA S 70% 30%SDA SCL tf tr tf tHD;DAT tr tSU;DAT 70% 30% tVD;DAT tHIGH . . . cont. . . . cont. SDA SCL Figure 6-1. I2C Timing Requirements ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

7 Detailed Description

7.1 Overview

The ADS101xL are very small, low-power, noise-free, 12-bit, delta-sigma ( ΔΣ) analog-to-digital converters (ADCs). The ADS101xL consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator, and an I2C interface. The ADS101xL also integrate a programmable gain amplifier (PGA) and a programmable digital comparator. Figure 7-1 and Figure 7-2 show the functional block diagrams of the ADS1014L and ADS1015L, respectively. The ADS101xL ADC core measures a differential signal, V IN, that is the difference of V (AINP) and V (AINN). The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. The ADS101xL have two available conversion modes: single-shot and continuous-conversion. In single-shot mode, the ADC performs one conversion of the input signal upon request, stores the conversion value to an internal Conversion register, and then enters a power-down state. This mode is intended to provide significant power savings in systems that only require periodic conversions or when there are long idle periods between conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recently completed conversion.

7.2 Functional Block Diagrams

12-Bit ΔƩ ADC Oscillator Figure 7-1. ADS1014L Block Diagram Comparator ALERT/RDYVoltage Reference SCL SDA ADDR ADS1015L I2C Interface 12-Bit ΔƩ ADC Oscillator PGA GND VDD MUX AIN1 AIN2 AIN0 AIN3 Figure 7-2. ADS1015L Block Diagram www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: ADS1014L ADS1015L

7.3 Feature Description

7.3.1 Multiplexer

As shown in Figure 7-3 , the ADS1015L contains an input multiplexer (MUX). Either four single-ended or two differential signals can be measured. Additionally, AIN0 and AIN1 can be measured differentially to AIN3. The multiplexer is configured by the MUX[2:0] bits in the Configuration register . When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer. VDD GND AIN0 VDD GND AIN1 VDD GND AIN2 VDD GND AIN3 AINP AINN GND ADS1015L Figure 7-3. Input Multiplexer The ADS1014L does not have an input multiplexer and can measure either one differential signal or one single-ended signal. For single-ended measurements, connect the AIN1 pin to GND externally. In subsequent sections of this document, AINP refers to AIN0 and AINN refers to AIN1 for the ADS1014L. Electrostatic discharge (ESD) diodes connected to VDD and GND protect the ADS101xL analog inputs. Keep the absolute voltage of any input within the range shown in Equation 1 to prevent the ESD diodes from turning on. GND – 0.3 V < V(AINX) < VDD + 0.3 V (1) If the voltages on the input pins can potentially violate these conditions, use external Schottky diodes and series resistors to limit the input current to safe values (see the Absolute Maximum Ratings ). Overdriving an input on the ADS1015L can affect conversions taking place on other inputs. If overdriving an input is possible, clamp the signal with external Schottky diodes. ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

7.3.2 Analog Inputs

The ADS101xL use a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AIN P and AINN. The frequency at which the input signal is sampled is called the sampling frequency or the modulator frequency (fMOD). The ADS101xL has a 1-MHz internal oscillator that is further divided by a factor of 4 to generate f MOD at 250 kHz. The capacitors used in this input stage are small, and to external circuitry, the average loading appears resistive. Figure 7-4 shows this structure. The capacitor values set the resistance and switching rate. Figure 7-5 shows the timing for the switches in Figure 7-4. During the sampling phase, switches S1 are closed. This event charges CA1 to V(AINP), CA2 to V(AINN), and CB to (V(AINP) – V(AINN)). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then discharge to approximately 0.7 V and C B discharges to 0 V. This charging draws a very small transient current from the source driving the ADS101xL analog inputs. The average value of this current can be used to calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE. Equivalent Circuit fMOD = 250 kHz ZCM ZDIFF ZCM AINN AINP 0.7 V 0.7 V CA1 CB CA2 0.7 V 0.7 V AINN AINP Figure 7-4. Simplified Analog Input Circuit tSAMPLE ON OFF OFF ON Figure 7-5. S1 and S2 Switch Timing The common-mode input impedance is measured by applying a common-mode signal to the shorted AIN P and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the full-scale range, but is approximately 6 M Ω for the default full-scale range. In Figure 7-4, the common-mode input impedance is ZCM. The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and scales with the full-scale range. In Figure 7-4, the differential input impedance is ZDIFF. Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance, the ADS101xL input impedance can affect measurement accuracy. For sources with high-output impedance, buffering can be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications. The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most applications, this input impedance drift is negligible, and can be ignored. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: ADS1014L ADS1015L

7.3.3 Full-Scale Range (FSR) and LSB Size

A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the ADS101xL. The full-scale range is configured by the PGA[2:0] bits in the Configuration register and can be set to ±6.144 V, ±4.096 V, ±2.048 V, 2 shows how to calculate the LSB size from the selected full-scale range. LSB = FSR / 216 (2) Table 7-1. Full-Scale Range and Corresponding LSB Size FSR LSB SIZE ±6.144 V(1) 187.5 μV ±4.096 V(1) 125 μV ±2.048 V 62.5 μV ±1.024 V 31.25 μV ±0.512 V 15.625 μV ±0.256 V 7.8125 μV (1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to the analog inputs of the device. Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings. The ±4.096-V and ±6.144-V full-scale range settings allow input voltages to extend up to the supply. Although in this case, or whenever the supply voltage is less than the full-scale range (for example, VDD = 3.3 V and full-scale range = ±4.096 V), a full-scale ADC output code cannot be obtained. For example, with VDD = 3.3 V and FSR = ±4.096 V, only differential signals up to V IN = ±3.3 V can be measured. The code range that represents voltages |VIN| > 3.3 V is not used in this case.

7.3.4 Voltage Reference

The ADS101xL have an integrated voltage reference. An external reference cannot be used with these devices. The ADS101xL do not use a traditional band-gap reference to generate the internal voltage reference. For that reason, the reference does not have an actual specified voltage value. Instead of using the reference voltage value and the gain setting to derive the full-scale range of the ADC, use the FSR values provided in Table 7-1 directly. Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included in the gain error and gain drift specifications in the Electrical Characteristics table.

7.3.5 Oscillator

The ADS101xL have an integrated oscillator running at 1 MHz. No external clock can be applied to operate these devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally with the oscillator frequency.

7.3.6 Output Data Rate and Conversion Time

The ADS101xL offer programmable output data rates. Use the DR[2:0] bits in the Configuration register to select output data rates of 128 SPS, 250 SPS, 490 SPS, 920 SPS, 1600 SPS, 2400 SPS, or 3300 SPS. Conversions in the ADS101xL settle within a single cycle; thus, the conversion time is equal to 1 / DR. ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

7.3.7 Digital Comparator

The ADS101xL features a programmable digital comparator that can issue an alert on the ALERT/RDY pin. The COMP_MODE bit in the Configuration register configures the comparator as either a traditional comparator or a window comparator. In traditional comparator mode, the ALERT/RDY pin asserts (active low by default) when conversion data exceed the limit set in the High-threshold register (Hi_thresh). The comparator then deasserts only when the conversion data falls below the limit set in the Low-threshold register (Lo_thresh). In window comparator mode, the ALERT/RDY pin asserts when the conversion data exceed the Hi_thresh register or fall below the Lo_thresh register value. In either window or traditional comparator mode, the comparator can be configured to latch after being asserted by the COMP_LAT bit in the Configuration register. This setting causes the assertion to remain even if the input signal is not beyond the bounds of the threshold registers. This latched assertion can only be cleared by issuing an SMBus alert response or by reading the Conversion register. The ALERT/RDY pin can be configured as active high or active low by the COMP_POL bit in the Configuration register. Figure 7-6 shows operational diagrams for both comparator modes. The comparator can also be configured to activate the ALERT/RDY pin only after a set number of successive readings exceed the threshold values set in the threshold registers (Hi_thresh and Lo_thresh). The COMP_QUE[1:0] bits in the Configuration register configure the comparator to wait for one, two, or four readings beyond the threshold before activating the ALERT/RDY pin. The COMP_QUE[1:0] bits can also disable the comparator function and put the ALERT/RDY pin into a high state. TH_H TH_L Time Time Time Successful SMBus Alert Response Successful SMBus Alert Response Latching Comparator Output Non-Latching Comparator Output Input Signal TH_H TH_L Time Time Time Successful SMBus Alert Response Latching Comparator Output Non-Latching Comparator Output Input Signal WINDOW COMPARATOR MODETRADITIONAL COMPARATOR MODE Figure 7-6. ALERT Pin Timing Diagram www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: ADS1014L ADS1015L

7.3.8 Conversion-Ready Pin

The ALERT/RDY pin can also be configured as a conversion-ready pin. Set the most-significant bit of the Hi_thresh register to 1b and the most-significant bit of the Lo_thresh register to 0b to enable the pin as a conversion-ready pin. The COMP_POL bit continues to function as expected. Set the COMP_QUE[1:0] bits to any 2-bit value other than 11b to keep the ALERT/RDY pin enabled, and to allow the conversion-ready signal to appear at the ALERT/RDY pin output. The COMP_MODE and COMP_LAT bits no longer control any function. When configured as a conversion-ready pin, ALERT/RDY continues to require a pullup resistor. As shown in Figure 7-7, the ADS101xL provides an approximate 8-µs conversion-ready pulse on the ALERT/RDY pin at the end of each conversion in continuous-conversion mode. In single-shot mode, the ALERT/RDY pin asserts low at the end of a conversion if the COMP_POL bit is set to 0b. ADS101xL Status ALERT/RDY (active high) 8 µs Converting Converting Converting Converting Conversion Ready Conversion Ready Conversion Ready Figure 7-7. Conversion-Ready Pulse in Continuous-Conversion Mode

7.3.9 SMBus Alert Response

In latching comparator mode (COMP_LAT = 1b), the ALERT/RDY pin asserts when the comparator detects a conversion that exceeds the upper or lower threshold value. This assertion is latched and can be cleared only by reading conversion data, or by issuing a successful SMBus alert response and reading the asserting device I 2C address. If conversion data exceed the upper or lower threshold values after being cleared, the ALERT/RDY pin reasserts. This assertion does not affect conversions that are already in progress. The open-drain ALERT/RDY output allows several devices to share the same interface bus. When disabled, the ALERT/RDY pin holds a high state so that the pin does not interfere with other devices on the same bus line. When the controller senses that the ALERT/RDY pin has latched, the controller issues an SMBus alert command (00011001b) to the I2C bus. Any ADS101xL devices on the I2C bus with the ALERT/RDY pins asserted respond to the command with the target address. If more than one ADS101xL on the I 2C bus assert the latched ALERT/RDY pin, arbitration during the address response portion of the SMBus alert determines which device clears assertion. The device with the lowest I2C address always wins arbitration. If a device loses arbitration, the device does not clear the comparator output pin assertion. The controller then repeats the SMBus alert response until all devices have the respective assertions cleared. In window comparator mode, the SMBus alert status bit indicates a 1b if signals exceed the high threshold, and a 0b if signals exceed the low threshold. ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

7.4 Device Functional Modes

7.4.1 Reset and Power-Up

The ADS101xL resets on power-up and sets all bits in the Configuration register to the respective default settings. The ADS101xL enters a power-down state after the reset process completes. The device interface and digital blocks are active, but no data conversions are performed. The initial power-down state of the ADS101xL relieves systems with tight power-supply requirements from encountering a surge during power-up. The ADS101xL responds to the I 2C general-call reset commands. When the ADS101xL receives a general-call reset command (06h), an internal reset is performed as if the device is powered up.

7.4.2 Operating Modes

The ADS101xL operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the Configuration register selects the respective operating mode.

7.4.2.1 Single-Shot Mode

When the MODE bit in the Configuration register is set to 1b, the ADS101xL enter a power-down state, and operate in single-shot mode. This power-down state is the default state for the ADS101xL when power is first applied. Although powered down, the devices still respond to commands. The ADS101xL remain in this power-down state until a 1b is written to the operational status (OS) bit in the Configuration register. When the OS bit is asserted, the device powers up in approximately 25 μs, resets the OS bit to 0b, and starts a single conversion. When conversion data are ready for retrieval, the device powers down again. Writing a 1b to the OS bit while a conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0b to the MODE bit in the Configuration register.

7.4.2.2 Continuous-Conversion Mode

In continuous-conversion mode (MODE bit set to 0b), the ADS101xL perform conversions continuously. When a conversion is complete, the ADS101xL place the result in the Conversion register and immediately begin another conversion. When writing new configuration settings, the currently ongoing conversion completes with the previous configuration settings. Thereafter, continuous conversions with the new configuration settings start. To switch to single-shot conversion mode, write a 1b to the MODE bit in the Configuration register or reset the device. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: ADS1014L ADS1015L

7.5 Programming

7.5.1 I2C Interface

The ADS101xL uses an inter-integrated circuit (I 2C) compatible interface for serial communication. I 2C is a 2-wire, open-drain communication interface that allows for communication between a controller device and multiple target devices on the same bus by using device addressing. Each target device on an I 2C bus must have a unique address. Communication on the I 2C bus always takes place between two devices: one acting as the controller and the other as the target. Both the controller and target can receive and transmit data, but the target can only read or write under the direction of the controller. The ADS101xL always acts as an I 2C target device. An I2C bus consists of two lines: SDA and SCL. SDA carries data and SCL provides the clock. Devices on the I2C bus drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors; thus, the bus wires are always high when a device is not driving the lines low. As a result of this configuration, two devices do not conflict. If two devices drive the bus simultaneously, there is no driver contention. See the I2C-Bus Specification and User Manual from NXP Semiconductors™ for more details.

7.5.1.1 I2C Address Selection

The ADS101xL has one address pin (ADDR) that configures the I 2C address of the device. The ADDR pin can connect to GND, VDD, SDA, or SCL (as shown in Table 7-2), which allows four different addresses to be selected with one pin. At the start of every transaction, that is between the START condition (first falling edge of SDA) and the first falling SCL edge of the address byte, the ADS101xL decodes the address configuration again. Use the GND, VDD, or SCL connections first for address selection. If the SDA connection is used for address selection, hold the SDA line low for at least 100 ns after the SCL line goes low to make sure the device decodes the address correctly during I2C communication. Table 7-2. ADDR Pin Connection and Corresponding Target Address ADDR PIN CONNECTION TARGET ADDRESS GND 1001 000b VDD 1001 001b SDA 1001 010b SCL 1001 011b

7.5.1.2 I2C Interface Speed

The ADS101xL supports the following I 2C interface speeds: Standard-mode (Sm) with bit rates up to 100 kbit/s, and fast-mode (Fm) with bit rates up to 400 kbit/s. Fast-mode plus (Fm+) and high-speed mode (Hs-mode) are not supported.

7.5.1.2.1 Serial Clock (SCL) and Serial Data (SDA)

The serial clock (SCL) line clocks data in and out of the device. The controller always drives the clock line. The ADS101xL cannot act as a controller and, as a result, can never drive SCL. The serial data (SDA) line allows for bidirectional communication between the host (the controller) and the ADS101xL (the target). When the controller reads from a ADS101xL device, the ADS101xL drives the data line; when the controller writes to a ADS101xL device, the controller drives the data line. Data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the SCL line is low. One clock pulse is generated for each data bit transferred. When in an idle state, the controller should hold SCL high. After the SDA line settles, the SCL line is brought high and then is brought low. This pulse on SCL clocks the SDA bit into the receiver shift register. ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

16 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

7.5.1.3 I2C Data Transfer Protocol

Figure 7-8 shows the format of the data transfer. The controller initiates all transactions with the ADS101xL by generating a START (S) condition. A high-to-low transition on the SDA line while SCL is high defines a START condition. The bus is considered to be busy after the START condition. Following the START condition, the controller sends the 7-bit target address corresponding to the address of the ADS101xL that the controller wants to communicate with. The controller then sends an eighth bit that is a data-direction bit (R/ W). An R/ W bit of 0b indicates a write operation, and an R/ W bit of 1b indicates a read operation. After the R/W bit, the controller generates a ninth SCLK pulse and releases the SDA line to allow the ADS101xL to acknowledge (ACK) the reception of the target address by pulling SDA low. If the device does not recognize the target address, the ADS101xL holds SDA high to indicate a not acknowledge (NACK) signal. Data transmission follows next in the process. If the transaction is a read (R/ W = 1b), the ADS101xL outputs data on SDA. If the transaction is a write (R/ W = 0b), the host outputs data on SDA. Data are transferred byte- wise, most significant bit (MSB) first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be acknowledged (with the ACK bit) by the receiver. If the transaction is a read, the controller issues the ACK bit. If the transaction is a write, the ADS101xL issues the ACK bit. The controller terminates all transactions by generating a STOP (P) condition. A low-to-high transition on the SDA line while SCL is high defines a STOP condition. The bus is considered free again t BUF (bus-free time) after the STOP condition. S P 1 - 7 8 9 1 - 8 9 1 - 8 9 ADDRESS R/W ACK from target DATA DATA ACK from receiver START Condition STOP Condition A6 – A0 D7 – D0 D7 – D0 ACK from receiver Figure 7-8. I2C Data Transfer Format

7.5.1.4 Timeout

The ADS101xL offer an I 2C timeout feature that can be used to recover communication when a serial interface transmission is interrupted. If the host initiates contact with the ADS101xL but subsequently remains idle for 25 ms before completing a command, the ADS101xL interface is reset. If the ADS101xL interface resets because of a timeout condition, the host must abort the transaction and restart the communication again by issuing a new START condition.

7.5.1.5 I2C General-Call (Software Reset)

The ADS101xL respond to the I 2C general-call address (0000 000b) if the R/ W bit is 0b. The devices acknowledge the general-call address and, if the next byte is 06h, the ADS101xL reset the internal registers and enter a power-down state. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: ADS1014L ADS1015L

7.5.2 Reading and Writing Register Data

To access a specific register from the ADS101xL, the controller must first write an appropriate value to the register address pointer bits P[1:0] in the Address Pointer register . The Address Pointer register is written to directly after the target address byte, low R/ W bit, and a successful target acknowledgment. After the Address Pointer register is written, the target acknowledges, and the controller issues a STOP or a repeated START condition.

7.5.2.1 Reading Conversion Data or the Configuration Register

Read the Conversion register or Configuration register as shown in Figure 7-9 by using two I 2C communication frames. The first frame is an I 2C write operation where the R/ W bit at the end of the target address is 0b to indicate a write. In this frame, the host sends the Address Pointer register that points to the register to read from. The second frame is an I2C read operation where the R/W bit at the end of the target address is 1b to indicate a read. The ADS101xL transmits the contents of the register in this second I2C frame. The controller can terminate the transmission after any byte by not acknowledging or issuing a START or STOP condition. When repeatedly reading the same register, the Address Pointer register does not need to be written every time again because the ADS101xL store the value of the Address Pointer register until a write operation modifies the value. S TARGET ADDRESS W A ADDRESS POINTER REGISTER A S TARGET ADDRESS R A REGISTER DATA (MSB) REGISTER DATA (LSB) A PA (1) P The controller can terminate the transmission after the first byte by not acknowledging. Figure 7-9. Reading Register Data

7.5.2.2 Writing the Configuration Register

Write the Configuration register (as shown in Figure 7-10) using a single I 2C communication frame. The R/ W bit at the end of the target address is 0b to indicate a write. The host first sends the Address Pointer register that points to the Configuration register, followed by two bytes that represent the register content to write. The ADS101xL acknowledge each received byte. S TARGET ADDRESS W A ADDRESS POINTER REGISTER A REGISTER DATA (MSB)

• ••
• •• REGISTER DATA (LSB) PA A Figure 7-10. Writing Register Data Figure 7-11 provides a legend for Figure 7-9 and Figure 7-10. S = START condition P = STOP condition A = acknowledge (SDA low) A = not acknowledge (SDA high) From controller to target From target to controller Figure 7-11. Legend for the I2C Sequence Diagrams ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

7.5.3 Data Format

The ADS101xL provides 12 bits of data in binary two's-complement format that is left-justified within the 16-bit Conversion register. A positive full-scale (+FS) input produces an output code of 7FFh and a negative full-scale (–FS) input produces an output code of 800h. The output clips at these codes for signals that exceed full-scale. Table 7-3 summarizes the ideal output codes for different input signals. Figure 7-12 shows code transitions versus input voltage. Table 7-3. Input Signal Versus Ideal Output Code INPUT SIGNAL VIN = (VAINP – VAINN) IDEAL OUTPUT CODE(1) ≥ +FS (211 – 1) / 211 7FFh +FS / 211 001h 0 000h –FS / 211 FFFh ≤ –FS 800h (1) Excludes the effects of noise, INL, offset, and gain errors. The D[11:0] bits of the Conversion register are shown. 7FF0h Output Code -FS 0 +FS Input Voltage VIN 7FE0h 0010h 0000h 8000h FFF0h 8010h -FS 2 - 1 211 +FS 2 - 1 211 . . . . . . Figure 7-12. Code Transition Diagram Note Single-ended signal measurements, where V AINN = 0 V and V AINP = 0 V to +FS, only use the positive code range from 000h to 7FFh. However, because of device offset, the ADS101xL can still output negative codes if VAINP is close to 0 V. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: ADS1014L ADS1015L

8 Register Map

The ADS101xL has four registers that are accessible through the I 2C interface using the Address Pointer register. The Conversion register contains the result of the last conversion. The Configuration register is used to change the ADS101xL operating modes and query the device status. The other two registers, Lo_thresh and Hi_thresh, set the threshold values used for the comparator function.

8.1 Address Pointer Register (address = N/A) [reset = N/A]

All four registers are accessed by writing to the Address Pointer register. Figure 8-1. Address Pointer Register 7 6 5 4 3 2 1 0 RESERVED P[1:0] W-000000b W-00b Table 8-1. Address Pointer Register Field Descriptions Bit Field Type Reset Description 7:2 Reserved W 000000b Always write 000000b 1:0 P[1:0] W 00b Register address pointer 00b : Conversion register 01b : Configuration register 10b : Lo_thresh register 11b : Hi_thresh register

8.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]

The 16-bit Conversion register contains the result of the last conversion in binary two's-complement format. Following power-up, the Conversion register is cleared to 0000h, and remains 0000h until the first conversion completes. Figure 8-2. Conversion Register 15 14 13 12 11 10 9 8 D[11:4] R-00h 7 6 5 4 3 2 1 0 D[3:0] RESERVED R-0h R-0h Table 8-2. Conversion Register Field Descriptions Bit Field Type Reset Description 15:4 D[11:0] R 000h 12-bit conversion result 3:0 Reserved R 0h Always reads back 0h ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

8.3 Configuration Register (P[1:0] = 01b) [reset = 8583h]

The 16-bit Configuration register controls the operating mode, input selection, data rate, full-scale range, and comparator modes. Figure 8-3. Configuration Register: ADS1014L 15 14 13 12 11 10 9 8 OS RESERVED PGA[2:0] MODE R/W-1b R/W-000b R/W-010b R/W-1b 7 6 5 4 3 2 1 0 DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0] R/W-100b R/W-0b R/W-0b R/W-0b R/W-11b Figure 8-4. Configuration Register: ADS1015L 15 14 13 12 11 10 9 8 OS MUX[2:0] PGA[2:0] MODE R/W-1b R/W-000b R/W-010b R/W-1b 7 6 5 4 3 2 1 0 DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0] R/W-100b R/W-0b R/W-0b R/W-0b R/W-11b Table 8-3. Configuration Register Field Descriptions Bit Field Type Reset Description

15 OS R/W 1b

Operational status or single-shot conversion start This bit determines the operational status of the device. OS can only be written when in power-down state and has no effect when a conversion is ongoing. When writing: 0b : No effect 1b : Start a single conversion (when in power-down state) When reading: 0b : Device is currently performing a conversion 1b : Device is not currently performing a conversion 14:12 MUX[2:0] R/W 000b Input multiplexer configuration (ADS1015L only) These bits configure the input multiplexer. These bits serve no function on the ADS1014L. The ADS1014L always uses inputs AINP = AIN0 and AINN = AIN1. 000b : AINP = AIN0 and AINN = AIN1 001b : AINP = AIN0 and AINN = AIN3 010b : AINP = AIN1 and AINN = AIN3 011b : AINP = AIN2 and AINN = AIN3 100b : AINP = AIN0 and AINN = GND 101b : AINP = AIN1 and AINN = GND 110b : AINP = AIN2 and AINN = GND 111b : AINP = AIN3 and AINN = GND 11:9 PGA[2:0] R/W 010b Programmable gain amplifier configuration These bits set the FSR of the programmable gain amplifier. 000b : FSR = ±6.144 V(1) 001b : FSR = ±4.096 V(1) 010b : FSR = ±2.048 V 011b : FSR = ±1.024 V 100b : FSR = ±0.512 V 101b : FSR = ±0.256 V 110b : FSR = ±0.256 V 111b : FSR = ±0.256 V

8 MODE R/W 1b

This bit controls the operating mode. 0b : Continuous-conversion mode 1b : Single-shot mode or power-down state www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: ADS1014L ADS1015L

Table 8-3. Configuration Register Field Descriptions (continued) Bit Field Type Reset Description 7:5 DR[2:0] R/W 100b Data rate These bits control the data rate setting. 000b : 128 SPS 001b : 250 SPS 010b : 490 SPS 011b : 920 SPS 100b : 1600 SPS 101b : 2400 SPS 110b : 3300 SPS 111b : 3300 SPS

4 COMP_MODE R/W 0b

This bit configures the comparator operating mode. 0b : Traditional comparator 1b : Window comparator

3 COMP_POL R/W 0b

This bit controls the polarity of the ALERT/RDY pin. 0b : Active low 1b : Active high

2 COMP_LAT R/W 0b

This bit controls whether the ALERT/RDY pin latches after being asserted or clears after conversions are within the margin of the upper and lower threshold values. 0b : Nonlatching comparator. The ALERT/RDY pin does not latch when asserted. 1b : Latching comparator. The asserted ALERT/RDY pin remains latched until conversion data are read by the controller or an appropriate SMBus alert response is sent by the controller. The device responds with an address, and is the lowest address currently asserting the ALERT/RDY bus line. 1:0 COMP_QUE[1:0] R/W 11b Comparator queue and disable These bits perform two functions. When set to 11b, the comparator is disabled and the ALERT/RDY pin is set to a high-impedance state. When set to any other value, the ALERT/RDY pin and the comparator function are enabled, and the set value determines the number of successive conversions exceeding the upper or lower threshold required before asserting the ALERT/RDY pin. 00b : Assert after one conversion 01b : Assert after two conversions 10b : Assert after four conversions 11b : Disable the comparator and set the ALERT/RDY pin to high impedance (1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to the analog inputs of the device. ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

8.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers

The upper and lower threshold values used by the comparator are stored in two 16-bit registers in two's- complement format. The comparator is implemented as a digital comparator; therefore, the values in these registers must be updated whenever the PGA settings are changed. The conversion-ready function of the ALERT/RDY pin is enabled by setting the Hi_thresh register MSB to 1b and the Lo_thresh register MSB to 0b. To use the comparator function of the ALERT/RDY pin, the Hi_thresh register value must always be greater than the Lo_thresh register value. The threshold register formats are shown in the Lo_thresh Register and Hi_thresh Register. When set to RDY mode, the ALERT/RDY pin outputs the OS bit when in single-shot mode, and provides a continuous-conversion ready pulse when in continuous-conversion mode. Figure 8-5. Lo_thresh Register 15 14 13 12 11 10 9 8 Lo_thresh[11:4] R/W-80h 7 6 5 4 3 2 1 0 Lo_thresh[3:0] RESERVED R/W-0h R-0h Figure 8-6. Hi_thresh Register 15 14 13 12 11 10 9 8 Hi_thresh[11:4] R/W-7Fh 7 6 5 4 3 2 1 0 Hi_thresh[3:0] RESERVED R/W-Fh R-Fh Table 8-4. Lo_thresh and Hi_thresh Register Field Descriptions Bit Field Type Reset Description 15:4 Lo_thresh[11:0] R/W 800h Low threshold value 15:4 Hi_thresh[11:0] R/W 7FFh High threshold value www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: ADS1014L ADS1015L

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The following sections give example circuits and suggestions for using the ADS101xL in various situations.

9.1.1 Basic Connections

Figure 9-1 shows the principle I2C connections for the ADS1015L. VDD SDA SCL GPIO Microcontroller or Microprocessor with I2C Port Inputs Selected from Configuration Register

1.8 V1-k to 10-k (typ)

0.1 μF (typ) ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015L Figure 9-1. Typical Connections of the ADS1015L The fully differential voltage input of the ADS101xL is designed for connection to differential sources with moderately low source impedance, such as thermocouples and thermistors. Although the ADS101xL can read bipolar differential signals, these devices cannot accept negative voltages on either input. The ADS101xL draws transient currents during conversion. A 0.1- μF power-supply bypass capacitor supplies the momentary bursts of extra current required from the supply. The ADS101xL interfaces directly to standard mode and fast mode I 2C controllers. Any microcontroller I 2C peripheral, including controller-only and single-controller I 2C peripherals, operates with the ADS101xL. The ADS101xL does not perform clock-stretching (that is, the device never pulls the clock line low), so this function does not need to be provided for unless other clock-stretching devices are on the same I2C bus. Pullup resistors are required on both the SDA and SCL lines because I 2C bus drivers are open drain. The size of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors consume less power, but increase the transition times on the bus, thus limiting the bus speed. Lower-value resistors allow higher speed, but at the expense of higher power consumption. Long bus lines have higher capacitance and require smaller pullup resistors to compensate. Do not use resistors that are too small to avoid bus drivers being unable to pull the bus lines low. ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

24 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

9.1.2 Unused Inputs and Outputs

Follow the guidelines below for the connection of unused device pins:

• Either float unused analog inputs, or tie unused analog inputs to GND
• Either float NC (not connected) pins, or tie the NC pins to GND
• If the ALERT/RDY output pin is not used, leave this pin unconnected or tie this pin to VDD using a weak pullup resistor

9.1.3 Single-Ended Inputs

The ADS1014L can measure one, and the ADS1015L up to four, single-ended signals. The ADS1014L can measure single-ended signals by connecting AIN1 to GND externally. The ADS1015L measures single-ended signals by appropriate configuration of the MUX[2:0] bits in the Configuration register . Figure 9-2 shows a single-ended connection scheme for the ADS1015L. The single-ended signal ranges from 0 V up to positive supply or +FS, whichever is lower. Negative voltages cannot be applied to these devices because the ADS101xL can only accept positive voltages with respect to ground. The ADS101xL do not lose linearity within the input range. The ADS101xL offer a differential input voltage range of ±FSR. Single-ended configurations use only one-half of the full-scale input voltage range. Differential configurations maximize the dynamic range of the ADC, and provide better common-mode noise rejection than single-ended configurations.

0.1 F (typ)

NOTE: Digital pin connections omitted for clarity. Figure 9-2. Measuring Single-Ended Inputs The ADS1015L also allows AIN3 to serve as a common point for measurements by appropriate setting of the MUX[2:0] bits. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the ADS1015L operates with inputs, where AIN3 serves as the common point. This ability improves the usable range over the single-ended configuration because negative differential voltages are allowed when GND < V(AIN3) < VDD; however, common-mode noise attenuation is not offered.

9.1.4 Input Protection

The ADS101xL are fabricated in a small-geometry, low-voltage process. The analog inputs feature protection diodes to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS101xL can be permanently damaged by analog input voltages that exceed approximately 300 mV beyond the rails for extended periods. One way to protect against overvoltage is to place current-limiting resistors on the input lines. The ADS101xL analog inputs can withstand continuous currents as large as 10 mA. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: ADS1014L ADS1015L

9.1.5 Analog Input Filtering

Analog input filtering serves two purposes: 1. Limits the effect of aliasing during the sampling process 2. Reduces external noise from being a part of the measurement Aliasing occurs when frequency components are present in the input signal that are higher than half the sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components fold back and show up in the actual frequency band of interest below half the sampling frequency. The filter response of the digital filter, as shown in Figure 9-3, repeats at multiples of the sampling frequency, also known as the modulator frequency (fMOD). Signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. Any frequency components present in the input signal around the modulator frequency, or multiples thereof, are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter. Magnitude fMOD / 2 fMODOutput Data Rate Frequency External Antialiasing Filter Roll-Off Magnitude fMOD / 2 fMODOutput Data Rate Frequency Digital Filter Magnitude fMOD / 2 fMODOutput Data Rate Frequency Sensor Signal Unwanted Signals Unwanted Signals Aliasing of Unwanted Signals Figure 9-3. Effect of Aliasing Many sensor signals are inherently band-limited (for example, the output of a thermocouple has a limited rate of change). In this case, the sensor signal does not alias back into the pass band when using a ΔΣ ADC. However, any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass band. Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors and cellular phones. Another noise source typically exists on the printed circuit board (PCB) in the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement result. A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. Generally, any signal beyond f MOD / 2 is attenuated to a level below the noise floor of the ADC. The digital filter of the ADS101xL attenuates signals to a certain degree. In addition, noise components are usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC filter with a cutoff frequency set at the output data rate or 10 times higher is generally a good starting point for a system design. ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

26 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

9.1.6 Connecting Multiple Devices

Up to four ADS101xL devices can be connected to a single I 2C bus using different address pin configurations for each device. Use the address pin to set the ADS101xL to one of four different I 2C addresses. Use the GND, VDD, and SCL addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns after the SCL line goes low to make sure the device decodes the address correctly during I 2C communication. Figure 9-4 shows an example of four ADS101xL devices on the same I 2C bus. One set of pullup resistors is required per bus. If needed, lower the pullup resistor values to compensate for the additional bus capacitance presented by multiple devices and increased line length. 1.8 V SDA SCL Microcontroller or Microprocessor With I2C Port 1-k to 10-k (typ) I2C Pullup Resistors VDD GND ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015L ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015L ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015L ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015L NOTE: The ADS101xL power and input connections are omitted for clarity. The ADDR pin selects the I2C address. Figure 9-4. Connecting Multiple ADS101xL Devices www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: ADS1014L ADS1015L

9.1.7 Duty Cycling For Low Power

The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more samples of the internal modulator are averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates is not always required. For these applications, the ADS101xL supports duty cycling that yields significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an ADS101xL in power-down state with a data rate set to 3300 SPS can be operated by a microcontroller that instructs a single-shot conversion every 7.8 ms (128 SPS) . A conversion at 3300 SPS only requires approximately 0.3 ms , so the ADS101xL enters power-down state for the remaining 7.5 ms. In this configuration, the ADS101xL consumes approximately 1/25th the power that is otherwise consumed in continuous-conversion mode. The duty cycling rate is completely arbitrary and is defined by the controller. The ADS101xL offers lower data rates that do not implement duty cycling and also offers improved noise performance if required.

9.1.8 I2C Communication Sequence Example

This section provides an example of an I 2C communication sequence between a microcontroller (the controller) and a ADS101xL (the target) configured with a target address of 1001 000b to start a single-shot conversion and subsequently read the conversion result. 1. Write the Configuration register as shown in Figure 9-6 to configure the device (for example, when using the ADS1015L, write MUX[2:0] = 000b, PGA[2:0] = 010b, MODE = 1b, and DR[2:0] = 110b) and start a single-shot conversion (OS = 1b). S TARGET ADDRESS (1001 000b) W A ADDRESS POINTER REGISTER (01h) A CONFIGURATION DATA (85h)

• ••
• •• CONFIGURATION DATA (C0h) PA A Figure 9-5. Write the Configuration Register 2. Wait at least t = 1 / DR ± 10% for the conversion to complete. Alternatively, poll the OS bit for a 1b as shown in Figure 9-6 to determine when the conversion result is ready for retrieval. This option does not work in continuous-conversion mode because the OS bit always reads 0b. S TARGET ADDRESS (1001 000b) R A CONFIGURATION DATA (MSB) CONFIGURATION DATA (LSB) A PA (1) Figure 9-6. Read the Configuration Register to Check for OS = 1b 3. Then, as shown in Figure 9-7, read the Conversion register. S TARGET ADDRESS (1001 000b) W A ADDRESS POINTER REGISTER (00h) A S TARGET ADDRESS (1001 000b) R A CONVERSION DATA (MSB) CONVERSION DATA (LSB) A PA (1) P Figure 9-7. Read the Conversion Register 4. Start a new single-shot conversion by writing a 1b to the OS bit in the Configuration register. To save time, a new conversion can also be started (step 4) before reading the conversion result (step 3). Figure 9-8 lists a legend for Figure 9-5 to Figure 9-7. S = START condition P = STOP condition A = acknowledge (SDA low) A = not acknowledge (SDA high) From controller to target From target to controller Figure 9-8. Legend for the I2C Sequence Diagrams ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

28 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

9.2 Typical Application

This application example describes how to use the ADS1015L to monitor two different supply voltage rails in a system. Figure 9-9 shows a typical implementation for monitoring two supply voltage rails. 1.8 V 3.3 V 0.1 F ADS1015L AIN0 AIN1 AIN3 Mux Oscillator PGA 12-Bit ADC Voltage Reference GND VDD I2C Interface SDA ADDR SCL AIN2 100 0.47 F 100 0.47 F 3.3 V 1.8 V I2C Bus 1-k to 10-k Pullup ResistorsALERT/ RDY Figure 9-9. Monitoring Two Supply Voltage Rails Using the ADS1015L

9.2.1 Design Requirements

Table 9-1 lists the design requirements for this application. Table 9-1. Design Requirements DESIGN PARAMETER VALUE Device supply voltage 3.3 V Voltage rails to monitor 1.8 V, 3.3 V Measurement accuracy ±0.5% Update rate 1 ms per rail

9.2.2 Detailed Design Procedure

The analog inputs, AIN0 and AIN3, connect directly to the supply voltage rails that are monitored through RC filter resistors. Small filter resistor values of 100 Ω are chosen to reduce voltage drops (and therefore offset errors) caused by the input currents of the ADS1015L to a minimum. Filter capacitors of 0.47 µF are chosen to set the filter cutoff frequencies at 3.39 kHz. To get one reading from each of the two supplies within 2 ms, a data rate of 2400 SPS is selected. The device is set up for single-ended measurements using MUX[2:0] settings 100b and 101b. An FSR = ±4.096 V is selected to measure the 3.3-V rail. The same FSR can also be used to measure the 1.8-V rail or the FSR can be set to FSR = ±2.048 V. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: ADS1014L ADS1015L

9.2.3 Application Curve

The measurement results in Figure 9-10 show that the two supplies can be measured with ±0.5% accuracy over the complete operating ambient temperature range without any offset or gain calibration. Temperature (qC) Measurement Error (%) -40 -20 0 20 40 60 80 100 -0.1 -0.075 -0.05 -0.025 0.025 0.05 0.075 0.1

3.3 V rail monitor

1.8 V rail monitor

Figure 9-10. Measurement Error vs Temperature

9.3 Power Supply Recommendations

The device requires a single unipolar supply, VDD, to power both the analog and digital circuitry of the device.

9.3.1 Power-Supply Sequencing

Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up reset process to complete.

9.3.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. As shown in Figure 9-11, VDD must be decoupled with at least a 0.1-µF capacitor. The 0.1- μF bypass capacitor supplies the momentary bursts of extra current required from the supply when the device is converting. Place the bypass capacitor as close to the power-supply pin of the device as possible using low-impedance connections. Use multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, do not use vias to connect capacitors to the device pins for better noise immunity. Using multiple vias in parallel lowers the overall inductance, and is beneficial for connections to ground planes. VDD 0.1 μF ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 TI Device Figure 9-11. ADS1015L Power-Supply Decoupling ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

30 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

9.4 Layout

9.4.1 Layout Guidelines

Employ best design practices when laying out a printed circuit board (PCB) for both analog and digital components. For optimal performance, separate the analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. Figure 9-12 shows an example of good component placement. Although Figure 9-12 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component. Device Microcontroller Signal Conditioning (RC Filters and Amplifiers) Supply Generation Connector or Antenna Ground Fill or Ground Plane Optional: SplitGround Cut Ground Fill or Ground Plane Optional: SplitGround Cut Interface Transceiver Ground Fill or Ground Plane Ground Fill or Ground Plane Figure 9-12. System Component Placement The following outlines some basic recommendations for the layout of the ADS101xL to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout.

• Separate analog and digital signals. To start, partition the board into analog and digital sections where the layout permits. Route digital lines away from analog lines. This placement prevents digital noise from coupling back into analog signals.
• Fill void areas on signal layers with ground fill.
• Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing right next to the signal trace, the current must find another path to return to the source and complete the circuit. A longer return current path increases the chance that the signal radiates. Sensitive signals are more susceptible to EMI interference.
• Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active device yields the best results.
• Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react with the input bias current and cause an added error voltage. Reduce the loop area enclosed by the source signal and the return current to reduce the inductance in the path. Reduce the inductance to reduce the EMI pickup, and reduce the high-frequency impedance observed by the device.
• Differential inputs must be matched for both the inputs going to the measurement source.
• Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best input combinations for differential measurements use adjacent analog input lines (such as AIN0, AIN1 and AIN2, AIN3). The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G (NPO), which have stable properties and low-noise characteristics. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: ADS1014L ADS1015L

9.4.2 Layout Example

Figure 9-13. ADS1015L VSSOP Package ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 www.ti.com

32 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS1014L ADS1015L

10 Device and Documentation Support

10.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.3 Trademarks

NXP Semiconductors™ is a trademark of NXP Semiconductors. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES January 2024 * Initial Release

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com ADS1014L, ADS1015L SBASAV7 – JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: ADS1014L ADS1015L

www.ti.com 10-Apr-2025 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADS1014LIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 014L Samples ADS1014LIYCJR ACTIVE DSBGA YCJ 12 3000 RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 3K7X Samples ADS1015LIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 015L Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 10-Apr-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1014LIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0 ADS1015LIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP5.05 4.75

1.1 MAX

8X 0.5 10X 0.27 0.17 0.15 0.05 TYP0.23 0.13 0 - 8 0.25 GAGE PLANE 0.7 0.4 A NOTE 3 3.1 2.9 B NOTE 4 3.1 2.9 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA.

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (4.4)

0.05 MAX

0.05 MIN

10X (1.45) 10X (0.3) 8X (0.5) (R ) TYP 0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 5 6 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (4.4) 8X (0.5) 10X (0.3) 10X (1.45) (R ) TYP0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 5 6 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com PACKAGE OUTLINE C

0.35 MAX

0.125 0.075 1.05 TYP

0.7 TYP

0.35 TYP 0.35 TYP12X 0.195 0.155 B E A D 4224964/A 04/2019 DSBGA - 0.35 mm max heightYCJ0012 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C A 2 3

0.015 C A B

B C D SCALE 12.000 D: Max = E: Max = 1.462 mm, Min = 1.022 mm, Min = 1.402 mm 0.962 mm

www.ti.com EXAMPLE BOARD LAYOUT 0.0325 MIN0.0325 MAX 12X ( 0.18) (0.35) TYP (0.35) TYP ( 0.18) SOLDER MASK OPENING ( 0.18) METAL 4224964/A 04/2019 DSBGA - 0.35 mm max heightYCJ0012 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). SOLDER MASK DETAILS NOT TO SCALE SYMM SYMM C 1 2 3 A B D LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 50X NON-SOLDER MASK DEFINED EXPOSED METALSOLDER MASK OPENING SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.35) TYP (0.35) TYP 4224964/A 04/2019 DSBGA - 0.35 mm max heightYCJ0012 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL SCALE: 50X METAL TYP C 1 2 3 A B D

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated