ADS1014IRUGR.A

ADS1013 TI | Alldatasheet

Document overview

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Technical content

ADS101x Ultra-Small, Low-Power, I2C-Compatible, 3.3kSPS, 12-Bit ADCs With Internal Reference, Oscillator, and Programmable Comparator

1 Features

• Ultra-small packages: – X2QFN: 1.5mm × 2mm × 0.4mm – SOT: 2.9mm × 2.8mm × 0.6mm
• Noise-free resolution: 12 bits
• Wide supply range: 2.0V to 5.5V
• Low current consumption: 150μA (continuous-conversion mode)
• Programmable data rate: 128SPS to 3.3kSPS
• Single-cycle settling
• Internal low-drift voltage reference
• Internal oscillator
• I2C interface: Four pin-selectable addresses
• Operating temperature range: –40°C to +125°C
• Family of devices: – ADS1013: 1 single-ended (SE) or differential (DE) input – ADS1014: 1 single-ended or differential input with comparator and PGA – ADS1015: 4 single-ended or 2 differential inputs with comparator and PGA

2 Applications

• Portable instrumentation
• Battery voltage and current monitoring
• Temperature measurement systems
• Consumer electronics
• Factory automation and process control

3 Description

The ADS1013, ADS1014, and ADS1015 ( ADS101x) are precision, low-power, 12-bit, I 2C-compatible, analog-to-digital converters (ADCs) offered in a leadless X2QFN-10, a SOT-10, and a VSSOP-10 package. The ADS101x incorporates a low-drift voltage reference and an oscillator. The ADS1014 and ADS1015 also incorporate a programmable gain amplifier (PGA) and a digital comparator. These features, along with a wide operating supply range, are useful for power- and space-constrained, sensor measurement applications. The ADS101x perform conversions at data rates up to 3300 samples per second (SPS). The PGA offers input ranges from ±256mV to ±6.144V, allowing precise large- and small-signal measurements. The ADS1015 features an input multiplexer (MUX) that allows two differential or four single-ended input measurements. Use the digital comparator in the ADS1014 and ADS1015 for under- and overvoltage detection.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) ADS101x RUG (X2QFN, 10) 1.5mm × 2mm DYN (SOT, 10) 2.9mm × 2.8mm DGS (VSSOP, 10) 3mm × 4.9mm (1) For more information, see the Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Device Information PART NUMBER INPUT CHANNELS FEATURES(1) ADS1013 1 DE (1 SE) — ADS1014 1 DE (1 SE) PGA, comparator ADS1015 2 DE (4 SE) PGA, comparator (1) See the Device Comparison Table for details. Voltage Reference Oscillator SCL SDA ADDR ADS1013 AIN1 GND AIN0 VDD I2C Interface 12-Bit ADC ADS1014 Oscillator Comparator ALERT/ RDY PGA ADS1015 AIN0 AIN1 AIN2 AIN3 AIN1 AIN0 MUXSCL SDA ADDR I2C Interface 12-Bit ADC Voltage Reference Oscillator Comparator ALERT/ RDY PGA SCL SDA ADDR I2C Interface 12-Bit ADC Voltage Reference GND VDD GND VDD Simplified Block Diagrams ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10.2 Receiving Notification of Documentation Updates..36

12 Mechanical, Packaging, and Orderable

ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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4 Device Comparison Table

(Bits) MAXIMUM SAMPLE RATE (SPS) INPUT CHANNELS Differential (Single-Ended) PGA INTERFACE SPECIAL

FEATURES

ADS1015 12 3300 2 (4) Yes I2C Comparator ADS1014 12 3300 1 (1) Yes I2C Comparator ADS1013 12 3300 1 (1) No I2C None ADS1115 16 860 2 (4) Yes I2C Comparator ADS1114 16 860 1 (1) Yes I2C Comparator ADS1113 16 860 1(1) No I2C None ADS1018 12 3300 2 (4) Yes SPI Temperature sensor ADS1118 16 860 2 (4) Yes SPI Temperature sensor

5 Pin Configuration and Functions

6 AIN2

7 AIN3

8 VDD

9 SDA

10 SCL

Figure 5-1. RUG Package, 10-Pin (Top View) 1ADDR 10 SCL 2ALERT/RDY 9 SDA 3GND 8 VDD 4AIN0 7 AIN3 5AIN1 6 AIN2 Not to scale Figure 5-2. DYN and DGS Packages, 10-Pin (Top View) Table 5-1. Pin Functions: RUG, DYN, and DGS Packages PIN TYPE DESCRIPTION(1)NAME ADS1013 ADS1014 ADS1015 ADDR 1 1 1 Digital input I2C target address select AIN0 4 4 4 Analog input Analog input 0 AIN1 5 5 5 Analog input Analog input 1 AIN2 — — 6 Analog input Analog input 2 (ADS1015 only) AIN3 — — 7 Analog input Analog input 3 (ADS1015 only) ALERT/RDY — 2 2 Digital output Comparator output or conversion ready (ADS1014 and ADS1015 only) Open-drain output. Connect to VDD using a pullup resistor. GND 3 3 3 Analog Ground NC 2, 6, 7 6, 7 — — No connect. Leave pin floating or connect to GND. SCL 10 10 10 Digital input Serial clock input. Connect to VDD using a pullup resistor. SDA 9 9 9 Digital I/O Serial data input and output. Connect to VDD using a pullup resistor. VDD 8 8 8 Analog Power supply. Connect a 0.1μF, power-supply decoupling capacitor to GND. (1) See the Unused Inputs and Outputs section for unused pin connections. www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: ADS1013 ADS1014 ADS1015

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Power-supply voltage VDD to GND –0.3 7 V Analog input voltage AIN0, AIN1, AIN2, AIN3 GND – 0.3 VDD + 0.3 V Digital input voltage SDA, SCL, ADDR, ALERT/RDY GND – 0.3 5.5 V Input current, continuous Any pin except power supply pins –10 10 mA Temperature Operating ambient, TA –40 125 °CJunction, TJ –40 150 Storage, Tstg –60 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Power supply (VDD to GND) 2 5.5 V ANALOG INPUTS(1) FSR Full-scale input voltage range(2) (VIN = V(AINP) – V(AINN)) ±0.256 ±6.144 V V(AINx) Absolute input voltage GND VDD V DIGITAL INPUTS VDIG Digital input voltage GND 5.5 V TEMPERATURE TA Operating ambient temperature –40 125 °C (1) AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four available analog inputs. (2) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3V must be applied to the analog inputs of the device. See Table 7-1 for more information.

6.4 Thermal Information

THERMAL METRIC(1) RUG (X2QFN) DYN (SOT) DGS (VSSOP) UNIT

10 PINS 10 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 245.2 147.1 182.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.3 59.3 67.2 °C/W RθJB Junction-to-board thermal resistance 172.0 71.3 103.8 °C/W ψJT Junction-to-top characterization parameter 8.2 2.8 10.2 °C/W ψJB Junction-to-board characterization parameter 170.8 70.4 102.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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6.5 Electrical Characteristics

at VDD = 3.3V, data rate = 128SPS, and full-scale input-voltage range (FSR) = ±2.048V (unless otherwise noted); maximum and minimum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Common-mode input impedance MΩ FSR = ±1.024V 3 FSR = ±0.512V, FSR = ±0.256V 100 Differential input impedance MΩ FSR = ±2.048V 4.9 FSR = ±1.024V 2.4 FSR = ±0.512V, ±0.256V 710 kΩ SYSTEM PERFORMANCE Resolution (no missing codes) 12 Bits DR Data rate 128, 250, 490, 920, 1600, 2400, 3300 SPS Data rate variation All data rates –10% 10% INL Integral nonlinearity DR = 128SPS, FSR = ±2.048V(2) 0.5 LSB Offset error FSR = ±2.048V, differential inputs -0.5 0 0.5 LSB FSR = ±2.048V, single-ended inputs ±0.25 Offset drift over temperature FSR = ±2.048V 0.005 LSB/°C Long-term offset drift FSR = ±2.048V, TA = 125°C, 1000 hrs ±1 LSB Offset channel match Match between any two inputs 0.25 LSB Gain error(3) FSR = ±2.048V, TA = 25°C 0.05% 0.25% Gain drift over temperature(3) FSR = ±0.256V 7 ppm/°CFSR = ±2.048V 5 40 FSR = ±6.144V(1) 5 Long-term gain drift FSR = ±2.048V, TA = 125°C, 1000 hrs ±0.05 % Gain match(3) Match between any two gains 0.02% 0.1% Gain channel match Match between any two inputs 0.05% 0.1% DIGITAL INPUT/OUTPUT VIH High-level input voltage 0.7 VDD 5.5 V VIL Low-level input voltage GND 0.3 VDD V VOL Low-level output voltage IOL = 3mA GND 0.15 0.4 V Input leakage current GND < VDIG < VDD –10 10 μA www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: ADS1013 ADS1014 ADS1015

6.5 Electrical Characteristics (continued)

at VDD = 3.3V, data rate = 128SPS, and full-scale input-voltage range (FSR) = ±2.048V (unless otherwise noted); maximum and minimum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-SUPPLY IVDD Supply current Power-down TA = 25°C 0.5 2 μA Operating TA = 25°C 150 200 300 PD Power dissipation VDD = 5.0V 0.9 mWVDD = 3.3V 0.5 VDD = 2.0V 0.3 (1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3V must be applied to the analog inputs of the device. See Table 7-1 for more information. (2) Best-fit INL; covers 99% of full-scale. (3) Includes all errors from onboard PGA and voltage reference.

6.6 Timing Requirements: I2C

over operating ambient temperature range and VDD = 2.0V to 5.5V (unless otherwise noted) FAST MODE HIGH-SPEED MODE UNITMIN MAX MIN MAX fSCL SCL clock frequency 0.01 0.4 0.01 3.4 MHz tBUF Bus free time between START and STOP condition 600 160 ns tHDSTA Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns tSUSTA Setup time for a repeated START condition 600 160 ns tSUSTO Setup time for STOP condition 600 160 ns tHDDAT Data hold time 0 0 ns tSUDAT Data setup time 100 10 ns tLOW Low period of the SCL clock pin 1300 160 ns tHIGH High period for the SCL clock pin 600 60 ns tF Fall time for both SDA and SCL signals(1) 300 160 ns tR Rise time for both SDA and SCL signals(1) 300 160 ns (1) For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400pF.

6.7 Timing Diagram

Figure 6-1. I2C Interface Timing ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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6.8 Typical Characteristics

at TA = 25°C, VDD = 3.3V, FSR = ±2.048V, DR = 128SPS (unless otherwise noted) 300 250 200 150 100 Operating Current (µA) -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD = 5 V VDD = 2 V VDD = 3.3 V Figure 6-2. Operating Current vs Temperature 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Power-Down Current (µA) -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD = 3.3 V VDD = 5 V VDD = 2 V Figure 6-3. Power-Down Current vs Temperature 150 100 -50 100 150 200 250 300 Offset Error (µV) -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD = 2 V FSR = ±4.096 V FSR = ±2.048 V FSR = ±1.024 V FSR = ±0.512 V VDD = 5 V Figure 6-4. Single-Ended Offset Error vs Temperature -10 20 - Offset Voltage (µV) -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD = 3 V VDD = 2 V VDD = 5 V VDD = 4 V Figure 6-5. Differential Offset Error vs Temperature 0.05 0.04 0.03 0.02 0.01 -0.01 0.02 0.03 0.04 Gain Error (%) -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FSR = ±0.512 V FSR = 0.256 V± FSR = 1.024 V, 2.048 V, 4.096 V, and 6.144 V ± ± ± ± Figure 6-6. Gain Error vs Temperature www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: ADS1013 ADS1014 ADS1015

7 Detailed Description

7.1 Overview

The ADS101x are very small, low-power, noise-free, 12-bit, delta-sigma ( ΔΣ) analog-to-digital converters (ADCs). The ADS101x consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator and an I 2C interface. The ADS1014 and ADS1015 also integrate a programmable gain amplifier (PGA) and a programmable digital comparator. Figure 7-1 , Figure 7-2 , and Figure 7-3 show the functional block diagrams of ADS1015, ADS1014, and ADS1013, respectively. The ADS101x ADC core measures a differential signal, V IN, that is the difference of V (AINP) and V (AINN). The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. The ADS101x have two available conversion modes: single-shot and continuous-conversion. In single-shot mode, the ADC performs one conversion of the input signal upon request, stores the conversion value to an internal conversion register, and then enters a power-down state. This mode is intended to provide significant power savings in systems that only require periodic conversions or when there are long idle periods between conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recent completed conversion.

7.2 Functional Block Diagrams

Figure 7-1. ADS1015 Block Diagram Comparator ALERT/RDY PGA Voltage Reference SCL SDA ADDR ADS1014 AIN1 GND AIN0 VDD I2C Interface 12-Bit ADC Oscillator Figure 7-2. ADS1014 Block Diagram Voltage Reference SCL SDA ADDR ADS1013 AIN1 GND AIN0 VDD I2C Interface 12-Bit ADC Oscillator Figure 7-3. ADS1013 Block Diagram ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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7.3 Feature Description

7.3.1 Multiplexer

The ADS1015 contains an input multiplexer (MUX), as shown in Figure 7-4 . Either four single-ended or two differential signals can be measured. Additionally, AIN0 and AIN1 can be measured differentially to AIN3. The multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer. VDD GND AIN0 VDD GND AIN1 VDD GND AIN2 VDD GND AIN3 AINP AINN GND ADS1015 Figure 7-4. Input Multiplexer The ADS1013 and ADS1014 do not have an input multiplexer and can measure either one differential signal or one single-ended signal. For single-ended measurements, connect the AIN1 pin to GND externally. In subsequent sections of this data sheet, AIN P refers to AIN0 and AIN N refers to AIN1 for the ADS1013 and ADS1014. Electrostatic discharge (ESD) diodes connected to VDD and GND protect the ADS101x analog inputs. Keep the absolute voltage of any input within the range shown in Equation 1 to prevent the ESD diodes from turning on. GND – 0.3V < V(AINX) < VDD + 0.3V (1) If the voltages on the input pins can potentially violate these conditions, use external Schottky diodes and series resistors to limit the input current to safe values (see the Absolute Maximum Ratings table). Overdriving an input on the ADS1015 can affect conversions taking place on other inputs. If overdriving an input is possible, clamp the signal with external Schottky diodes. www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: ADS1013 ADS1014 ADS1015

7.3.2 Analog Inputs

The ADS101x use a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AIN P and AINN. The frequency at which the input signal is sampled is called the sampling frequency or the modulator frequency (f MOD). The ADS101x has a 1MHz internal oscillator that is further divided by a factor of 4 to generate f MOD at 250kHz. The capacitors used in this input stage are small, and to external circuitry, the average loading appears resistive. Figure 7-5 shows this structure. The capacitor values set the resistance and switching rate. Figure 7-6 shows the timing for the switches in Figure 7-5. During the sampling phase, switches S 1 are closed. This event charges C A1 to V (AINP), CA2 to V (AINN), and CB to (V (AINP) – V (AINN)). During the discharge phase, S 1 is first opened and then S 2 is closed. Both C A1 and CA2 then discharge to approximately 0.7V and C B discharges to 0V. This charging draws a very small transient current from the source driving the ADS101x analog inputs. The average value of this current can be used to calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE. Equivalent Circuit fMOD = 250 kHz ZCM ZDIFF ZCM AINN AINP 0.7 V 0.7 V CA1 CB CA2 0.7 V 0.7 V AINN AINP Figure 7-5. Simplified Analog Input Circuit tSAMPLE ON OFF OFF ON Figure 7-6. S1 and S2 Switch Timing The common-mode input impedance is measured by applying a common-mode signal to the shorted AIN P and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the full-scale range, but is approximately 6M Ω for the default full-scale range. In Figure 7-5, the common-mode input impedance is ZCM. The differential input impedance is measured by applying a differential signal to AIN P and AIN N inputs where one input is held at 0.7V. The current that flows through the pin connected to 0.7V is the differential current and scales with the full-scale range. In Figure 7-5, the differential input impedance is ZDIFF. Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance, the ADS101x input impedance can affect the measurement accuracy. For sources with high-output impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications. The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most applications, this input impedance drift is negligible, and can be ignored. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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7.3.3 Full-Scale Range (FSR) and LSB Size

A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the ADS1014 and ADS1015. The full-scale range is configured by bits PGA[2:0] in the Config register and can be set to ±6.144V, ±4.096V, Equation 2 shows how to calculate the LSB size from the selected full-scale range. LSB = FSR / 212 (2) Table 7-1. Full-Scale Range and Corresponding LSB Size FSR LSB SIZE ±6.144V(1) 3mV ±4.096V(1) 2mV ±2.048V 1mV ±1.024V 0.5mV ±0.512V 0.25mV ±0.256V 0.125mV (1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3V to the analog inputs of the device. The FSR of the ADS1013 is fixed at ±2.048V. Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings. If a VDD supply voltage greater than 4V is used, the ±6.144V full-scale range allows input voltages to extend up to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range), a full-scale ADC output code cannot be obtained. For example, with VDD = 3.3V and FSR = ±4.096V, only differential signals up to VIN = ±3.3V can be measured. The code range that represents voltages |V IN| > 3.3V is not used in this case.

7.3.4 Voltage Reference

The ADS101x have an integrated voltage reference. An external reference cannot be used with these devices. The ADS101x does not use a traditional band-gap reference to generate the internal voltage reference. For that reason, the reference does not have an actual specified voltage value. Instead of using the reference voltage value and the gain setting to derive the full-scale range of the ADC, use the FSR values provided in Table 7-1 directly. Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included in the gain error and gain drift specifications in the Electrical Characteristics table.

7.3.5 Oscillator

The ADS101x have an integrated oscillator running at 1MHz. No external clock can be applied to operate these devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally with the oscillator frequency.

7.3.6 Output Data Rate and Conversion Time

The ADS101x offer programmable output data rates. Use the DR[2:0] bits in the Config register to select output data rates of 128SPS, 250SPS, 490SPS, 920SPS, 1600SPS, 2400SPS, or 3300SPS. Conversions in the ADS101x settle within a single cycle; thus, the conversion time is equal to 1 / DR. www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: ADS1013 ADS1014 ADS1015

7.3.7 Digital Comparator (ADS1014 and ADS1015 Only)

The ADS1015 and ADS1014 feature a programmable digital comparator that can issue an alert on the ALERT/RDY pin. The COMP_MODE bit in the Config register configures the comparator as either a traditional comparator or a window comparator. In traditional comparator mode, the ALERT/RDY pin asserts (active low by default) when conversion data exceeds the limit set in the high-threshold register (Hi_thresh). The comparator then deasserts only when the conversion data falls below the limit set in the low-threshold register (Lo_thresh). In window comparator mode, the ALERT/RDY pin asserts when the conversion data exceed the Hi_thresh register or fall below the Lo_thresh register value. In either window or traditional comparator mode, the comparator can be configured to latch after being asserted by the COMP_LAT bit in the Config register. This setting causes the assertion to remain even if the input signal is not beyond the bounds of the threshold registers. This latched assertion can only be cleared by issuing an SMBus alert response or by reading the Conversion register. The ALERT/RDY pin can be configured as active high or active low by the COMP_POL bit in the Config register. Operational diagrams for both the comparator modes are shown in Figure 7-7. The comparator can also be configured to activate the ALERT/RDY pin only after a set number of successive readings exceed the threshold values set in the threshold registers (Hi_thresh and Lo_thresh). The COMP_QUE[1:0] bits in the Config register configures the comparator to wait for one, two, or four readings beyond the threshold before activating the ALERT/RDY pin. The COMP_QUE[1:0] bits can also disable the comparator function, and put the ALERT/RDY pin into a high state. TH_H TH_L Time Time Time Successful SMBus Alert Response Successful SMBus Alert Response Latching Comparator Output Non-Latching Comparator Output Input Signal TH_H TH_L Time Time Time Successful SMBus Alert Response Latching Comparator Output Non-Latching Comparator Output Input Signal WINDOW COMPARATOR MODETRADITIONAL COMPARATOR MODE Figure 7-7. ALERT Pin Timing Diagram ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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7.3.8 Conversion Ready Pin (ADS1014 and ADS1015 Only)

The ALERT/RDY pin can also be configured as a conversion ready pin. Set the most-significant bit of the Hi_thresh register to 1b and the most-significant bit of Lo_thresh register to 0b to enable the pin as a conversion-ready pin. The COMP_POL bit continues to function as expected. Set the COMP_QUE[1:0] bits to any 2-bit value other than 11b to keep the ALERT/RDY pin enabled, and allow the conversion-ready signal to appear at the ALERT/RDY pin output. The COMP_MODE and COMP_LAT bits no longer control any function. When configured as a conversion-ready pin, ALERT/RDY continues to require a pullup resistor. The ADS101x provide an approximately 8µs, conversion-ready pulse on the ALERT/RDY pin at the end of each conversion in continuous-conversion mode, as shown in Figure 7-8. In single-shot mode, the ALERT/RDY pin asserts low at the end of a conversion if the COMP_POL bit is set to 0b. ADS1014/5 Status ALERT/RDY (active high) 8 µs Converting Converting Converting Converting Conversion Ready Conversion Ready Conversion Ready Figure 7-8. Conversion Ready Pulse in Continuous-Conversion Mode

7.3.9 SMbus Alert Response

In latching comparator mode (COMP_LAT = 1b), the ALERT/RDY pin asserts when the comparator detects a conversion that exceeds the upper or lower threshold value. This assertion is latched and can be cleared only by reading conversion data, or by issuing a successful SMBus alert response and reading the asserting device I 2C address. If conversion data exceed the upper or lower threshold values after being cleared, the pin reasserts. This assertion does not affect conversions that are already in progress. The ALERT/RDY pin is an open-drain output. This architecture allows several devices to share the same interface bus. When disabled, the pin holds a high state so that the pin does not interfere with other devices on the same bus line. When the controller senses that the ALERT/RDY pin has latched, the controller issues an SMBus alert command (00011001b) to the I2C bus. Any ADS1014 and ADS1015 data converters on the I 2C bus with the ALERT/RDY pins asserted respond to the command with the target address. If more than one ADS101x on the I2C bus assert the latched ALERT/RDY pin, arbitration during the address response portion of the SMBus alert determines which device clears assertion. The device with the lowest I 2C address always wins arbitration. If a device loses arbitration, the device does not clear the comparator output pin assertion. The controller then repeats the SMBus alert response until all devices have the respective assertions cleared. In window comparator mode, the SMBus alert status bit indicates a 1b if signals exceed the high threshold, and a 0b if signals exceed the low threshold. www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: ADS1013 ADS1014 ADS1015

7.4 Device Functional Modes

7.4.1 Reset and Power-Up

The ADS101x reset on power-up and set all the bits in the Config register to the respective default settings. The ADS101x enter a power-down state after completion of the reset process. The device interface and digital blocks are active, but no data conversions are performed. The initial power-down state of the ADS101x relieves systems with tight power-supply requirements from encountering a surge during power-up. The ADS101x respond to the I 2C general-call reset command. When the ADS101x receive a general-call reset command (06h), an internal reset is performed as if the device is powered-up.

7.4.2 Operating Modes

The ADS101x operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the Config register selects the respective operating mode.

7.4.2.1 Single-Shot Mode

When the MODE bit in the Config register is set to 1b, the ADS101x enter a power-down state, and operate in single-shot mode. This power-down state is the default state for the ADS101x when power is first applied. Although powered down, the devices still respond to commands. The ADS101x remain in this power-down state until a 1b is written to the operational status (OS) bit in the Config register. When the OS bit is asserted, the device powers up in approximately 25 μs, resets the OS bit to 0b, and starts a single conversion. When conversion data are ready for retrieval, the device powers down again. Writing a 1b to the OS bit while a conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0b to the MODE bit in the Config register.

7.4.2.2 Continuous-Conversion Mode

In continuous-conversion mode (MODE bit set to 0b), the ADS101x perform conversions continuously. When a conversion is complete, the ADS101x place the result in the Conversion register and immediately begin another conversion. When writing new configuration settings, the currently ongoing conversion completes with the previous configuration settings. Thereafter, continuous conversions with the new configuration settings start. To switch to single-shot conversion mode, write a 1b to the MODE bit in the configuration register or reset the device.

7.4.3 Duty Cycling For Low Power

The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more samples of the internal modulator are averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates is not always required. For these applications, the ADS101x support duty cycling that yield significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an ADS101x in power-down state with a data rate set to 3300SPS can be operated by a microcontroller that instructs a single-shot conversion every 7.8ms (128SPS). A conversion at 3300SPS only requires approximately 0.3ms, so the ADS101x enter power-down state for the remaining 7.5ms. In this configuration, the ADS101x consume approximately 1/25th the power that is otherwise consumed in continuous-conversion mode. The duty cycling rate is completely arbitrary and is defined by the controller. The ADS101x offer lower data rates that do not implement duty cycling and also offer improved noise performance if required. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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7.5 Programming

7.5.1 I2C Interface

The ADS101x communicate through an I 2C interface. I 2C is a two-wire open-drain interface that supports multiple devices and controllers on a single bus. Devices on the I 2C bus only drive the bus lines low by connecting them to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors, so the bus wires are always high when no device is driving them low. As a result of this configuration, two devices cannot conflict. If two devices drive the bus simultaneously, there is no driver contention. Communication on the I 2C bus always takes place between two devices, one acting as the controller and the other as the target. Both the controller and target can read and write, but the target can only do so under the direction of the controller. Some I2C devices can act as a controller or target, but the ADS101x can only act as a target device. An I 2C bus consists of two lines: SDA and SCL. SDA carries data; SCL provides the clock. All data are transmitted across the I 2C bus in groups of eight bits. To send a bit on the I 2C bus, drive the SDA line to the appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). After the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift register. If the I2C bus is held idle for more than 25ms, the bus times out. The I 2C bus is bidirectional; that is, the SDA line is used for both transmitting and receiving data. When the controller reads from a target, the target drives the data line; when the controller writes to a target, the controller drives the data line. The controller always drives the clock line. The ADS101x cannot act as a controller, and therefore can never drive SCL. Most of the time the bus is idle; no communication occurs, and both lines are high. When communication takes place, the bus is active. Only a controller device can start a communication and initiate a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line changes state while the clock line is high, this change is either a START condition or a STOP condition. A START condition occurs when the clock line is high, and the data line goes from high to low. A STOP condition occurs when the clock line is high, and the data line goes from low to high. After the controller issues a START condition, the controller sends a byte that indicates with which target device to communicate with. This byte is called the address byte . Each device on an I 2C bus has a unique 7-bit address that the device responds to. The controller sends an address in the address byte, together with a bit that indicates whether the controller wishes to read from or write to the target device. Every byte (address and data) transmitted on the I 2C bus is acknowledged with an acknowledge bit. When the controller finishes sending a byte (eight data bits) to a target, the controller stops driving SDA and waits for the target to acknowledge the byte. The target acknowledges the byte by pulling SDA low. The controller then sends a clock pulse to clock the acknowledge bit. Similarly, when the controller completes reading a byte, the controller pulls SDA low to acknowledge this completion to the target. The controller then sends a clock pulse to clock the bit. The controller always drives the clock line. If a device is not present on the bus, and the controller attempts to address the device, the controller receives a not-acknowledge because no device is present at that address to pull the line low. A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. When the controller has finished communicating with a target, the controller can issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. The controller can also issue another START condition. When a START condition is issued while the bus is active, this condition is called a repeated start condition. The Timing Requirements section provides a timing diagram for the ADS101x I2C communication. www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: ADS1013 ADS1014 ADS1015

7.5.1.1 I2C Address Selection

The ADS101x have one address pin, ADDR, that configures the I 2C address of the device. This pin can be connected to GND, VDD, SDA, or SCL, allowing for four different addresses to be selected with one pin, as shown in Table 7-2. The state of address pin ADDR is sampled continuously. Use the GND, VDD, and SCL addresses first. If SDA is used as the device address, hold the SDA line low for at least 100ns after the SCL line goes low to make sure the device decodes the address correctly during I2C communication. Table 7-2. ADDR Pin Connection and Corresponding Target Address ADDR PIN CONNECTION TARGET ADDRESS GND 1001000b VDD 1001001b SDA 1001010b SCL 1001011b

7.5.1.2 I2C General Call

The ADS101x respond to the I 2C general call address (0000000b) if the eighth bit is 0b. The devices acknowledge the general call address and respond to commands in the second byte. If the second byte is 00000110b (06h), the ADS101x reset the internal registers and enter a power-down state.

7.5.1.3 I2C Speed Modes

The I2C bus operates at one of three speeds. Standard mode allows a clock frequency of up to 100kHz; fast mode permits a clock frequency of up to 400kHz; and high-speed mode (also called Hs mode) allows a clock frequency of up to 3.4MHz. The ADS101x are fully compatible with all three modes. No special action is required to use the ADS101x in standard or fast mode, but high-speed mode must be activated. To activate high-speed mode, send a special address byte of 00001xxxb following the START condition, where xxx are bits unique to the Hs-capable controller. This byte is called the Hs controller code, and is different from normal address bytes; the eighth bit does not indicate read/write status. The ADS101x do not acknowledge this byte; the I2C specification prohibits acknowledgment of the Hs controller code. Upon receiving a controller code, the ADS101x switch on Hs mode filters, and communicate at up to 3.4MHz. The ADS101x switch out of Hs mode with the next STOP condition. For more information on high-speed mode, consult the I2C specification.

7.5.2 Target Mode Operations

The ADS101x act as target receivers or target transmitters. The ADS101x cannot drive the SCL line as target devices.

7.5.2.1 Receive Mode

In target receive mode, the first byte transmitted from the controller to the target consists of the 7-bit device address followed by a low R/ W bit. The next byte transmitted by the controller is the Address Pointer register . The ADS101x then acknowledge receipt of the Address Pointer register byte. The next two bytes are written to the address given by the register address pointer bits, P[1:0]. The ADS101x acknowledge each byte sent. Register bytes are sent with the most significant byte first, followed by the least significant byte.

7.5.2.2 Transmit Mode

In target transmit mode, the first byte transmitted by the controller is the 7-bit target address followed by the high R/ W bit. This byte places the target into transmit mode and indicates that the ADS101x are being read from. The next byte transmitted by the target is the most significant byte of the register that is indicated by the register address pointer bits, P[1:0]. This byte is followed by an acknowledgment from the controller. The remaining least significant byte is then sent by the target and is followed by an acknowledgment from the controller. The controller can terminate transmission after any byte by not acknowledging or issuing a START or STOP condition. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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7.5.3 Writing To and Reading From the Registers

To access a specific register from the ADS101x, the controller must first write an appropriate value to register address pointer bits P[1:0] in the Address Pointer register. The Address Pointer register is written to directly after the target address byte, low R/W bit, and a successful target acknowledgment. After the Address Pointer register is written, the target acknowledges, and the controller issues a STOP or a repeated START condition. When reading from the ADS101x, the previous value written to bits P[1:0] determines the register that is read. To change which register is read, a new value must be written to P[1:0]. To write a new value to P[1:0], the controller issues a target address byte with the R/ W bit low, followed by the Address Pointer register byte. No additional data has to be transmitted, and a STOP condition can be issued by the controller. The controller can now issue a START condition and send the target address byte with the R/ W bit high to begin the read. Figure 7-9 details this sequence. If repeated reads from the same register are desired, there is no need to continually send the Address Pointer register, because the ADS101x store the value of P[1:0] until modified by a write operation. However, for every write operation, the Address Pointer register must be written with the appropriate values. Frame 1: Target Address Byte Frame 2: Address Pointer Register Start By Controller ACK By ADS1013/4/5 ACK By ADS1013/4/5 Frame 3: Target Address Byte Frame 4: Data Byte 1 Read Register Start By Controller ACK By ADS1013/4/5 ACK By Controller(2) From ADS1013/4/5 1 9 1 9 1 9 1 9 SDA SCL 0 0 1 R/W 0 0 0 0 0 0 P1 P0 /c188 /c188 /c188 SDA (Continued) SCL (Continued) SDA (Continued) SCL (Continued) 1 0 0 1 0 A1 (1) (1)

0 A1(1) A0(1) R/W D15 D14 D13 D12 D11 D10 D9 D8

Frame 5: Data Byte 2 Read Register Stop By Controller ACK By Controller(3) From ADS1013/4/5 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Stop By Controller A. The values of A0 and A1 are determined by the ADDR pin. B. The controller can leave SDA high to terminate a single-byte read operation. C. The controller can leave SDA high to terminate a two-byte read operation. Figure 7-9. Timing Diagram for Reading From ADS101x www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: ADS1013 ADS1014 ADS1015

Frame 1: Target Address Byte Frame 2: Address Pointer Register Frame 4: Data Byte 2 Start By Controller ACK By ADS1013/4/5 ACK By ADS1013/4/5 ACK By ADS1013/4/5 Stop By Controller 1 9 1 D7 D6 D5 D4 D3 D2 D1 D0 Frame 3: Data Byte 1 ACK By ADS1013/4/5 D15SDA (Continued) SCL (Continued) D14 D13 D12 D11 D10 D9 D8 SDA SCL 0 0 1 0 A1(1) A0(1) R/W 0 0 0 0 0 0 P1 P0 /c188 /c188 A. The values of A0 and A1 are determined by the ADDR pin. Figure 7-10. Timing Diagram for Writing to ADS101x Frame 1: SMBus ALERT Response Address Byte Frame 2: Target Address Start By Controller ACK By ADS1013/4/5 From ADS1013/4/5 NACK By Controller Stop By Controller 1 9 1 9 SDA SCL ALERT 0 0 0 1 1 0 0 R/ W 1 0 0 1 A1 A0 Status A. The values of A0 and A1 are determined by the ADDR pin. Figure 7-11. Timing Diagram for SMBus Alert Response ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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7.5.4 Data Format

The ADS101x provide 12 bits of data in binary two's-complement format that is left-justified within the 16-bit Conversion register. A positive full-scale (+FS) input produces an output code of 7FFh and a negative full-scale (–FS) input produces an output code of 800h. The output clips at these codes for signals that exceed full-scale. Table 7-3 summarizes the ideal output codes for different input signals. Figure 7-12 shows code transitions versus input voltage. Table 7-3. Input Signal Versus Ideal Output Code INPUT SIGNAL VIN = (VAINP – VAINN) IDEAL OUTPUT CODE(1) ≥ +FS (211 – 1) / 211 7FFh +FS / 211 001h 0 000h –FS / 211 FFFh ≤ –FS 800h (1) Excludes the effects of noise, INL, offset, and gain errors. Bits D[11:0] of the conversion register are shown. 7FFhOutput Code -FS0 +FSInput Voltage VIN 7FEh001h000h800hFFFh801h -FS2 - 111211 +FS2 - 111211 Figure 7-12. Code Transition Diagram Note Single-ended signal measurements, where V AINN = 0V and V AINP = 0V to +FS, only use the positive code range from 000h to 7FFh. However, because of device offset, the ADS101x can still output negative codes in case VAINP is close to 0V. www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: ADS1013 ADS1014 ADS1015

8 Register Map

The ADS101x have four registers that are accessible through the I 2C interface using the Address Pointer register. The Conversion register contains the result of the last conversion. The Config register is used to change the ADS101x operating modes and query the status of the device. The other two registers, Lo_thresh and Hi_thresh, set the threshold values used for the comparator function, and are not available in the ADS1013. Table 8-1 lists the access codes for the ADS101x registers. Table 8-1. Register Section/Block Access Type Codes Access Type Code Description R R Read only R/W R/W Read or write W W Write only Reset or Default Value -n Value after reset or the default value Address Pointer Register (address = N/A) [reset = N/A] All four registers are accessed by writing to the Address Pointer register; see Figure 7-9. Figure 8-1. Address Pointer Register 7 6 5 4 3 2 1 0 RESERVED P[1:0] W-000000b W-00b Table 8-2. Address Pointer Register Field Descriptions Bit Field Type Reset Description 7:2 Reserved W 000000b Always write 000000b 1:0 P[1:0] W 00b Register address pointer 00b : Conversion register 01b : Config register 10b : Lo_thresh register 11b : Hi_thresh register Conversion Register (P[1:0] = 00b) [reset = 0000h] The 16-bit Conversion register contains the result of the last conversion in binary two's-complement format. Following power-up, the Conversion register is cleared to 0000h, and remains 0000h until the first conversion completes. Figure 8-2. Conversion Register 15 14 13 12 11 10 9 8 D[11:4] R-00h 7 6 5 4 3 2 1 0 D[3:0] RESERVED R-0h R-0h Table 8-3. Conversion Register Field Descriptions Bit Field Type Reset Description 15:4 D[11:0] R 000h 12-bit conversion result 3:0 Reserved R 0h Always reads back 0h ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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Config Register (P[1:0] = 01b) [reset = 8583h] The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and comparator modes. Figure 8-3. Config Register - ADS1013 15 14 13 12 11 10 9 8 OS RESERVED MODE R/W-1b R/W-000010b R/W-1b 7 6 5 4 3 2 1 0 DR[2:0] RESERVED R/W-100b R/W-00011b Figure 8-4. Config Register - ADS1014 15 14 13 12 11 10 9 8 OS RESERVED PGA[2:0] MODE R/W-1b R/W-000b R/W-010b R/W-1b 7 6 5 4 3 2 1 0 DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0] R/W-100b R/W-0b R/W-0b R/W-0b R/W-11b Figure 8-5. Config Register - ADS1015 15 14 13 12 11 10 9 8 OS MUX[2:0] PGA[2:0] MODE R/W-1b R/W-000b R/W-010b R/W-1b 7 6 5 4 3 2 1 0 DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0] R/W-100b R/W-0b R/W-0b R/W-0b R/W-11b Table 8-4. Config Register Field Descriptions Bit Field Type Reset Description

15 OS R/W 1b

Operational status or single-shot conversion start This bit determines the operational status of the device. OS can only be written when in power-down state and has no effect when a conversion is ongoing. When writing: 0b : No effect 1b : Start a single conversion (when in power-down state) When reading: 0b : Device is currently performing a conversion 1b : Device is not currently performing a conversion 14:12 MUX[2:0] R/W 000b Input multiplexer configuration (ADS1015 only) These bits configure the input multiplexer. These bits serve no function on the ADS1013 and ADS1014. ADS1013 and ADS1014 always use inputs AINP = AIN0 and AINN = AIN1. 000b : AINP = AIN0 and AINN = AIN1 (default) 001b : AINP = AIN0 and AINN = AIN3 010b : AINP = AIN1 and AINN = AIN3 011b : AINP = AIN2 and AINN = AIN3 100b : AINP = AIN0 and AINN = GND 101b : AINP = AIN1 and AINN = GND 110b : AINP = AIN2 and AINN = GND 111b : AINP = AIN3 and AINN = GND www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: ADS1013 ADS1014 ADS1015

Table 8-4. Config Register Field Descriptions (continued) Bit Field Type Reset Description 11:9 PGA[2:0] R/W 010b Programmable gain amplifier configuration These bits set the FSR of the programmable gain amplifier. These bits serve no function on the ADS1013. ADS1013 always uses FSR = ±2.048V. 010b : FSR = ±2.048V (default) 011b : FSR = ±1.024V 100b : FSR = ±0.512V 101b : FSR = ±0.256V 110b : FSR = ±0.256V 111b : FSR = ±0.256V

8 MODE R/W 1b

This bit controls the operating mode. 0b : Continuous-conversion mode 1b : Single-shot mode or power-down state (default) 7:5 DR[2:0] R/W 100b Data rate These bits control the data rate setting. 000b : 128SPS 001b : 250SPS 010b : 490SPS 011b : 920SPS 100b : 1600SPS (default) 101b : 2400SPS 110b : 3300SPS 111b : 3300SPS

4 COMP_MODE R/W 0b

Comparator mode (ADS1014 and ADS1015 only) This bit configures the comparator operating mode. This bit serves no function on the ADS1013. 0b : Traditional comparator (default) 1b : Window comparator

3 COMP_POL R/W 0b

Comparator polarity (ADS1014 and ADS1015 only) This bit controls the polarity of the ALERT/RDY pin. This bit serves no function on the ADS1013. 0b : Active low (default) 1b : Active high

2 COMP_LAT R/W 0b

Latching comparator (ADS1014 and ADS1015 only) This bit controls whether the ALERT/RDY pin latches after being asserted or clears after conversions are within the margin of the upper and lower threshold values. This bit serves no function on the ADS1013. 0b : Nonlatching comparator . The ALERT/RDY pin does not latch when asserted (default). 1b : Latching comparator. The asserted ALERT/RDY pin remains latched until conversion data are read by the controller or an appropriate SMBus alert response is sent by the controller. The device responds with an address, and is the lowest address currently asserting the ALERT/RDY bus line. 1:0 COMP_QUE[1:0] R/W 11b Comparator queue and disable (ADS1014 and ADS1015 only) These bits perform two functions. When set to 11, the comparator is disabled and the ALERT/RDY pin is set to a high-impedance state. When set to any other value, the ALERT/RDY pin and the comparator function are enabled, and the set value determines the number of successive conversions exceeding the upper or lower threshold required before asserting the ALERT/RDY pin. These bits serve no function on the ADS1013. 00b : Assert after one conversion 01b : Assert after two conversions 10b : Assert after four conversions 11b : Disable comparator and set ALERT/RDY pin to high-impedance (default) (1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3V to the analog inputs of the device. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers These two registers are applicable to the ADS1015 and ADS1014. These registers serve no purpose in the ADS1013. The upper and lower threshold values used by the comparator are stored in two 16-bit registers in two's-complement format. The comparator is implemented as a digital comparator; therefore, the values in these registers must be updated whenever the PGA settings are changed. The conversion-ready function of the ALERT/RDY pin is enabled by setting the Hi_thresh register MSB to 1b and the Lo_thresh register MSB to 0b. To use the comparator function of the ALERT/RDY pin, the Hi_thresh register value must always be greater than the Lo_thresh register value. The threshold register formats are shown in Lo_thresh register. When set to RDY mode, the ALERT/RDY pin outputs the OS bit when in single-shot mode, and provides a continuous-conversion ready pulse when in continuous-conversion mode. Figure 8-6. Lo_thresh Register 15 14 13 12 11 10 9 8 Lo_thresh[11:4] R/W-80h 7 6 5 4 3 2 1 0 Lo_thresh[3:0] RESERVED R/W-0h R-0h Table 8-5. Hi_thresh Register 15 14 13 12 11 10 9 8 Hi_thresh[11:4] R/W-7Fh 7 6 5 4 3 2 1 0 Hi_thresh[3:0] RESERVED R/W-Fh R-Fh Table 8-6. Lo_thresh and Hi_thresh Register Field Descriptions Bit Field Type Reset Description 15:4 Lo_thresh[11:0] R/W 800h Low threshold value 15:4 Hi_thresh[11:0] R/W 7FFh High threshold value www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: ADS1013 ADS1014 ADS1015

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The following sections give example circuits and suggestions for using the ADS101x in various situations.

9.1.1 Basic Connections

The principle I2C connections for the ADS1015 are shown in Figure 9-1. VDD SDA SCL GPIO Microcontroller or Microprocessor with I2C Port Inputs Selected from Configuration Register VDD1-k to 10-k (typ) Pullup Resistors ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 0.1 μF (typ) Figure 9-1. Typical Connections of the ADS1015 The fully differential voltage input of the ADS101x is ideal for connection to differential sources with moderately low source impedance, such as thermocouples and thermistors. Although the ADS101x can read bipolar differential signals, these devices cannot accept negative voltages on either input. The ADS101x draw transient currents during conversion. A 0.1 μF power-supply bypass capacitor supplies the momentary bursts of extra current required from the supply. The ADS101x interface directly to standard mode, fast mode, and high-speed mode I 2C controllers. Any microcontroller I2C peripheral, including controller-only and single-controller I 2C peripherals, operates with the ADS101x. The ADS101x does not perform clock-stretching (that is, the device never pulls the clock line low), so this function does not need to be provided for unless other clock-stretching devices are on the same I2C bus. Pullup resistors are required on both the SDA and SCL lines because I 2C bus drivers are open drain. The size of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors consume less power, but increase the transition times on the bus, thus limiting the bus speed. Lower-value resistors allow higher speed, but at the expense of higher power consumption. Long bus lines have higher capacitance and require smaller pullup resistors to compensate. Do not use resistors that are too small to avoid bus drivers being unable to pull the bus lines low. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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9.1.2 Single-Ended Inputs

The ADS1013 and ADS1014 can measure one, and the ADS1015 up to four, single-ended signals. The ADS1013 and ADS1014 can measure single-ended signals by connecting AIN1 to GND externally. The ADS1015 measures single-ended signals by appropriate configuration of the MUX[2:0] bits in the Config register. Figure 9-2 shows a single-ended connection scheme for ADS1015. The single-ended signal ranges from 0V up to positive supply or +FS, whichever is lower. Negative voltages cannot be applied to these devices because the ADS101x can only accept positive voltages with respect to ground. The ADS101x do not lose linearity within the input range. The ADS101x offer a differential input voltage range of ±FSR. Single-ended configurations use only one-half of the full-scale input voltage range. Differential configurations maximize the dynamic range of the ADC, and provide better common-mode noise rejection than single-ended configurations.

0.1 F (typ)

NOTE: Digital pin connections omitted for clarity. Figure 9-2. Measuring Single-Ended Inputs The ADS1015 also allows AIN3 to serve as a common point for measurements by appropriate setting of the MUX[2:0] bits. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the ADS1015 operates with inputs, where AIN3 serves as the common point. This ability improves the usable range over the single-ended configuration because negative differential voltages are allowed when GND < V(AIN3) < VDD; however, common-mode noise attenuation is not offered.

9.1.3 Input Protection

The ADS101x are fabricated in a small-geometry, low-voltage process. The analog inputs feature protection diodes to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS101x can be permanently damaged by analog input voltages that exceed approximately 300mV beyond the rails for extended periods. One way to protect against overvoltage is to place current-limiting resistors on the input lines. The ADS101x analog inputs can withstand continuous currents as large as 10mA.

9.1.4 Unused Inputs and Outputs

Follow the guidelines below for the connection of unused device pins:

• Either float unused analog inputs, or tie unused analog inputs to GND
• Either float NC (not connected) pins, or tie the NC pins to GND
• If the ALERT/RDY output pin is not used, leave the pin unconnected or tie the pin to VDD using a weak pullup resistor www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: ADS1013 ADS1014 ADS1015

9.1.5 Analog Input Filtering

Analog input filtering serves two purposes: 1. Limits the effect of aliasing during the sampling process 2. Reduces external noise from being a part of the measurement Aliasing occurs when frequency components are present in the input signal that are higher than half the sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components fold back and show up in the actual frequency band of interest below half the sampling frequency. The filter response of the digital filter repeats at multiples of the sampling frequency, also known as the modulator frequency (f MOD), as shown in Figure 9-3. Signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. Any frequency components present in the input signal around the modulator frequency, or multiples thereof, are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter. Magnitude fMOD / 2 fMODOutput Data Rate Frequency External Antialiasing Filter Roll-Off Magnitude fMOD / 2 fMODOutput Data Rate Frequency Digital Filter Magnitude fMOD / 2 fMODOutput Data Rate Frequency Sensor Signal Unwanted Signals Unwanted Signals Aliasing of Unwanted Signals Figure 9-3. Effect of Aliasing Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of change. In this case, the sensor signal does not alias back into the pass band when using a ΔΣ ADC. However, any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass band. Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors and cellular phones. Another noise source typically exists on the printed-circuit-board (PCB) in the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement result. A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond f MOD / 2 is attenuated to a level below the noise floor of the ADC. The digital filter of the ADS101x attenuate signals to a certain degree. In addition, noise components are usually smaller in magnitude than the actual sensor signal. Therefore, use a first-order RC filter with a cutoff frequency set at the output data rate or 10x higher as a generally good starting point for a system design. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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9.1.6 Connecting Multiple Devices

Up to four ADS101x devices can be connected to a single I 2C bus using different address pin configurations for each device. Use the address pin to set the ADS101x to one of four different I2C addresses. Use the GND, VDD, and SCL addresses first. If SDA is used as the device address, hold the SDA line low for at least 100ns after the SCL line goes low to make sure the device decodes the address correctly during I 2C communication. An example showing four ADS101x devices on the same I2C bus is shown in Figure 9-4. One set of pullup resistors is required per bus. The pullup resistor values may need to be lowered to compensate for the additional bus capacitance presented by multiple devices and increased line length. VDD SDA SCL Microcontroller or Microprocessor With I2C Port 1-k to 10-k (typ) I2C Pullup Resistors VDDGND ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 NOTE: ADS101x power and input connections omitted for clarity. The ADDR pin selects the I2C address. Figure 9-4. Connecting Multiple ADS101x Devices www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: ADS1013 ADS1014 ADS1015

9.1.7 Quick-Start Guide

This section provides a brief example of ADS101x communications. Hardware for this design includes: one ADS101x configured with an I 2C address of 1001000b; a microcontroller with an I 2C interface; discrete components such as resistors, capacitors, and serial connectors; and a 2V to 5V power supply. Figure 9-5 shows the basic hardware configuration. The ADS101x communicate with the controller (microcontroller) through an I2C interface. The controller provides a clock signal on the SCL pin and data are transferred using the SDA pin. The ADS101x never drive the SCL pin. For information on programming and debugging the microcontroller being used, see the device-specific product data sheet. The first byte sent by the controller is the ADS101x address, followed by the R/W bit that instructs the ADS101x to listen for a subsequent byte. The second byte is the Address Pointer register byte. The third and fourth bytes sent from the controller are written to the register indicated in register address pointer bits P[1:0]. See Figure 7-9 and Figure 7-10 for read and write operation timing diagrams, respectively. All read and write transactions with the ADS101x must be preceded by a START condition, and followed by a STOP condition. For example, to write to the configuration register to set the ADS101x to continuous-conversion mode and then read the conversion result, send the following bytes in this order: 1. Write to Config register:

• First byte: 10010000b (first 7-bit I2C address followed by a low R/W bit)
• Second byte: 00000001b (points to Config register)
• Third byte: 10000100b (MSB of the Config register to be written)
• Fourth byte: 10000011b (LSB of the Config register to be written) 2. Write to Address Pointer register:
• First byte: 10010000b (first 7-bit I2C address followed by a low R/W bit)
• Second byte: 00000000b (points to Conversion register) 3. Read Conversion register:
• First byte: 10010001b (first 7-bit I2C address followed by a high R/W bit)
• Second byte: the ADS101x responds with the MSB of the Conversion register
• Third byte: the ADS101x responds with the LSB of the Conversion register VDD GND SCL SDA ADDR ALERT (ADS1014/5 Only) AIN0 AIN1 AIN2 (ADS1015 Only) AIN3 (ADS1015 Only) SCL (P1.6) SDA (P1.7) I2C-Capable Controller (MSP430F2002) ADS101x 3.3 V VDD GND JTAG Serial/UART 3.3 V 10 k 0.1 µF 10 k 3.3 V 0.1 µF Figure 9-5. Basic Hardware Configuration ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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9.2 Typical Application

Shunt-based, current-measurement solutions are widely used to monitor load currents. Low-side, current-shunt measurements are independent of the bus voltage because the shunt common-mode voltage is near ground. Figure 9-6 shows an example circuit for a bidirectional, low-side, current-shunt measurement system. The load current is determined by measuring the voltage across the shunt resistor that is amplified and level-shifted by a low-drift operational amplifier, OPA333 . The OPA333 output voltage is digitized with ADS1015 and sent to the microcontroller using the I2C interface. This circuit is capable of measuring bidirectional currents flowing through the shunt resistor with great accuracy and precision. VSHUNT LOAD High-Voltage Bus RSHUNT ILOAD R2R1 VDD AINP AINN ADS1015 I2C OPA333 VDD VCM VOUT CCM1 CDIFF VINX 4-Wire Kelvin Connection CCM2 Figure 9-6. Low-Side Current Shunt Monitoring

9.2.1 Design Requirements

Table 9-1 shows the design parameters for this application. Table 9-1. Design Parameters DESIGN PARAMETER VALUE Supply voltage (VDD) 5V Voltage across shunt resistor (VSHUNT) ±50mV Output data rate (DR) ≥200 readings per second Typical measurement accuracy at TA = 25°C(1) ±0.25% (1) Does not account for inaccuracy of shunt resistor and the precision resistors used in the application.

9.2.2 Detailed Design Procedure

The first stage of the application circuit consists of an OPA333 in a noninverting summing amplifier configuration and serves two purposes: 1. To level-shift the ground-referenced signal to allow bidirectional current measurements while running off a unipolar supply. The voltage across the shunt resistor, VSHUNT, is level-shifted by a common-mode voltage, VCM, as shown in Figure 9-6. The level-shifted voltage, VINX, at the noninverting input is given by Equation 3. VINX = (VCM · R3 + VSHUNT · R4) / (R3 + R4) (3) 2. To amplify the level-shifted voltage (VINX). The OPA333 is configured in a noninverting gain configuration with the output voltage, VOUT, given by Equation 4. VOUT = VINX · (1 + R2 / R1) (4) Using Equation 3 and Equation 4, VOUT is given as a function of VSHUNT and VCM by Equation 5. VOUT = (VCM · R3 + VSHUNT · R4) / (R3 + R4) · (1 + R2 / R1) (5) www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: ADS1013 ADS1014 ADS1015

Using Equation 5 the ADC differential input voltage, before the first-order RC filter, is given by Equation 6. VOUT – VCM = VSHUNT · (1 + R2 / R1) / (1 + R4 / R3) + VCM · (R2 / R1 – R3 / R4) / (1 + R3 / R4) (6) If R1 = R4 and R2 = R3, Equation 6 is simplified to Equation 7. VOUT – VCM = VSHUNT · (1 + R2 / R1) / (1 + R4 / R3) (7)

9.2.2.1 Shunt Resistor Considerations

A shunt resistor (R SHUNT) is an accurate resistance inserted in series with the load as described in Figure 9-6. If the absolute voltage drop across the shunt, |V SHUNT|, is a larger percentage of the bus voltage, the voltage drop can reduce the overall efficiency and system performance. If |V SHUNT| is too low, measuring the small voltage drop requires careful design attention and proper selection of the ADC, operation amplifier, and precision resistors. Make sure that the absolute voltage at the shunt terminals does not result in violation of the input common-mode voltage range requirements of the operational amplifier. The power dissipation on the shunt resistor increases the temperature because of the current flowing through the resistor. To minimize the measurement errors resulting from variation in temperature, select a low-drift shunt resistor. To minimize the measurement gain error, select a shunt resistor with a low tolerance value. To remove the errors caused by stray ground resistance, use a four-wire Kelvin-connected shunt resistor; see Figure 9-6.

9.2.2.2 Operational Amplifier Considerations

The operational amplifier used for this design example requires the following features:

• Unipolar supply operation (5V)
• Low input offset voltage (< 10µV) and input offset voltage drift (< 0.5µV/°C)
• Rail-to-rail input and output capability
• Low thermal and flicker noise
• High common-mode rejection (> 100dB) The OPA333 offers all these benefits and is selected for this application.

9.2.2.3 ADC Input Common-Mode Considerations

VCM sets the VOUT common-mode voltage by appropriate selection of precision resistors R1, R2, R3, and R4. If R1 = R3, R2 = R4, and VSHUNT = 0V, VOUT is given by Equation 8. VOUT = VCM (8) If V OUT is connected to the ADC positive input (AINP) and V CM is connected to the ADC negative input (AINN), V CM appears as a common-mode voltage to the ADC. This configuration allows pseudo-differential measurements and uses the maximum dynamic range of the ADC if VCM is set at midsupply (VDD / 2). A resistor divider from VDD to GND followed by a buffer amplifier can be used to generate VCM.

9.2.2.4 Resistor (R1, R2, R3, R4) Considerations

Proper selection of resistors R1, R2, R3, and R4 is critical for meeting the overall accuracy requirements. Using Equation 6 , the offset term, V OUT-OS, and the gain term, A OUT, of the differential ADC input are represented by Equation 9 and Equation 10 respectively. The error contributions from the first-order RC filters are ignored. VOUT-OS = VCM · (R2 / R1 - R3 / R4) / (1 + R3 / R4) (9) The tolerance, drift, and linearity performance of these resistors is critical to meeting the overall accuracy requirements. In Equation 9, if R 1 = R 3 and R 2 = R 4, VOUT-OS = 0V and therefore, the common-mode voltage, ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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VCM, only contributes to level-shift V SHUNT and does not introduce any error at the differential ADC inputs. High-precision resistors provide better common-mode rejection from VCM.

9.2.2.5 Noise and Input Impedance Considerations

If v n_res represents the input-referred rms noise from all the resistors, v n_op represents the input-referred rms noise of the OPA333, and v n_ADC represents the input-referred rms noise of the ADS1015, the total input- referred noise of the entire system, vN, can be approximated by Equation 11. vN 2 = vn_res 2 + vn_op 2 + vn_ADC/ (1 + R2 / R1)2 (11) The ADC noise contribution, vn_ADC, is attenuated by the noninverting gain stage. If the gain of the noninverting gain stage is high ( ≥ 5), a good approximation for v n_res 2 is given by Equation 12. The noise contribution from resistors R2, R4, R5, and R6 when referred to the input is smaller in comparison to R1 and R3 and can be neglected for approximation purposes. vn_res 2 = 4 · k · T · (R1 + R3) · Δf (12) where

• k = Boltzmann constant
• T = Temperature (in kelvins)
• Δf = Noise bandwidth An approximation for the input impedance, R IN, of the application circuit is given by Equation 13. RIN can be modeled as a resistor in parallel with the shunt resistor, and can contribute to additional gain error. RIN = R3 + R4 (13) From Equation 12 and Equation 13, a trade-off exists between vN and RIN. If R3 increases, vn_res increases, and therefore, the total input-referred rms system noise, v N, increases. If R 3 decreases, the input impedance, R IN, drops, and causes additional gain error.

9.2.2.6 First-Order RC Filter Considerations

Although the device digital filter attenuates high-frequency noise, use a first-order, low-pass RC filter at the ADC inputs to further reject out-of-bandwidth noise and avoid aliasing. A differential low-pass RC filter formed by R5, R6, and the differential capacitor C DIFF sets the –3dB cutoff frequency, f C, given by Equation 14 . These filter resistors produce a voltage drop because of the input currents flowing into and out of the ADC. This voltage drop can contribute to an additional gain error. Limit the filter resistor values to below 1kΩ. fC = 1 / [2π · (R5 + R6) · CDIFF] (14) Two common-mode filter capacitors (C CM1 and C CM2) are also added to offer attenuation of high-frequency, common-mode noise components. Select a differential capacitor, C DIFF, that is at least an order of magnitude (10x) larger than these common-mode capacitors because mismatches in these common-mode capacitors can convert common-mode noise into differential noise. www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: ADS1013 ADS1014 ADS1015

9.2.2.7 Circuit Implementation

Table 9-2 shows the chosen values for this design. Table 9-2. Parameters PARAMETER VALUE VCM 2.5V FSR of ADC ±0.256V Output data rate 250SPS R1, R3 1kΩ(1) R2, R4 5kΩ(1) R5, R6 100Ω(1) CDIFF 0.22µF CCM1, CCM2 0.022µF (1) 1% precision resistors are used. Using Equation 5, if VSHUNT ranges from –50mV to +50mV, the application circuit produces a differential voltage ranging from –0.250V to +0.250V across the ADC inputs. The ADC is therefore configured at a FSR of ±0.256V to maximize the dynamic range of the ADC. The –3dB cutoff frequencies of the differential low-pass filter and the common-mode low-pass filters are set at 3.6kHz and 0.36kHz, respectively. RSHUNT typically ranges from 0.01m Ω to 100m Ω. Therefore, if R 1 = R 3 = 1k Ω, a good trade-off exists between the circuit input impedance and input-referred resistor noise as explained in the Noise and Input Impedance Considerations section. A simple resistor divider followed by a buffer amplifier is used to generate VCM of 2.5V from a 5V supply.

9.2.2.8 Results Summary

A precision voltage source is used to sweep V SHUNT from –50mV to +50mV. The application circuit produces a differential voltage of –250mV to +250mV across the ADC inputs. Figure 9-7 and Figure 9-8 show the measurement results. The measurements are taken at T A = 25°C. Although 1% tolerance resistors are used, the exact value of these resistors are measured with a Fluke 4.5 digit multimeter to exclude the errors due to inaccuracy of these resistors. In Figure 9-7, the x-axis represents V SHUNT and the black line represents the measured digital output voltage in mV. In Figure 9-8 , the x-axis represents V SHUNT, the black line represents the total measurement error in %, the blue line represents the total measurement error in % after excluding the errors from precision resistors and the green line represents the total measurement error in % after excluding the errors from precision resistors and performing a system offset calibration with V SHUNT = 0V. Table 9-3 shows a results summary. Table 9-3. Results Summary (1) PARAMETER VALUE Total error, including errors from 1% precision resistors 1.89% Total error, excluding errors from 1% precision resistors 0.17% Total error, after offset calibration, excluding errors from 1% precision resistors 0.11% (1) TA = 25°C, not accounting for inaccuracy of shunt resistor. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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9.2.3 Application Curves

Shunt Voltage (mV) Measured Output (mV) -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 -250 -200 -150 -100 -50 100 150 200 250 D004 Figure 9-7. Measured Output vs Shunt Voltage (VSHUNT) Shunt Voltage (mV) Measurement Error () -50 -40 -30 -20 -10 0 10 20 30 40 50 -1.75 -1.5 -1.25 -0.75 -0.5 -0.25 0.25 0.5 0.75 1.25 1.5 1.75 D005 Including all errors Excluding resistor errors Excluding resistor errors, after offset calibration Figure 9-8. Measurement Error vs Shunt Voltage (VSHUNT)

9.3 Power Supply Recommendations

The device requires a single unipolar supply, VDD, to power both the analog and digital circuitry of the device.

9.3.1 Power-Supply Sequencing

Wait approximately 50µs after VDD is stabilized before communicating with the device to allow the power-up reset process to complete.

9.3.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at least a 0.1µF capacitor, as shown in Figure 9-9. The 0.1 μF bypass capacitor supplies the momentary bursts of extra current required from the supply when the device is converting. Place the bypass capacitor as close to the power-supply pin of the device as possible using low-impedance connections. Use multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoid the use of vias for connecting the capacitors to the device pins for better noise immunity. The use of multiple vias in parallel lowers the overall inductance, and is beneficial for connections to ground planes. 0.1 µF VDD ADDR GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 TI Device ALERT/RDY Figure 9-9. ADS1015 Power-Supply Decoupling www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: ADS1013 ADS1014 ADS1015

9.4 Layout

9.4.1 Layout Guidelines

Employ best design practices when laying out a printed-circuit board (PCB) for both analog and digital components. For optimal performance, separate the analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 9-10. Although Figure 9-10 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component. Device Microcontroller Signal Conditioning (RC Filters and Amplifiers) Supply Generation Connector or Antenna Ground Fill or Ground Plane Optional: SplitGround Cut Ground Fill or Ground Plane Optional: SplitGround Cut Interface Transceiver Ground Fill or Ground Plane Ground Fill or Ground Plane Figure 9-10. System Component Placement The following outlines some basic recommendations for the layout of the ADS101x to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout.

• Separate analog and digital signals. To start, partition the board into analog and digital sections where the layout permits. Route digital lines away from analog lines. This placement prevents digital noise from coupling back into analog signals.
• Fill void areas on signal layers with ground fill.
• Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing right next to the signal trace, the current must find another path to return to the source and complete the circuit. A longer return current path increases the chance that the signal radiates. Sensitive signals are more susceptible to EMI interference.
• Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active device yields the best results.
• Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react with the input bias current and cause an added error voltage. Reduce the loop area enclosed by the source signal and the return current in order to reduce the inductance in the path. Reduce the inductance to reduce the EMI pickup, and reduce the high frequency impedance observed by the device.
• Differential inputs must be matched for both the inputs going to the measurement source.
• Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best input combinations for differential measurements use adjacent analog input lines such as AIN0, AIN1 and AIN2, AIN3. The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G (NPO), which have stable properties and low-noise characteristics. ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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9.4.2 Layout Example

Figure 9-11. ADS1015 X2QFN Package Figure 9-12. ADS1015 VSSOP Package www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: ADS1013 ADS1014 ADS1015

10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, OPAx333 1.8-V, microPower, CMOS Operational Amplifiers, Zero-Drift Series data sheet
• Texas Instruments, MSP430F20x3, MSP430F20x2, MSP430F20x1 Mixed-Signal Microcontrollers data sheet
• Texas Instruments, TIDA-00824 Human Skin Temperature Sensing for Wearable Applications Reference Design design guide

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from February 1, 2018 to January 7, 2025 (from Revision E (January 2018) to Revision F (January 2025)) Page

• Added Device Information table, added DYN package to Package Information table, and deleted last
• Moved ALERT Pin Timing Diagram figure from Conversion Ready Pin section to Digital Comparator section... ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 www.ti.com

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• Corrected cross reference to Timing Diagram for Reading From the ADS101x figure in Writing to and
• Changed bit setting notation from hexadecimal to binary where beneficial for clarity throughout Register Map
• Added dedicated Config Register tables for ADS1013, ADS1014, and ADS1015 and changed bit descriptions Changes from Revision D (December 2016) to Revision E (January 2018) Page

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com ADS1013, ADS1014, ADS1015 SBAS473F – MAY 2009 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: ADS1013 ADS1014 ADS1015

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS1013IDGSR Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRMI ADS1013IDGSR.A Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRMI ADS1013IDGSR.B Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRMI ADS1013IDGST Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRMI ADS1013IDGST.A Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRMI ADS1013IDGST.B Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRMI ADS1013IRUGR Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1013IRUGR.A Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1013IRUGR.B Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1013IRUGT Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1013IRUGT.A Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1013IRUGT.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1013IRUGTG4 Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1013IRUGTG4.A Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1013IRUGTG4.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N9J ADS1014IDGSR Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRQI ADS1014IDGSR.A Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRQI ADS1014IDGSR.B Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRQI ADS1014IDGST Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRQI ADS1014IDGST.A Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRQI ADS1014IDGST.B Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRQI ADS1014IRUGR Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J ADS1014IRUGR.A Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J ADS1014IRUGR.B Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J ADS1014IRUGT Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J ADS1014IRUGT.A Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J ADS1014IRUGT.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J ADS1014IRUGTG4 Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J ADS1014IRUGTG4.A Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS1014IRUGTG4.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N8J ADS1015IDGSR Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRPI ADS1015IDGSR.A Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRPI ADS1015IDGSR.B Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRPI ADS1015IDGST Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRPI ADS1015IDGST.A Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRPI ADS1015IDGST.B Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 BRPI ADS1015IRUGR Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J ADS1015IRUGR.A Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J ADS1015IRUGR.B Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J ADS1015IRUGT Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J ADS1015IRUGT.A Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J ADS1015IRUGT.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J ADS1015IRUGTG4 Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J ADS1015IRUGTG4.A Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J ADS1015IRUGTG4.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 N7J (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 2

www.ti.com 7-Oct-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS1013, ADS1014, ADS1015 :

• Automotive : ADS1013-Q1 , ADS1014-Q1 , ADS1015-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1013IDGSR VSSOP DGS 10 2500 367.0 367.0 38.0 ADS1013IDGST VSSOP DGS 10 250 213.0 191.0 35.0 ADS1013IRUGR X2QFN RUG 10 3000 210.0 185.0 35.0 ADS1013IRUGT X2QFN RUG 10 250 210.0 185.0 35.0 ADS1013IRUGTG4 X2QFN RUG 10 250 210.0 185.0 35.0 ADS1014IDGSR VSSOP DGS 10 2500 367.0 367.0 38.0 ADS1014IDGST VSSOP DGS 10 250 213.0 191.0 35.0 ADS1014IRUGR X2QFN RUG 10 3000 210.0 185.0 35.0 ADS1014IRUGT X2QFN RUG 10 250 210.0 185.0 35.0 ADS1014IRUGTG4 X2QFN RUG 10 250 210.0 185.0 35.0 ADS1015IDGSR VSSOP DGS 10 2500 367.0 367.0 38.0 ADS1015IDGST VSSOP DGS 10 250 213.0 191.0 35.0 ADS1015IRUGR X2QFN RUG 10 3000 210.0 185.0 35.0 ADS1015IRUGT X2QFN RUG 10 250 210.0 185.0 35.0 ADS1015IRUGTG4 X2QFN RUG 10 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 1.6 1.4 2.1 1.9 0.40 0.34 0.05 0.00 2X 1.5 6X 0.5 10X 0.45 0.35 4X 0.25 0.15 2X 0.35 0.25 4X 0.3 0.2

0.1 MIN

(0.127) TYP X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Minimum 0.1 mm solder wetting on pin side wall. Available for wettable flank version only. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 X 0.1) SYMM SYMM

0.1 C A B

0.05 C 0.05 C 0.05 C SCALE 7.500 50.000 OPTIONAL: SIDE WALL PIN DETAIL NOTE 3 AB C

www.ti.com EXAMPLE BOARD LAYOUT 6X (0.5) (R0.05) TYP

0.05 MAX

0.05 MIN

10X (0.6) 4X (0.25) (1.8) (1.3) 4X (0.2) 2X (0.3) X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 35X SEE SOLDER MASK DETAIL METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 10X (0.6) 4X (0.25) 6X (0.5) (R0.05) TYP (1.8) (1.3) 4X (0.2) 2X (0.3) X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 35X SYMM SYMM

www.ti.com PACKAGE OUTLINE C TYP5.05 4.75

1.1 MAX

8X 0.5 10X 0.27 0.17 0.15 0.05 TYP0.23 0.13 0 - 8 0.25 GAGE PLANE 0.7 0.4 A NOTE 3 3.1 2.9 B NOTE 4 3.1 2.9 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (4.4) 10X (1.45) 10X (0.3) 8X (0.5) (R ) TYP 0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 5 6 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (4.4) 8X (0.5) 10X (0.3) 10X (1.45) (R ) TYP0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 5 6 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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