ADS1015IRUGT TI1 | Alldatasheet
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/c68/c83 I C Interface Voltage Reference Oscillator SCL SDA ADDR ADS1013 AIN1 AIN0 12-Bit ADC /c68/c83 I C Interface Voltage Reference Oscillator ALERT/RDY SCL SDA ADDR PGA ComparatorADS1015 ADS1014 MUX AIN1 AIN2 AIN0 AIN3 ADS1015 Only VDD GND VDD GND ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 Ultra-Small,Low-Power,12-Bit Analog-to-DigitalConverterwithInternalReference Check forSamples: ADS1013 ADS1014 ADS1015 1FEATURES DESCRIPTION 23• ULTRA-SMALL QFN PACKAGE: The ADS1013, ADS1014, and ADS1015 are 2mm × 1,5mm × 0,4mm precisionanalog-to-digitalconverters(ADCs) with12 bitsof resolutionofferedin an ultra-small,leadless• WIDE SUPPLY RANGE: 2.0Vto5.5V QFN-10 package or an MSOP-10 package. The• LOW CURRENT CONSUMPTION: ADS1013/4/5aredesignedwithprecision,power,andContinuous Mode: Only 150μA ease of implementationin mind. The ADS1013/4/5Single-ShotMode: Auto Shut-Down featurean onboardreferenceand oscillator.Data are
- PROGRAMMABLE DATA RATE: transferredviaan I2C-compatibleserialinterface;four I2C slave addresses can be selected. The128SPS to3.3kSPS ADS1013/4/5 operate from a singlepower supply• INTERNAL LOW-DRIFT rangingfrom2.0Vto5.5V.VOLTAGE REFERENCE The ADS1013/4/5 can performconversionsat rates• INTERNAL OSCILLATOR up to 3300 samples per second (SPS).An onboard• INTERNAL PGA PGA isavailableon theADS1014 and ADS1015 that
- I2C ™ INTERFACE: Pin-SelectableAddresses offersinputranges from the supply to as low as ±256mV, allowingbothlargeand smallsignalstobe• FOUR SINGLE-ENDED OR TWO measured withhigh resolution.The ADS1015 alsoDIFFERENTIAL INPUTS (ADS1015) featuresan inputmultiplexer(MUX) thatprovidestwo• PROGRAMMABLE COMPARATOR differentialorfoursingle-endedinputs.(ADS1014 and ADS1015) The ADS1013/4/5 operate eitherin continuous conversion mode or a single-shotmode thatAPPLICATIONS automaticallypowers down aftera conversionand• PORTABLE INSTRUMENTATION greatlyreduces currentconsumption during idle• CONSUMER GOODS periods.The ADS1013/4/5 are specifiedfrom –40°C
- BATTERY MONITORING to+125°C.
- TEMPERATURE MEASUREMENT
- FACTORY AUTOMATION AND PROCESS CONTROLS Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2I2C isa trademarkofNXP Semiconductors. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications.
ORDERING INFORMATION
For themost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthis document,orsee theTIweb siteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS (1) ADS1013, ADS1014, ADS1015 UNIT VDD toGND –0.3to+5.5 V Analoginputcurrent 100,momentary mA Analoginputcurrent 10,continuous mA AnaloginputvoltagetoGND –0.3toVDD + 0.3 V SDA, SCL, ADDR, ALERT/RDY voltagetoGND –0.5to+5.5 V Maximum junctiontemperature +150 °C Storagetemperaturerange –60 to+150 °C (1) Stressesabove thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.Exposuretoabsolute maximum conditionsforextendedperiodsmay affectdevicereliability. PRODUCT FAMILY PACKAGE INPUT CHANNELS DESIGNATOR RESOLUTION MAXIMUM SAMPLE (Differential/ DEVICE MSOP/QFN (Bits) RATE (SPS) COMPARATOR PGA Single-Ended) ADS1113 BROI/N6J 16 860 No No 1/1 ADS1114 BRNI/N5J 16 860 Yes Yes 1/1 ADS1115 BOGI/N4J 16 860 Yes Yes 2/4 ADS1013 BRMI/N9J 12 3300 No No 1/1 ADS1014 BRQI/N8J 12 3300 Yes Yes 1/1 ADS1015 BRPI/N7J 12 3300 Yes Yes 2/4
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ELECTRICAL CHARACTERISTICS
Allspecificationsat–40°C to+125°C, VDD = 3.3V,and Full-Scale(FS)= ±2.048V,unlessotherwisenoted. Typicalvaluesareat+25°C. ADS1013, ADS1014, ADS1015 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scaleinputvoltage(1) VIN = (AINP)– (AINN ) ±4.096/PGA V Analoginputvoltage AINP orAINN toGND GND VDD V Differentialinputimpedance See Table2 FS = ±6.144V(1) 10 M Ω Common-mode inputimpedance FS = ±1.024V 3 M Ω FS = ±0.512V,±0.256V 100 M Ω SYSTEM PERFORMANCE Resolution No missingcodes 12 Bits 128,250, 490,920,Data rate(DR) SPS1600,2400, 3300 Data ratevariation Alldatarates –10 10 % Outputnoise See TypicalCharacteristics Integralnonlinearity DR = 128SPS, FS = ±2.048V,bestfit(2) 0.5 LSB FS = ±2.048V,differentialinputs 0 ±0.5 LSB Offseterror FS = ±2.048V,single-endedinputs ±0.25 LSB Offsetdrift FS = ±2.048V 0.005 LSB/°C Gain error(3) FS = ±2.048Vat25°C 0.05 0.25 % FS = ±0.256V 7 ppm/°C Gain drift(3) FS = ±2.048V 5 40 ppm/°C FS = ±6.144V(1) 5 ppm/°C PGA gainmatch(3) Match between any two PGA gains 0.02 0.1 % Gain match Match between any two inputs 0.05 0.1 % Offsetmatch Match between any two inputs 0.25 LSB DIGITAL INPUT/OUTPUT Logiclevel VIH 0.7VDD 5.5 V VIL GND – 0.5 0.3VDD V VOL IOL = 3mA GND 0.15 0.4 V Inputleakage IH VIH = 5.5V 10 μA IL VIL= GND 10 μA (1) Thisparameterexpressesthefull-scalerangeoftheADC scaling.Inno eventshouldmore thanVDD + 0.3Vbe appliedtothisdevice. (2) 99% offull-scale. (3) IncludesallerrorsfromonboardPGA and reference. Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
ALERT/RDY (ADS1014/5□Only) GND AIN0 AIN1 SCL SDA VDD AIN3 (ADS1015□Only) AIN2 (ADS1015□Only) ADS1013 ADS1014 ADS1015 DGS□PACKAGE MSOP-10 (TOP□VIEW) ADDR ALERT/RDY□(ADS1014/5□Only) GND AIN0 AIN1 SCL SDA VDD AIN3 (ADS1015□Only) AIN2 (ADS1015□Only) ADS1013 ADS1014 ADS1015 RUG□PACKAGE QFN-10 (TOP□VIEW) ADS1013 ADS1014 ADS1015 SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Allspecificationsat–40°C to+125°C, VDD = 3.3V,and Full-Scale(FS)= ±2.048V,unlessotherwisenoted. Typicalvaluesareat+25°C. ADS1013, ADS1014, ADS1015 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-SUPPLY REQUIREMENTS Power-supplyvoltage 2 5.5 V Power-down currentat25°C 0.5 2 μA Power-down currentup to125°C 5 μA Supplycurrent Operatingcurrentat25°C 150 200 μA Operatingcurrentup to125°C 300 μA VDD = 5.0V 0.9 mW Power dissipation VDD = 3.3V 0.5 mW VDD = 2.0V 0.3 mW TEMPERATURE Storagetemperature –60 +150 °C Specifiedtemperature –40 +125 °C PIN CONFIGURATIONS PIN DESCRIPTIONS DEVICE PIN # ADS1013 ADS1014 ADS1015 FUNCTION DESCRIPTION
1 ADDR ADDR ADDR Digitalinput I2C slaveaddressselect
2 NC (1) ALERT/RDY ALERT/RDY Digitaloutput Digitalcomparatoroutputorconversionready(NC forADS1013)
3 GND GND GND Supply Ground
4 AIN0 AIN0 AIN0 Analoginput Differentialchannel1:Positiveinputorsingle-endedchannel1 input
5 AIN1 AIN1 AIN1 Analoginput Differentialchannel1:Negativeinputorsingle-endedchannel2 input
6 NC NC AIN2 Analoginput Differentialchannel2:Positiveinputorsingle-endedchannel3 input(NC forADS1013/4) Differentialchannel2:Negativeinputorsingle-endedchannel4 input7 NC NC AIN3 Analoginput (NC forADS1013/4) 8 VDD VDD VDD Supply Power supply:2.0Vto5.5V
9 SDA SDA SDA DigitalI/O Serialdata:Transmitsand receivesdata
10 SCL SCL SCL Digitalinput Serialclockinput:Clocksdataon SDA
(1) NC pinsmay be leftfloatingortiedtoground.
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www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 TIMING REQUIREMENTS Figure1. I2C Timing Diagram Table1.I2C Timing Definitions FAST MODE HIGH-SPEED MODE PARAMETER MIN MAX MIN MAX UNIT SCL operatingfrequency fSCL 0.01 0.4 0.01 3.4 MHz Bus freetimebetween START and STOP tBUF 600 160 nscondition HoldtimeafterrepeatedSTART condition. tHDSTA 600 160 nsAfterthisperiod,thefirstclockisgenerated. Repeated START conditionsetuptime tSUSTA 600 160 ns Stopconditionsetuptime tSUSTO 600 160 ns Data holdtime tHDDAT 0 0 ns Data setuptime tSUDAT 100 10 ns SCL clocklowperiod tLOW 1300 160 ns SCL clockhighperiod tHIGH 600 60 ns Clock/datafalltime tF 300 160 ns Clock/datarisetime tR 300 160 ns Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
Operating□Current□( A) /c109 /c45 40 /c45 20 0 20 40 60 80 100 120 140 T emperature□(/c176 C) VDD =□5V VDD =□2V VDD =□3.3V 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Shutdown□Current□( A) /c109 /c45 40 /c45 20 0 20 40 60 80 100 120 140 T emperature□(/c176 C) VDD =□3.3V VDD =□2V VDD =□5V 150 100 100 150 200 250 300 /c45 /c45 /c45 /c45 /c45 /c45 Offset□Error□( V) /c109 /c45 40 /c45 20 0 20 40 60 80 100 120 140 T emperature□( C)/c176 VDD□=□2V FS□= 4.096V/c177 (1) FS□= 2.048V/c177 FS□= 1.024V/c177 FS□= 0.512V/c177 VDD□=□5V /c45 /c45 Offset□Voltage□( V) /c109 /c45 40 /c45 20 0 20 40 60 80 100 120 140 T emperature□(/c176 C) VDD =□3V VDD =□2V VDD =□5V VDD =□4V 0.05 0.04 0.03 0.02 0.01 0.01 0.02 0.03 0.04 /c45 /c45 /c45 /c45 Gain□Error□(%) /c45 40 /c45 20 0 20 40 60 80 100 120 140 T emperature□(/c176 C) FS□= 0.512V/c177 FS□= 0.256V/c177 4.096V ,□and 6.144V /c177 /c177 /c177 /c177 (1) (1) /c45 /c45 /c45 /c45 Output□Code□(LSBs) 0 2000 4000 6000 8000 10000 12000 14000 Reading□Number DR□=□3300SPS FS□= 2.048V 14k□Samples /c177 ADS1013 ADS1014 ADS1015 SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS AtTA = +25°C and VDD = 3.3V,unlessotherwisenoted. OPERATING CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs TEMPERATURE Figure2. Figure3. SINGLE-ENDED OFFSET ERROR vs TEMPERATURE (1) DIFFERENTIAL OFFSET vs TEMPERATURE Figure4. Figure5. GAIN ERROR vs TEMPERATURE NOISE PLOT Figure6. Figure7. (1) Thisparameterexpressesthefull-scalerangeoftheADC scaling.Inno eventshouldmore thanVDD + 0.3Vbe appliedtothisdevice.
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/c68/c83 I C Interface Voltage Reference Oscillator ALERT/RDY SCL SDA ADDR Gain□=□2/3, 1, 2,□4,□8,□or□16 PGA ComparatorADS1015 AIN1 AIN2 GND AIN0 AIN3 VDD MUX ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 OVERVIEW of a differential,switched-capacitorΔΣ modulatorThe ADS1013/4/5 are verysmall,low-power,12-bit, followedby a digitalfilter.Inputsignalsarecompareddelta-sigma(ΔΣ) analog-to-digitalconverters(ADCs). to the internalvoltagereference.The digitalfilterThe ADS1013/4/5 are extremelyeasy to configure receivesa high-speedbitstreamfrom the modulatorand designintoa wide varietyof applications,and and outputsa code proportionaltotheinputvoltage.allowprecisemeasurements tobe obtainedwithvery littleeffort.Both experiencedand novice users of The ADS1013/4/5 have two availableconversion dataconvertersfinddesigningwiththeADS1013/4/5 modes: single-shotmode and continuousconversion familytobe intuitiveand problem-free. mode. In single-shotmode, the ADC performsone equaltotheprogrammed datarate.Data can be readThe ADS1013/4/5 A/D core measures a differential at any time and always reflectthe most recentsignal,VIN,thatisthedifferenceofAINP and AINN .A completedconversion.MUX isavailableon theADS1015. Thisarchitecture results in a very strong attenuationof any common-mode signals.The convertercore consists Figure8. ADS1015 FunctionalBlock Diagram Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
(ADS1014/5□Only) LER AIN0 AIN1 AIN2□(ADS1015□Only) AIN3□(ADS1015□Only) SCL SDA
1 F00n
( )MSP430 ADS1 13/4/0 5 +3.3V VDD GND +3.3V JTAG Serial AR/U T +3.3V 10k/c87 10k/c87 ADS1013 ADS1014 ADS1015 SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com QUICKSTART GUIDE For example,to writeto the configurationregisterto settheADS1013/4/5 tocontinuousconversionmodeThissectionprovidesa briefexample ofADS1013/4/5 and then read the conversionresult,send thecommunications.Refertosubsequentsectionsofthis followingbytesinthisorder:datasheetformore detailedexplanations.Hardware forthisdesignincludes:one ADS1013/4/5 configured WritetoConfigregister: withan I2C address of 1001000; a microcontroller Firstbyte: 0b10010000 (first7-bitI2C addresswithan I2C interface(TIrecommends the MSP430 followedby a lowread/writebit)productline);discretecomponents such as resistors, capacitors,and serialconnectors;and a 2V to 5V Second byte:0b00000001 (pointstoConfigregister) power supply.Figure9 shows the basichardware Thirdbyte:0b00000100 (MSB of the Configregisterconfiguration. tobe written) The ADS1013/4/5 communicate with the master Fourthbyte:0b10000011 (LSB oftheConfigregister(microcontroller)throughan I2C interface.The master tobe written)providesa clocksignalon theSCL pinand dataare transferredviatheSDA pin.The ADS1013/4/5 never WritetoPointerregister: drivethe SCL pin.For informationon programming Firstbyte: 0b10010000 (first7-bitI2C addressand debuggingthe microcontrollerbeingused,refer followedby a lowread/writebit)tothedevice-specificproductdatasheet. Second byte: 0b00000000 (pointsto ConversionThe firstbyte sent by the master should be the register)ADS1013/4/5 addressfollowedby a bitthatinstructs theADS1013/4/5 tolistenfora subsequentbyte.The Read Conversion register:second byteistheregisterpointer.RefertoTable6 Firstbyte: 0b10010001 (first7-bitI2C addressfora registermap. The thirdand fourthbytessent followedby a highread/writebit)fromthemasterarewrittentotheregisterindicatedin thesecond byte.RefertoFigure16 and Figure17 for Second byte:the ADS1013/4/5 response with theread and write operation timing diagrams, MSB oftheConversionregisterrespectively.Allread and writetransactionswiththe Thirdbyte:the ADS1013/4/5 responsewiththe LSBADS1013/4/5 must be preceded by a startcondition oftheConversionregisterand followedby a stopcondition. Figure9. Basic Hardware Configuration
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www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 MULTIPLEXER Ifitispossiblethatthevoltageson theinputpinsmay violatethese conditions,externalSchottky clampThe ADS1015 containsan input multiplexer,as diodesand/orseriesresistorsmay be requiredtolimitshown inFigure10. Eitherfoursingle-endedor two the inputcurrentto safe values(see the Absolutedifferentialsignalscan be measured. Additionally, Maximum Ratingstable).AIN0 and AIN1 may be measured differentiallyto AIN3. The multiplexerisconfiguredby threebitsin Also,overdrivingone unused inputon the ADS1015 the Configregister.When single-endedsignalsare may affectconversionstakingplace on otherinput measured,thenegativeinputoftheADC isinternally pins.Ifoverdriveon unused inputsispossible,again connectedtoGND by a switchwithinthemultiplexer. itisrecommended to clamp the signalwithexternal Schottkydiodes. ANALOG INPUTS The ADS1013/4/5 use a switched-capacitorinput stagewhere capacitorsarecontinuouslychargedand then dischargedto measure the voltagebetween AINP and AINN .The capacitorsused aresmall,and to external circuitrythe average loading appears resistive.This structureisshown in Figure12. The resistanceissetby thecapacitorvaluesand therate at which they are switched.Figure11 shows the on/offsettingoftheswitchesillustratedinFigure12. Duringthe samplingphase,S1 switchesare closed. ThiseventchargesC A1 toAINP,C A2 toAINN ,and C B to (AINP – AINN ).Duringthe dischargephase,S1 is firstopened and thenS2 isclosed.Both C A1 and C A2 then discharge to approximately0.7V and C B dischargesto 0V. Thischargingdraws a verysmall transientcurrent from the source drivingtheFigure10. ADS1015 MUX ADS1013/4/5 analog inputs.The average value of thiscurrentcan be used to calculatethe effective The ADS1013 and ADS1014 do not have a impedance (Reff)where R eff= VIN/IAVERAGE . multiplexer.Either one differentialor one single-endedsignalmay be measured with these devices.For single-endedmeasurements, connect the AIN1 pin to GND. Note that in subsequent sectionsof thisdata sheet,AINP refersto AIN0 and AINN referstoAIN1 fortheADS1013 and ADS1014. When measuringsingle-endedinputsitisimportantto notethatthenegativerange oftheoutputcodes are not used. These codes are formeasuring negative Figure11. S1 and S2 Switch Timing forFigure12differentialsignalssuch as (AINP – AINN ) < 0. ESD diodes to VDD and GND protectthe inputson all threedevices(ADS1013, ADS1014, and ADS1015). To preventthe ESD diodes from turningon, the absolutevoltageon any inputmust staywithinthe followingrange: GND – 0.3V< AINx < VDD + 0.3V Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
f =□250kHzCLK ZCM ZDIFF ZCM AINN AINP 0.7V 0.7V CA1 CB CA2 0.7V 0.7V AINN AINP ADS1013 ADS1014 ADS1015 SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com Figure12. SimplifiedAnalog InputCircuit The common-mode inputimpedance ismeasured by The typicalvalueof the inputimpedance cannotbe applyinga common-mode signaltoshortedAINP and neglected.Unless the input source has a low AINN inputsand measuring the average current impedance,the ADS1013/4/5 inputimpedance may consumed by each pin.The common-mode input affectthe measurement accuracy.For sourceswith impedance changes depending on the PGA gain highoutputimpedance,bufferingmay be necessary. setting,butisapproximately6M Ω forthedefaultPGA Activebuffersintroducenoise,and also introduce gain setting.In Figure12, the common-mode input offsetand gainerrors.Allofthesefactorsshouldbe impedance isZCM . consideredinhigh-accuracyapplications. The differentialinputimpedance is measured by Because the clockoscillatorfrequencydriftsslightly applyinga differentialsignaltoAINP and AINN inputs withtemperature,theinputimpedances alsodrift.For where one inputis held at 0.7V.The currentthat many applications,thisinputimpedance driftcan be flows through the pin connected to 0.7V is the ignored,and the valuesgiveninTable 2 fortypical differentialcurrentand scales with the PGA gain inputimpedance arevalid. setting.InFigure12,thedifferentialinputimpedance isZDIFF.Table2 describesthetypicaldifferentialinput FULL-SCALE INPUT impedance. A programmablegainamplifier(PGA) isimplemented beforetheΔΣ coreoftheADS1014/5. The PGA canTable2.DifferentialInputImpedance be set to gainsof 2/3,1, 2, 4, 8, and 16. Table 3 FS (V) DIFFERENTIAL INPUT IMPEDANCE shows thecorrespondingfull-scale(FS)ranges.The ±6.144V(1) 22M Ω PGA isconfiguredby threebitsintheConfigregister. The ADS1013 has a fixedfull-scaleinputrange of±4.096V(1) 15M Ω ±2.048V. The PGA = 2/3 settingallows input±2.048V 4.9MΩ measurement to extend up to the supply voltage±1.024V 2.4MΩ when VDD islargerthan4V. Note thoughthatinthis ±0.512V 710kΩ case (aswellas forPGA = 1 and VDD < 4V),itisnot ±0.256V 710kΩ possibleto reach a full-scaleoutputcode on the Table3.PGA Gain Full-ScaleRange PGA SETTING FS (V) 2/3 ±6.144V(1) 1 ±4.096V(1) 2 ±2.048V 4 ±1.024V 8 ±0.512V 16 ±0.256V 1. Thisparameterexpressesthefull-scalerange of the ADC scaling.In no eventshouldmore than VDD + 0.3Vbe appliedtothisdevice.
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Output□Code /c45 FS /c188 0 /c188 FS Input□Voltage□(AIN AIN )/c45P N 0x7FE0 0x0001 /c188 0x0000 0x8000 0xFFF0 0x8010 /c188 /c45 FS 2 /c45 1 FS 2 /c45 1 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 DATA FORMAT The ADS1013/4/5 digitalfilterprovides some attenuationof high-frequencynoise,but the digitalThe ADS1013/4/5 provide12 bitsof data in binary Sinc filterfrequency response cannot completelytwos complement format.The positivefull-scaleinput replacean anti-aliasingfilter.For a few applications,producesan outputcode of7FF0h and thenegative some externalfilteringmay be needed; in suchfull-scaleinputproduces an outputcode of 8000h. instances,a simpleRC filterisadequate.The output clipsat these codes for signalsthat exceed full-scale.Table 4 summarizes the ideal When designingan inputfiltercircuit,be suretotake outputcodes fordifferentinputsignals.Figure13 intoaccounttheinteractionbetween thefilternetwork shows code transitionsversusinputvoltage. and theinputimpedance oftheADS1013/4/5. Table4.InputSignalversus IdealOutput Code OPERATING MODES INPUT SIGNAL, VIN The ADS1013/4/5 operate in one of two modes:(AINP – AINN ) IDEAL OUTPUT CODE (1) continuousconversionor single-shot.In continuous ≥ FS (211 – 1)/211 7FF0h conversion mode, the ADS1013/4/5 continuously +FS/211 0010h performconversions.Once a conversionhas been completed,the ADS1013/4/5 placethe resultin the0 0 Conversionregisterand immediatelybeginsanother–FS/211 FFF0h conversion.In single-shotmode, the ADS1013/4/5≤ –FS 8000h waituntiltheOS bitissethigh.Once asserted,thebit issetto'0',indicatingthata conversioniscurrentlyin1. Excludes the effectsof noise,INL, offset,and progress.Once conversiondataareready,theOS bitgainerrors. reassertsand the devicepowers down. Writinga '1' totheOS bitduringa conversionhas no effect. RESET AND POWER-UP When the ADS1013/4/5 powers up, a reset is performed. As part of the reset process, the ADS1013/4/5 setallofthebitsintheConfigregister totherespectivedefaultsettings. The ADS1013/4/5 respond to the I2C generalcall resetcommand. When the ADS1013/4/5 receivea generalcallreset,an internalresetisperformedas if thedevicehad been powered on. DUTY CYCLING FOR LOW POWER For many applications,the improvedperformanceat low data rates may not be required.For these applications,the ADS1013/4/5 supportduty cycling Figure13. ADS1013/4/5 Code TransitionDiagram that can yield significantpower savings by periodicallyrequestinghighdata ratereadingsat an effectivelylower data rate. For example, anALIASING ADS1013/4/5 offerlower data rates that do not implement duty cyclingand offerimproved noise performanceifitisneeded. Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
TH_H TH_L Time Time Time Successful SMBus□Alert Response Latching Comparator Output Non-Latching Comparator Output Input□Signal TH_H TH_L Time Time Time Successful SMBus□Alert Response Successful SMBus□Alert Response Latching Comparator Output Non-Latching Comparator Output Input□Signal ADS1013 ADS1014 ADS1015 SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com COMPARATOR (ADS1014/15 ONLY) The ADS1014/5 are each equipped with a customizablecomparatorthatcan issuean alerton the ALERT/RDY pin.This featurecan significantly reduce externalcircuitryformany applications.The comparator can be implemented as either a traditionalcomparatorora window comparatorviathe COMP_MODE bit in the Config register.When implemented as a traditionalcomparator, the ALERT/RDY pinasserts(activelow by default)when conversiondata exceed the limitset in the high thresholdregister.The comparatorthen deasserts when the inputsignalfallsbelow the low threshold registervalue.In window comparator mode, the ALERT/RDY pin assertsifconversiondata exceed the high thresholdregisteror fallbelow the low thresholdregister. Ineitherwindow or traditionalcomparatormode, the comparatorcan be configuredtolatchonce asserted by the COMP_LAT bitin the Configregister.This settingcauses the assertionto remain even ifthe inputsignalisnotbeyond thebounds ofthethreshold registers.This latchedassertioncan be clearedby issuingan SMBus alertresponseor by readingthe Conversion register.The COMP_POL bit in the Config registerconfiguresthe ALERT/RDY pin as Figure14. AlertPin Timing Diagram When activehigh or activelow.Operationaldiagrams for Configuredas a TraditionalComparator the comparatormodes are shown inFigure14 and Figure15. The comparatorcan be configuredto activatethe ALERT/RDY pin aftera set number of successive readingsexceed the threshold.The comparatorcan be configuredto waitforone, two,or fourreadings beyond the threshold before activatingthe ALERT/RDY pinby changingtheCOMP_QUE bitsin the Configregister.The COMP_QUE bitscan also disablethecomparatorfunction. CONVERSION READY PIN (ADS1014/5 ONLY) The ALERT/RDY pin can also be configuredas a conversionreadypin.Thismode ofoperationcan be realizedifthe MSB of the highthresholdregisteris setto'1'and theMSB ofthelow thresholdregisteris setto '0'.The COMP_POL bitcontinuesto function and the COMP_QUE bits can disablethe pin; however,theCOMP_MODE and COMP_LAT bitsno longercontrolany function.When configuredas a conversionready pin, ALERT/RDY continuesto require a pull-upresistor.When in continuous conversionmode, the ADS1013/4/5 providea brief (~8µs) pulseon the ALERT/RDY pin at the end of each conversion.When in single-shotshutdown mode, theALERT/RDY pinassertslow attheend of a conversioniftheCOMP_POL bitissetto'0'. Figure15. AlertPin Timing Diagram When Configuredas a Window Comparator
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www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 SMBus ALERT RESPONSE An I2C bus consistsoftwo lines,SDA and SCL. SDA afterbeingcleared,thepinreasserts.Thisassertion The I2C bus isbidirectional:theSDA lineisused for does not affectconversionsthat are already in both transmittingand receivingdata. When the progress.The ALERT/RDY pin,as withtheSDA pin, masterreadsfrom a slave,theslavedrivesthedata isan open-drainpin.Thisarchitectureallowsseveral line;when the master sends to a slave,the master devices to share the same interfacebus. When drivesthe data line.The master always drivesthe disabled,thepinholdsa highstateso thatitdoes not clock line.The ADS1013/4/5 never drive SCL, interferewithotherdeviceson thesame bus line. because they cannot act as a master. On the ADS1013/4/5,SCL isan inputonly.When the master senses thatthe ALERT/RDY pin has latched,itissues an SMBus alertcommand Most of the time the bus isidle;no communication (00011001) to the I2C bus. Any ADS1014/5 data occurs,and bothlinesarehigh.When communication converterson theI2C bus withtheALERT/RDY pins istakingplace,thebus isactive.Only masterdevices assertedrespond to the command with the slave can starta communication and initiatea START address.Thissequence isillustratedinFigure18.In conditionon the bus.Normally,the data lineisonly the event that two or more ADS1014/5 data allowedtochange statewhiletheclocklineislow.If converterspresenton the bus assertthe latched the data linechanges statewhilethe clocklineis ALERT/RDY pin, arbitrationduring the address high,itis eithera START conditionor a STOP response portionof the SMBus alertdecideswhich condition.A START conditionoccurswhen theclock deviceclearsitsassertion.The devicewiththelowest lineishighand thedatalinegoes fromhightolow.A I2C addressalwayswinsarbitration.Ifa deviceloses STOP conditionoccurswhen the clocklineishigh arbitration,itdoes notclearthecomparatoroutputpin and thedatalinegoes fromlowtohigh. indicateswhetheritwishes to read from or writetoI2C INTERFACE theslavedevice. pulsetoclockthebit.(The masteralwaysdrivestheCommunication on the I2C bus always takes place clockline.)between two devices,one actingas the master and Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com When themasterhas finishedcommunicatingwitha byte;the I2C specificationprohibitsacknowledgment slave,itmay issuea STOP condition.When a STOP of the Hs master code. Upon receivinga master conditionisissued,thebus becomes idleagain.The code, the ADS1013/4/5 switchon Hs mode filters, master may also issue another START condition. and communicate atup to3.4MHz. The ADS1013/4/5 When a START conditionisissuedwhilethe bus is switchoutofHs mode withthenextSTOP condition. active,itiscalleda repeatedSTART condition. For more informationon high-speedmode, consult See the Timing Requirementssectionfora timing theI2C specification. diagramshowingtheADS1013/4/5I2C transaction. SLAVE MODE OPERATIONS I2C ADDRESS SELECTION The ADS1013/4/5 can actas eitherslavereceiversor The ADS1013/4/5 have one addresspin,ADDR, that slave transmitters.As a slave device, the setsthe I2C address.Thispincan be connectedto ADS1013/4/5cannotdrivetheSCL line. ground,VDD, SDA, or SCL, allowingfouraddresses tobe selectedwithone pinas shown inTable5.The Receive Mode: state of the address pin ADDR is sampled Inslavereceivemode thefirstbytetransmittedfromcontinuously. the master to the slaveisthe addresswiththe R/W bitlow.This byte allowsthe slaveto be writtento.Table5.ADDR Pin Connection and The next byte transmittedby the master is theCorresponding SlaveAddress registerpointer byte. The ADS1013/4/5 then ADDR PIN SLAVE ADDRESS acknowledgereceiptoftheregisterpointerbyte.The Ground 1001000 nexttwo bytesarewrittentotheaddressgivenby the registerpointer.The ADS1013/4/5 acknowledgeeachVDD 1001001 byte sent.Registerbytes are sent with the mostSDA 1001010 significantbytefirst,followedby the leastsignificantSCL 1001011 byte. I2C GENERAL CALL TransmitMode: The ADS1013/4/5 respond to the I2C generalcall In slavetransmitmode, the firstbytetransmittedby address(0000000)iftheeighthbitis'0'.The devices themasteristhe7-bitslaveaddressfollowedby the acknowledgethegeneralcalladdressand respondto highR/W bit.Thisbyteplacestheslaveintotransmit commands inthesecond byte.Ifthesecond byteis mode and indicatesthatthe ADS1013/4/5 are being 00000110 (06h),the ADS1013/4/5 resetthe internal read from.The nextbytetransmittedby theslaveis registersand enterpower-down mode. the most significantbyte of the registerthat is indicatedby theregisterpointer.Thisbyteisfollowed by an acknowledgment from the master. TheI2C SPEED MODES ADS1013/4/5 are fullycompatiblewith all three WRITING/READING THE REGISTERSmodes. status.)The ADS1013/4/5 do not acknowledge this
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www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 When readingfrom the ADS1013/4/5,the previous POINTER REGISTER valuewrittento the Pointerregisterdeterminesthe The fourregistersare accessed by writingto theregisterthatisreadfrom.To change whichregisteris Pointerregisterbyte;see Figure16. Table 6 andread,a new value must be writtento the Pointer Table7 indicatethePointerregisterbytemap.register.To writea new valuetothePointerregister, themasterissuesa slaveaddressbytewiththeR/W Table6.RegisterAddressbitlow, followedby the Pointerregisterbyte.No BIT 1 BIT 0 REGISTERadditionaldata need to be transmitted,and a STOP conditioncan be issuedby the master.The master 0 0 Conversionregister may now issue a START conditionand send the 0 1 Configregister slaveaddressbytewiththeR/W bithightobeginthe 1 0 Lo_threshregisterread.Figure16 detailsthissequence. Ifrepeated 1 1 Hi_threshregisterreadsfromthesame registeraredesired,thereisno need to continuallysend Pointerregisterbytes, because the ADS1013/4/5 storethe value of the CONVERSION REGISTER Pointerregisteruntilit is modified by a write The 16-bitregistercontainsthe resultof the lastoperation.However, every writeoperationrequires conversion in binary twos complement format.thePointerregistertobe written. Followingresetor power-up,theConversionregister is cleared to '0',and remains '0'untilthe firstREGISTERS conversioniscompleted. The ADS1013/4/5 have four registersthat are The registerformatisshown inTable8.accessibleviathe I2C port.The Conversionregister containstheresultofthelastconversion.The Config CONFIG REGISTERregisterallowsthe user to change the ADS1013/4/5 operatingmodes and querythestatusofthedevices. The 16-bitregistercan be used to controlthe Two registers,Lo_thresh and Hi_thresh,set the ADS1013/4/5 operatingmode, inputselection,data thresholdvaluesused forthecomparatorfunction. rate,PGA settings,and comparator modes. The registerformatisshown inTable9. Table7.PointerRegisterByte (Write-Only) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 Registeraddress Table8.Conversion Register(Read-Only) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 Table9.ConfigRegister(Read/Write) BIT 15 14 13 12 11 10 9 8 NAME OS MUX2 MUX1 MUX0 PGA2 PGA1 PGA0 MODE blank BIT 7 6 5 4 3 2 1 0 NAME DR2 DR1 DR0 COMP_MODE COMP_POL COMP_LAT COMP_QUE1 COMP_QUE0 Default= 8583h. Bit[15] OS: Operationalstatus/single-shotconversionstart Thisbitdeterminestheoperationalstatusofthedevice. Thisbitcan onlybe writtenwhen inpower-down mode. Fora writestatus: 0 :No effect 1 :Begina singleconversion(when inpower-down mode) Fora readstatus: 0 :Deviceiscurrentlyperforminga conversion 1 :Deviceisnotcurrentlyperforminga conversion Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com Bits[14:12] MUX[2:0]:Inputmultiplexerconfiguration(ADS1015 only) These bitsconfiguretheinputmultiplexer.They serveno functionon theADS1013/4. 000 :AINP = AIN0 and AINN = AIN1 (default) 100 :AINP = AIN0 and AINN = GND 001 :AINP = AIN0 and AINN = AIN3 101 :AINP = AIN1 and AINN = GND 010 :AINP = AIN1 and AINN = AIN3 110 :AINP = AIN2 and AINN = GND 011 :AINP = AIN2 and AINN = AIN3 111 :AINP = AIN3 and AINN = GND Bits[11:9] PGA[2:0]:Programmable gainamplifierconfiguration(ADS1014 and ADS1015 only) These bitsconfiguretheprogrammablegainamplifier.They serveno functionon theADS1013. 010 :FS = ±2.048V(default) 110 :FS = ±0.256V 011 :FS = ±1.024V 111 :FS = ±0.256V Bit[8] MODE: Device operatingmode Thisbitcontrolsthecurrentoperationalmode oftheADS1013/4/5. 0 :Continuousconversionmode 1 :Power-down single-shotmode (default) Bits[7:5] DR[2:0]:Data rate These bitscontrolthedataratesetting. 000 :128SPS 100 :1600SPS (default) 001 :250SPS 101 :2400SPS 010 :490SPS 110 :3300SPS 011 :920SPS 111 :3300SPS Bit[4] COMP_MODE: Comparator mode (ADS1014 and ADS1015 only) Thisbitcontrolsthecomparatormode ofoperation.Itchanges whetherthecomparatorisimplementedas a traditionalcomparator(COMP_MODE = '0')oras a window comparator(COMP_MODE = '1').Itservesno functionon theADS1013. 0 :Traditionalcomparatorwithhysteresis(default) 1 :Window comparator Bit[3] COMP_POL: Comparator polarity(ADS1014 and ADS1015 only) ThisbitcontrolsthepolarityoftheALERT/RDY pin.When COMP_POL = '0'thecomparatoroutputisactive low.When COMP_POL='1' theALERT/RDY pinisactivehigh.Itservesno functionon theADS1013. 0 :Activelow(default) 1 :Activehigh Bit[2] COMP_LAT: Latchingcomparator (ADS1014 and ADS1015 only) ThisbitcontrolswhethertheALERT/RDY pinlatchesonce assertedorclearsonce conversionsarewithinthe marginoftheupperand lowerthresholdvalues.When COMP_LAT = '0',theALERT/RDY pindoes notlatch when asserted.When COMP_LAT = '1',theassertedALERT/RDY pinremainslatcheduntilconversiondata arereadby themasteroran appropriateSMBus alertresponseissentby themaster,thedevicerespondswith itsaddress,and itisthelowestaddresscurrentlyassertingtheALERT/RDY bus line.Thisbitservesno functionon theADS1013. 0 :Non-latchingcomparator(default) 1 :Latchingcomparator Bits[1:0] COMP_QUE: Comparator queue and disable(ADS1014 and ADS1015 only) These bitsperformtwo functions.When setto'11',theydisablethecomparatorfunctionand putthe ALERT/RDY pinintoa highstate.When settoany othervalue,theycontrolthenumber ofsuccessive conversionsexceedingtheupperorlowerthresholdsrequiredbeforeassertingtheALERT/RDY pin.They serveno functionon theADS1013. 00 :Assertafterone conversion 01 :Assertaftertwo conversions 10 :Assertafterfourconversions 11 :Disablecomparator(default) (1) Thisparameterexpressesthefull-scalerangeoftheADC scaling.Inno eventshouldmore thanVDD + 0.3Vbe appliedtothisdevice.
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www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 Lo_threshAND Hi_threshREGISTERS registerMSB to‘0’. However, inallothercases,the A secondary conversion ready functionof the comparatoroutputpincan be realizedby settingthe Hi_threshregisterMSB to '1'and the Lo_thresh Table10.Lo_threshand Hi_threshRegisters REGISTER Lo_thresh(Read/Write) BIT 15 14 13 12 11 10 9 8 NAME Lo_thresh11 Lo_thresh10 Lo_thresh9 Lo_thresh8 Lo_thresh7 Lo_thresh6 Lo_thresh5 Lo_thresh4 blank BIT 7 6 5 4 3 2 1 0 NAME Lo_thresh3 Lo_thresh2 Lo_thresh1 Lo_thresh0 0 0 0 0 REGISTER Hi_thresh(Read/Write) BIT 15 14 13 12 11 10 9 8 NAME Hi_thresh11 Hi_thresh10 Hi_thresh9 Hi_thresh8 Hi_thresh7 Hi_thresh6 Hi_thresh5 Hi_thresh4 blank BIT 7 6 5 4 3 2 1 0 NAME Hi_thresh3 Hi_thresh2 Hi_thresh1 Hi_thresh0 1 1 1 1 Lo_threshdefault= 8000h. Hi_threshdefault= 7FFFh. Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
Frame□1□T wo-Wire□Slave□Address□Byte Frame□2□Pointer□Register□Byte Start□By Master ACK□By ADS1013/4/5 ACK□By ADS1013/4/5 Frame□3□T wo-Wire□Slave□Address□Byte Frame□4□Data□Byte□1□Read□Register Start□By Master ACK□By ADS1013/4/5 ACK□By Master (2) From ADS1013/4/5 1 9 1 9 1 9 1 9 SDA SCL 0 0 1 R/W 0 0 0 0 0 0 P1 P0 /c188 /c188 /c188 SDA (Continued) SCL (Continued) SDA (Continued) SCL (Continued) 1 0 0 1 0 A1 (1) (1) 0 A1 (1) (1) R/W D15 D14 D13 D12 D11 D10 D9 D8 Frame□5□Data□Byte□2□Read□Register Stop□By Master ACK□By Master (3) From ADS1013/4/5 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Stop□By Master ADS1013 ADS1014 ADS1015 SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com (1)The valuesofA0 and A1 aredeterminedby theADDR pin. (2)Mastercan leaveSDA hightoterminatea single-bytereadoperation. (3)Mastercan leaveSDA hightoterminatea two-bytereadoperation. Figure16. Two-Wire Timing Diagram forRead Word Format
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Frame□1□T wo-Wire□Slave□Address□Byte Frame□2□Pointer□Register□Byte Frame□4□Data□Byte□2 Start□By Master ACK□By ADS1013/4/5 ACK□By ADS1013/4/5 ACK□By ADS1013/4/5 Stop□By Master 1 9 1 D7 D6 D5 D4 D3 D2 D1 D0 Frame□3□Data□Byte□1 ACK□By ADS1013/4/5 D15SDA (Continued) SCL (Continued) D14 D13 D12 D11 D10 D9 D8 SDA SCL 0 0 1 0 A1(1) A0(1) R/W 0 0 0 0 0 0 P1 P0 /c188 /c188 Frame□1□SMBus□ALERT□Response□Address□Byte Frame□2□Slave□Address□From□ADS1015 Start□By Master ACK□By ADS1013/4/5 From ADS1013/4/5 NACK□By Master Stop□By Master 1 9 1 9 SDA SCL ALERT 0 0 0 1 1 0 0 R/W 1 0 0 1 A1 A0 Status ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 (1)The valuesofA0 and A1 aredeterminedby theADDR pin. Figure17. Two-Wire Timing Diagram forWriteWord Format (1)The valuesofA0 and A1 aredeterminedby theADDR pin. Figure18. Timing Diagram forSMBus ALERT Response Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
0.1 F□(typ)/c109
Microcontroller□or Microprocessor with□I C□Port Pull-Up□Resistors 1k to□10k (typ)/c87 /c87 ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 Inputs□Selected from□Configuration Register ADS1013 ADS1014 ADS1015 SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com
APPLICATION INFORMATION
The followingsectionsgive example circuitsand The ADS1013/4/5interfacedirectlytostandardmode, suggestionsforusing the ADS1013/4/5 in various fastmode, and high-speedmode I2C controllers.Any situations. microcontrollerI2C peripheral,includingmaster-only and non-multiple-masterI2C peripherals,can operate with the ADS1013/4/5. The ADS1013/4/5 do notBASIC CONNECTIONS performclock-stretching(thatis,theynever pulltheFor many applications,connectingthe ADS1013/4/5 clocklinelow),so itisnot necessaryto provideforis simple. A basic connection diagram for the thisfunctionunlessotherclock-stretchingdevicesareADS1015 isshown inFigure19. on thesame I2C bus. smallerpull-upresistorstocompensate.The resistorsWhen the ADS1013/4/5 are convertingdata,they shouldnot be too small;iftheyare,the bus driversdraw currentin short spikes.The 0.1μF bypass may notbe abletopullthebus lineslow.capacitorsuppliesthe momentary burstsof extra currentneeded fromthesupply. Figure19. TypicalConnections oftheADS1015
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GPIO_0 GPIO_1 Microcontroller□or Microprocessor with□GPIO□Ports ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 CONNECTING MULTIPLE DEVICES states.To drivethelinelow,thepinissettooutput '0';toletthelinego high,thepinissettoinput.WhenConnectingmultipleADS1013/4/5s toa singlebus is the pin isset to input,the stateof the pin can besimple.Using theaddresspin,theADS1013/4/5 can read;ifanotherdeviceis pullingthe linelow,thisbe set to one of fourdifferentI2C addresses.An configurationreadsas a '0'intheportinputregister.example showing fourADS1013/4/5 devicesisgiven in Figure 21. Up to four ADS1013/4/5s (using Note thatno pull-upresistoris shown on the SCL differentaddress pin configurations)can be line.In thissimplecase,the resistorisnot needed; connectedtoa singlebus. the microcontrollercan simply leave the lineon The TMP421 and DAC8574 devices detect the Ifthereareany deviceson thebus thatmay drivetherespectiveI2C bus addressesbased on thestatesof clocklineslow,thismethod shouldnotbe used;thepins.In Figure22, the TMP421 has the address SCL lineshouldbe high-Zor'0'and a pull-upresistor0101010, and the DAC8574 has the address providedas usual.1001100. Consultthe DAC8574 and TMP421 data sheets,availableatwww.ti.com,forfurtherdetails. Some microcontrollershave selectablestrongpull-up circuitsbuiltin to the GPIO ports.In some cases, thesecircuitscan be switchedon and used inplaceUSING GPIO PORTS FOR COMMUNICATION ofan externalpull-upresistor.Weak pull-upsarealsoMost microcontrollers have programmable providedon some microcontrollers,butusuallytheseinput/output(I/O)pinsthatcan be setinsoftwareto are too weak forI2C communication.Ifthereisanyact as inputsor outputs.Ifan I2C controllerisnot doubt about the matter,test the circuitbeforeavailable,the ADS1013/4/5 can be connected to committingittoproduction.GPIO pins and the I2C bus protocolsimulated,or bit-banged, in software. An example of this configurationfora singleADS1013/4/5 isshown in Figure20. Bit-bangingI2C with GPIO pins can be done by settingthe GPIO lineto '0'and togglingitbetween inputand outputmodes to apply the proper bus NOTE: ADS1013/4/5power and inputconnectionsomittedforclarity. Figure20. Using GPIO witha SingleADS1015 Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
Microcontroller□or Microprocessor with□I C□Port I C□Pull-Up□Resistors 1k to□10k (typ.)/c87 /c87 VDDGND ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 DXP DXN SCL SDA TMP421 V AOUT V BOUT V HREF VDD V LREF GND IOVDD SDA V COUT V DOUT SCL LDAC DAC8574 Leave Floating 4 5 A0 GND VDD SDA SCL Microcontroller□or Microprocessor with□I C□Port I C□Pull-Up□Resistors 1k to□10k (typ.)/c87 /c87 VDDGND ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADDR ALERT/RDY GND AIN0 AIN1 SCL SDA VDD AIN3 AIN2 ADS1015 ADS1013 ADS1014 ADS1015 SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com NOTE: ADS1013/4/5power and inputconnectionsomittedfor clarity.ADDR, A3,A2,A1,and A0 selecttheI2C addresses. NOTE: ADS1013/4/5power and inputconnectionsomittedfor Figure22. Connecting MultipleDevice Typesclarity.The ADDR pinselectstheI2C address. Figure21. Connecting MultipleADS1013/4/5s
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Inputs□Selected from□Configuration Register Output□Codes 0 32767/c45 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009 SINGLE-ENDED INPUTS The ADS1015 inputrange isbipolardifferentialwith respectto the reference.The single-endedcircuitAlthoughtheADS1015 has two differentialinputs,the shown in Figure23 covers only halfthe ADS1015devicecan easilymeasure foursingle-endedsignals. inputscalebecause itdoes notproducedifferentiallyFigure23 shows a single-endedconnectionscheme. negativeinputs;therefore,one bitofresolutionislost.The ADS1015 is configured for single-ended measurement by configuringthe MUX to measure each channelwithrespectto ground.Data are then read out of one inputbased on the selectionon the configurationregister.The single-endedsignalcan range from 0V to supply.The ADS1015 loses no linearityanywhere withinthe inputrange.Negative voltagescannotbe appliedtothiscircuitbecause the ADS1015 can onlyacceptpositivevoltages. NOTE: Digitaland addresspinconnectionsomittedforclarity. Figure23. Measuring Single-EndedInputs Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
2.0V□to□5V V 3k/c87 I C 1k/c87R (2) S Load (PGA□Gain□=□16) 256mV□FS FS□=□0.2V G□=□4 /c45 5V R (1) 49.9k/c87 OPA335
0.1 F□T yp/c109
SBAS473C –MAY 2009–REVISED OCTOBER 2009 www.ti.com LOW-SIDE CURRENT MONITOR The ADS1013/4/5 arefabricatedina small-geometry, placecurrent-limitingresistorson theinputlines.TheItissuggestedthattheADS1014/5 be operatedata ADS1013/4/5analoginputscan withstandmomentarygainof16.The gainoftheOPA335 can thenbe set currentsas largeas 100mA.lower.For a gainof16,theop amp shouldbe setup op amps driftto one of the supplyrailsimmediately when power isapplied,usuallybeforethe inputhas stabilized;thismomentary spike can damage the ADS1013/4/5. This incrementaldamage resultsin slow,long-termfailure,which can be disastrousfor permanentlyinstalled,low-maintenancesystems. Ifan op amp or otherfront-endcircuitryisused with an ADS1013/4/5, performancecharacteristicsmust be takenintoaccountwhen designingtheapplication. (1)Pull-downresistortoallowaccurateswingto0V. (2)R S issizedfora 50mV dropatfull-scalecurrent. Figure24. Low-Side CurrentMeasurement
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www.ti.com SBAS473C –MAY 2009–REVISED OCTOBER 2009
REVISION HISTORY
NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionB (September 2009)toRevisionC Page Copyright© 2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS1013 ADS1014 ADS1015
www.ti.com 19-Nov-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Samples (Requires Login) ADS1013IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1013IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1013IRUGR ACTIVE X2QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1013IRUGT ACTIVE X2QFN RUG 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1014IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1014IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1014IRUGR ACTIVE X2QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1014IRUGT ACTIVE X2QFN RUG 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1015IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1015IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1015IRUGR ACTIVE X2QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1015IRUGT ACTIVE X2QFN RUG 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
www.ti.com 19-Nov-2012 Addendum-Page 2 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS1015 :
- Automotive: ADS1015-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Nov-2012 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1013IDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 ADS1013IDGST VSSOP DGS 10 250 195.0 200.0 45.0 ADS1013IRUGR X2QFN RUG 10 3000 203.0 203.0 35.0 ADS1013IRUGT X2QFN RUG 10 250 203.0 203.0 35.0 ADS1014IDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 ADS1014IDGST VSSOP DGS 10 250 195.0 200.0 45.0 ADS1014IRUGR X2QFN RUG 10 3000 203.0 203.0 35.0 ADS1014IRUGT X2QFN RUG 10 250 203.0 203.0 35.0 ADS1015IDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 ADS1015IDGST VSSOP DGS 10 250 195.0 200.0 45.0 ADS1015IRUGR X2QFN RUG 10 3000 203.0 203.0 35.0 ADS1015IRUGT X2QFN RUG 10 250 203.0 203.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Nov-2012 Pack Materials-Page 2
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