ADS10-V1EBZ

ADRV9032R AD | Alldatasheet

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Technical content

Integrated 2T2R TDD and FDD RadioVerse Transceiver with Dual Observation Paths Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. All Analog Devices products contained herein are subject to release and availability.

FEATURES

►2 differential transmitters ►2 differential receivers ►2 differential observation receivers ►LO tunable range: 450 MHz to 7125 MHz ►RF range: 350 MHz to 7225 MHz1 ►Maximum transmitter large-signal bandwidth: 200 MHz ►Maximum transmitter synthesis bandwidth: 450 MHz ►Maximum receiver signal bandwidth: 200 MHz ►Maximum observation receiver signal bandwidth: 450 MHz ►Fully integrated fractional-N RF synthesizer ►Fully integrated clock synthesizer ►Dual external LO inputs supporting operation up to 6 GHz ►JESD204B and JESD204C digital interface: up to 16.5 Gbps ►TDD and FDD operation ►Simplifying thermal and power consumption challenges ►4.82 W power consumption for the TDD mode, enabled use case with 200 MHz iBW/OBW2

APPLICATIONS

►Software defined radios ►Portable instrumentation ►Military communications ►General-purpose radios ►Wireless infrastructure ►TDD and FDD applications GENERAL DESCRIPTION The ADRV9032R is a highly integrated, RF agile transceiver of- fering two transmitters, two observation receivers for monitoring transmitter channels, two receivers, integrated local oscillator (LO) and clock synthesizers, and digital-signal processing functions to provide a complete transceiver solution. The device provides the high radio performance and low-power consumption demanded by cellular infrastructure applications, software-defined radios, portable instruments, and military communications. The receiver and transmitter signal paths use a zero-IF (ZIF) archi- tecture that provides wide bandwidth with dynamic range suitable for non-contiguous multicarrier applications. The ZIF architecture has the benefits of low power and RF and bandwidth agility. The lack of aliases and out-of-band images eliminates anti-aliasing and image filters, reducing system size and cost, and making band independent solutions possible. The device also includes two wide-bandwidth observation path receiver sub-systems for monitoring transmitter outputs. The com- plete transceiver subsystem includes automatic and manual attenu- ation control, DC offset correction, quadrature error correction (QEC), and digital filtering. General-purpose inputs and outputs (GPIOs) that provide an array of digital control options are also integrated. The transceiver includes four fully integrated phase-locked loops (PLLs). A single PLL provides high performance, low-power frac- tional-N RF LO synthesis supporting single and multiband time division duplex (TDD) and frequency division duplex (FDD) oper- ation with large-signal bandwidth up to 200 MHz. An additional PLL provides a second RF LO in order to support multiband appli- cations with spacing greater than 200 MHz, or to enable unique transmitter and receiver LO frequencies for frequency planning flexibility. A multichip synchronization mechanism synchronizes the phases of all local oscillators and clocks between multiple chips. All voltage-controlled oscillators (VCOs) and loop filter components are integrated and can be adjusted through the serial-peripheral interface (SPI). External LO paths are supported on the ADRV9032RBBPZ-2T1 model to provide an option for improved phase noise performance, which meets the more restrictive performance requirements de- manded by some radar and instrumentation applications. The serial-data interface consists of eight serializer lanes and eight deserializer lanes. The interface supports both the JESD204B and JESD204C standards, and it operates at data rates up to 16.5 Gbps. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be transparent to the baseband processor. The ADRV9032R is powered directly from the 0.8 V, 1.0 V, and 1.8 V regulators and is controlled by a standard SPI serial port. Comprehensive power-down modes are included to minimize pow- er consumption in normal use. The device is packaged in a 506-ball ball grid array, thermally enhanced [BGA_ED]. 1 The relationship between the LO and RF ranges can be expressed as: RF range = LO tuning range ± (large-signal bandwidth/2). 2 Power consumption values shown are for a typical use case. Power consumption depends heavily on the device configuration (use case). Please refer to the power analysis tab in the EVAL-ADRV903X evaluation software (ACE) to estimate the power consumption for the specified use case.

analog.com Rev. A | 2 of 163

REVISION HISTORY

9/2025—Rev. 0 to Rev. A 1/2025—Revision 0: Initial Version

Figure 1. Functional Block Diagram

circuit board (PCB) and matching circuit losses, unless otherwise noted. Table 1. Specifications

900 MHz 5 dBm

5600 MHz 2 dBm

6300 MHz 2 dBm

7100 MHz 2 dBm

800 MHz synthesis bandwidth use

Table 1. Specifications (Continued)

100 MHz RF Bandwidth ±1 Degrees

450 MHz RF Bandwidth ±5 Degrees

20 MHz LTE at −12 dBFS

450 MHz −67 dBc

900 MHz −67 dBc

1800 MHz −67 dBc

2600 MHz −67 dBc

3500 MHz −65 dBc

4500 MHz −62 dBc

5600 MHz −60 dBc

6300 MHz −57 dBc

7100 MHz −57 dBc

450 MHz −75 dBc

900 MHz −75 dBc

1800 MHz −75 dBc

2600 MHz −70 dBc

3500 MHz −70 dBc

4500 MHz −70 dBc

5600 MHz −67 dBc

6300 MHz −65 dBc

7100 MHz −65 dBc

450 MHz −70 dBc

900 MHz −70 dBc

1800 MHz −70 dBc

2600 MHz −65 dBc

4500 MHz −65 dBc

5600 MHz −63 dBc

6300 MHz −60 dBc

7100 MHz −60 dBc

5600 MHz −64 dBc

6300 MHz −62 dBc

5000 MHz ≤ LO ≤ 6300 MHz 60 dBc

3 Maximum value to ensure adequate

450 MHz −84 dBFS

900 MHz −84 dBFS

1800 MHz −84 dBFS

2600 MHz −84 dBFS

3500 MHz −84 dBFS

4500 MHz −82 dBFS

5600 MHz −82 dBFS

6300 MHz −82 dBFS

7100 MHz −82 dBFS

450 MHz −71 dBFS

900 MHz −71 dBFS

1800 MHz −71 dBFS

2600 MHz −71 dBFS

3500 MHz −71 dBFS

4500 MHz −71 dBFS

5600 MHz −71 dBFS

6300 MHz −71 dBFS

7100 MHz −71 dBFS

7100 MHz −9 dBm

450 MHz 2 Degrees

900 MHz 3 Degrees

1800 MHz 6 Degrees

2600 MHz 9 Degrees

3500 MHz 12 Degrees

4500 MHz 16 Degrees

5600 MHz 19 Degrees

6300 MHz 22 Degrees

7100 MHz 25 Degrees

200 MHz RF Bandwidth 1 dB

450 MHz −68 dBm

900 MHz −70 dBm

1800 MHz −65 dBm

2600 MHz −65 dBm

3500 MHz −65 dBm

4500 MHz −65 dBm

5600 MHz −65 dBm

6300 MHz −65 dBm

7100 MHz −60 dBm

5600 MHz 14 dB

7100 MHz 15 dB

1800 MHz −80 dBc Two CW tones at −7 dBFS, 600 MHz

2600 MHz −80 dBc Two CW tones at −7 dBFS, 600 MHz

3500 MHz −80 dBc Two CW tones at −7 dBFS, 600 MHz

4500 MHz −80 dBc Two CW tones at −7 dBFS, 600 MHz

5600 MHz −80 dBc Two CW tones at −7 dBFS, 600 MHz

6300 MHz −78 dBc Two CW tones at −7 dBFS, 600 MHz

7100 MHz −78 dBc Two CW tones at −7 dBFS, 600 MHz

1800 MHz −60 dBc Two CW tones at −7 dBFS, 600 MHz

2600 MHz −61 dBc Two CW tones at −7 dBFS, 600 MHz

3500 MHz −61 dBc Two CW tones at −7 dBFS, 600 MHz

4500 MHz −61 dBc Two CW tones at −7 dBFS, 600 MHz

5600 MHz −61 dBc Two CW tones at −7 dBFS, 600 MHz

6300 MHz −60 dBc Two CW tones at −7 dBFS, 600 MHz

7100 MHz −60 dBc Two CW tones at −7 dBFS, 600 MHz

5600 MHz 9 dBm

6300 MHz 10 dBm

7100 MHz 11 dBm

2949.12 MHz Sampling

3932.16 MHz Sampling

5898.24 MHz Sampling

7864.32 MHz Sampling

450 MHz 73 dB

900 MHz 73 dB

1800 MHz 73 dB

2600 MHz 69 dB

3500 MHz 67 dB

4500 MHz 66 dB

5600 MHz 65 dB

6300 MHz 65 dB

7100 MHz 63 dB

450 MHz 70 dB

900 MHz 70 dB

1800 MHz 70 dB

2600 MHz 65 dB

3500 MHz 63 dB

4500 MHz 61 dB

5600 MHz 60 dB

6300 MHz 60 dB

7100 MHz 60 dB

450 MHz 75 dB

900 MHz 75 dB

1800 MHz 75 dB

2600 MHz 74 dB

3500 MHz 70 dB

4500 MHz 67 dB

7100 MHz 65 dB

2600 MHz 75 dB

4500 MHz 62 dB

3500 MHz 75 dB

4500 MHz 70 dB

5600 MHz 70 dB

6300 MHz 70 dB

7100 MHz 70 dB

4500 MHz 75 dB

5600 MHz 75 dB

6300 MHz 75 dB

7100 MHz 75 dB

450 MHz

900 MHz

1 MHz Offset −139 dBc/Hz

10 MHz Offset −160 dBc/Hz

1800 MHz

1 MHz Offset −132 dBc/Hz

10 MHz Offset −156 dBc/Hz

2600 MHz

1 MHz Offset −125 dBc/Hz

10 MHz Offset −150 dBc/Hz

3500 MHz

1 MHz Offset −120 dBc/Hz

10 MHz Offset −148 dBc/Hz

4500 MHz

1 MHz Offset −122 dBc/Hz

10 MHz Offset −149 dBc/Hz

5600 MHz

1 MHz Offset −119 dBc/Hz

10 MHz Offset −146 dBc/Hz

6300 MHz

1 MHz Offset −117 dBc/Hz

10 MHz Offset −144 dBc/Hz

7100 MHz

1 MHz Offset −114 dBc/Hz

10 MHz Offset −142 dBc/Hz

1 MHz Offset −151 dBc/Hz

1.2 MHz Offset −152 dBc/Hz

1.8 MHz Offset −155 dBc/Hz

6 MHz Offset −159 dBc/Hz

10 MHz Offset −159 dBc/Hz

1 MHz Offset −144 dBc/Hz

1.2 MHz Offset −146 dBc/Hz

1.8 MHz Offset −150 dBc/Hz

6 MHz Offset −158 dBc/Hz

1 MHz Offset −138 dBc/Hz

1.2 MHz Offset −140 dBc/Hz

1.8 MHz Offset −144 dBc/Hz

6 MHz Offset −154 dBc/Hz

1 MHz Offset −130 dBc/Hz

1 MHz Offset −123 dBc/Hz

1 MHz Offset −128 dBc/Hz

1 MHz Offset −124 dBc/Hz

1 MHz Offset −121 dBc/Hz

3 MHz −153 dBc/Hz

10 MHz −156 dBc/Hz

2949.12 MHz Sample Clock

3932.16 MHz Sample Clock

3 MHz Offset −140 dBc/Hz

3 MHz Offset −139 dBc/Hz

Figure 2. LVDS Input Levels for SYSREF

Table 2. Power Supply Specifications Table 3. Digital Interface and Timing Specifications

Table 4. Absolute Maximum Ratings Maximum Input Power into Rx Ports See Table 9 for limits vs. dBm for all ORx attenuations.

2 Operation up to 125°C is supported, but specification compliance is only

maximum lifetime is 10 years. ing conditions for extended periods may affect product reliability. Table 5. Acceleration Factors for High Temperature Operation temperature with a duty cycle. Table 6. Example Scenario to Estimate Impact of Accelerating Factor on within guidance, see Table 4 for reference. liability for the operation of the hardware. environment. Careful attention to PCB thermal design is required. techniques improve thermal resistance values.

resistance, and ΨJB is the junction to the board thermal resistance. Table 7. Thermal Resistance sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDDEC JS-001. Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 8. ADRV9032R, 506-Ball CSP_BGA

1 All pins except transmitter channel pins and EXT LO pins rated at ±250 V CDM

classification test level (Class C1). Table 9. Maximum Input Power into Receiver Ports vs. Lifetime Table 10. VDDA_1P0 Voltage vs. Duty Cycle to Maintain 10-Year Lifetime

analog.com Rev. A | 22 of 163 ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protec- tion circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 11. Pin Function Descriptions

Table 11. Pin Function Descriptions (Continued) A3 VVCO0_1P8 I 1.8 V Supply Voltage. Requires local bypass to ground. A6 VRXLO0_1P0 I 1.0 V Supply Voltage. A8 VTXLO0_1P0 I 1.0 V Supply Voltage. A10 VLO0_1P0 I 1.0 V Supply Voltage. A13 VLO1_1P0 I 1.0 V Supply Voltage. A15 VTXLO1_1P0 I 1.0 V Supply Voltage. A17 VRXLO1_1P0 I 1.0 V Supply Voltage. A19 VVCO1_1P0 O 1.0 V Internal LDO Output. Connect a 4.7 µF ceramic capacitor from the A19 pin to VSSA. A20 VVCO1_1P8 I 1.8 V Supply Voltage. Requires local bypass to ground. B1, C1 TX0N, TX0P O Differential Outputs for Transmitter Channel 0. Do not connect if unused. B22, C22 TX4P, TX4N O Differential Outputs for Transmitter Channel 4. Do not connect if unused. C4, D4 RX0P, RX0N I Differential Inputs for Receiver Channel 0. Do not connect if unused. C6 VANA0_1P8 I 1.8 V Supply Voltage. C7 VBB0_1P0 I 1.0 V Supply Voltage. I Differential External LO Input 0. Do not connect if unused. I Differential External LO Input 1. Do not connect if unused. C16 VBB1_1P0 I 1.0 V Supply Voltage. C17 VANA1_1P8 I 1.8 V Supply Voltage. C19, D19 RX4N, RX4P I Differential Inputs for Receiver Channel 4. Do not connect if unused. E8 VSYN0_1P0 I 1.0 V Supply Voltage. I Device Clock Differential Inputs. E15 VSYN1_1P0 I 1.0 V Supply Voltage.

DNC N/A Do Not Connect. Do not connect to the DNC pins. F10 VDEV_1P0 I 1.0 V Supply Voltage. F13 VSYS_1P8 I 1.8 V Supply Voltage. I LVDS System Reference Clock Inputs for the Serializer/Deserializer (SERDES) Interface. H7 VCONV0_1P0 I 1.0 V Supply Voltage. or configured as outputs, driven low, and left disconnected. H16 VCONV2_1P0 I 1.0 V Supply Voltage. J7 VCONV0_1P8 I 1.8 V Supply Voltage. J16 VCONV2_1P8 I 1.8 V Supply Voltage. K1, L1 ORX0N, ORX0P I Differential Inputs for Observation Receiver Channel 0. Do not connect if unused. K7 VORX0_1P8 I 1.8 V Supply Voltage. K11, L11, M11, N11, P11, R11, U11VSSD I Digital Grounds. K16 VORX1_1P8 I 1.8 V Supply Voltage. K22, L22 ORX1P, ORX1N I Differential Inputs for Observation Receiver Channel 1. Do not connect if unused. L7, M7 VSCLK0_1P0 I 1.0 V Supply Voltages. L16, M16 VSCLK1_1P0 I 1.0 V Supply Voltages. N7 VORX0_1P0 I 1.0 V Supply Voltage. N16 VORX1_1P0 I 1.0 V Supply Voltage. P7 VCONV1_1P8 I 1.8 V Supply Voltage. P16 VCONV3_1P8 I 1.8 V Supply Voltage. R7 VCONV1_1P0 I 1.0 V Supply Voltage. R9 RESET I Active-Low Chip Reset. boundary scan. Connect to VSSA if unused. R16 VCONV3_1P0 I 1.0 V Supply Voltage. O LVDS Sync Signal Output 1. Do not connect if unused. T9, T14 GPINT0, GPINT1O General-Purpose Interrupt Pins. T11 SPI_DIO I/O SPI Data In and Out. T13 SPI_EN I Active-Low SPI Enable. I LVDS Sync Signal Input 1. Connect to VSSA if unused.

O LVDS Sync Signal Output 0. Do not connect if unused. U12 VIF_1P8 I 1.8 V Supply Voltage. I LVDS Sync Signal Input 0. Connect to VSSA if unused. U16 VCLKSYN_1P0 I 1.0 V Supply Voltage. V8 VSERVCO_1P0 O 1.0 V Internal LDO Output. Connect a 4.7 µF ceramic capacitor from V8 to VSSA. V9 VSERVCO_1P8 I 1.8 V Supply Voltage. I LVDS Sync Signal Input 2. Connect to VSSA if unused. V14 VCLKVCO_1P0 O 1.0 V Internal LDO Output. Connect a 4.7 µF ceramic capacitor from V14 to VSSA. V15 VCLKVCO_1P8 I 1.8 V Supply Voltage. V16 VCLKGEN_1P0 I 1.0 V Supply Voltage. W3 VTX0_1P8 I 1.8 V Supply Voltage. W20 VTX1_1P8 I 1.8 V Supply Voltage. O SERDES Differential Output 1. Do not connect if unused. O SERDES Differential Output 4. Do not connect if unused. I SERDES Differential Input 5. Do not connect if unused. I SERDES Differential Input 1. Do not connect if unused. O SERDES Differential Output 0. Do not connect if unused. O SERDES Differential Output 5. Do not connect if unused. AA11 VSERSYN_1P0 I 1.0 V Supply Voltage. I SERDES Differential Input 4. Do not connect if unused. I SERDES Differential Input 0. Do not connect if unused. O SERDES Differential Output 3. Do not connect if unused. O SERDES Differential Output 6. Do not connect if unused. AB11, AC11 VSER_1P0 I 1.0 V Supply Voltages. AB12, AC12 VDES_1P0 I 1.0 V Supply Voltages. I SERDES Differential Input 6. Do not connect if unused. I SERDES Differential Input 3. Do not connect if unused. O SERDES Differential Output 2. Do not connect if unused. O SERDES Differential Output 7. Do not connect if unused. I SERDES Differential Input 7. Do not connect if unused.

I SERDES Differential Input 2. Do not connect if unused. 1 I is input, O is output, I/O is input and output, and N/A means not applicable.

450 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 450 MHz, unless otherwise noted. Figure 4. Transmitter Noise vs. Transmitter Attenuation Setting,

50 MHz Offset

Figure 5. Transmitter Passband Flatness vs. Baseband Offset Frequency Figure 6. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz LTE,

10 MHz Offset, −10 dBFS RMS, 1 MHz Resolution Bandwidth, TJ = 25ºC

Figure 7. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 8. Adjacent Channel Power vs. Transmitter Attenuation,

190 MHz Offset, 20 MHz LTE, PAR = 12 dB

Figure 9. Adjacent Channel Power vs. Transmitter Attenuation,

Figure 10. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs. Figure 11. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting,

10 MHz Offset, −12 dBFS CW Signal

Figure 12. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 13. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 14. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 15. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation

Figure 58. Receiver IM3 Sum Image, 2F2 + F1 vs. F1 Frequency Offset, Figure 59. Receiver Phase vs. Receiver Attenuation Figure 60. Receiver Baseband Flatness vs. Baseband Offset Figure 61. Receiver Error Vector Magnitude vs. Receiver Input Power,

20 MHz LTE, TDD Mode, AGC Enabled

Figure 62. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 60 kHz, Figure 63. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 500 kHz,

Figure 76. Observation Receiver Signal Power at SMA Connector vs.

900 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 900 MHz, unless otherwise noted. Figure 77. Transmitter Noise vs. Transmitter Attenuation Setting,

100 MHz Offset

Figure 78. Transmitter Passband Flatness vs. Baseband Offset Frequency Figure 79. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz Figure 80. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 81. Adjacent Channel Power vs. Transmitter Attenuation, Figure 82. Adjacent Channel Power vs. Transmitter Attenuation,

Figure 83. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs. Figure 84. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting,

30 MHz Offset, −12 dBFS CW Signal

Figure 85. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 86. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 87. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 88. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation

Figure 131. Receiver IM3 Sum Image, 2F2 + F1 vs. F1 Frequency Offset, Figure 132. Receiver IM3 Sum Image, 2F1 + F2 vs. F1 Frequency Offset, Figure 133. Receiver IM3 Sum Image, 2F2 + F1 vs. F1 Frequency Offset, Figure 134. Receiver Phase vs. Receiver Attenuation Figure 135. Receiver Baseband Flatness vs. Baseband Offset Figure 136. Receiver Error Vector Magnitude vs. Receiver Input Power,

Figure 149. Observation Receiver HD2 vs. Observation Receiver Attenuation,

80 MHz Offset, −10 dBFS Input Signal

Figure 150. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 151. Observation Receiver Signal Power at SMA Connector vs.

1800 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 1800 MHz, unless otherwise noted. Figure 152. Transmitter Noise vs. Transmitter Attenuation Setting,

150 MHz Offset

Figure 153. Transmitter Passband Flatness vs. Baseband Offset Frequency Figure 154. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz Figure 155. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 156. Adjacent Channel Power vs. Transmitter Attenuation,

290 MHz Offset, 20 MHz LTE, PAR = 12 dB

Figure 157. Adjacent Channel Power vs. Transmitter Attenuation,

Figure 158. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs. Figure 159. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting, Figure 160. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 161. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 162. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 163. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation

Figure 176. Receiver Same Side HD3 vs. Fundamental Baseband Offset Figure 177. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 178. Receiver Gain Step Error vs. Receiver Attenuation,

30 MHz Offset, −1 dBFS Input Signal

Figure 179. Receiver Normalized Gain vs. Receiver Attenuation, Figure 180. Receiver DC Offset vs. Receiver Attenuation, 30 MHz Offset, Figure 181. Receiver Image vs. Receiver Attenuation, 30 MHz Offset,

Figure 212. Receiver Error Vector Magnitude vs. Receiver Input Power,

10 MHz Offset, 20 MHz LTE, TDD Mode, AGC Enabled

Figure 213. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 60 kHz, Figure 214. LO Phase Noise vs. Frequency Offset, Figure 215. Observation Receiver Baseband Flatness vs. Baseband Offset Figure 216. Observation Receiver HD2 vs. Fundamental Baseband Offset Figure 217. Observation Receiver HD3 vs. Fundamental Baseband Offset

Figure 224. Observation Receiver IM3 Difference, 2F2 − F1 vs. F1 Frequency Figure 225. Observation Receiver HD2 vs. Observation Receiver Attenuation, Figure 226. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 227. Observation Receiver Signal Power at SMA Connector vs.

2600 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 2600 MHz, unless otherwise noted. Figure 228. Transmitter Noise vs. Transmitter Attenuation Setting, Figure 229. Transmitter Passband Flatness vs. Baseband Offset Frequency Figure 230. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz Figure 231. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 232. Adjacent Channel Power vs. Transmitter Attenuation, Figure 233. Adjacent Channel Power vs. Transmitter Attenuation,

Figure 234. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs. Figure 235. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting, Figure 236. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 237. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 238. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 239. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation

Figure 252. Receiver Same Side HD3 vs. Fundamental Baseband Offset Figure 253. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 254. Receiver Gain Step Error vs. Attenuation, 30 MHz Offset, Figure 255. Receiver Normalized Gain vs. Receiver Attenuation, Figure 256. Receiver DC Offset vs. Receiver Attenuation, 30 MHz Offset, Figure 257. Receiver Image vs. Receiver Attenuation, 30 MHz Offset,

Figure 288. Receiver Error Vector Magnitude vs. Receiver Input Power, Figure 289. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 60 kHz, Figure 290. LO Phase Noise vs. Frequency Offset, Figure 291. Observation Receiver Baseband Flatness vs. Baseband Offset Figure 292. Observation Receiver HD2 vs. Fundamental Baseband Offset Figure 293. Observation Receiver HD3 vs. Fundamental Baseband Offset

Figure 300. Observation Receiver IM3 Difference, 2F2 − F1 vs. F1 Frequency Figure 301. Observation Receiver HD2 vs. Observation Receiver Attenuation, Figure 302. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 303. Observation Receiver Signal Power at SMA Connector vs.

3500 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 3500 MHz, unless otherwise noted. Figure 304. Transmitter Noise vs. Transmitter Attenuation Setting, Figure 305. Transmitter Passband Flatness vs. Baseband Offset Frequency Figure 306. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz Figure 307. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 308. Adjacent Channel Power vs. Transmitter Attenuation, Figure 309. Adjacent Channel Power vs. Transmitter Attenuation,

Figure 310. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs. Figure 311. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting, Figure 312. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 313. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 314. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 315. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation

Figure 328. Receiver Same Side HD3 vs. Fundamental Baseband Offset Figure 329. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 330. Receiver Gain Step Error vs. Receiver Attenuation, Figure 331. Receiver Normalized Gain vs. Receiver Attenuation, Figure 332. Receiver DC Offset vs. Receiver Attenuation, 30 MHz Offset, Figure 333. Receiver Image vs. Receiver Attenuation, 30 MHz Offset,

Figure 364. Receiver Error Vector Magnitude vs. Receiver Input Power, Figure 365. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 60 kHz, Figure 366. LO Phase Noise vs. Frequency Offset, Figure 367. Observation Receiver Baseband Flatness vs. Baseband Offset Figure 368. Observation Receiver HD2 vs. Fundamental Baseband Offset Figure 369. Observation Receiver HD3 vs. Fundamental Baseband Offset

Figure 376. Observation Receiver IM3 Difference, 2F2 − F1 vs. F1 Frequency Figure 377. Observation Receiver HD2 vs. Observation Receiver Attenuation, Figure 378. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 379. Observation Receiver Signal Power at SMA Connector vs.

4500 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 4500 MHz, unless otherwise noted. Figure 380. Transmitter Noise vs. Transmitter Attenuation Setting, Figure 381. Transmitter Passband Flatness vs. Baseband Offset Frequency Figure 382. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz Figure 383. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 384. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs. Figure 385. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting,

Figure 386. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 387. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 388. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 389. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation Figure 390. Transmitter IM3 Difference, 2F2 − F1 vs. Transmitter Attenuation Figure 391. Transmitter IM3 Sum, 2F1 + F2 vs. Baseband Tone Swept Across

Figure 404. Receiver Gain Step Error vs. Receiver Attenuation, Figure 405. Receiver Normalized Gain vs. Receiver Attenuation, Figure 406. Receiver DC Offset vs. Receiver Attenuation, 30 MHz Offset, Figure 407. Receiver Image vs. Receiver Attenuation, 30 MHz Offset, Figure 408. Receiver IM2 Difference, F1 − F2 vs. Receiver Attenuation, Figure 409. Receiver IM2 Difference, F1 − F2 vs. Receiver Attenuation,

Figure 434. Receiver IM3 Sum Image, 2F1 + F2 vs. F1 Frequency Offset, Figure 435. Receiver IM3 Sum Image, 2F2 + F1 vs. F1 Frequency Offset, Figure 436. Receiver Phase vs. Receiver Attenuation Figure 437. Receiver Baseband Flatness vs. Baseband Offset Figure 438. Receiver Error Vector Magnitude vs. Receiver Input Power, Figure 439. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 60 kHz,

Figure 446. Observation Receiver IM3 Difference, 2F2 − F1 vs. Observation Figure 447. Observation Receiver IM3 Difference, 2F1 − F2 vs. Observation Figure 448. Observation Receiver IM3 Difference, 2F2 − F1 vs. Observation Figure 449. Observation Receiver IM3 Difference, 2F1 − F2 vs. F1 Frequency Figure 450. Observation Receiver IM3 Difference, 2F2 − F1 vs. F1 Frequency Figure 451. Observation Receiver HD2 vs. Observation Receiver Attenuation,

Figure 452. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 453. Observation Receiver Signal Power at SMA Connector vs.

5600 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 5600 MHz, unless otherwise noted. Figure 454. Transmitter Noise vs. Transmitter Attenuation Setting, Figure 455. Transmitter Passband Flatness vs. Baseband Offset Frequency Figure 456. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz Figure 457. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 458. Adjacent Channel Power vs. Transmitter Attenuation, Figure 459. Adjacent Channel Power vs. Transmitter Attenuation,

Figure 460. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs. Figure 461. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting, Figure 462. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 463. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 464. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 465. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation

Figure 472. Transmitter Error Vector Magnitude vs. Transmitter Attenuation,

20 MHz LTE, PAR = 12 dB

Figure 473. Receiver Carrier Rejection vs. Fundamental Baseband Offset Figure 474. Receiver Image Rejection vs. Fundamental Baseband Offset Figure 475. Receiver Signal Power at SMA Connector vs. Fundamental Figure 476. Receiver Opposite Side HD2 vs. Fundamental Baseband Offset Figure 477. Receiver Opposite Side HD3 vs. Fundamental Baseband Offset

Figure 478. Receiver Same Side HD2 vs. Fundamental Baseband Offset Figure 479. Receiver Same Side HD3 vs. Fundamental Baseband Offset Figure 480. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 481. Receiver Gain Step Error vs. Receiver Attenuation, 30 MHz Figure 482. Receiver Normalized Gain vs. Receiver Attenuation, Figure 483. Receiver DC Offset vs. Receiver Attenuation, 30 MHz Offset,

Figure 514. Receiver Error Vector Magnitude vs. Receiver Input Power, Figure 515. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 60 kHz, Figure 516. LO Phase Noise vs. Frequency Offset, Figure 517. Observation Receiver Baseband Flatness vs. Baseband Offset Figure 518. Observation Receiver HD2 vs. Fundamental Baseband Offset Figure 519. Observation Receiver HD3 vs. Fundamental Baseband Offset

Figure 526. Observation Receiver IM3 Difference, 2F2 − F1 vs. F1 Frequency Figure 527. Observation Receiver HD2 vs. Observation Receiver Attenuation, Figure 528. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 529. Observation Receiver Signal Power at SMA Connector vs.

6300 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 6300 MHz, unless otherwise noted. Figure 530. Transmitter Noise vs. Transmitter Attenuation Setting, Figure 531. Transmitter Passband Flatness vs. Baseband Offset Frequency Figure 532. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz Figure 533. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 534. Adjacent Channel Power vs. Transmitter Attenuation, Figure 535. Adjacent Channel Power vs. Transmitter Attenuation,

Figure 536. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs. Figure 537. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting, Figure 538. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 539. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 540. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 541. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation

Figure 548. Transmitter Error Vector Magnitude vs. Transmitter Attenuation, Figure 549. Receiver Carrier Rejection vs. Fundamental Baseband Offset Figure 550. Receiver Image Rejection vs. Fundamental Baseband Offset Figure 551. Receiver Signal Power at SMA Connector vs. Fundamental Figure 552. Receiver Opposite Side HD2 vs. Fundamental Baseband Offset Figure 553. Receiver Opposite Side HD3 vs. Fundamental Baseband Offset

Figure 554. Receiver Same Side HD2 vs. Fundamental Baseband Offset Figure 555. Receiver Same Side HD3 vs. Fundamental Baseband Offset Figure 556. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 557. Receiver Gain Step Error vs. Receiver Attenuation, 30 MHz Figure 558. Receiver Normalized Gain vs. Receiver Attenuation, Figure 559. Receiver DC Offset vs. Receiver Attenuation, 30 MHz Offset,

Figure 590. Receiver Error Vector Magnitude vs. Receiver Input Power, Figure 591. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 60 kHz, Figure 592. LO Phase Noise vs. Frequency Offset, Figure 593. Observation Receiver Baseband Flatness vs. Baseband Offset Figure 594. Observation Receiver HD2 vs. Observation Receiver Attenuation, Figure 595. Observation Receiver HD2 vs. Fundamental Baseband Offset

Figure 602. Observation Receiver IM3 Difference, 2F2 − F1 vs. Observation Figure 603. Observation Receiver IM3 Difference, 2F1 − F2 vs. F1 Frequency Figure 604. Observation Receiver IM3 Difference, 2F2 − F1 vs. F1 Frequency Figure 605. Observation Receiver HD2 vs. Observation Receiver Attenuation, Figure 606. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 607. Observation Receiver Signal Power at SMA Connector vs.

7100 MHZ BAND

The temperature settings refer to the die temperature. All LO frequencies set to 7100 MHz, unless otherwise noted. Figure 608. Transmitter Noise vs. Transmitter Attenuation Setting, Figure 609. Transmitter Output Power Spectrum vs. Frequency, Tx0, 5 MHz Figure 610. Transmitter Image Rejection vs. Baseband Offset Frequency, Figure 611. Adjacent Channel Power vs. Transmitter Attenuation, Figure 612. Adjacent Channel Power vs. Transmitter Attenuation, Figure 613. Transmitter Opposite Side Second Harmonic Distortion (HD2) vs.

Figure 614. Transmitter Same Side HD2 vs. Transmitter Attenuation Setting, Figure 615. Transmitter Opposite Side Third Harmonic Distortion (HD3) vs. Figure 616. Transmitter Same Side HD3 vs. Transmitter Attenuation Setting, Figure 617. Transmitter Attenuation Step Error vs. Transmitter Attenuation Figure 618. Transmitter IM3 Difference, 2F1 − F2 vs. Transmitter Attenuation Figure 619. Transmitter IM3 Difference, 2F2 − F1 vs. Transmitter Attenuation

Figure 620. Transmitter IM3 Sum, 2F1 + F2 vs. Baseband Tone Swept Across Figure 621. Transmitter IM3 Sum, 2F2 + F1 vs. Baseband Tone Swept Across Figure 622. Transmitter IM3 Difference, 2F1 − F2 vs. Baseband Tone Swept Figure 623. Transmitter IM3 Difference, 2F2 − F1 vs. Baseband Tone Swept Figure 624. Transmitter Phase vs. Transmitter Attenuation Figure 625. Transmitter Error Vector Magnitude vs. Transmitter Attenuation,

Figure 632. Receiver Same Side HD3 vs. Fundamental Baseband Offset Figure 633. Receiver Integrated Noise Figure vs. Baseband Offset Frequency, Figure 634. Receiver Gain Step Error vs. Receiver Attenuation, 30 MHz Figure 635. Receiver Normalized Gain vs. Receiver Attenuation, Figure 636. Receiver DC Offset vs. Receiver Attenuation, 30 MHz Offset, Figure 637. Receiver Image vs. Receiver Attenuation, 30 MHz Offset,

Figure 662. Receiver IM3 Sum Image, 2F2 + F1 vs. F1 Frequency Offset, Figure 663. Receiver IM3 Sum Image, 2F1 + F2 vs. F1 Frequency Offset, Figure 664. Receiver IM3 Sum Image, 2F2 + F1 vs. F1 Frequency Offset, Figure 665. Receiver Phase vs. Receiver Attenuation Figure 666. Receiver Error Vector Magnitude vs. Receiver Input Power, Figure 667. LO Phase Noise vs. Frequency Offset, Loop Bandwidth = 60 kHz,

Figure 680. Observation Receiver HD2 vs. Observation Receiver Attenuation, Figure 681. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 682. Observation Receiver Signal Power at SMA Connector vs.

The ultralow band match board frequency range is 100 MHz to 1000 MHz. The temperature settings refer to the die temperature. Figure 683. Transmitter Output Power vs. LO Frequency, 10 MHz Offset, Figure 684. Transmitter LO Leakage vs. LO Frequency Figure 685. Receiver Integrated Noise Figure vs. LO Frequency,

200 MHz Integration Bandwidth

Figure 686. Receiver LO Leakage vs. Receiver LO Frequency,

Figure 687. Receiver Carrier Rejection vs. LO Frequency Figure 688. Receiver Signal Power at SMA Connector vs. LO Frequency Figure 689. Observation Receiver (ORX) Integrated NSD vs. LO Frequency,

5898.24 MSPS Sample Rate

Figure 690. Transmitter to Transmitter Isolation vs. Transmitter LO Figure 691. Transmitter to Receiver Isolation vs. Receiver LO Frequency Figure 692. Transmitter to Observation Receiver Isolation vs. Observation

The low band match board frequency range is 600 MHz to 2800 MHz. The temperature settings refer to the die temperature. Figure 696. Transmitter Output Power vs. LO Frequency, 30 MHz Offset, Figure 697. Transmitter LO Leakage vs. LO Frequency Figure 698. Receiver Integrated Noise Figure vs. LO Frequency,

400 MHz Integration Bandwidth

Figure 699. Receiver LO Leakage vs. Receiver LO Frequency, Figure 700. Receiver Carrier Rejection vs. LO Frequency Figure 701. Receiver Signal Power at SMA Connector vs. LO Frequency

Figure 702. Observation Receiver (ORX) Integrated NSD vs. LO Frequency, Figure 703. Transmitter to Transmitter Isolation vs. Transmitter LO Figure 704. Transmitter to Receiver Isolation vs. Receiver LO Frequency Figure 705. Transmitter to Observation Receiver Isolation vs. Observation Figure 706. Receiver to Receiver Isolation vs. Receiver LO Frequency Figure 707. Observation Receiver to Receiver Isolation vs. Receiver LO

Figure 708. Observation Receiver to Observation Receiver Isolation vs.

The midband match board frequency range is 1800 MHz to 4800 MHz. The temperature settings refer to the die temperature. Figure 709. Transmitter Output Power vs. LO Frequency, 30 MHz Offset, Figure 710. Transmitter LO Leakage vs. LO Frequency Figure 711. Receiver Integrated Noise Figure vs. LO Frequency,

600 MHz Integration Bandwidth

Figure 712. Receiver LO Leakage vs. Receiver LO Frequency, Figure 713. Receiver Carrier Rejection vs. LO Frequency Figure 714. Receiver Signal Power at SMA Connector vs. LO Frequency

Figure 715. Observation Receiver (ORX) Integrated NSD vs. LO Frequency, Figure 716. Transmitter to Transmitter Isolation vs. Transmitter LO Figure 717. Transmitter to Receiver Isolation vs. Receiver LO Frequency Figure 718. Transmitter to Observation Receiver Isolation vs. Observation Figure 719. Receiver to Receiver Isolation vs. Receiver LO Frequency Figure 720. Observation Receiver to Receiver Isolation vs. Receiver LO

Figure 721. Observation Receiver to Observation Receiver Isolation vs.

The high band match board frequency range is 4500 MHz to 6000 MHz. The temperature settings refer to the die temperature. Figure 722. Transmitter Output Power vs. LO Frequency, 10 MHz Offset, Figure 723. Transmitter LO Leakage vs. LO Frequency Figure 724. Receiver Integrated Noise Figure vs. LO Frequency, Figure 725. Receiver LO Leakage vs. LO Frequency, Figure 726. Receiver Carrier Rejection vs. LO Frequency Figure 727. Receiver Signal Power at SMA Connector vs. LO Frequency

Figure 728. Observation Receiver (ORX) Integrated NSD vs. LO Frequency,

7864.32 MSPS Sample Rate

Figure 729. Transmitter to Transmitter Isolation vs. Transmitter LO Figure 730. Transmitter to Receiver Isolation vs. Receiver LO Frequency Figure 731. Transmitter to Observation Receiver Isolation vs. Observation Figure 732. Receiver to Receiver Isolation vs. Receiver LO Frequency Figure 733. Observation Receiver to Receiver Isolation vs. Receiver LO

Figure 734. Observation Receiver to Observation Receiver Isolation vs.

The ultrahigh band match board frequency range is 6000 MHz to 7100 MHz. The temperature settings refer to the die temperature. Figure 735. Transmitter Output Power vs. LO Frequency, 10 MHz Offset, Figure 736. Transmitter LO Leakage vs. LO Frequency Figure 737. Receiver Integrated Noise Figure vs. LO Frequency, Figure 738. Receiver LO Leakage vs. Receiver LO Frequency, Figure 739. Receiver Carrier Rejection vs. LO Frequency Figure 740. Receiver Signal Power at SMA Connector vs. LO Frequency

Figure 741. Observation Receiver (ORX) Integrated NSD vs. LO Frequency, Figure 742. Transmitter to Transmitter Isolation vs. Transmitter LO Figure 743. Transmitter to Receiver Isolation vs. Receiver LO Frequency Figure 744. Transmitter to Observation Receiver Isolation vs. Observation Figure 745. Receiver to Receiver Isolation vs. Receiver LO Frequency Figure 746. Observation Receiver to Receiver Isolation vs. Receiver LO

Figure 747. Observation Receiver to Observation Receiver Isolation vs.

analog.com Rev. A | 160 of 163 The ADRV9032R is a highly integrated RF transceiver capable of configuration for a wide range of applications. The device integrates all the RF, mixed-signal, and digital blocks necessary to provide all transmitter, traffic receiver, and observation receiver functions in a single device. Programmability allows the device to be adapted for use in many applications. Two observation receiver channels monitor the transmitter outputs and provide tracking correction of DC offset, quadrature error, and transmitter LO leakage to maintain a high-performance level under varying temperatures and input signal conditions. Firmware sup- plied with the device implements all initialization and calibration with no user interaction. Additionally, the device includes test modes allowing system designers to debug designs during prototyping and to optimize radio configurations. The ADRV9032R contains eight high-speed serial interface (SERDES) links for the transmit chain and eight high-speed links shared by the receiver and observation receiver chains (JESD204B Subclass 1 compliant and supports JESD204C). TRANSMITTER The ADRV9032R transmitter section consists of two identical and independently controlled channels that provide all the digital proc- essing, mixed-signal, and RF blocks necessary to implement a direct conversion system while sharing a common frequency syn- thesizer. The digital data from the SERDES lanes pass through a digital processing block that includes a series of programmable half-band filters, interpolation stages, and FIR filters, including a programmable FIR filter with variable interpolation rates and up to 24 taps. The output of this digital chain is connected to the digital-to-analog converter (DAC). The DAC sample rate is adjusta- ble for either 2949.12 MHz or 3932.16 MHz. The in-phase (I) and quadrature (Q) channels are identical in each transmitter signal chain. After conversion to baseband analog signals, the I and Q signals are filtered to remove sampling artifacts and fed to the upcon- version mixers. Each transmit chain provides a wide attenuation adjustment range with fine granularity to help designers optimize SNR. RECEIVER The ADRV9032R provides two independent receiver channels. Each channel contains all the blocks necessary to receive RF signals and convert these signals to digital data usable by a base- band processor. Each channel contains a programmable attenuator stage, followed by matched I and Q mixers that downconvert received signals to baseband for digitization. Two gain-control options are available, as follows: ►Users can implement their own gain-control algorithms using their baseband processor to manage manual gain-control mode. ►Users can use the on-chip AGC system. Performance is optimized by mapping each gain-control setting to specific attenuation levels at each adjustable gain block in the re- ceive signal path. Additionally, each channel contains independent receive signal power measurement capability, DC offset tracking, and all the circuitry necessary for self-calibration. The receivers include ADCs and adjustable sample rates that produce data streams from the received signals. The signals can be conditioned further by a series of decimation filters and a program- mable FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing decimation factors to produce the desired output data rate. All receiver outputs are connected to the SERDES block, where the data is formatted and serialized for transmission to the baseband processor. OBSERVATION RECEIVER The ADRV9032R provides two independent observation receiver inputs. Unlike the receiver channels, the observation receiver chan- nels' path implements direct RF sampling. An RF ADC eliminates the need for a LO, which eliminates spurious often seen with LO coupling. Each channel also contains a programmable attenuator stage that provides 16 dB attenuation in analog domain with rough- ly 1 dB step size. REFERENCE CLOCK INPUT The ADRV9032R requires a differential clock connected to the DEVCLK± pins. The frequency of the clock input must be between 61.44 MHz and 491.52 MHz and must have low phase noise because this signal generates the RF LO and internal sampling clocks. SYNTHESIZERS The ADRV9032R contains four fractional-N PLLs to generate the RF LO for the signal paths and all internal clock sources. This group of PLLs includes two RF PLLs for transmit and receive LO generation, an SERDES PLL, and a clock PLL. Each PLL is independently controlled with no need for external components to set frequencies. RF Synthesizers The two RF synthesizers use fractional-N PLLs to generate RF LOs for multiple receiver and transmitter channels. The fractional-N PLL incorporates a four-core internal voltage-controlled oscillator (VCO) and loop filter, capable of generating low phase noise signals with no external components required. An internal LO multiplexer (mux) enables each PLL to supply LOs to the desired receivers and trans- mitters (for example, LO1 to all transmitters, LO2 to all receivers), resulting in maximum flexibility when configuring the device for TDD operation. The LOs on multiple devices can be phase synchronized to support active antenna systems and beam forming applications.

analog.com Rev. A | 161 of 163 SERDES Synthesizer The SERDES synthesizer uses a single core VCO fractional‑ N PLL to generate the required clock for the serializer/deserializer physical layer (SERDES PHY) to achieve the desired lane rate. Clock Synthesizer The ADRV9032R contains a single core VCO fractional-N PLL synthesizer that generates all baseband related clock signals and SERDES clocks. This fractional-N PLL is programmed based on the data rate and sample rate requirements of the system, which typically require the system to operate in integer mode. External LO Inputs The ADRV9032R provides two external LO inputs, which allow an external synthesizer to be used with the device. These inputs must be at least 2× the desired LO frequency. See the external LO input section in Table 1 for more information. SPI The ADRV9032R uses an SPI to communicate with the baseband processor. This interface can be configured as a 4-wire interface with dedicated receive and transmit ports, or the interface can be configured as a 3-wire interface with a bidirectional data communi- cations port. This bus allows the baseband processor to set all device control parameters using a simple address data serial bus protocol. Write commands follow a 24-bit format. The first bit sets the bus direction of the bus transfer. The next 15 bits set the address where data is written. The final eight bits are the data being transferred to the specific register address. Read commands follow a similar format with the exception that the first 16 bits are transferred on the SPI_DIO pin, and the final eight bits are read from the ADRV9032R, either on the SPI_DO pin in 4-wire mode or on the SPI_DIO pin in 3-wire mode. GPIO_X PINS The ADRV9032R provides 24 GPIOs referenced to VIF that can be configured for numerous functions. When configured as outputs, certain pins can provide real-time signal information to the base- band processor, allowing the baseband processor to determine receiver performance. A pointer register selects what information is output to these pins. The signals used for manual gain mode, calibration flags, state machine status, and various receiver parameters are among the outputs that can be monitored on the GPIO pins. Additionally, certain GPIO pins can be configured as inputs and used for various functions, such as setting the receiver gain in real time. GPIO_ANA_x The ADRV9032R contains 16 analog GPIOs ports that can be used to control other analog devices or receive control inputs referenced to the VDDA_1P8 supply.

analog.com Rev. A | 162 of 163 POWER SUPPLY SEQUENCE The ADRV9032R requires a specific power-up sequence to avoid undesired power-up currents. In the optimal power-up sequence, the VDIG_0P8 supply is activated first. After the VDIG_0P8 source is enabled, the VANA_1P0 supplies must be enabled next, followed by the VANA_1P8 supplies. Note that the VIF_1P8 supply can be enabled at any time without affecting the other circuits in the device. In addition to this sequence, it is also recommended to toggle the RESET signal after power has stabilized before initializing the device. The power-down sequence recommendation is similar to power-up. All supplies must be disabled in reverse order (or all together) before VDIG_0P8 is disabled. If such a sequence is not possible, then all supplies must have their sources disabled simultaneously to ensure no back feeding to circuits that have been powered down. DATA INTERFACE The digital data interface for the ADRV9032R implements the JESD204B and JESD204C JEDEC standards. The serial interface operates at speeds of up to 16,500 Mbps.

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 748. 506-Ball Grid Array Thermally Enhanced [BGA_ED] Table 12. Evaluation Boards