ADRV9009

ADRV9009 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 127

Technical content

Integrated Dual RF Transmitter, Receiver, and Observation Receiver Data Sheet ADRV9009 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz Maximum tunable transmitter synthesis bandwidth:

450 MHz

Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz

APPLICATIONS

3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment GENERAL DESCRIPTION The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications. The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to- analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated. In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically. The received signals are digitized with a set of four high dynamic range, continuous time Σ-Δ ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers. The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise. The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range. The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated. The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device. The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

Rev. B | Page 4 of 127 FUNCTIONAL BLOCK DIAGRAM RX1_IN + RX1_IN – RX2_IN + RX2_IN – ORX1_IN + ORX1_IN – ORX2_IN + ORX2_IN – RF_EXT_LO_I/O+ RF_EXT_LO_I/O– TX1_OUT + TX1_OUT – TX2_OUT + TX2_OUT – Rx1 Rx2 ORx2 LO SYNTH LPF LPF LPF GPIOS, AUXADCs, AND AUXDACs GPIO_3P3_x GPIO_x AUXADC_0 THROUGH AUXADC_3 CLOCK GENERATION SYNCINx± SERDOUTx± SERDINx± SYNCOUTx± SYSREF_IN± GP_INTERRUPT RXx_ENABLE TXx_ENABLE RESET TEST SCLK CS SDO SDIO REF_CLK_IN + REF_CLK_IN – DIGITAL PROCESSING DECIMATION pFIR AGC DC-OFFSET QEC LOL JESD204B CIF/RIF LPF DAC DAC ADC ARM ADC ORx1 ADRV9009 16499-001 Tx1 Tx2 F igure 1.

Rev. B | Page 5 of 127 SPECIFICATIONS operating temperature range. LO frequency (fLO) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the Typical Performance Characteristics section for input and output circuit path loss. The device configuration profile for the 75 MHz to 525 MHz frequency range is as follows: receiver = 50 MHz bandwidth (inphase quadrature (IQ) rate = 61.44 MHz), transmitter = 50 MHz transmitter large signal bandwidth and 100 MHz transmitter synthesis bandwidth (IQ rate = 122.88 MHz), observation receiver = 100 MHz bandwidth (IQ rate = 122.88 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Unless otherwise specified, the device configuration for all other frequency ranges is as follows: receiver = 200 MHz bandwidth (IQ rate = 245.76 MHz), transmitter = 200 MHz transmitter large signal bandwidth and 450 MHz transmitter synthesis bandwidth (IQ rate = 491.52 MHz), observation receiver = 450 MHz bandwidth (IQ rate = 491.52 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments T R A N S M I T T E R S Center Frequency 75 6000 MHz Transmitter Synthesis Bandwidth

200 MHz

1.0 dB 450 MHz bandwidth, compensated by programmable finite impulse response (FIR) filter Gain Slope ±0.1 dB Any 20 MHz bandwidth span, compensated by programmable FIR filter Deviation from Linear Phase 1 Degrees 450 MHz bandwidth Transmitter Attenuation Power Control Range 0 32 dB Signal-to-noise ratio (SNR) maintained for attenuation between 0 dB and 20 dB Transmitter Attenuation Power Control Resolution 0.05 dB Transmitter Attenuation Integral Nonlinearity INL 0.1 dB For any 4 dB step Transmitter Attenuation Differential Nonlinearity DNL 0.04 dB Monotonic Transmitter Attenuation Serial Peripheral Interface 2 (SPI 2) Timing S e e F i g u r e 4 Time from CS Going High to Change in Transmitter Attenuation tSCH 19.5 24 ns Time Between Consecutive Microattenuation Steps tACH 6.5 8.1 ns A large change in attenuation can be broken up into a series of smaller attenuation changes Time Required to Reach Final Attenuation Value tDCH 800 ns Time required to complete the change in attenuation from start attenuation to final attenuation value Maximum Attenuation Overshoot During Transition −1.0 +0.5 dB Change in Attenuation per Microstep 0.5 dB Maximum Attenuation Change when CS Goes High 32 dB

Rev. B | Page 6 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Adjacent Channel Leakage Ratio (ACLR) Long Term Evolution (LTE)

20 MHz LTE at −12 dBFS

−67 dB 75 MHz < f ≤ 2800 MHz −64 dB 2800 MHz < f ≤ 4800 MHz −60 dB 4800 MHz < f ≤ 6000 MHz In Band Noise Floor 0 dB attenuation, in band noise falls 1 dB for each dB of attenuation for attenuation between 0 dB and 20 dB −147 dBm/Hz 75 MHz < f ≤ 600 MHz −148 dBm/Hz 600 MHz < f ≤ 3000 MHz −149 dBm/Hz 3000 MHz < f ≤ 4800 MHz −150.5 dBm/Hz 4800 MHz < f ≤ 6000 MHz Out of Band Noise Floor 0 dB attenuation, 3 × bandwidth/2 offset −147 dBm/Hz 75 MHz < f ≤ 600 MHz −153 dBm/Hz 600 MHz < f ≤ 3000 MHz −154 dBm/Hz 3000 MHz < f ≤ 4800 MHz −155.5 dBm/Hz 4800 MHz < f ≤ 6000 MHz Interpolation Images −80 dBc Transmitter to Transmitter Isolation 85 dB 75 MHz < f ≤ 600 MHz 75 dB 600 MHz < f ≤ 2800 MHz 70 dB 2800 MHz < f ≤ 4800 MHz 65 dB 4800 MHz < f ≤ 5700 MHz 56 dB 5700 MHz < f ≤ 6000 MHz I m a g e R e j e c t i o n Within Large Signal Bandwidth Q E C a c t i v e 70 dB 75 MHz < f ≤ 600 MHz 65 dB 600 MHz < f ≤ 4000 MHz 62 dB 4000 MHz < f ≤ 4800 MHz 60 dB 4800 MHz < f ≤ 6000 MHz Beyond Large Signal Bandwidth 40 dB Assumes that distortion power density is 25 dB below desired power density Maximum Output Power 0 dBFS, continuous wave (CW) tone into 50 Ω load, 0 dB transmitter attenuation 9 dBm 75 MHz < f ≤ 600 MHz 7 dBm 600 MHz < f ≤ 3000 MHz 6 dBm 3000 MHz < f ≤ 4800 MHz 4.5 dBm 4800 MHz < f ≤ 6000 MHz Third-Order Output Intermodulation Intercept Point OIP3 0 dB transmitter attenuation 29 dBm 75 MHz < f ≤ 600 MHz 27 dBm 600 MHz < f ≤ 4000 MHz 23 dBm 4000 MHz < f ≤ 6000 MHz Carrier Leakage With LO leakage correction active, 0 dB attenuation, scales decibel for decibel with attenuation, measured in 1 MHz bandwidth, resolution bandwidth and video bandwidth = 100 kHz, rms detector, 100 trace average Carrier Offset from LO −84 dBFS 75 MHz < f ≤ 600 MHz −82 dBFS 600 MHz < f ≤ 4800 MHz −80 dBFS 4800 MHz < f ≤ 6000 MHz Carrier on LO −71 dBFS

Rev. B | Page 7 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Error Vector Magnitude (Third Generation Partnership Project (3GPP) Test Signals) EVM 75 MHz LO 0.5 % 300 kHz RF PLL loop bandwidth, test equipment phase noise performance limited 1900 MHz LO 0.7 % 50 kHz RF PLL loop bandwidth 3800 MHz LO 0.7 % 300 kHz RF PLL loop bandwidth 5900 MHz LO 1.1 % 300 kHz RF PLL loop bandwidth Output Impedance Z OUT 50 Ω Differential (see Figure 427) OBSERVATION RECEIVER ORx Center Frequency 75 6000 MHz Gain Range 30 dB Third-order input intermodulation intercept point (IIP3) improves decibel for decibel for the first 18 dB of gain attenuation, QEC performance optimi- zed for 0 dB to 6 dB of attenuation only Analog Gain Step 0.5 dB For at tenuator steps from 0 dB to 6 dB Peak-to-Peak Gain Deviation 1 dB 450 MHz bandwidth, compensated by programmable FIR filter Gain Slope ±0.1 dB Any 20 MHz bandwidth span, compens- ated by programmable FIR filter Deviation from Linear Phase 1 Degree s

450 MHz RF bandwidth

Observation Receiver Alias Band Rejection 60 dB Due to digital filters Maximum Useable Input Level PHIGH 0 dB attenuation, increases decibel for decibel with attenuation, CW corresponds to −1 dBFS at ADC −11 dBm 75 MHz < f ≤ 3000 MHz −9.5 dBm 3000 MHz < f ≤ 4800 MHz −8 dBm 4800 MHz < f ≤ 6000 MHz Integrated Noise −58.5 dBFS 450 MHz integration bandwidth −57.5 dBFS 491.52 MHz integration bandwidth Second-Order Input Intermodulation Intercept Point IIP2 62 dBm Maximum observation receiver gain, HIGH − 14 dB) per tone (see the Terminology section), 75 MHz < f ≤

600 MHz

62 dBm Maximum observation receiver gain, (PHIGH − 8 dB) per tone (see the Terminology section), 600 MHz < f ≤

3000 MHz

Narrow Band 4 dBm 75 MHz < f ≤ 300 MHz, test condition: (PHIGH − 14) dB per tone 11 dBm 300 MHz < f ≤ 600 MHz, (PHIGH − 14) dB per tone Third-order intermodulation product (IM3) product < 130 MHz at baseband, HIGH − 8) dB per tone 12 dBm 600 MHz < f ≤ 3000 MHz 12 dBm 3000 MHz < f ≤ 4800 MHz 11 dBm 4800 MHz < f ≤ 6000 MHz

Rev. B | Page 8 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Wide Band 7 dBm 600 MHz < f ≤ 3000 MHz 7 dBm 3000 MHz < f ≤ 4800 MHz 6 dBm 4800 MHz < f ≤ 6000 MHz Third-Order Intermodulation Product IM3 IM3 product < 130 MHz at baseband, two tones, each at (PHIGH − 12) dB −70 dBc 600 MHz < f ≤ 3000 MHz −67 dBc 3000 MHz < f ≤ 4800 MHz −62 dBc 4800 MHz < f ≤ 6000 MHz Fifth-Order Intermodulation Product (1800 MHz) IM5 −80 dBc IM5 product < 50 MHz at baseband, two tones, each at (PHIGH − 12) dB,

600 MHz < f ≤ 6000 MHz

(1800 MHz) IM7 −80 dBc IM7 product < 50 MHz at baseband, two tones, each at (P HIGH − 12) dB, SFDR 70 dB Non IMx related spurs, does not include HDx, (PHIGH − 9) dB input signal, Harmonic Distortion (P HIGH − 11) dB input signal Second-Order Harmonic Distortion Product HD2 −80 dBc (PHIGH – 11) dB input signal 75 MHz < f ≤

600 MHz, (PHIGH – 9) dB input signal

600 MHz < f ≤ 6000 MHz, in band harmo-

nic distortion falls within ±100 MHz −80 dBc Out of band harmonic distortion falls within ±225 MHz Third-Order Harmonic Distortion Product HD3 −70 dBc In band harmonic distortion falls within ±100 MHz −60 dBc Out of band harmonic distortion falls within ±225 MHz Image Rejection QEC active Within Large Signal Bandwidth 65 dB Outside Large Signal Bandwidth 55 dB Input Impedance 100 Ω Differential (see Figure 428) Isolation Transmitter 1 (Tx1) to Observation Receiver 1 (ORx1) and Transmitter 2 (Tx2) to Observation Receiver 2 (ORx2) 100 dB 75 MHz < f ≤ 600 MHz 65 dB 600 MHz < f ≤ 5300 MHz 55 dB 5300 MHz < f ≤ 6000 MHz Tx1 to ORx2 and Tx2 to ORx1 105 dB 75 MHz < f ≤ 600 MHz 65 dB 600 MHz < f ≤ 5300 MHz 55 dB 5300 MHz < f ≤ 6000 MHz RECEIVERS Center Frequency 75 6000 MHz Gain Range 30 dB Analog Gain Step 0.5 dB Attenuator steps from 0 dB to 6 dB 1 dB Attenuator steps from 6 dB to 30 dB Bandwidth Ripple ±0.5 dB 200 MHz bandwidth, compensated by programmable FIR filter ±0.2 dB Any 20 MHz bandwidth span, compens- ated by programmable FIR filter

Rev. B | Page 9 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Receiver Bandwidth 200 MHz Receiver Alias Band Rejection 80 dB Due to digital filters Maximum Useable Input Level PHIGH 0 dB attenuation, increases decibel for decibel with attenuation, CW =

1800 MHz, corresponds to −1 dBFS at

−11 dBm 75 MHz < f ≤ 3000 MHz −10.2 dBm 3000 MHz < f ≤ 4800 MHz −9.5 dBm 4800 MHz < f ≤ 6000 MHz Noise Figure NF 0 dB attenuation, at receiver port 11.5 dB 75 MHz < f ≤ 600 MHz 12 dB 600 MHz < f ≤ 3000 MHz 13 dB 3000 MHz < f ≤ 4800 MHz 15.2 dB 4800 MHz < f ≤ 6000 MHz Ripple 1.8 dB At band edge maximum bandwidth mode Third-Order Input Intermodulation Intercept Point IIP3 Difference Product IIP3D 12 dBm 75 MHz < f ≤ 600 MHz, (PHIGH − 12) dB per tone, 600 MHz < f ≤ 6000 MHz, HIGH − 10) dB per tone, two tones near band edge Sum Product IIP3S 12 dBm 75 MHz < f ≤ 600 MHz, (PHIGH − 12) dB per tone, 600 MHz < f ≤ 6000 MHz, HIGH − 10) dB per tone, two tones at bandwidth/6 offset from the LO Third-Order Harmonic Distortion Product HD3 75 MHz < f ≤ 600 MHz, (PHIGH − 6) dB,

600 MHz < f ≤ 6000 MHz, (PHIGH − 4) dB,

CW tone at bandwidth/6 offset from the LO −65 dBc 75 MHz < f ≤ 600 MHz −66 dBc 600 MHz < f ≤ 4800 MHz −62 dBc 4800 MHz < f ≤ 6000 MHz Second-Order Input Intermodulation Intercept Point IIP2 62 dBm 75 MHz < f ≤ 600 MHz, (P HIGH − 12) dB per tone, 600 MHz < f ≤ 6000 MHz, HIGH − 10) dB per tone, 0 dB attenuation, complex Image Rejection 75 dB QEC active, within 200 MHz receiver bandwidth Input Impedance 100 Ω Differential (see Figure 429) Receiver to Receiver Isolation 77 dB 75 MHz < f ≤ 600 MHz 65 dB 600 MHz < f ≤ 4800 MHz 61 dB 4800 MHz < f ≤ 6000 MHz Receiver Band Spurs Referenced to RF Input at Maximum Gain −95 dBm No more than one spur at this level per

10 MHz of receiver bandwidth

Leakage decreases decibel for decibel with attenuation for first 12 dB −70 dBm 75 MHz < f ≤ 600 MHz −70 dBm 600 MHz < f ≤ 3000 MHz −65 dBm 3000 MHz < f ≤ 6000 MHz

Rev. B | Page 10 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments LO SYNTHESIZER LO Frequency Step 2.3 Hz 1.5 GHz to 2.8 GHz, 76.8 MHz phase frequency detector (PFD) frequency LO Spur −85 dBc Excludes integer boundary spurs Integrated Phase Noise 2 kHz to 18 MHz 75 MHz LO 0.014 °rms Narrow PLL loop bandwidth (50 kHz) 1900 MHz LO 0.2 °rms Narrow PLL loop bandwidth (50 kHz) 3800 MHz LO 0.36 °rms Wide PLL loop bandwidth (300 kHz) 5900 MHz LO 0.54 °rms Wide PLL loop bandwidth (300 kHz) Spot Phase Noise

75 MHz LO Narrow PLL loop bandwidth

10 kHz Offset −126.5 dBc/Hz 100 kHz Offset −132.8 dBc/Hz 1 MHz Offset −150.1 dBc/Hz 10 MHz Offset −150.7 dBc/Hz

1900 MHz LO Narrow PLL loop bandwidth

100 kHz Offset −100 dBc/Hz 200 kHz Offset −115 dBc/Hz 400 kHz Offset −120 dBc/Hz 600 kHz Offset −129 dBc/Hz 800 kHz Offset −132 dBc/Hz

1.2 MHz Offset −135 dBc/Hz

1.8 MHz Offset −140 dBc/Hz

6 MHz Offset −150 dBc/Hz

10 MHz Offset −153 dBc/Hz

3800 MHz LO Wide PLL loop bandwidth

100 kHz Offset −104 dBc/Hz

1.2 MHz Offset −125 dBc/Hz

10 MHz Offset −145 dBc/Hz

5900 MHz LO Wide PLL loop bandwidth

100 kHz Offset −99 dBc/Hz 1.2 MHz Offset −119.7 dBc/Hz 10 MHz Offset −135.4 dBc/Hz LO PHASE SYNCHRONIZATION Phase Deviation 1.6 ps/°C Change in LO delay per temperature change EXTERNAL LO INPUT Input Frequency f EXTLO 150 8000 MHz Input frequency must be 2 × the desired LO frequency Input Signal Power 0 12 dBm 50 Ω matching at the source 3 dBm fEXTLO ≤ 2 GHz, add 0.5 dBm/GHz above

2 GHz

6 dBm f EXTLO = 8 GHz External LO Input Signal Differential To ensure adequate QEC Phase Error 3.6 ps Amplitude Error 1 dB Duty Cycle Error 2 % Even Order Harmonics −50 dBc CLOCK SYNTHESIZER Integrated Phase Noise 1 kHz to 100 MHz 1966.08 MHz LO 0.4 °rms PLL optimized for close in phase noise

Rev. B | Page 11 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Spot Phase Noise

1966.08 MHz

100 kHz Offset −109 dBc/Hz

1 MHz Offset −129 dBc/Hz

10 MHz Offset −149 dBc/Hz

(REF_CLK_IN±) Frequency Range 10 1000 MHz Signal Level 0.3 2.0 V p-p AC-coupled, common-mode voltage (VCM) = 618 mV, for best spurious performance use <1 V p-p input clock AUXILIARY CONVERTERS ADC Resolution 12 Bits Input Voltage Minimum 0.05 V Maximum VDDA_ 3P3 − 0.05 V DAC Resolution 10 Bits Includes four offset levels Output Voltage Minimum 0.7 V 1 V voltage reference (VREF) Maximum VDDA_ 3P3 − 0.3 V 2.5 V VREF Output Drive Capability 10 mA DIGITAL SPECIFICATIONS (COMPLEMENTARY METAL- OXIDE SEMICONDUCTOR (CMOS)) FOR SPI, GPIO_x, TXx_ENABLE, ORXx_ENABLE Logic Inputs Input Voltage High Level VDD_ INTERFACE × 0.8 VDD_ INTERFACE V Low Level 0 VDD_ INTERFACE × 0.2 V Input Current High Level −10 +10 μA Low Level −10 +10 μA Logic Outputs Output Voltage High Level VDD_ INTERFACE × 0.8 V Low Level VDD_ INTERFACE × 0.2 V Drive Capability 3 mA

Rev. B | Page 12 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments DIGITAL SPECIFICATIONS (CMOS) FOR GPIO_3P3_x Logic Inputs Input Voltage High Level VDDA_ 3P3 × 0.8 VDDA_3P3 V Low Level 0 VDDA_ 3P3 × 0.2 V Input Current High Level −10 +10 μA Low Level −10 +10 μA Logic Outputs Output Voltage High Level VDDA_ 3P3 × 0.8 V Low Level VDDA_ 3P3 × 0.2 V Drive Capability 4 mA DIGITAL SPECIFICATIONS (LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)) Logic Inputs (SYSREF_IN±, SYNCINx±) Input Voltage Range 825 1675 mV Each differential input in the pair Input Differential Voltage Threshold −100 +100 mV Receiver Differential Input Impedance 100 Ω Internal termination enabled Logic Outputs (SYNCOUTx±) Output Voltage High 1375 mV Low 1025 mV Output Differential Voltage 225 mV Programmable in 75 mV steps Output Offset Voltage 1200 mV SPI TIMING SCLK Period t CP 20 ns SCLK Pulse Width t MP 10 ns CS Setup to First SCLK Rising Edge tSC 3 ns Last SCLK Falling Edge to CS Hold tHC 0 ns SDIO Data Input Setup to SCLK tS 2 ns SDIO Data Input Hold to SCLK tH 0 ns SCLK Rising Edge to Output Data Delay (3-Wire or 4-Wire Mode) t CO 3 8 ns Bus Turnaround Time, Read After Baseband Processor (BBP) Drives Last Address Bit t HZM t H t CO ns Bus Turnaround Time, Read After ADRV9009 Drives Last Data Bit t HZS 0 t CO ns

Rev. B | Page 13 of 127 Parameter Symbol Min Typ Max Unit Test Conditions/Comments JESD204B DATA OUTPUT TIMING AC-coupled Unit Interval UI 81.38 320 ps Data Rate per Channel, Nonreturn to Zero (NRZ) 3125 12,288 Mbps Rise Time t R 24 39.5 ps 20% to 80% in 100 Ω load Fall Time t F 24 39.4 ps 20% to 80% in 100 Ω load Output Common-Mode Voltage VCM 0 1.8 V AC-coupled Differential Output Voltage V DIFF 360 600 770 mV Short-Circuit Current I DSHORT −100 +100 mA Differential Termination Impedance 80 94.2 120 Ω Total Jitter 15.13 ps Bit error rate (BER) = 10 −15 Uncorrelated Bounded High Probability Jitter UBHPJ 0.56 ps Duty Cycle Distortion DCD 0.369 ps SYSREF_IN± Setup Time to REF_CLK_IN± 2.5 ns See Figure 2 SYSREF_IN± Hold Time to REF_CLK_IN± −1.5 ns See Figure 2 Latency t LAT_FRM REF_CLK_IN± = 245.76 MHz

116.5 Clock

Observation receiver bandwidth = 450 MHz, IQ rate = 491.52 MHz, lane rate = 9830.4 MHz, number of converters (M) = 4, number of lanes (L) = 2, converter resolution (N) = 16, number of samples per converter (S) = 1 237.02 ns

89.4 Clock

Receiver bandwidth = 200 MHz, IQ rate = 245.76 MHz, lane rate = 9830.4 MHz, 364.18 ns JESD204B DATA INPUT TIMING AC-coupled Unit Interval UI 81.38 320 ps Data Rate per Channel (NRZ) 3125 12288 Mbps Differential Voltage V DIFF 125 750 mV Termination Voltage (VTT) Source Impedance ZTT 8.9 30 Ω Differential Impedance Z RDIFF 80 105.1 120 Ω Termination Voltage V TT Ω AC-Coupled 1.267 1.33 V Latency t LAT_DEFRM 74.45 Clock cycles Device clock = 245.76 MHz, transmitter bandwidth = 200 MHz, IQ rate = 491.52 MHz, lane rate = 9830.4 MHz, 153.5 ns 1 VDDA1P3 refers to all analog 1.3 V supplies, including: VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO, VDDA1P3_DES, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

Rev. B | Page 14 of 127 CURRENT AND POWER CONSUMPTION SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY CHARACTERISTICS VDDA1P31 Analog Supply 1.267 1.3 1.33 V VDDD1P3_DIG Supply 1.267 1.3 1.33 V VDDA1P8_TX Supply 1.71 1.8 1.89 V VDDA1P8_BB Supply 1.71 1.8 1.89 V VDDA_3P3 Supply 3.135 3.3 3.465 V POSITIVE SUPPLY CURRENT L O at 2600 MHz

450 MHz Transmitter Bandwidth,

Observation Receiver Disabled T wo transmitters enabled VDDA1P31 Analog Supply 152 0 mA VDDD1P3_DIG Supply 619 mA T ransmitter QEC active VDDA1P8_TX Supply 455 mA T ransmitter RF attenuation = 0 dB, full-scale CW 135 mA T ransmitter RF attenuation = 15 dB, full-scale CW VDDA1P8_BB Supply 30 mA VDD_INTERFACE Supply 8 mA V DD_INTERFACE = 2.5 V VDDA_3P3 Supply 3 mA N o Auxiliary DAC x or AUXADC_x enabled, if enabled, AUXADC_x adds 2.7 mA and each Auxiliary DAC x adds 1.5 mA Total Power Dissipation 3. 68 W Typical supply voltages, 0 dB transmitter attenuation, transmitter QEC active 3. 11 W Typical supply voltages, 15 dB transmitter attenuation, transmitter QEC active Observation Receiver Enabled T wo transmitters enabled, one ORx enabled VDDA1P31 Analog Supply 207 3 mA VDDD1P3_DIG Supply 1541 mA Transmitter QEC tracking active, observation receiver QEC enabled, transmitter L TE20 centered on LO, observation receiver L TE20 at −16 dBm centered on LO 210 0 mA T ransmitter two tone = −99 MHz and 100 MHz at −7 dBFS each, observation receiver one tone = 100 MHz at −16 dBm VDDA1P8_TX Supply 455 mA T ransmitter RF attenuation = 0 dB, full scale CW 135 mA T ransmitter RF attenuation = 15 dB, full scale CW VDDA1P8_BB Supply 63 mA VDD_INTERFACE Supply 8 mA V DD_INTERFACE = 2.5 V VDDA_3P3 Power Supply 3 mA N o Auxiliary DAC x or AUXADC_x enabled, if enabled, AUXADC_x adds 2.7 mA and each Auxiliary DAC x adds 1.5 mA Total Power Dissipation 5.66 W Typical supply voltages, 0 dB transmitter attenuation, transmitter QEC active 5. 08 W Typical supply voltages, 15 dB transmitter attenuation, transmitter QEC active

200 MHz Receiver Bandwidth,

Observation Receiver Disabled T wo receivers enabled VDDA1P31 Analog Supply 164 5 mA VDDD1P3_DIG Supply 984 mA R eceiver QEC active VDDA1P8_TX Supply 0. 4 mA VDDA1P8_BB Supply 68 mA VDD_INTERFACE Supply 8 mA VDDA_3P3 Supply 3 mA N o Auxiliary DAC x or AUXADC_x enabled, if enabled, AUXADC_x adds 2.7 mA and each Auxiliary DAC x adds 1.5 mA Total Power Dissipation 3. 57 W Typical supply voltages, receiver QEC active 1 VDDA1P3 refers to all analog 1.3 V supplies, including: VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO, VDDA1P3_DES, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

Rev. B | Page 15 of 127 TIMING DIAGRAMS REF_CLK_IN± AT DEVICE PINS AT DEVICE COREREF_CLK_IN± DELAY IN REFERENCE TO SYSREF_IN± CLK DELAY = 2nstH = –1.5ns tS = +2.5ns t’H = +0.5ns t’S = +0.5ns tS tH tS tH t’H t’S t’S t’H 16499-005 NOTES 1. tH AND tS ARE THE HOLD AND SETUP TIMES FOR THE REF_CLK_IN± PINS. t’H AND t’S REFER TO THE DELAYED HOLD AND SETUP TIMES AT THE DEVICE CORE IN REFERENCE TO THE SYSREF_N± SIGNALS DUE TO AN INTERNAL BUFFER THAT THE SIGNAL PASSES THROUGH. F igure 2. SYSREF_IN± Setup and Hold Timing REF_CLK_IN± SYSREF_IN± VALID SYSREF INVALID SYSREF tH = –1.5ns tS = +2.5ns tS tH tS tH tS tH tS tH 16499-006 F igure 3. SYSREF_IN± Setup and Hold Timing Examples, Relative to Device Clock tDCH tSCH tACH SCLK SDIO CS Tx ATTENUATION 16499-007 F igure 4. Transmitter Attenuation Update via SPI 2 Port

1 VDDA1P3 refers to all analog 1.3 V supplies. 3 W depending on the user application and configuration. where the case temperature is measured at the top of the package. accurately reflects the PCB used in customer applications. Table 4. Thermal Resistance1, 2 assumed to have 3.6 thermal conductivity watts/(meter × Kelvin).

2 Using enhanced heat removal techniques such as PCB, heat sink, and airflow

improves the thermal resistance values.

Table 5. Pin Function Descriptions

Rev. B | Page 18 of 127 Pin No. Type Mnemonic Description A5, A6 Input RX2_IN+, RX2_IN− Differential Input for Main Receiver 2. When unused, connect these pins to ground. A9, A10 Input RX1_IN+, RX1_IN− Differential Input for Main Receiver 1. When unused, connect these pins to ground. A12, A13 Input ORX1_IN+, ORX1_IN− Differential Input for Observation Receiver 1. When unused, connect these pins to ground. B1 Input VDDA1P3_RX_RF Observation Receiver Supply. B7, B8 Input RF_EXT_LO_I/O−, RF_EXT_LO_I/O+, Differential External LO Input/Output. If these pins are used for the external LO, the input frequency must be 2× the desired carrier frequency. When unused, do not connect these pins. C1 Input/ output GPIO_3P3_0 GPIO Pin Referenced to 3.3 V Supply. The alternate function is AUXDAC_4. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or this pin can be left floating, programmed as outputs, and driven low. C2 Input/ output GPIO_3P3_3 GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. C13 Input/ output GPIO_3P3_9 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_9. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. D1 Input/ output GPIO_3P3_1 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_5. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. D2 Input/ output GPIO_3P3_4 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_6. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. D13 Input/ output GPIO_3P3_8 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_1. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. D14 Input/ output GPIO_3P3_10 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_0. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. E1 Input/ output GPIO_3P3_2 GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. E2 Input/ output GPIO_3P3_5 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_7. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. E3 Input/ output GPIO_3P3_6 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_8. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low.

Rev. B | Page 19 of 127 Pin No. Type Mnemonic Description E13 Input/ output GPIO_3P3_7 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_2. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. E14 Input/ output GPIO_3P3_11 GPIO Pin Referenced to 3.3 V Supply. The alternative function is AUXDAC_3. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or these pins can be left floating, programmed as outputs, and driven low. C3 Input VDDA1P3_RX_TX 1.3 V Supply for Transmitter/Receiver Baseband Circuits, Transimpedance Amplifier (TIA), Transmitter Transconductance (GM), Baseband Filters, and Auxiliary DACs. C5, C6 Input VDDA1P3_RF_VCO_LDO RF VCO LDO Supply Inputs. Connect Pin C5 to Pin C6. Use a separate trace on the PCB back to a common supply point. C7 Input VDDA1P1_RF_VCO 1.1 V VCO Supply. Decouple this pin with 1 μF . C8 Input VDDA1P3_RF_LO 1.3 V LO Generator for the RF Synthesizer. This pin is sensitive to supply noise. C10 Input VDDA1P3_AUX_VCO_LDO 1.3 V Supply. C12 Input VDDA_3P3 General-Purpose Output Pull-Up Voltage and Auxiliary DAC Supply Voltage. C14 Input/ output RBIAS Bias Resistor. Tie this pin to ground using a 14.3 kΩ resistor. This pin generates an internal current based on an external 1% resistor. D10 Input VDDA1P1_AUX_VCO 1.1 V VCO Supply. Decouple this pin with 1 μF . E4 Input VDDA1P8_BB 1.8 V Supply for the ADC and DAC. E5 Input VDDA1P3_BB 1.3 V Supply for the ADC, DAC, and AUXADC. E7, E8 Input REF_CLK_IN+, REF_CLK_IN− Device Clock Differential Input. E10 Output AUX_SYNTH_OUT Auxiliary PLL Output. When unused, do not connect this pin. E12 Input VDDA1P8_TX 1.8 V Supply for Transmitter. F3, F4, F11, E11 Input AUXADC_0 to AUXADC_3 Auxiliary ADC Input. When unused, connect these pins to ground with a pull-down resistor, or connect directly to ground. G5 Input VDDA1P3_CLOCK_SYNTH 1.3 V Supply Input for Clock Synthesizer. Use a separate trace on the PCB back to a common supply point. G7 Input VDDA1P3_RF_SYNTH 1.3 V RF Synthesizer Supp ly Input. This pin is sensitive to supply noise. G8 Input VDDA1P3_AUX_SYNTH 1.3 V Auxiliary Synthesizer Supply Input. G9 Output RF_SYNTH_VTUNE RF Synthesizer VTUNE Output. H11 Input/ output GPIO_12 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. H12 Input/ output GPIO_11 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. J11 Input/ output GPIO_13 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. J12 Input/ output GPIO_10 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low.

Rev. B | Page 20 of 127 Pin No. Type Mnemonic Description J3 Input/ output GPIO_18 Digital GPIO, 1.8 V to 2.5 V. The joint test action group (JTAG) function is TCLK. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. J7 Input/ output GPIO_2 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. J8 Input/ output GPIO_1 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. K5 Input/ output GPIO_5 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TDO. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. K6 Input/ output GPIO_4 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TRST . Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. K7 Input/ output GPIO_3 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. K8 Input/ output GPIO_0 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. K11 Input/ output GPIO_14 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. K12 Input/ output GPIO_9 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. L5 Input/ output GPIO_6 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TDI. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. L6 Input/ output GPIO_7 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is TMS. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. L11 Input/ output GPIO_15 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low.

Rev. B | Page 21 of 127 Pin No. Type Mnemonic Description L12 Input/ output GPIO_8 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. M10 Input/ output GPIO_17 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. M11 Input/ output GPIO_16 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor (to safeguard against misconfiguration), or it can be left floating, programmed as output, and driven low. H14, J14 Output TX1_OUT+, TX1_OUT− Transmitter 1 Output. When unused, do not connect these pins. H1, J1 Output TX2_OUT−, TX2_OUT+ Transmitter 2 Output. When unused, do not connect these pins. J4 Input RESET Active Low Chip Reset. J5 Output GP_INTERRUPT General-Purpose Digital Interrupt Output Signal. When unused, do not connect this pin. J6 Input TEST Pin Used for JTAG Boundary Scan. When unused, connect this pin to ground. J9 Input/ output SDIO Serial Data Input in 4-Wire Mo de or Input/Output in 3-Wire Mode. J10 Output SDO Serial Data Output. In SPI 3-wire mode, do not connect this pin. K3, K4 Input SYSREF_IN+, SYSREF_IN− LVDS Input. K9 Input SCLK Serial Data Bus Clock. K10 Input CS Serial Data Bus Chip Select, Active Low. L3, L4 Input SYNCIN1−, SYNCIN1+ LVDS Input. These pins form the sync signal associated with receiver channel data on the JESD204B interface. When unused, connect these pins to ground with a pull-down resistor, or connect these pins directly to ground. L7, L10 Input VSSD Digital V SS. L8, L9 Input VDDD1P3_DIG 1.3 V Digital Core. Connect Pin L8 and Pin L9 together. Use a wide trace to connect to a separate power supply domain. L13, L14 Output SYNCOUT1−, SYNCOUT1+ LVDS Output. These pins form the sync signal associated with transmitter channel data on the JESD204B interface. When unused, do not connect these pins. M1 Input VDDA1P1_CLOCK_VCO 1.1 V VCO Supply. Decouple this pin with 1 μF . M3, M4 Input SYNCIN0−, SYNCIN0+ LVDS Input. These pins form the sync signal associated with receiver channel data on the JESD204B interface. When unused, connect these pins to ground with a pull-down resistor, or connect these pins directly to ground. M5 Input RX1_ENABLE Receiver 1 Enable Pin. When unused, connect this pin to ground with a pull-down resistor, or connect this pin directly to ground. M6 Input TX1_ENABLE Transmitter 1 Enable Pin. When unused, connect this pin to ground with a pull-down resistor, or connect this pin directly to ground. M7 Input RX2_ENABLE Receiver 2 Enable Pin. When unused, connect this pin to ground with a pull-down resistor, or connect this pin directly to ground. M8 Input TX2_ENABLE Transmitter 2 Enable Pin. When unused, connect this pin to ground with a pull-down resistor, or connect this pin directly to ground. M12 Input VDD_INTERFACE Input/Output Interface Supply, 1.8 V to 2.5 V. M13, M14 Output SYNCOUT0−, SYNCOUT0+ LVDS Output. These pins form the sync signal associated with transmitter channel data on the JESD204B interface. When unused, do not connect these pins.

Rev. B | Page 22 of 127 Pin No. Type Mnemonic Description N1 Input VDDA1P3_CLOCK_ VCO_LDO 1.3 V Use Separate Trace to Common Supply Point. N3, N4 Output SERDOUT3−, SERDOUT3+ RF Current Mode Logic (CML) Differential Output 3. When unused, do not connect these pins. N5, N6 Output SERDOUT2−, SERDOUT2+ RF CML Differential Output 2. When unused, do not connect these pins. N8, P8 Input VDDA1P3_SER 1.3 V Supply for JESD204B Serializer. N9, P9 Input VDDA1P3_DES 1.3 V Supply for JESD204B Deserializer. N10, N11 Input SERDIN1−, SERDIN1+ RF CML Differential Input 1. When unused, do not connect these pins. N13, N12 Input SERDIN0+, SERDIN0− RF CML Differential Input 0. When unused, do not connect these pins. P1 Output AUX_SYNTH_VTUNE Auxiliary Synthesizer VTUNE Output. P4, P5 Output SERDOUT1−, SERDOUT1+, RF CML Differential Output 1. When unused, do not connect these pins. P6, P7 Output SERDOUT0−, SERDOUT0+, RF CML Differential Output 0. When unused, do not connect these pins. P11, P12 Input SERDIN3−, SERDIN3+ RF CML Differential Input 3. When unused, do not connect these pins. P13, P14 Input SERDIN2−, SERDIN2+ RF CML Differential Input 2. When unused, do not connect these pins.

75 MHz TO 525 MHz BAND

Figure 7. Transmitter CW Output Power vs. Transmitter LO Frequency, Transmitter Figure 8. Transmitter Image Rejection vs. Baseband Offset Frequency and

48 MHz, and 100 MHz (Tracking On), Total Combined Power = −10 dBFS,

Figure 9. Transmitter Image Rejection vs. Baseband Offset Frequency and Figure 10. Transmitter Image Rejection vs. Baseband Offset Frequency and

Figure 23. Transmitter OIP3 Right vs. Baseband Frequency Offset, LO =

300 MHz, Total RMS Power = −12 dBFS, Transmitter Attenuation = 4 dB

Figure 24. Transmitter OIP3 Right vs. Baseband Frequency Offset, Figure 25. Transmitter HD2 vs. Transmitter Attenuator Setting, Figure 26. Transmitter HD2 vs. Transmitter Attenuator Setting, Figure 27. Transmitter HD2 vs. Transmitter Attenuator Setting, Figure 28. Transmitter HD3 vs. Transmitter Attenuator Setting,

Figure 35. Transmitter Attenuator Step Error vs. Transmitter Attenuator Figure 36. Transmitter Attenuator Step Error vs. Transmitter Attenuator Figure 37. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz, Figure 38. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz, Figure 39. Transmitter EVM vs. Transmitter Attenuation, LTE = 20 MHz, Figure 40. Observation Receiver LO Leakage vs. LO Frequency, LO = 75 MHz,

300 MHz, and 525 MHz, Attenuation = 0 dB

Figure 47. Observation Receiver IIP2, Sum and Difference Products vs. Observation Figure 48. Observation Receiver IIP2, Sum and Difference Products vs. Figure 49. Observation Receiver IIP2, Sum and Difference Products vs. Observation Figure 50. Observation Receiver IIP2, f1 − f2 (Where f2 is Frequency 2) vs. Figure 51. Observation Receiver IIP2, f1 − f2 vs. Intermodulation Frequency, Figure 52. Observation Receiver IIP2, f1 − f2 vs. Intermodulation Frequency, LO =

525 MHz, Tone 1 = 527 MHz, Tone 2 = Swept, −25 dBm Each, Attenuation = 0 dB

Figure 53. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver Figure 54. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver Figure 55. Observation Receiver IIP2, f1 − f2 vs. Observation Receiver Attenuation, Figure 56. Observation Receiver IIP3, 2f1 (Where 2f1 is 2 × f1) − f2 vs. Figure 57. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency, LO =

300 MHz, Attenuation = 0 dB, Tones Separated by 1 MHz Swept Across Pass Band

Figure 58. Observation Receiver IIP3, 2f1 − f2 vs. Observation Receiver

Figure 77. Transmitter to Observation Receiver Isolation vs. LO Frequency, Figure 78. LO Phase Noise vs. Frequency Offset, LO = 75 MHz, PLL Loop Figure 79. LO Phase Noise vs. Frequency Offset, LO = 300 MHz, PLL Loop Figure 80. LO Phase Noise vs. Frequency Offset, LO = 525 MHz, PLL Loop Figure 81. Receiver LO Leakage vs. Receiver LO Frequency = 75 MHz,

300 MHz, and 525 MHz, Receiver Attenuation = 0 dB, RF Bandwidth =

Figure 82. Receiver Noise Figure vs. Receiver Attenuation, LO = 75 MHz,

650 MHz TO 3000 MHz BAND

Figure 128. Transmitter Matching Circuit Path Loss vs. LO Frequency, Can be Figure 129. Transmitter CW Output Power vs. Transmitter LO Frequency, Figure 130. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 131. Transmitter Pass Band Flatness vs. Baseband Offset Frequency, Figure 132. Transmitter LO Leakage vs. Baseband LO Frequency, Transmitter Figure 133. Transmitter to Receiver Isolation vs. Receiver LO Frequency

Figure 140. Transmitter OIP3, Right vs. Transmitter Attenuator Setting, LO =

1850 MHz, 15 dB Digital Backoff per Tone

Figure 141. Transmitter OIP3, Right vs. Transmitter Attenuator Setting, LO =

2650 MHz, 15 dB Digital Backoff per Tone

Figure 142. Transmitter OIP3, Right vs. Baseband Tone Pair Swept Across Pass Figure 143. Transmitter OIP3, Right vs. Baseband Tone Pair Swept Across Pass Figure 144. Transmitter OIP3, Right vs. Baseband Tone Pair Swept Across Pass Figure 145. Transmitter HD2 vs. Transmitter Attenuator Setting, Baseband

Figure 164. Observation Receiver IIP2, f1 − f2 vs. f1 Offset Frequency, LO =

650 MHz, Tone 1 = 652 MHz, Tone 2 = Swept at −19 dBm Each, Attenuation = 0 dB

Figure 165. Observation Receiver IIP2, f1 − f2 vs. f1 Offset Frequency, LO =

1800 MHz, Tone 1 = 1802 MHz, Tone 2 = Swept at −19 dBm Each, Attenuation =

Figure 166. Observation Receiver IIP2, f1 − f2 vs. f1 Offset Frequency, LO =

2850 MHz, Tone 1 = 2852 MHz, Tone 2 = Swept at −19 dBm Each,

Figure 167. Observation Receiver IIP2, f1 − f2 vs. Attenuation, Figure 168. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency, Figure 169. Observation Receiver IIP3, 2f1 − f2 vs. f1 Offset Frequency,

3400 MHz TO 4800 MHz BAND

Figure 240. Transmitter Path Loss vs. LO Frequency (Simulation), Can Be Figure 241. Transmitter CW Output Power vs. Transmitter LO Frequency, Figure 242. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 243. Transmitter Image Rejection Across Large Signal Bandwidth vs. Figure 244. Transmitter Pass Band Flatness vs. Baseband Offset Frequency, Figure 245. Transmitter Pass Band Flatness vs. Baseband Offset Frequency,

Figure 264. Amplitude vs. Frequency, Transmitter Output Spurious, Figure 265. Observation Receiver Off Chip Matching Circuit Path Loss vs. LO Figure 266. Observation Receiver LO Leakage vs. LO Frequency, from

3600 MHz to 4600 MHz

Figure 267. Observation Receiver Noise Figure vs. Observation Receiver Figure 268. Observation Receiver Noise Figure vs. Observation Receiver Figure 269. Observation Receiver IIP2, Sum and Difference Products vs. f1

Figure 312. Receiver IIP3 vs. Attenuation, LO = 3600 MHz, Tone 1 = 3695 MHz, Figure 313. Receiver IIP3 vs. Receiver Attenuation Swept, LO = 4600 MHz,

10 Rx1 = +110°C

Figure 314. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Figure 315. Receiver IIP3 vs. Receiver Attenuation, Receiver Attenuation = 0 dB, Figure 316. Receiver IIP3 vs. Receiver Attenuation, LO = 3600 MHz, Figure 317. Receiver IIP3 vs. Receiver Attenuation, LO = 4600 MHz,

Figure 318. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Figure 319. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Figure 320. Receiver Image vs. Baseband Frequency Offset, Attenuation = Figure 321. Receiver Image vs. Baseband Frequency Offset, Attenuation =

245.76 MSPS, LO = 4600 MHz

Figure 322. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz, Figure 323. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz,

5100 MHz TO 5900 MHz BAND

Figure 340. Transmitter Path Loss vs. LO Frequency (Simulation), Useful for Figure 341. Transmitter CW Output Power vs. Transmitter LO Frequency, Figure 342. Transmitter Image Rejection vs. Baseband Offset Frequency, QEC Figure 343. Transmitter Image Rejection vs. Baseband Offset Frequency, QEC Figure 344. Transmitter Image Rejection vs. Baseband Offset Frequency, QEC Figure 345. Transmitter Pass Band Flatness vs. Baseband Offset Frequency,

Figure 364. Transmitter HD3 on Opposite Sideband vs. Transmitter

10 MHz

Figure 365. Transmitter HD3 Image on Same Sideband as Signal vs. Figure 366. Transmitter HD3 Image on Same Sideband as Signal vs. Figure 367. Transmitter HD3 Image on Same Sideband as Signal vs. Figure 368. Transmitter Attenuation Step Error vs. Transmitter Attenuator Figure 369. Transmitter Attenuation Step Error vs. Transmitter Attenuator

Figure 400. Receiver Path Loss vs. LO Frequency, Can Be Used for De- Figure 401. Receiver LO Leakage vs. Receiver LO Frequency, LO = 5200 MHz,

5500 MHz, and 5800 MHz, Receiver Attenuation = 0 dB, RF

Figure 402. Receiver IIP2 vs. Attenuation, LO = 5800 MHz LO, Tones Placed at

5845 MHz and 5846 MHz, −21 dBm Plus Attenuation

Figure 403. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Figure 404. Receiver IIP2 vs. Receiver Attenuation, LO = 5800 MHz, Tones Figure 405. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept

Figure 406. Receiver IIP3 vs. Receiver Attenuation, LO = 5800 MHz, Tone 1 =

5895 MHz, Tone 2 = 5896 MHz, −21 dBm Plus Attenuation

Figure 407. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Figure 408. Receiver IIP3 vs. Receiver Attenuation, LO = 5800 MHz, Figure 409. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Figure 410. Receiver Image vs. Baseband Frequency Offset, Attenuation = Figure 411. Receiver Image vs. Baseband Frequency Offset, Attenuation =

Figure 412. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz, Figure 413. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz, Figure 414. Receiver Gain Step Error vs. Receiver Attenuator Setting, Figure 415. Receiver Gain Step Error vs. Receiver Attenuator Setting, LO =

5600 MHz

Figure 416. Receiver Gain Step Error vs. Receiver Attenuator Setting, LO =

6000 MHz

Figure 417. Normalized Receiver Baseband Flatness vs. Baseband and Frequency

Figure 429. Receiver Input Impedance SEDZ

Rev. B | Page 97 of 127 TERMINOLOGY Large Signal Bandwidth Large signal bandwidth, otherwise known as instantaneous bandwidth or signal bandwidth, is the bandwidth over which there are large signals. For example, for Band 42 LTE, the large signal bandwidth is 200 MHz. Occupied Bandwidth Occupied bandwidth is the total bandwidth of the active signals. For example, three 20 MHz carriers have a 60 MHz occupied bandwidth, regardless of where the carriers are placed within the large signal bandwidth. Synthesis Bandwidth Synthesis bandwidth is the bandwidth over which digital predistortion (DPD) linearization is transmitted. Synthesis bandwidth is the 1 dB bandwidth of the transmitter. The power density of the signal outside the occupied bandwidth is assumed to be 25 dB below the signal in the occupied bandwidth, which also assumes that the unlinearized power amplifier (PA) achieves 25 dB ACLR. Observation Bandwidth Observation bandwidth is the 1 dB bandwidth of the observation receiver. With the observation receiver sharing the transmitter LO, the observation receiver senses similar power densities, such as those in the occupied bandwidth and synthesis bandwidth of the transmitter. Backoff Backoff is the difference (in dB) between full scale and the rms signal power. P HIGH PHIGH is the largest signal that can be applied without overloading the ADC for the receiver or observation receiver input. This input level results in slightly less than full scale at the digital output because of the nature of the continuous time Σ-Δ ADCs, which, for example, exhibit a soft overload in contrast to the hard clipping of pipeline ADCs.

Rev. B | Page 98 of 127 THEORY OF OPERATION The ADRV9009 is a highly integrated RF transmitter subsystem capable of configuration for a wide range of applications. The device integrates all RF, mixed-signal, and digital blocks necessary to provide all transmitter traffic and DPD observation receiver functions in a single device. Programmability allows the transmitter to be adapted for use in many TDD systems and 3G/4G/5G cellular standards. The ADRV9009 contains four high speed serial interface links for the transmitter chain, and two high speed links each for the receiver and observation receiver chains. The links are JESD204B, Subclass 1 compliant. The two receiver lanes can be reused for the observation receiver, providing a low pin count and a reliable data interface to field programmable gate arrays (FPGAs) or integrated baseband solutions. The ADRV9009 also provides tracking correction of dc offset QEC errors and transmitter LO leakage to maintain high performance under varying temperatures and input signal conditions. The device also includes test modes that allow system designers to debug designs during prototyping and to optimize radio configurations. TRANSMITTER The ADRV9009 transmitter section consists of two identical and independently controlled channels that provide all digital processing, mixed-signal, and RF blocks necessary to implement a direct conversion system while sharing a common frequency synthesizer. The digital data from the JESD204B lanes pass through a fully programmable, 128-tap FIR filter with variable interpolation rates. The FIR output is sent to a series of interpolation filters that provide additional filtering and interpolation prior to reaching the DAC. Each 14-bit DAC has an adjustable sample rate. When converted to baseband analog signals, the inphase (I) and quadrature (Q) signals are filtered to remove sampling artifacts and are fed to the upconversion mixers. Each transmitter chain provides a wide attenuation adjustment range with fine granularity to optimize SNR. RECEIVER The ADRV9009 receiver contains all the blocks necessary to receive RF signals and convert them to digital data usable by a BBP . Each receiver can be configured as a direct conversion system that supports up to a 200 MHz bandwidth. Each receiver contains a programmable attenuator stage, followed by matched I and Q mixers that downconvert received signals to baseband for digitization. Gain control can be achieved by using the on-chip AGC or by allowing the BBP to make gain adjustments in a manual gain control mode. Performance is optimized by mapping each gain control setting to specific attenuation levels at each adjustable gain block in the receiver signal path. Additionally, each channel contains independent receive signal strength indicator (RSSI) measurement capability, dc offset tracking, and all circuitry necessary for self calibration. The receivers include ADCs and adjustable sample rates that produce data streams from the received signals. The signals can be conditioned further by a series of decimation filters and a programmable FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing decimation factors to produce the desired output data rate. OBSERVATION RECEIVER The ADRV9009 contains an independent DPD observation receiver front end with two multiplexed inputs and a common digital back end that is shared with the traffic receiver. This configuration enables an efficient shared receiver and observation receiver mode where the device can support fast switching between receiver and observation receiver mode in TDD applications. The observation receiver shares the common frequency synthesizer with the transmitter. The observation receiver is a direct conversion system that contains a programmable attenuator stage, followed by matched I and Q mixers, baseband filters, and ADCs. The continuous time Σ-Δ ADCs have inherent antialiasing that reduces the RF filtering requirement. The ADC outputs can be conditioned further by a series of decimation filters and a programmable FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing decimation factors to produce the desired output data rate. CLOCK INPUT The ADRV9009 requires a differential clock connected to the REF_CLK_IN± pins. The frequency of the clock input must be between 10 MHz and 1000 MHz and must have very low phase noise because this signal generates the RF LO and internal sampling clocks. SYNTHESIZERS RF PLL The ADRV9009 contains a fractional-N PLL to generate the RF LO for the signal paths. The PLL incorporates an internal VCO and loop filter, requiring no external components. The LOs on multiple chips can be phase synchronized to support active antenna systems and beamforming applications. Clock PLL The ADRV9009 contains a PLL synthesizer that generates all the baseband related clock signals and serialization/deserial- ization (SERDES) clocks. This PLL is programmed based on the data rate and sample rate requirements of the system.

the data to be transferred to the specific register address. in 4-wire mode or on the SDIO pin in 3-wire mode. these pins, listed in Table 5, to access the on-chip test access port. GPIO_0 pin to 1001, and then pull the TEST pin high. includes all 1.3 V domains) power up first and at the same time. that no device damage occurs if this sequence is not followed. signal after power stabilizes, prior to configuration. avoid any back biasing of the digital control lines. setting the observation receiver gain in real time. Twelve 3.3 V GPIO_x pins are also included on the device. These pins provide control signals to external components. with an input voltage range of 0.05 V to VDDA_3P3 − 0.05 V . DAC x) that can be used for bias or other system functionality. floating point data formats for observation receiver data. Table 6. Observation Path Interface Rates

Table 9. ADRV9009-W/PCBZ Single Ended Impedance and Stackup1 Table 10. ADRV9009-W/PCBZ Differential Impedance and Stackup1

2 N/A N/A N/A N/ A N/A N/A N/A

3 N/A N/A N/A N/ A N/A N/A N/A

4 N/A N/A N/A N/ A N/A N/A N/A

6 N/A N/A N/A N/ A N/A N/A N/A

9 N/A N/A N/A N/ A N/A N/A N/A

11 N/A N/A N/A N/ A N/A N/A N/A

12 N/A N/A N/A N/ A N/A N/A N/A

Figure 438. Placement Example of 0 Ω Resistor Placeholders for FBs, Reservoir Capacitors, and Bypass Capacitors on the ADRV9009-W/PCBZ (Layer 12 to Power Layer and

1. Use ceramic 1 μF bypass capacitors at the VDDA1P1_
2. Connect a 14.3 kΩ resistor to the RBIAS pin (C14). This

resistor must have a 1% tolerance.

1. Pull the TEST pin (J6) to ground for normal operation.

Boundary Scan section for JTAG boundary scan information. dotted line in Figure 439, by any digital signal routing. Figure 439. Auxiliary ADC, Analog, and Digital GPIO Signals Routing Guidelines

Figure 441. Pi Network Matching Components Available on Observation Receiver Inputs

1.8 V plane so that each balun supply or each set of two chokes

used on the ADRV9009-W/PCBZ. Figure 442. Transmitter Power Supply Planes (VDDA1P8_TX) on the ADRV9009-W/PCBZ

Figure 447. Via Fencing Around JESD204B Lines, PCB Layer 10 ADRV9009 port impedances are required.  The ADRV9009 ball pads are the reference plane for this data.  Single-ended mode port impedance data is not available. the real and imaginary components by 2. impedance data in Touchstone format.

Figure 452. REF_CLK_IN± SEDZ and PEDZ Data, On Average, the Real Part of the Parallel Equivalent Differential Impedance (R P) = Approximately 70 kΩ

with appropriate component population.

1. The DataAccessComponent block reads the rf port.s1p

file. This file is the device RF port reflection coefficient.

1. The two equations convert the RF port reflection coefficient to

a complex impedance. The result is the RX_SEDZ variable.

1. The RF port calculated complex impedance (RX_SEDZ)

defines the Term 2 impedance.

1. Term 2 is used in a differential mode, and Term 1 is used in

operations within the display page. matching components and balun must be used in the simulations. Figure 453. Simulation Setup in ADS with SEDZ .s1p Files and DataAccessComponent Table 11. Sample Wire Wound DC Bias Choke Resistance vs. Size vs. Inductance

200 MHz bandwidth, and the observation receivers can support

observation receiver channels are designed for differential use.

0.7 V and may need to be ac-coupled, depending on the

common-mode voltage level of the external circuit. voltage is 0.7 V bias to ground. impedance matching, for example). described in this data sheet. in a relatively small (0603, 0805) package. Figure 460. Differential Receiver Interface Using a Transformer Figure 461. Differential Receiver Interface Using a Transmission Line Balun models are required to build an accurate system level simulation. The board layout model can be obtained from an EM simulator. applications engineering for ADRV9009 modeling details. determine appropriate conditions for dc biasing.

Figure 462. Impedance Matching Topology

Figure 463. Transmitter 1 and Transmitter 2 Generic Matching Network Topology

0805 FOOTPRINT

Figure 464. Receiver 1 and Receiver 2 Generic Matching Network Topology Figure 465. Observation Receiver 1 and Observation Receiver 2 Generic Matching Network Topology

be used in all frequency bands. Table 12. Receiver 1 Evaluation Board Matching Components

625 MHz to 2815 MHz 22 nH 12 pF 62 nH 180 nH 39 pF 91 nH Johanson 1720BL15A0100

Table 13. Receiver 2 Evaluation Board Matching Components Table 14. Observation Receiver 1 Evaluation Board Matching Components Table 15. Observation Receiver 2 Evaluation Board Matching Components Table 16. Transmitter 1 Evaluation Board Matching Components1 1 These matches provide VDDA1P8_TX to the TXx_OUT± pins through the balun. Table 17. Transmitter 2 Evaluation Board Matching Components1, 1 These matches provide VDDA1P8_TX to the TXx_OUT± pins through the balun.

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

0.80 REF

0.44 REF

7.755 REF

8.090 REF

Figure 466. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 2 See the Thermal Management section. registered trademarks are the prop erty of their respective owners.