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Dual Narrow-Band and Wideband RF Transceiver Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►2 × 2 highly integrated transceiver ►Frequency range of 30 MHz to 6000 MHz ►Transmitter and receiver bandwidth from 12 kHz to 40 MHz ►Two fully integrated, fractional-N, RF synthesizers ►LVDS and CMOS synchronous serial data interface options ►Low power monitor and sleep modes ►Multichip synchronization capabilities ►Fast frequency hopping ►Dynamic profile switching for dynamic data rates and sample rates ►Fully integrated DPD for narrow-band and wideband waveforms ►Fully programmable via a 4-wire SPI ►12 mm × 12 mm, 196-ball CSP_BGA
APPLICATIONS
►Mission critical communications ►Very high frequency (VHF), ultrahigh frequency (UHF), and cellu- lar to 6 GHz ►Time division duplexing (TDD) and frequency division duplexing (FDD) applications GENERAL DESCRIPTION The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated syn- thesizers, and digital signal processing functions. The ADRV9002 is a high performance, highly linear, high dynamic range transceiver designed for performance vs. power consumption system optimization. The device is configurable and ideally suited to demanding, low power, portable and battery powered equipment. The ADRV9002 operates from 30 MHz to 6000 MHz and covers the UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellu- lar frequency bands in narrow-band (kHz) and wideband operation up to 40 MHz. The ADRV9002 is capable of both TDD and FDD operation. The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, which eliminate the need for these functions in the digital baseband. In ad- dition, several auxiliary functions, such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs), are integrated to pro- vide additional monitoring and control capability. The fully integrated phase-locked loops (PLLs) provide high per- formance, low power, fractional-N frequency synthesis for the trans- mitter, receiver, and clock sections. Careful design and layout tech- niques provide the isolation required in high performance personal radio applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. The local oscillators (LOs) have flexible configuration options and include fast lock modes. The transceiver includes low power sleep and monitor modes to save power and extend the battery life of portable devices while monitoring communications. The fully integrated, low power digital predistortion (DPD) is opti- mized for both narrow-band and wideband signals and enables linearization of high efficiency power amplifiers. The ADRV9002 core can be powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard 4-wire serial port. Other voltage supplies are used to provide proper digital inter- face levels and to optimize the receiver, transmitter, and auxiliary converter performance. High data rate and low data rate interfaces are supported using configurable CMOS or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice. The ADRV9002 is packaged in a 12 mm × 12 mm, 196-ball chip scale package ball grid array (CSP_BGA).
analog.com Rev. 0 | 2 of 92 Current Consumption Estimates (Typical
REVISION HISTORY
4/2021—Revision 0: Initial Version
analog.com Rev. 0 | 3 of 92 Figure 1.
Table 1. Transmitters (Tx1 and Tx2)
30 MHz 98 dB
470 MHz 97 dB
900 MHz 93 dB
2400 MHz 93 dB
3500 MHz 79 dB
5800 MHz 70 dB
50 MHz 55 dBc
470 MHz 63 dBc
900 MHz 59 dBc
2400 MHz 60 dBc
3500 MHz 57 dBc
5800 MHz 55 dBc
30 MHz 61 dBc
470 MHz 68 dBc
900 MHz 65 dBc
3500 MHz 50 dBc
5800 MHz 50 dBc
50 MHz 57 dBc
470 MHz 66 dBc
900 MHz 63 dBc
3500 MHz 61 dBc
5800 MHz 57 dBc
3 Use the maximum value to ensure adequate calibration
30 MHz 17 dB
470 MHz 18 dB
900 MHz 17 dB
2400 MHz 23 dB
3500 MHz 13 dB
5800 MHz 10 dB
50 MHz 31 dBm
470 MHz 31 dBm
900 MHz 30 dBm
2400 MHz 28 dBm
3500 MHz 29 dBm
5800 MHz 27 dBm
30 MHz 30 dBm
3500 MHz 27 dBm
5800 MHz 25 dBm
50 MHz −68 dBm
470 MHz −65 dBm
900 MHz −67 dBm
2400 MHz −68 dBm
3500 MHz −62 dBm
5800 MHz −56 dBm
30 MHz −70 dBm
470 MHz −72 dBm
900 MHz −74 dBm
2400 MHz −71 dBm
3500 MHz −71 dBm
5800 MHz −58 dBm
1 dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting. 2 A continuous wave is a single frequency signal. 3 Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal. Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B)
50 MHz 21 dB
470 MHz 22 dB
900 MHz 22 dB
2400 MHz 22 dB
3500 MHz 21 dB
5800 MHz 21 dB
30 MHz 21 dB
30 MHz 20 dB
470 MHz 21 dB
900 MHz 20 dB
3500 MHz 9 dB
50 MHz 79 dBm
470 MHz 81 dBm
900 MHz 85 dBm
2400 MHz 73 dBm
3500 MHz 60 dBm
5800 MHz 60 dBm
50 MHz 70 dBm
470 MHz 74 dBm
900 MHz 72 dBm
2400 MHz 65 dBm
3500 MHz 59 dBm
50 MHz 22 dBm
470 MHz 26 dBm
900 MHz 27 dBm
3500 MHz 26 dBm
50 MHz 21 dBm
470 MHz 22 dBm
900 MHz 22 dBm
2400 MHz 21 dBm
3500 MHz 23 dBm
5800 MHz 20 dBm
50 MHz −84 dBc
470 MHz −74 dBc
900 MHz −82 dBc
2400 MHz −92 dBc
3500 MHz −93 dBc
5800 MHz −89 dBc
30 MHz −102 dBc
470 MHz −97 dBc
900 MHz −89 dBc
2400 MHz −79 dBc
3500 MHz −80 dBc
5800 MHz −72 dBc
5.6 MHz at maximum gain at Rx input port, f1dB of the TIA = 20 MHz, HD3
50 MHz −90 dBc
470 MHz −71 dBc
900 MHz −79 dBc
2400 MHz −81 dBc
3500 MHz −82 dBc
5800 MHz −84 dBc
30 MHz −108 dBc
470 MHz −95 dBc
5800 MHz −71 dBc
50 MHz −91 dBc
470 MHz −93 dBc
900 MHz −93 dBc
2400 MHz −89 dBc
3500 MHz −83 dBc
5800 MHz −82 dBc
470 MHz −96 dBc
900 MHz −90 dBc
5.6 MHz at maximum gain at Rx input port, f1dB of the TIA = 20 MHz, HD2
50 MHz −92 dBc
470 MHz −92 dBc
900 MHz −91 dBc
3500 MHz −84 dBc
5800 MHz −79 dBc
30 MHz −109 dBc
470 MHz −94 dBc
5800 MHz −70 dBc
50 MHz 84 dBc
470 MHz 83 dBc
900 MHz 82 dBc
1900 MHz 81 dBc
3500 MHz 82 dBc
5800 MHz 78 dBc
50 MHz 87 dBc
470 MHz 90 dBc
900 MHz 86 dBc
1900 MHz 84 dBc
5800 MHz 75 dBc
50 MHz −66 dBm
470 MHz −66 dBm
900 MHz −66 dBm
2400 MHz −66 dBm
5800 MHz −60 dBm
30 MHz 100 dB
470 MHz 85 dB
900 MHz 78 dB
2400 MHz 77 dB
3500 MHz 62 dB
5800 MHz 64 dB
30 MHz 120 dB
470 MHz 110 dB
900 MHz 100 dB
2400 MHz 90 dB
3500 MHz 74 dB
5800 MHz 81 dB
30 MHz 106 dB
470 MHz 103 dB
900 MHz 98 dB
2400 MHz 92 dB
3500 MHz 83 dB
5800 MHz 71 dB
30 MHz 99 dB
900 MHz 90 dB
2400 MHz 86 dB
3500 MHz 84 dB
characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level.
30 MHz LO See Figure 292 PLL bandwidth = 300 kHz
470 MHz LO See Figure 293 PLL bandwidth = 300 kHz
900 MHz LO See Figure 294 PLL bandwidth = 300 kHz
2400 MHz LO See Figure 295 PLL bandwidth = 300 kHz
3500 MHz LO See Figure 296 PLL bandwidth = 300 kHz
5800 MHz LO See Figure 297 PLL bandwidth = 300 kHz
analog.com Rev. 0 | 13 of 92 Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments REFERENCE CLOCK (DEV_CLK_IN SIGNAL) Differential mode Frequency Range 10 1000 MHz Signal Level 0.2 1 V p-p AC-coupled, for optimal spurious performance and to meet the specified PLL performance parameters, use a 1 V p-p (2 V p-p differential) input clock. Single-Ended Mode Frequency Range 10 80 MHz Signal Level 0.2 1 V p-p AC-coupled, for optimal spurious performance and to meet the specified PLL performance parameters, use a 1 V p-p input clock. REFERENCE CLOCK (XTAL) Frequency Range 20 80 MHz CLOCK OUTPUT (DEV_CLK_OUT SIGNAL) Frequency Range 10 80 MHz DIGITAL INTERFACES AND AUXILIARY CONVERTERS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments AUXILIARY ADC CONVERTERS Resolution 10 Bits Input Voltage Minimum 0.05 V Maximum 0.95 V AUXILIARY DAC CONVERTERS Resolution 12 Bits Output Voltage Minimum 0.05 V Maximum VDDA_1P81 − 0.05 V Drive Capability 10 mA DIGITAL SPECIFICATIONS (CMOS SSI SIGNALS) Logic Inputs Input Voltage High Level VDIGIO_1P8 × 0.65 VDIGIO_1P8 + 0.18 V Low Level −0.30 VDIGIO_1P8 × 0.35 V Logic Outputs Output Voltage High Level VDIGIO_1P8 − 0.45 V Low Level 0.45 V Drive Capability 10 mA
analog.com Rev. 0 | 14 of 92 Table 4. Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL SPECIFICATIONS (DIGITAL GPIO SIGNALS) Logic Inputs Input Voltage High Level VDIGIO_1P8 × 0.65 VDIGIO_1P8 + 0.18 V Low Level −0.30 VDIGIO_1P8 × 0.35 V Logic Outputs Output Voltage High Level VDIGIO_1P8 − 0.45 V Low Level 0.45 V Drive Capability 10 mA DATAPORT SPECIFICATIONS (LVDS SSI, MCS+ and MCS−) Logic Inputs Input Voltage Range 825 1675 mV Each differential input in the pair Input Differential Voltage Threshold −100 +100 mV Receiver Differential Input Impedance 100 Ω Internal termination enabled Logic Outputs Output Voltage High Level 1390 mV Low Level 1000 mV Differential 300 mV Offset 1200 mV 17 mA Drivers are shorted to ground, there is no internal termination available, an off-chip 100 Ω termination is required Output Current 4.1 mA Drivers are shorted together Clock Signal Duty Cycle 45 50 55 % 500 MHz Output Rise and Fall Time 0.371 ns 300 mV p-p swing DIGITAL SPECIFICATIONS (ANALOG GPIO SIGNALS) Logic Inputs Input Voltage High Level VDDA_1P8 × 0.65 VDDA_1P8 + 0.18V Low Level −0.30 VDDA_1P8 × 0.35V Logic Outputs Output Voltage High Level VDDA_1P8 − 0.45 V Low Level 0.45 V Drive Capability 10 mA 1 VDDA_1P8 refers to all analog 1.8 V supplies including VCONV_1P8, VAGPIO_1P8, VANA2_1P8, and VANA1_1P8.
bypass includes VRFLO2_1P0, VRFLO1_1P0, VRX2LO_1P3, VRX1LO_1P3, VTX2LO_1P3, VCONV_1P3, and VTX1LO_1P3. 2 VDD_1P0 refers to all digital 1.0 V supplies including VDIG_1P0. VRFSYN1_1P3, VAUXSYN_1P3, VRX1LO_1P3, VTX2LO_1P3, VCLKVCO_1P3, VAUXVCO_1P3, VTX1LO_1P3, and VCONV_1P3. 4 VDD_1P8 refers to all digital 1.8 V supplies including VDIGIO_1P8. internal LDO regulators used to produce an on-chip, 1.0 V analog power domain. Table 6. Digital Mobile Radio (DMR) CMOS SSI Table 7. Long-Term Evolution (LTE) Dual Transmitter and Dual Receiver LVDS SSI
Table 8. DMR, 4× External LO, LO = 470 MHz, Low Power Mode Clock PLL, Processor Clock Divisor = 4, CMOS SSI Table 9. LTE40 Two Transmitters and Two Receivers (2T2R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI
61.44 MSPS Data Rate, Receiver QEC Enabled, QEC Engine Active, and
Table 10. LTE40 One Transmitter and One Receiver (1T1R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI
decreases power consumption by approximately 110 mW per receiver channel. No auxiliary DACs or auxiliary ADCs are enabled. Table 11. FDD Modes
analog.com Rev. 0 | 18 of 92 Table 12. Parameter Min Typ Max Unit Test Conditions/Comments tHC 0 ns Last SPI_CLK falling edge to SPI_EN hold tS 2 ns SPI_DIO data input setup to SPI_CLK tH 0 ns SPI_DIO data input hold to SPI_CLK tCO 3 15 ns SPI_CLK falling edge to output data delay (3-wire mode) 3 10 ns SPI_CLK falling edge to output data delay (4-wire mode) tHZM tH tCO ns Bus turnaround time after the baseband processor drives the last address bit tHZS 0 tCO ns Bus turnaround time after the ADRV9002 drives the last address bit, not shown in Figure 2 DIGITAL TIMING1 TX1_ENABLE or TX2_ENABLE Pulse Width 10 µs RX1_ENABLE or RX2_ENABLE Pulse Width 10 µs TX1_ENABLE or TX2_ENABLE Valid Data 2 µs RX1_ENABLE or RX2_ENABLE Valid Data 2 µs DIGITAL DATA TIMING (LVDS SSI) Zero on-chip lane skew and an adjustable delay of ±300 ps available per lane TXx_DCLK_IN±, RXx_DCLK_OUT± and TXx_DCLK_OUT± Clock Period 2 ns 500 MHz TXx_DCLK_IN±, RXx_DCLK_OUT± and TXx_DCLK_OUT± Pulse Width 1 ns Transmitter Data TXx_IDATA_IN± or TXx_QDATA_IN or TXx_STROBE_IN± Setup to TXx_DCLK_IN± 0.25 ns TXx_IDATA_IN± or TXx_QDATA_IN± or TXx_STROBE_IN± Hold to TXx_DCLK_IN± 0.55 ns Receiver Data RXx_DCLK_OUT± to RXx_IDATA_OUT± or RXx_QDATA_OUT± or RXx_STROBE_OUT± Delay 0.2 ns DC-coupled DIGITAL DATA TIMING (CMOS-SSI) TXx_DCLK_IN±, RXx_DCLK_OUT± and TXx_DCLK_OUT± Clock Period 12.5 ns 80 MHz TXx_DCLK_IN±, RXx_DCLK_OUT± and TXx_DCLK_OUT± Pulse Width 6.25 ns Transmitter Data TXx_DATA_IN± or TXx_STROBE_IN± Setup to TXx_DCLK_IN± 2 ns TXx_DATA_IN± or TXx_STROBE_IN± Hold to TXx_DCLK_IN± 2 ns Receiver Data RXx_DCLK_OUT± to RXx_DATA_OUT± or RXx_STROBE_OUT± Delay 4.5 ns DC-coupled MULTICHIP SYNCHRONIZATION (MCS) TIMING LVDS Setup 0.62 ns LVDS Hold 0 ns CMOS Setup 1 ns CMOS Hold 3 ns 1 TX1_ENABLE, TX2_ENABLE, RX1_ENABLE, and RX2_ENABLE are the channel enabling and disabling signals.
Figure 2. 3-Wire SPI Timing with Parameter Labels, SPI Read
Maximum Input Power into RF Ports See Table 14 for limits vs. ing conditions for extended periods may affect product reliability. Table 14. Maximum Input Power into RF Ports vs. Lifetime on) improves thermal resistance. soldered in a circuit board for surface-mount packages. Table 15. Thermal Resistance Values1, 2
2 Using enhanced heat removal (PCB, heat sink, airflow, and so on)
techniques improve thermal resistance values. sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 16. ADRV9002, 196-Ball CSP_BGA
500 C2A
damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 3. Pin Configuration Table 17. Pin Function Descriptions Input VSSA Analog Ground (VSSA). to 1 GHz, a 1× multiplier is available. If unused, connect EXT_LO2+ and EXT_LO2− to VSSA. Circuitry. VRFVCO2_1P3 is sensitive to supply noise. that is operated from VRFVCO2_1P3 is not in use. output. Connect MODEA to VSSA to enable the differential clock receiver at the DEV_CLK_IN± pins. DEV_CLK_IN+ or the crystal oscillator resonator at both of the DEV_CLK_IN± pins.
A8 Input RBIAS Bias Resistor Connection. RBIAS generates an internal current based on an external 1% resistor. Connect a 4.99 kΩ resistor between RBIAS and VSSA (analog ground) . operated from VRFVCO1_1P3 is not in use. GHz, a 1× multiplier is available. If unused, connect EXT_LO1+ and EXT_LO1− to VSSA. B1, C1 Input RX2A−, RX2A+ Differential Input A for Rx2. If unused, connect RX2A− and RX2A+ to VSSA. VRFVCO2_1P3 input is in use. B7 Input AUXADC_2 Input 2 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_2. B8 Input AUXADC_1 Input 1 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_1. the VRFVCO1_1P3 input is in use. B14, C14 Input RX1A−, RX1A+ Differential Input A for Rx1. If unused, connect RX1A− and RX1A+ to VSSA. C3, C4 Input RX2B+, RX2B− Differential Input B for Rx2. If unused, connect RX2B+ and RX2B− to VSSA. Baseband Filters, and Auxiliary DACs and ADCs. For normal operation, leave VANA2_1P0 unconnected. Filters, and Auxiliary DACs and ADCs. VANA2_1P3 is sensitive to supply noise. Filters. VANA1_1P3 is sensitive to supply noise. Filters. For normal operation, leave VANA1_1P0 unconnected. C11, C12 Input RX1B−, RX1B+ Differential Input B for Rx1. If unused, connect RX1B− and RX1B+ to VSSA. D7, D8 Input MCS+, MCS− Multichip Synchronization Reference Inputs. If unused, connect MCS+ and MCS− to VSSA. E1 Output VRX2LO_1P0 1.0 V Internal Supply Node for Rx2 LO Buffers and Mixers. VRX2LO_1P0 is sensitive to supply noise. Bypass VRX2LO_1P0 with a 4.7 µF capacitor. when the internal LDO regulator is not used. VRX2LO_1P3 is sensitive to supply noise. for mapping between AGPIO_xx and the auxiliary DAC signals. If unused, do not connect AGPIO_xx. E4 Input VRFSYN2_1P3 1.3 V Supply for RF LO2 Synthesizer. VRFSYN2_1P3 is sensitive to supply noise. E5 Input VCLKSYN_1P3 1.3 V Supply for Clock Synthesizer. VCLKSYN_1P3 is sensitive to supply noise. leave the DEV_CLK_IN− pin unconnected. E10 Input VAUXSYN_1P3 1.3 V Supply for Auxiliary Synthesizer. VAUXSYN_1P3 is sensitive to supply noise. E11 Input VRFSYN1_1P3 1.3 V Supply for RF LO1 Synthesizer. VRFSYN1_1P3 is sensitive to supply noise. when the internal LDO regulator is not used. VRX1LO_1P3 is sensitive to supply noise. E14 Output VRX1LO_1P0 1.0 V Internal Supply Node for Rx1 LO Buffers and Mixers. VRX1LO_1P0 is sensitive to supply noise. Bypass VRX1LO_1P0 with a 4.7 µF capacitor. G1, H1 Output TX2+, TX2− Differential Output for Transmitter Channel 2. If unused, do not connect TX2+ and TX2−.
when the internal LDO is not used. VTX2LO_1P3 is sensitive to supply noise. G7 Input VCONV_1P8 1.8 V Supply for Tx1 and Tx2 DAC and Rx1 and Rx2 ADC. G8 Input VAGPIO_1P8 1.8 V Supply for Auxiliary DACs, Auxiliary ADCs, and AGPIO Signals. to VTX1LO_1P3 when the internal LDO regulator is not used. VTX1LO_1P3 is sensitive to supply noise. G14, H14 Output TX1+, TX1− Differential Output for Transmitter Channel 1. If unused, do not connect TX1+ and TX1−. H2 Input VANA2_1P8 1.8 V Supply for Rx2 Mixer, Rx2 TIA, Tx2 LPF, and Internal References. H4 Input AUXADC_3 Input 3 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_3. VCONV_1P3 when the internal LDO regulator is not used. VCONV_1P3 is sensitive to supply noise. H11 Input AUXADC_0 Input 0 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_0. K1 Input SPI_CLK Serial Data Bus Clock Input. SPI_DIO Serial Data Input in 4-Wire Mode or Input and Output in 3-Wire Mode. K3 Input RX2_EN Enable Input for Rx2. If unused, do not connect RX2_EN. K4 Input VSSA/TESTCK+ Connect VSSA/TESTCK+ to VSSA for normal operation. K5 Input VSSA/TESTCK− Connect VSSA/TESTCK− to VSSA for normal operation. DGPIO_xx signal name. If unused, do not connect DGPIO_xx. K12 Input RX1_EN Enable Input for Rx1. If unused, do not connect RX1_EN. K13 Input RESETB Active Low Chip Reset. K14 Output GP_INT General-Purpose Digital Interrupt Output Signal. If unused, do not connect GP_INT. L1 Input SPI_EN Active Low Serial Data Bus Chip Select. L2 Output SPI_DO Serial Data Output. If unused in SPI 3-wire mode, do not connect SPI_DO. L3 Input TX2_EN Enable Input for Transmitter Channel 2. If unused, do not connect TX2_EN. to a separate power supply domain. Provide reservoir capacitance close to the chip. L12 Input TX1_EN Enable Input for Transmitter Channel 1. If unused, do not connect TX1_EN. to the baseband IC. If unused, do not connect DEV_CLK_OUT.
Output 0 or the Rx2 I and Q sample data output. If unused, do not connect RX2_IDATA_OUT−. RX2_IDATA_OUT+ is the Rx2 Data Output 1. If unused, do not connect RX2_IDATA_OUT+. RX2_DCLK_OUT− is not used. If unused, do not connect RX2_DCLK_OUT−. RX2_DCLK_OUT+ is the Rx2 data clock output. If unused, do not connect RX2_DCLK_OUT+. data port in LVDS SSI mode. If unused, do not connect DGPIO_15/TX2_DCLK_OUT+. data port in LVDS SSI mode. If unused, do not connect DGPIO_14/TX2_DCLK_OUT−. and Output Signals, and DGPIO Interface. M8 Output VDIG_0P9 1.0 V Internal Supply Node for Digital Circuitry. Bypass VDIG_0P9 with a 4.7 µF capacitor. data port in LVDS SSI mode. If unused, do not connect DGPIO_12/TX1_DCLK_OUT−. data port in LVDS SSI mode. If unused, do not connect DGPIO_13/TX1_DCLK_OUT+. RX1_DCLK_OUT+ is the Rx1 data clock output. If unused, do not connect RX1_DCLK_OUT+. RX1_DCLK_OUT− is not used. If unused, do not connect RX1_DCLK_OUT−. sample data output positive side. In CMOS SSI mode, RX1_IDATA_OUT+ is the Rx1 Data Output 1. the Rx1 I and Q sample data output. RX2_STROBE_OUT− is not used. If unused, do not connect RX2_STROBE_OUT−. RX2_STROBE_OUT+ is the Rx2 strobe output. If unused, do not connect RX2_STROBE_OUT+. mode, RX2_QDATA_OUT− is the Rx2 Data Output 2. If unused, do not connect RX2_QDATA_OUT−. mode, RX2_QDATA_OUT+ is the Rx2 Data Output 3. If unused, do not connect RX2_QDATA_OUT+. TX2_DCLK_IN+ is the Tx2 data clock input. If unused, do not connect TX2_DCLK_IN+. TX2_DCLK_IN− is not used. If unused, do not connect TX2_DCLK_IN−. N7, N8, P1, P14 Input VSSD Digital Supply Voltage (VSSD). TX1_DCLK_IN− is not used. If unused, do not connect TX1_DCLK_IN−. TX1_DCLK_IN+ is the Tx1data clock input. If unused, do not connect TX1_DCLK_IN+. mode, RX1_QDATA_OUT+ is the Rx1 Data Output 3. If unused, do not connect RX1_QDATA_OUT+.
mode, RX1_QDATA_OUT− is the Rx1 Data Output 2. If unused, do not connect RX1_QDATA_OUT−. RX1_STROBE_OUT+ is the Rx1 strobe output. If unused, do not connect RX1_STROBE_OUT+. RX1_STROBE_OUT− is not used. If unused, do not connect RX1_STROBE_OUT−. TX2_STROBE_IN+ is the Tx2 strobe input. If unused, do not connect TX2_STROBE_IN+. TX2_QDATA_IN− is the Tx2 Data Input 2. If unused, do not connect TX2_QDATA_IN−. TX2_QDATA_IN+ is the Tx2 Data Input 3. If unused, do not connect TX2_QDATA_IN+. do not connect TX2_IDATA_IN+. I and Q sample data input. If unused, do not connect TX2_IDATA_IN−. I and Q sample data input. If unused, do not connect TX1_IDATA_IN−. do not connect TX1_IDATA_IN+. TX1_QDATA_IN+ is the Tx1 Data Input 3. If unused, do not connect TX1_QDATA_IN+. TX1_QDATA_IN− is the Tx1 Data Input 2. If unused, do not connect TX1_QDATA_IN−. TX1_STROBE_IN+ is the Tx1 strobe input. If unused, do not connect TX1_STROBE_IN+.
considered a wideband profile. The performance of the ADRV9002 is measured for both wideband and narrow-band profiles.
50 MHz LO
The temperature settings refer to the die temperature. All LO frequencies are set to 50 MHz, unless otherwise noted. Figure 4. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 5. Receiver Absolute Gain (Complex) vs. LO Frequency, Baseband Figure 6. Receiver Noise Figure vs. Gain Index, Baseband Frequency =
5.6 MHz, ADC = High Performance
Figure 7. Receiver Noise Figure vs. LO Frequency, Baseband Frequency =
Figure 8. Receiver Noise Figure vs. Gain Index, Baseband Frequency =
5.6 MHz, ADC = Low Power
Figure 9. Receiver Noise Figure vs. LO Frequency, Baseband Frequency = Figure 10. Receiver Image Rejection vs. LO Frequency, Baseband Frequency Figure 11. Receiver Image Rejection vs. LO Frequency, Baseband Frequency Figure 12. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 13. Receiver Second-Order Harmonic Distortion vs. Baseband
470 MHz LO
The temperature settings refer to the die temperature. All LO frequencies set to 470 MHz, unless otherwise noted. Figure 37. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 38. Receiver Noise Figure vs. Gain Index, Baseband Frequency = Figure 39. Receiver Noise Figure vs. Gain Index, Baseband Frequency = Figure 40. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 41. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 42. Receiver Second-Order Harmonic Distortion vs. Gain Index,
900 MHz LO
The temperature settings refer to the die temperature. All LO frequencies set to 900 MHz, unless otherwise noted. Figure 64. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 65. Receiver Noise Figure vs. Gain Index, Baseband Frequency = Figure 66. Receiver Noise Figure vs. Gain Index, Baseband Frequency = Figure 67. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 68. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 69. Receiver Second-Order Harmonic Distortion vs. Gain Index,
2400 MHz LO
The temperature settings refer to the die temperature. All LO frequencies set to 2400 MHz, unless otherwise noted. Figure 91. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 92. Receiver Noise Figure vs. Gain Index, Baseband Frequency = Figure 93. Receiver Noise Figure vs. Gain Index, Baseband Frequency = Figure 94. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 95. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 96. Receiver Second-Order Harmonic Distortion vs. Gain Index,
Figure 97. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 98. Receiver Third-Order Harmonic Distortion vs. Gain Index, Figure 99. Receiver Third-Order Harmonic Distortion vs. Baseband Figure 100. Receiver Third-Order Harmonic Distortion vs. Gain Index, Figure 101. Receiver Third-Order Harmonic Distortion vs. Baseband Figure 102. Receiver DC Offset vs. Gain Index, Baseband Frequency =
3500 MHz LO
The temperature settings refer to the die temperature. All LO frequencies set to 3500 MHz, unless otherwise noted. Figure 118. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 119. Receiver Absolute Gain (Complex) vs. LO Frequency, Baseband Figure 120. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 5.6 Figure 121. Receiver Noise Figure vs. LO Frequency, Baseband Frequency = Figure 122. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 5.6 Figure 123. Receiver Noise Figure vs. LO Frequency, Baseband Frequency =
5800 MHz LO
The temperature settings refer to the die temperature. All LO frequencies set to 5800 MHz, unless otherwise noted. Figure 151. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 152. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 5.6 Figure 153. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 5.6 Figure 154. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 155. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 156. Receiver Second-Order Harmonic Distortion vs. Gain
= 144 kHz, device clock = 38.4 MHz, and an internal LO is used for all measurements. Measurements are at nominal power supply voltages. applicable over the lifetime of the device.
30 MHz LO
The temperature settings refer to the die temperature. All LO frequencies are set to 30 MHz, unless otherwise noted. Figure 178. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 179. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 180. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 181. Receiver Second-Order Harmonic Distortion vs. Gain Index,
The temperature settings refer to the die temperature. All LO frequencies set to 470 MHz, unless otherwise noted. Figure 197. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 198. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 199. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 200. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 201. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 202. Receiver Second-Order Harmonic Distortion vs. Gain Index,
The temperature settings refer to the die temperature. All LO frequencies set to 900 MHz, unless otherwise noted. Figure 216. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 217. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 218. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 219. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 220. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 221. Receiver Second-Order Harmonic Distortion vs. Gain Index,
The temperature settings refer to the die temperature. All LO frequencies set to 2400 MHz, unless otherwise noted. Figure 235. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 236. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 237. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 238. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 239. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 240. Receiver Second-Order Harmonic Distortion vs. Gain Index,
The temperature settings refer to the die temperature. All LO frequencies set to 3500 MHz, unless otherwise noted. Figure 254. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 255. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 256. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 257. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 258. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 259. Receiver Second-Order Harmonic Distortion vs. Gain Index,
The temperature settings refer to the die temperature. All LO frequencies set to 5800 MHz, unless otherwise noted. Figure 273. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband Figure 274. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 275. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1 Figure 276. Receiver Second-Order Harmonic Distortion vs. Gain Index, Figure 277. Receiver Second-Order Harmonic Distortion vs. Baseband Figure 278. Receiver Second-Order Harmonic Distortion vs. Gain Index,
analog.com Rev. 0 | 86 of 92 DPD The ADRV9002 provides a fully integrated DPD function that alters the digital waveform to compensate for nonlinearities in the power amplifier response, which linearizes the output of the power amplifi- er of the transmit system. The internal DPD block is optimized for both narrow-band and wideband signals. The DPD actuator and coefficient calculation engine are both integrated. This functionality uses the receive channel to monitor the output of the power am- plifier and calculates the appropriate predistortion to linearize the output. The integrated DPD capability allows the system to drive the power amplifier closer to saturation, enabling a higher efficiency power amplifier while maintaining linearity. Receiver as an Observation Receiver In FDD type applications where only one receiver is used or in the TDD type applications during transmitter time slots, unused receiver inputs can be used to perform transmitter observation. The observation receiver operates in a similar manner to the main receivers. Use the observation receiver channel to perform the following: ►Monitor the transmitter channels and implement transmitter local oscillator leakage (LOL) correction and transmitter QEC. ►Monitor signal levels after the power amplifier output. This data can be used by a fully integrated low power DPD block. The integrated DPD is optimized for both narrow-band and wideband signals and enables linearization of high efficiency power amplifi- ers. ►Monitor signal levels after the power amplifier output for further data processing in the external baseband processor. In cases where the observation receiver path is used for DPD oper- ation, there is a limit to the maximum bandwidth of the transmitter signal the DPD can support. For example, if the DPD observation factor is 5×, the transmitter signal bandwidth is limited to 1/5 of the DPD observation bandwidth. When using the ADRV9002 internal DPD block, the largest transmitter bandwidth that the internal DPD can support is 20 MHz because of the largest internal DPD obser- vation bandwidth of 100 MHz. When external DPD is used, the largest DPD observation bandwidth is limited by the transmitter and observation receiver RF bandwidth. 40 MHz is the largest RF band- width that can be received and sent over the digital data port to the baseband processor, which implies that 8 MHz represents the largest transmitter bandwidth that the DPD implemented externally to the ADRV9002 can support. CLOCK INPUT The reference clock inputs provide a low frequency clock from which all internal ADRV9002 clocks are derived. The ADRV9002 offers multiple reference input clocking options. The reference input clock pins on the device are labeled DEV_CLK_IN±. For optimal performance, drive the reference clock differentially via an external source or from an external crystal. If a differential input clock is provided, the clock signal must be ac-coupled with the input range limited from 10 MHz to 1 GHz. The ADRV9002 can also accept an external crystal (XTAL) as a clock source. The frequency range of the supported crystal is between 20 MHz to 80 MHz. The external crystal connection must be dc-coupled. If a differential clock is not available, a single-ended, ac-cou- pled, 1 V p-p (maximum) CMOS signal can be applied to the DEV_CLK_IN+ pin with the DEV_CLK_IN− pin unconnected. The maximum clock frequency in this mode is limited to 80 MHz. SYNTHESIZERS The ADRV9002 offers two distinct PLL paths, an RF PLL for the high frequency RF path and a baseband PLL for the digital and sampling clocks of the data converters. RF PLL The PLL structure in the ADRV9002 is unique in the sense that instead of having one dedicated PLL for the receive data path and a dedicated PLL for the transmit data path, two RF PLLs are in the device and both PLLs can source the receiver, the transmitter, both paths, or neither. This flexibility enables the ADRV9002 to meet various applications that require versatility. The RF PLL supports the use of both internal and external LO signals. The internal LO is generated by an on-chip VCO, which is tunable over a frequency range of 6.5 GHz to 13 GHz. The output of the VCO is phase-locked to an external reference clock through a fractional-N PLL that is programmable through the API command. The VCO outputs are steered through a combination of frequency dividers to produce in-phase and quadrature phase LO signals in the 30 MHz to 6 GHz frequency range. Alternatively, an external LO signal can be applied to the external LO inputs of the ADRV9002 to generate the LO signals in quadra- ture for the RF path. If the external LO path is chosen, the input frequency range is between 60 MHz and 12 GHz. PLL synthesizers are fractional-N designs that incorporate com- pletely integrated VCOs and loop filters. In TDD mode, LO distri- bution paths and receive and transmit data paths turn on and off as appropriate for the receive and transmit frames. In FDD mode, the transmit PLL and the receive PLL can be activated simultaneously. These PLLs require no external components. The RF LO generation circuits offer a trade-off between performance and power consumption.
Figure 300. RF LO using a simple address data serial bus protocol. gain or transmitter attenuation in real time. ing inputs connected to four dedicated input pins (AUXADC_x). 0.05 V to 0.95 V. When enabled, the auxiliary ADC is free running. triggered based on state of dedicated DGPIO pin.
are five dual function pins associated with the JTAG interface. Table 18. Pin Number to AGPIO_xx Mapping and AUXDAC_x Table 19. Pin Number to DGPIO_xx Mapping and JTAG Function
analog.com Rev. 0 | 89 of 92 POWER SUPPLY SEQUENCE The ADRV9002 requires a specific power-up sequence to avoid undesired power-up currents. The optimal power-on sequence re- quires VDD_1P0 to power up first. The VDDA_1P3 and VDDA_1P8 supplies must then power up after the VDD_1P0 supply. If VDDA_1P0 is used, VDDA_1P0 must be powered up after VDDA_1P3 and VDDA_1P8 are enabled. The user must toggle the RESET signal after power has stabilized prior to configuration. DIGITAL DATA INTERFACE The ADRV9002 data interface supports both CMOS and LVDS electrical interfaces. The CSSI is intended for narrow RF signal bandwidths, and the LVDS synchronous serial interface (LSSI) can support the full RF bandwidth of the ADRV9002. Table 20 provides a high level overview. For more details, refer to the ADRV9001 system development user guide. All signal lanes support both electrical interfaces, but concurrent operation of both interfaces is not supported. Additionally, each receive and transmit channel has a dedicated set of lanes for transferring information. The receive and transmit channels cannot be reconfigured to an alternative ball configuration that is different from how it has been assigned by design. CSSI The CSSI supports two modes of operation, 1-lane serialized data or 4-lane data. In either case, the maximum clock frequency sup- ported by the CMOS configuration is 80 MHz. For the CSSI in 1-lane data mode, 16 bits of I data and 16 bits of Q data (a total of 32 data bits) are serialized on a single lane. Figure 301 shows a graphical overview of the CSSI in 1-lane data mode. For the CSSI in 4-lane data mode, the I and Q digital data is spread across four data lanes. The 16 bits of I data and 16 bits of Q data are split into 8 bits and sent over one of four data lanes. For example, Lane 0 would have 8 LSB bits of I data, Lane 1 would have 8 MSB bits of I data, Lane 2 would have 8 LSB bits of Q data, and Lane 3 would have 8 MSB bits of Q data. The CSSI in 4-lane data mode supports both a full rate clock and a double data rate (DDR) clock. The DDR clock mode allows data to be latched on both the rising and falling edges, which enables twice the available RF bandwidth, as shown in Figure 302. CSSI Receive In the receive CMOS configuration, two additional signal lanes are required for the strobe and clock signals in addition to the data lane requirement as described for the CSSI in 1-lane mode and the CSSI in 4-lane mode, which allows a total of three signal lanes for the CSSI in 1-lane data mode and six total signal lanes for the CSSI in 4-lane data mode. RXx_DCLK_OUT is an output clock signal that synchronizes the data and strobe output signals. RXx_STROBE_OUT is a strobe output signal that indicates the first bit of the serial data stream. The RXx_STROBE_OUT signal can be configured to indicate the start of the I and Q samples. For a 16-bit data sample, the RXx_STROBE_OUT signal is high for one clock cycle and low for 31 clock cycles. Alternatively, the RXx_STROBE_OUT signal can be configured to be high for I data duration and low for Q data dura- tion. In this case, for a 16-bit data sample, the RXx_STROBE_OUT signal is high for 16 clock cycles (I data) and low for 16 clock cycles (Q data). CSSI Transmit For the transmit CMOS configuration, three additional signal lanes are required for the strobe, clock input, and clock output in addition to the data lane requirement as described for the CSSI in 1-lane data mode and the CSSI in 4-lane data mode, which allows a total of four signal lanes for the CSSI in 1-lane data mode and seven total signal lanes for the CSSI in 4-lane data mode. TXx_DCLK_IN is an input clock to the ADRV9002 that syn- chronizes to the data inputs (TXx_DATA_IN) and strobe inputs (TXx_STROBE_IN). TXx_STROBE_IN is an input signal that in- dicates the first bit of the serial data sample. Similar to the receive path, the transmit strobe has two configuration options. The TXx_DCLK_OUT is an output clock from the ADRV9002 to the external baseband device to generate the TXx_DCLK_IN, TXx_STROBE_IN, and TXx_DATA_IN signals. LSSI The LSSI supports the higher RF channel bandwidths and requires differential signal pairs. In LSSI mode, there are two data transfer formats, 1-lane data mode, where both the I and Q data are serialized on a single differential pair, or 2-lane data mode, where the I and Q data occupy separate differential pairs. The selection of either 1-lane data mode or 2-lane data mode depends on the RF channel bandwidth. To capture the maximum 40 MHz RF bandwidth of the ADRV9002, select the LSSI in 2-lane data mode. In either case, the maximum clock frequency supported by the LSSI configuration is 491.52 MHz and the clock type is DDR. Refer to Figure 303 for more details.
Table 20. ADRV9002 Data Port Interface Modes 1 Normal data type refers to data on the rising edges, and DDR is double data rate, where data is available on the rising and falling edges of the input clock. Figure 301. CSSI in 1-Lane Data Mode
registered trademarks are the property of their respective owners. Figure 304. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]