ADRF5422 AD | Alldatasheet
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Technical content
Die on Carrier, Silicon SPDT Switch, Nonreflective, 100 MHz to 55 GHz Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Ultrawideband frequency range: 100 MHz to 55 GHz ►Nonreflective design ►Low insertion loss ►1.3 dB typical to 18 GHz ►1.9 dB typical to 40 GHz ►2.5 dB typical to 50 GHz ►3.6 dB typical to 55 GHz ►High isolation ►43 dB typical to 40 GHz ►38 dB typical to 55 GHz ►High input linearity ►0.1 dB power compression (P0.1dB): 31 dBm ►Third-order intercept (IP3): 53 dBm ►High power handling at TCASE = 85°C ►30 dBm through path ►24 dBm terminated path ►30 dBm hot switching ►RF settling time (0.1 dB final RF output): 30 ns ►No low-frequency spurious signals ►All-off state control ►Positive control interface: CMOS-/LVTTL-compatible ►15-pad, 3.021 mm × 2.305 mm bare die [CHIP]
APPLICATIONS
►Test and instrumentation ►Cellular infrastructure: 5G millimeterwave (mmW) ►Military radios, radars, and electronic countermeasures (ECMs) ►Microwave radios and very small aperture terminals (VSATs) ►Industrial scanners FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram (LVTTL)-compatible controls. er handling performance is derated. For more details, see Table 2. 50 Ω and can operate from −40°C to +105°C.
analog.com Rev. 0 | 2 of 13 Input Power Compression and Third-Order
REVISION HISTORY
7/2024—Revision 0: Initial Version
VDD = 3.3 V, VSS = −3.3 V, VCTRL and VEN = 0 V or VDD, TCASE = 25°C, and 50 Ω system, unless otherwise noted. RFx refers to RF1 or RF2. Table 1. Electrical Specifications
26 GHz to 50 GHz 15 dB
50 GHz to 55 GHz 11 dB
26 GHz to 40 GHz 15 dB
40 GHz to 50 GHz 13 dB
50 GHz to 55 GHz 10 dB
40 GHz to 50 GHz 10 dB
50 GHz to 55 GHz 8 dB
26 GHz to 40 GHz 43 dB
40 GHz to 50 GHz 42 dB
50 GHz to 55 GHz 38 dB
18 GHz to 26 GHz 50 dB
40 GHz to 50 GHz 40 dB
50 GHz to 55 GHz 40 dB
Table 1. Electrical Specifications (Continued) 1 For input linearity performance over frequency, see Figure 2 and Figure 3. 2 For power derating over frequency, see Figure 2 and Figure 3. 3 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB. VDD = 3.3 V, VSS = 0 V, VCTRL and VEN = 0 V or VDD, TCASE = 25°C, and 50 Ω system, unless otherwise noted. Table 2. Single-Supply Operation Specifications
1 MHz
1 For power derating over frequency, see Figure 2 and Figure 3 . 2 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 5. ADRF5422, 15-Pad Bare Die [CHIP] damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 4. Pad Configuration Table 6. Pad Function Descriptions 1, 3, 4, 9, 10, 12, 13, 15 GND Ground. Bonding of these GND pads is optional. See the Applications Information section. required when the RF line potential is equal to 0 V DC. For the interface schematic, see Figure 5. required when the RF line potential is equal to 0 V DC. For the interface schematic, see Figure 5. 5 VDD Positive Supply Voltage. For the interface schematic, see Figure 6. 6 CTRL Control Input Voltage. For the interface schematic, see Figure 8. 7 EN Enable Input Voltage. For the interface schematic, see Figure 9. 8 VSS Negative Supply Voltage. For the interface schematic, see Figure 7. required when the RF line potential is equal to 0 V DC. For the interface schematic, see Figure 5. Carrier Bottom Exposed Pad. The exposed pad must be connected to the RF and DC ground of the PCB.
nally and to provide the advantage of a simplified control interface. VDD pad and a negative supply voltage applied to the VSS pad.
- Power up the VDD and VSS voltages. Power up VSS after VDD to
avoid current transients on VDD during ramp up.
- Power up the digital control inputs. The order of the digital
applied to the VDD, and the VSS pad is connected to ground. teristics and large signal. For more details, see Table 2. matching networks are not required. ed RF throw port that is terminated to an internal 50 Ω resistor. Table 7. Control Voltage Truth Table
One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 21. 15-Pad Bare Die [CHIP]