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Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 13
Technical content
Silicon, Transmit and Receive Switch with Limiter, 6 GHz to 12 GHz Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►High-power transmit and receive switch with an integrated power limiter on receive path ►Frequency range: 6 GHz to 12 GHz ►Reflective 50 Ω design ►Low insertion loss ►TX to ANT: 0.9 dB at 8 GHz to 11 GHz ►ANT to RX: 1.4 dB at 8 GHz to 11 GHz ►High isolation: 55 dB typical for TX to RX when TX selected ►High-power handling (TCASE = 50°C) ►Input at TX: pulsed 40 dBm, >100 ns pulse width at 15% duty cycle ►Input at ANT: pulsed 40 dBm, >100 ns pulse width at 15% duty cycle ►RX flat leakage: 17 dBm ►High linearity ►Input P0.1dB at TX arm: 41 dBm ►Fast switching time: 50 ns ►Fast response and recovery time: <10 ns ►Dual-supply, with no low-frequency spurious ►Positive control interface: CMOS-/LVTTL-compatible ►20-lead, 3 mm × 3 mm LGA package ►Pin compatible with the ADRF5144
APPLICATIONS
►X-band communications and radars ►Electronic warfare ►Satellite communications ►GaN and PIN diode replacement FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram applications with an integrated power limiter on the receive path. insertion loss of 0.9 dB at 8 GHz to 11 GHz. voltage transistor to transistor logic (LVTTL)-compatible controls.
analog.com Rev. 0 | 2 of 13 Input Power Compression, POUT vs. PIN,
REVISION HISTORY
10/2022—Revision 0: Initial Version
Ω system, unless otherwise noted. Table 1. Specifications
6 GHz to 12 GHz
1 For power derating vs. frequency for input at TX, see Figure 2. 2 For 105°C operation, the power handling degrades from the TCASE = 85°C specifications by 3 dB. 3 For different pulsed conditions, please contact applications support.
For recommended operating conditions, see Table 1. Table 2. Absolute Maximum Ratings 1 For power derating vs. frequency for the input at TX, see Figure 2.
2 For 105°C operation, the power handling degrades from the TCASE = 85°C
ing conditions for extended periods may affect product reliability. Table 3. Thermal Resistance Figure 2. Power Derating vs. Frequency for Input at TX, TCASE = 85°C sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 4. ADRF5141, 20-Terminal LGA damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
nally and to provide the advantage of a simplified control interface. VDD pin and a negative supply voltage applied to the VSS pin.
- Power up VDD and VSS. Power up VSS after VDD to avoid
current transients on VDD during ramp-up.
- Power up the digital control input (CTRL). Power up CTRL be-
- Apply an RF input signal.
matching networks are required. Table 6. Control Voltage Truth Table
Figure 25. Recommended RF Pin Transitions Request for further recommendations.
registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 26. 20-Terminal Land Grid Array [LGA] Table 7. Evaluation Boards