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Silicon SP4T Switch, Reflective, 9 kHz to 44 GHz Data Sheet ADRF5047 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Ultrawideband frequency range: 9 kHz to 44 GHz Reflective design Low insertion loss 1.5 dB to 18 GHz 2.4 dB to 40 GHz 2.7 dB to 44 GHz High isolation 47 dB to 18 GHz 33 dB to 40 GHz 31 dB to 44 GHz High input linearity P0.1dB: 26.5 dBm typical IP3: 50 dBm typical High RF input power handling Through path: 26 dBm Hot switching: 26 dBm No low frequency spurious 0.1 dB RF settling time: 5.2 µs 20-terminal, 3 mm × 3 mm, RoHS-compliant, LGA package Pin compatible with ADRF5046, fast switching version
APPLICATIONS
Cellular infrastructure—mmWave 5G Military radios, radars, and electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSA Ts) FUNCTIONAL BLOCK DIAGRAM GNDRF1GNDV2 GND GNDVDD RF4 GNDGND GND RFC GND VSS GND GND RF2 GND RF3 6 7 8 9 10 1617181920 DRIVER 16765-001 ADRF5047 Figure 1. GENERAL DESCRIPTION The ADRF5047 is a reflective, single-pole, four-throw (SP4T) switch manufactured in the silicon process. The ADRF5047 operates from 9 kHz to 44 GHz with an insertion loss of lower than 2.7 dB and an isolation of higher than 31 dB. The device has a radio frequency (RF) input power handling capability of 26.5 dBm for both through path and hot switching. The ADRF5047 draws a low current of 3 µA on the positive supply of +3.3 V, and −110 µA on the negative supply of −3.3 V. The device provides complementary metal-oxide semiconductor (CMOS)-/low voltage transistor-transistor logic (LVTTL)- compatible controls. The ADRF5047 is pin-compatible with the ADRF5046 fast switching version, which operates from 100 MHz to 44 GHz. The ADRF5047 comes in a 20-terminal, 3 mm × 3 mm, RoHS- compliant, land grid array (LGA) package and operates from −40°C to +105°C.
Rev. 0 | Page 2 of 15 TABLE OF CONTENTS
REVISION HISTORY
11/2019—Revision 0: Initial Version
Rev. 0 | Page 3 of 15 SPECIFICATIONS Positive supply voltage (VDD) = +3.3 V , negative supply voltage (VSS) = −3.3 V , digital control input voltage (VCTL) = 0 V or +3.3 V , and case temperature (TCASE) = 25°C on a 50 Ω system, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE f 0.009 44,000 MHz INSERTION LOSS Between RFC and RF1 to RF4 (On) 9 kHz to 18 GHz 1.5 dB 18 GHz to 26 GHz 1.6 dB 26 GHz to 35 GHz 2.2 dB 35 GHz to 40 GHz 2.4 dB 40 GHz to 44 GHz 2.7 dB ISOLATION Between RFC and RF1 to RF4 (Off ) 9 kHz to 18 GHz 47 dB
18 GHz to 26 GHz 41 dB
26 GHz to 35 GHz 35 dB
35 GHz to 40 GHz 33 dB
40 GHz to 44 GHz 31 dB
RFC and RF1 to RF4 (On) 9 kHz to 18 GHz 15 dB
18 GHz to 26 GHz 16 dB
26 GHz to 35 GHz 15 dB
35 GHz to 40 GHz 15 dB
40 GHz to 44 GHz 14 dB
Rise Time and Fall Time tRISE, tFAL L 10% to 90% of RF output 1.4 µs On Time and Off Time tON, tOFF 50% VCTL to 90% of RF output 3.4 µs RF Settling Time 0.1 dB 50% VCTL to 0.1 dB of final RF output 5.2 µs 0.05 dB 50% VCTL to 0.05 dB of final RF output 7.2 µs INPUT LINEARITY1 0.1 dB Power Compression P0.1dB f = 200 kHz to 40 GHz 26.5 dBm Third-Order Intercept IP3 Two-tone input power = 14 dBm each tone, f = 200 kHz to 40 GHz, Δf = 1 MHz 50 dBm Second-Order Intercept IP2 Two-tone input power = 14 dBm each tone, f = 10 GHz, Δf = 1 MHz 100 dBm VIDEO FEEDTHROUGH2 2 mV p-p SUPPLY CURRENT VDD, VSS pins Positive IDD 3 µA Negative ISS −110 µA DIGITAL CONTROL INPUTS V1, V2 pins Voltage Low VINL 0 0.8 V High VINH 1.2 3.3 V Current Low IINL <1 µA High IINH 35 µA
Rev. 0 | Page 4 of 15 Parameter Symbol Test Conditions/Comments Min Typ Max Unit RECOMMENDED OPERATING CONDITONS Supply Voltage Positive VDD 3.15 3.45 V Negative VSS −3.45 −3.15 V Digital Control Inputs Voltage VCTL 0 VDD V RFx Input Power3 PIN f = 200 kHz to 40 GHz, TCASE = 85°C4 Through Path RF signal is applied to RFC or through connected RF throw port 26 dBm Hot Switching RF signal is present at RFC while switching between RF throw port 26 dBm Case Temperature TCASE −40 +105 °C 1 For input linearity performance over frequency, see Figure 19 to Figure 22. 2 Video feedthrough is the spurious dc transient measured at the RF ports in a 50 Ω test setup, without an RF signal present while switching the control voltage. 3 For power derating over frequency, see Figure 2 and Figure 3. 4 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
For recommended operating conditions, see Table 1. 1 For power derating over frequency, see Figure 2 and Figure 3.
2 For 105°C operation, the power handling degrades from the TCASE = 85°C
Only one absolute maximum rating can be applied at any one time. PCB thermal design is required. Table 3. Thermal Resistance Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85°C
VDD pin and a negative supply voltage applied to the VSS pin. 50 Ω. Therefore, external matching networks are not required. design is bidirectional with equal power handling capabilities.
- Power up VDD and VSS. Power up VSS after VDD to avoid
current transients on VDD during ramp up.
- Apply digital control inputs, V1 and V2. Applying these
up and the control pins are not driven to a valid logic state.
- Apply an RF input signal to either the RFC port or the RF
Table 5. Control Voltage Truth Table
Figure 27. Evaluation Board Assembly Drawing
Figure 28. Evaluation Board Schematic Table 6. Evaluation Board Components U1 ADRF5047 SP4T switch, Analog Devices, Inc.
the top view of the probe matrix board layout. Figure 29. Probe Matrix Board Layout (Top View)
1.60 REF
Figure 30. 20-Terminal Land Grid Array [LGA] registered trademarks are the prop erty of their respective owners.